A reverse polarity protection circuit, a switching module and an application circuit thereof

Abstract

This invention relates to the field of circuit design technology, and more particularly to a reverse polarity protection circuit, a switching module, and its application circuit. The reverse polarity protection circuit includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, a first PMOS transistor MP1, and a second PMOS transistor MP2. This invention actively turns on the power transistors when a reverse polarity event occurs, forming a low-resistance path to replace the body diode's conduction, thereby significantly reducing power consumption. In all operating states (normal on / off, inductive load, reverse polarity), the gate-source and drain-source voltages of each MOS transistor remain within safe ranges, with no risk of overvoltage. It can be applied to standard processes, reducing manufacturing costs and design complexity.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to a reverse polarity protection circuit, a switching module, and its application circuit. Background Technology

[0002] High-side intelligent power switches are used to replace relays or fuses in a wide range of applications, offering higher reliability and stability, as well as smaller size and manufacturing cost compared to traditional mechanical switches and discrete switching devices. Sufficient reverse polarity protection is essential in typical battery-powered systems (such as automotive electronics). Reliable electronic devices typically need to withstand power supply voltages up to -16V (reverse voltage) for at least two minutes.

[0003] The output channel of a smart power switch chip typically includes a power semiconductor switch (usually a MOSFET), with the load connected to the output channel and then to the power supply voltage via the switch. Therefore, the load's connection to the power supply voltage is switched on or off depending on the on / off state of the semiconductor switch. Assuming the on-resistance of the semiconductor switch is 100mΩ and the rated load current is 1A, the power dissipation of the output channel during normal operation is 100mW. The power semiconductor switch typically has a reverse-biased body diode connected in parallel with the channel current path. During normal operation, this body diode is reverse-biased and off; however, when the power supply is reverse-connected (reverse polarity), the body diode conducts forward and provides a reverse load current path. Assuming the forward voltage drop of the body diode is 0.7V, the power dissipation of the output channel due to the body diode conducting in reverse polarity is 700mW, seven times that during normal operation. This can lead to significant heat generation and even device damage. Therefore, a reliable reverse polarity protection circuit is needed to prevent this from occurring.

[0004] Figure 1The image shows an example of a prior art implementation of reverse polarity protection. In the prior art, the gate of the main power transistor T1 is connected to the ground terminal via a reverse polarity protection circuit consisting of diode D2, D1, R1, and R2. During reverse polarity, the ground terminal charges the gate of the main power transistor T1 through the reverse polarity protection circuit and diode D2 (the ground terminal is at high voltage, e.g., 16V during reverse polarity), thereby turning on the main power transistor T1 and reducing the power consumption of the output channel. However, when the PMOS transistor MP2, which constitutes the reverse polarity protection, drives an inductive load, during the rapid demagnetization phase under normal polarity, the gate voltage of the main power transistor T1 is typically clamped to -27V (example level). Therefore, the drain voltage of MP2 is -26.3V, and the source voltage is ground (0V). Thus, MP2 needs to withstand a voltage of nearly 30V. Furthermore, to avoid affecting the normal operation of the MP2 transistor, the back gate and source need to be shorted. In n-substrate processes, isolated high-voltage P-type transistors require the implantation of a P-doped isolation region on the n-type substrate, followed by the implantation of an n-well within the P-doped isolation region. The n-well is then used as the substrate to fabricate the isolated high-voltage P-type transistor MP2. Achieving high voltage withstand capability with this structure requires specific processes. Therefore, this implementation method places certain requirements on process selection. Moreover, in applications where there is no specific internal clamping protection and an external Schottky diode is needed to protect the chip ground, additional packaging is required to connect to the external ground potential, increasing packaging costs.

[0005] exist Figure 2 The diagram shows parasitic devices near the gate of the main power transistor and the driving transistor DMN1. The push-pull NMOS transistor DMN1 is integrated in a p-doped well, and its n-type drain-p-doped well-n-type substrate constitutes an npn-type parasitic transistor Q1. When the base-emitter voltage of the parasitic transistor Q1 is greater than the threshold voltage, the parasitic transistor Q1 turns on, pulling the gate potential of the main power transistor to 0V, preventing the main power transistor from turning on, and causing the reverse polarity protection circuit to fail. Summary of the Invention

[0006] This invention provides a reverse polarity protection circuit, a switching module, and an application circuit thereof to solve the technical problems mentioned in the background art.

[0007] The first technical solution of the present invention is as follows: a reverse polarity protection circuit, comprising: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, a first PMOS transistor MP1, and a second PMOS transistor MP2;

[0008] The drain of the first NMOS transistor MN1 is connected to the internal power supply voltage VCC, the gate is connected to the internal ground GND_INT, and the source is connected to the source of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 is connected to the internal ground GND_INT, and the drain is connected to one end of the second resistor R2 and the cathode of the fourth diode D4. The anode of the fourth diode D4 is connected to the internal ground GND_INT. The other end of the second resistor R2 is connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and one end of the first resistor R1. The sources of the first PMOS transistor MP1, the sources of the second PMOS transistor MP2, and the other end of the first resistor R1 are connected to the input control signal. The drain of the first PMOS transistor MP1 is connected to the source of the third NMOS transistor MN3, one end of the third resistor R3, and the fifth NMOS transistor MN4. The gate of the fifth NMOS transistor MN5 is connected to the gate of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to the source of the fifth NMOS transistor MN5. The gate of the third NMOS transistor MN3 is connected to the level signal. The drain of the third NMOS transistor MN3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the output port OUTPUT. The other end of the third resistor R3 is connected to the source of the fourth NMOS transistor MN4. The gate of the fourth NMOS transistor MN4 is connected to the operating voltage VINT0. The drain of the fourth NMOS transistor MN4 is connected to the internal ground GND_INT. The drain of the fifth NMOS transistor MN5 is connected to the anode of the third diode D3. The cathode of the third diode D3 is connected to the main power transistor.

[0009] Furthermore, the input control signal is an externally input enable signal or signal ground GND.

[0010] Furthermore, it also includes a second protection circuit, which includes: a sixth NMOS transistor MN6, a sixth diode D6, a fifth diode D5, a fourth resistor R4, and a power transistor T2. The source of the sixth NMOS transistor MN6 is connected to the negative terminal of the first diode D1, the gate of the sixth NMOS transistor MN6 is connected to one end of the third resistor R3, the drain of the sixth NMOS transistor MN6 is connected to the positive terminal of the sixth diode D6, the negative terminal of the sixth diode D6 is connected to the positive terminal of the fifth diode D5, one end of the fourth resistor R4, and the gate of the power transistor T2, the positive terminal of the fifth diode D5, the other end of the fourth resistor R4, and the source of the power transistor T2 are connected to the output port OUTPUT, and the drain of the power transistor T2 is connected to the internal power supply voltage VCC.

[0011] Furthermore, when the supply voltage VCC is positive and the load is non-inductive, and when the supply voltage VCC is reversed, the level signal controls the third NMOS transistor MN3 to turn off; when the supply voltage VCC is positive and the load is inductive, the level signal controls the third NMOS transistor MN3 to turn on.

[0012] The second technical solution of the present invention is as follows: A switching module includes: a power supply port VCC, an output port OUTPUT, an input port IN, an enable port SEN, a power supply circuit, an interface circuit, a control circuit, a main power transistor, and any of the above-mentioned reverse polarity protection circuits. The power supply circuit is connected to the power supply port VCC, and the power supply port VCC is connected to an external system power supply VBAT, which is input into the switching module to form an internal power supply voltage VCC. The power supply circuit is used to convert the internal power supply voltage VCC into a working voltage VINT0 and supply power to the interface circuit, the control circuit, and the reverse polarity protection circuit.

[0013] The input terminal of the interface circuit is connected to the input port IN and the enable port SEN, and the output terminal of the interface circuit is connected to the input terminal of the control circuit. The interface circuit is used to receive the input signal of the input port IN and the enable signal of the enable port SEN.

[0014] The output terminal of the control circuit is connected to the gate of the main power transistor. The control circuit is used to generate a trigger signal based on the input signal and the enable signal. The trigger signal is used to control the main power transistor to turn on and off.

[0015] The input terminal of the reverse polarity protection circuit is connected to the input control signal, and the output terminal is connected to the output port OUTPUT and the gate of the main power transistor.

[0016] The source of the main power transistor is connected to the output port OUTPUT, and the drain is connected to the power supply port VCC.

[0017] Furthermore, the input control signal is either the enable signal input to the enable port SEN or the signal ground GND.

[0018] Furthermore, the gate of the main power transistor is connected to a push-pull circuit.

[0019] The third technical solution of the present invention is as follows: an application circuit for a switching module, including any of the switching modules, controllers and loads described above, wherein the controller is connected to an input port IN and an enable port SEN, the power supply port VCC is connected to an external system power supply VBAT, one end of the load is connected to an output port OUTPUT, and the other end is connected to signal ground.

[0020] The beneficial effects of this invention are as follows:

[0021] 1. Significantly reduces power consumption and heat generation during reverse polarity operation.

[0022] This invention forces the main power transistor to turn on during reverse polarity, making it work in channel conduction mode, reducing the voltage drop to about 0.1V and the power consumption to about 1 / 7 of the original, effectively preventing the device from overheating and being damaged.

[0023] 2. No high-pressure withstand risk, good process compatibility.

[0024] In all operating states (normal on / off, inductive load, reverse polarity), the gate-source and drain-source voltages of each MOS transistor are within a safe range, with no risk of overvoltage. This circuit can be applied to standard processes, reducing manufacturing costs and design complexity.

[0025] 3. Supports port multiplexing, saving package pins.

[0026] This invention can configure the input control signal of the protection circuit as an external enable signal (such as SEN), realize pin function multiplexing, complete reverse polarity protection without adding extra pins, and improve system integration and flexibility.

[0027] 4. Effectively inhibits parasitic effects, making the protective function more reliable.

[0028] To address the issue of parasitic NPN transistor conduction that may be triggered by the N-type substrate vertical power transistor in high-side switches under reverse polarity, this invention adds a second protection circuit (including power transistor T2, etc.) to actively establish a low-resistance path under reverse polarity, suppress malfunctions of parasitic devices, ensure reliable turn-on of the main power transistor, and improve protection robustness.

[0029] 5. Modular design, easy to integrate and apply.

[0030] The protection circuit can be integrated as an independent module into the high-side intelligent power switch, working in conjunction with the power supply circuit, interface circuit, control circuit, etc., without affecting the original control logic.

[0031] The protection circuit is completely shut off during normal polarity operation, without introducing additional static power consumption, making it suitable for power-sensitive battery-powered systems (such as automotive electronics).

[0032] 6. Improve system reliability and lifespan

[0033] By effectively addressing harsh operating conditions such as reverse power connection and inductive load impact, the thermal and electrical stress of the chip is reduced, significantly improving the overall system reliability, stability and lifespan, meeting the high reliability requirements of automotive electronics, industrial control and other fields. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a reverse polarity protection circuit in existing technology.

[0035] Figure 2 This is a schematic diagram of the parasitic NPN transistor in the main power transistor drive circuit.

[0036] Figure 3 This is a schematic diagram of the reverse polarity protection circuit in Embodiment 1 of the first technical solution of the present invention.

[0037] Figure 4 This is a schematic diagram of the reverse polarity protection circuit in Embodiment 2 of the first technical solution of the present invention.

[0038] Figure 5 This is one of the schematic diagrams of the reverse polarity protection circuit in Embodiment 3 of the first technical solution of the present invention.

[0039] Figure 6 This is the second schematic diagram of the reverse polarity protection circuit in Embodiment 3 of the first technical solution of the present invention.

[0040] Figure 7 This is one of the structural block diagrams of the second and third technical solutions of the present invention.

[0041] Figure 8 This is the second structural block diagram of the second and third technical solutions of the present invention.

[0042] Figure 9 This is the third structural block diagram of the second and third technical solutions of the present invention. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0044] It should be noted that, to avoid making the manual cumbersome, the names of various components will be simplified as necessary in the following text, such as the first NMOS transistor MN1 being simplified to MN1. Those skilled in the art will understand that MN1 alone refers to the first NMOS transistor MN1.

[0045] In the first technical solution of the present invention, Figure 3 This is a schematic diagram of an embodiment 1 of the reverse polarity protection circuit according to the present technical solution. Its core lies in detecting the power supply polarity and actively turning on the power transistor when a reverse polarity event occurs, forming a low-resistance path to replace the body diode's conduction, thereby significantly reducing power consumption. Figure 3 As shown, Example 1 includes:

[0046] First NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, first diode D1, second diode D2, third diode D3, fourth diode D4, first resistor R1, second resistor R2, third resistor R3, fifth resistor R5, first PMOS transistor MP1, second PMOS transistor MP2;

[0047] The drain of the first NMOS transistor MN1 is connected to the internal power supply voltage VCC, the gate is connected to the internal ground GND_INT, and the source is connected to the source of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 is connected to the internal ground GND_INT, and the drain is connected to one end of the second resistor R2 and the cathode of the fourth diode D4. The anode of the fourth diode D4 is connected to the internal ground GND_INT. The other end of the second resistor R2 is connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and one end of the first resistor R1. The sources of the first PMOS transistor MP1, the sources of the second PMOS transistor MP2, and the other end of the first resistor R1 are connected to the input control signal. The drain of the first PMOS transistor MP1 is connected to the source of the third NMOS transistor MN3, one end of the third resistor R3, and the fifth NMOS transistor MN4. The gate of the fifth NMOS transistor MN5 is connected to the gate of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to the source of the fifth NMOS transistor MN5. The gate of the third NMOS transistor MN3 is connected to the level signal. The drain of the third NMOS transistor MN3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the output port OUTPUT. The other end of the third resistor R3 is connected to the source of the fourth NMOS transistor MN4. The gate of the fourth NMOS transistor MN4 is connected to the operating voltage VINT0. The drain of the fourth NMOS transistor MN4 is connected to the internal ground GND_INT. The drain of the fifth NMOS transistor MN5 is connected to the anode of the third diode D3. The cathode of the third diode D3 is connected to the main power transistor.

[0048] In this embodiment, the input control signal is signal ground GND.

[0049] It should be noted that the first NMOS transistor MN1 is a high-voltage power dissipation transistor; the first PMOS transistor MP1 and the second PMOS transistor MP2 are high-voltage P transistors; and the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are high-voltage N transistors.

[0050] Working principle:

[0051] Under normal polarity operation (e.g., VCC=16V, GND=0V): At this time, the gate potentials (connected to GND_INT) of the first NMOS transistor MN1 and the second NMOS transistor MN2 are lower than their drain potentials (connected to VCC), and both are cut off. The gates and sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are close to the GND potential (0V), and are also cut off. The level signal controls the third NMOS transistor MN3 to turn off. The fourth NMOS transistor MN4 is turned on because its gate is connected to a valid operating voltage VINT0, pulling down the voltage at node VA (i.e., the drain of MP1) to GND_INT (0V), thereby turning off the fifth NMOS transistor MN5. At this time, the gate of the main power transistor T1 is completely driven by the external control circuit, and this protection circuit has no effect.

[0052] Reverse polarity operation (e.g., VCC=0V, GND=16V): The voltage between the gate (GND_INT=0V) and drain (VCC≈0V) of the first NMOS transistor MN1 is close to 0V, and MN1 is turned on. Simultaneously, the second NMOS transistor MN2 is also turned on. The high voltage (16V) from signal ground GND, through the turned-on MN1 and MN2 and the voltage divider network formed by the first resistor R1 and the second resistor R2, causes the first PMOS transistor MP1 and the second PMOS transistor MP2 to obtain a positive gate-source voltage and turn on. The high potential is then transmitted to node VA, turning on the fifth NMOS transistor MN5. At this time, due to the reverse power supply, the internal operating voltage VINT0 may fail, and the fourth NMOS transistor MN4 is turned off. The conduction of the fifth NMOS transistor MN5 transmits the high potential to the gate of the main power transistor T1 through the third diode D3, forcibly turning on T1 and forming a low-resistance path (voltage drop of about 0.1V) between the output port OUTPUT and the internal supply voltage VCC, avoiding current flowing through the body diode (voltage drop of 0.7V) and achieving reverse polarity protection.

[0053] Pressure resistance safety analysis:

[0054] When the supply voltage VCC is positive and the load is non-inductive, and when the supply voltage VCC is reversed, the level signal controls the third NMOS transistor MN3 to turn off. When the supply voltage VCC is positive and the load is inductive, the level signal controls the third NMOS transistor MN3 to turn on.

[0055] It should be noted that the level signal can be generated by an internal control circuit or an external controller, and therefore, this invention does not impose any restrictions.

[0056] Under normal polarity and with the main power transistor off, the voltage at the GATE terminal is 0V, the gate-source-drain voltages of MN3 and MN5 are both 0V, and the gate-source-drain voltages of MP1 and MP2 are also both 0V. The circuit has no withstand voltage risk.

[0057] Under normal polarity and with the main power transistor on, GATE is at a high level of approximately 21V (VCC=16V), the gate-source voltages of MP1 and MP2 are 0V, the gate-source voltage of MN2 is 0V, and the drain voltage is within the withstand voltage range, so the circuit has no withstand voltage risk.

[0058] When driving an inductive load under normal polarity, the voltage level signal is negative, turning on MN3. The VA node is pulled down to the negative voltage protection transistor MN5, and the source-drain withstand voltage is 0V-GATE, which is within the withstand voltage range. Transistors MP1 and MP2 are off, and the gate-source-drain voltage is 0V. Under reverse polarity, MN1 and MN5 are on, and the gate-source voltage is 0.7V. The drain voltage is approximately equal to the low-voltage MOS turn-on threshold, which is within the withstand voltage range. When MP1 and MP2 are on, the gate-source voltage is a resistive voltage divider, and the source-drain voltage is almost equal, so there is no risk of overvoltage.

[0059] This circuit has no risk of overvoltage under all operating conditions. Under normal polarity, the gate-source and drain-source voltages of each MOSFET are within safe limits. When driving an inductive load to generate a negative voltage, the voltage level signal will turn on the third NMOS transistor MN3, pulling down the VA node potential and protecting the fifth NMOS transistor MN5. Under reverse polarity, the voltage difference between each conducting component is designed to be within safe values.

[0060] In Embodiment 2 of this technical solution, Figure 4 Another embodiment of the reverse polarity protection circuit of the present invention is shown, characterized in that the input control signal is not fixed to signal ground GND, but is connected to an external input enable signal, i.e., the external enable port SEN. This design allows the reverse polarity protection function to reuse the same pin as other functions of the chip (such as current sampling enable), thereby saving package pins and reducing costs.

[0061] The connection relationship of this circuit is... Figure 1 The embodiments are basically the same, with the core difference being that the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, and the other end of the first resistor R1 are all connected to the enable port SEN.

[0062] SEN is often configured as an external enable for the current sampling function of the high-side switch. It is required that the battery reverse bias circuit and normal operation do not affect the operating state of SEN. Under normal polarity, when SEN is low, MN1 and MN5 are off, the gate voltages and source voltages of MP1 and MP2 are 0, MP1 and MP2 are off, and there is no path from the reverse polarity protection circuit to the SEN port. Under normal polarity, when SEN is high, MN1 and MN5 are off, the gate voltages and source voltages of MP1 and MP2 are equal to SEN, MP1 and MP2 are off, and there is no path from the reverse polarity protection circuit to the SEN port. In reverse polarity connection, the external port is usually controlled by an MCU. SEN is equal to GND - 0.7V and is clamped by the chip's Zener diode, typically 6V. The external command signal SEN can replace GND to transfer the potential to the gate of power transistor T1 to turn on T1, achieving reverse polarity protection.

[0063] In summary: Under normal polarity, regardless of whether the SEN terminal is high or low, the gate-source voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both 0 or negative, remaining off. The protection circuit does not operate, and the original function of the SEN port is not affected. Under reverse polarity, the external controller can place the SEN port at an effective potential (e.g., clamped to a safe voltage by an internal Zener diode). This potential can effectively replace the role of GND in Embodiment 1. After being transmitted through this protection circuit, it can also turn on the main power transistor T1, achieving reverse polarity protection.

[0064] Considerations regarding pressure resistance:

[0065] Under normal polarity and with the main power transistor off, the voltage at the GATE terminal is 0V, the gate-source-drain voltages of MN2 and MN3 are both 0V, and the gate-source-drain voltages of MP1 and MP2 are also both 0V. The circuit has no withstand voltage risk.

[0066] Under normal polarity and with the main power transistor on, GATE is at a high level of approximately 18V, the gate-source voltages of MP1 and MP2 are 0V, the gate-source voltage of MN2 is 0V, and the drain voltage is within the withstand voltage range, so the circuit has no withstand voltage risk.

[0067] When driving an inductive load under normal polarity, during the demagnetization phase of T1, the voltage level signal is negative, turning on MN3. The VA node is pulled down to a negative voltage to protect MN2. The source-drain withstand voltage is 0V-GATE, which is within the withstand voltage range. MP1 and MP2 are off, and the gate-source-drain voltage is 0V. In reverse polarity, MN1 and MN5 are on, and the gate-source voltage is 0.7V. The drain voltage is approximately equal to the low-voltage MOS turn-on threshold, which is within the withstand voltage range. MP1 and MP2 are on, and the gate-source voltage is a resistive voltage divider. The source and drain voltages are almost equal, and there is no risk of overvoltage.

[0068] In Embodiment 3 of this technical solution, addressing the problem that when the main power transistor uses an N-type substrate vertical structure, the drive circuit may fail due to the conduction of parasitic NPN transistors under reverse polarity, leading to protection failure. This invention further proposes an enhanced solution including a second-stage protection circuit, such as... Figure 5 As shown.

[0069] This embodiment also includes a second protection circuit, such as Figure 5 and Figure 6 As shown, the second protection circuit includes: a sixth NMOS transistor MN6, a sixth diode D6, a fifth diode D5, a fourth resistor R4, and a power transistor T2. The source of the sixth NMOS transistor MN6 is connected to the cathode of the first diode D1, the gate of the sixth NMOS transistor MN6 is connected to one end of the third resistor R3, the drain of the sixth NMOS transistor MN6 is connected to the anode of the sixth diode D6, the cathode of the sixth diode D6 is connected to the anode of the fifth diode D5, one end of the fourth resistor R4, and the gate of the power transistor T2, the anode of the fifth diode D5, the other end of the fourth resistor R4, and the source of the power transistor T2 are connected to the output port OUTPUT, and the drain of the power transistor T2 is connected to the internal power supply voltage VCC.

[0070] Among them, the power transistor T2 can be configured as an N-type vertical transistor, but it has a smaller size than the main power transistor T1.

[0071] The enhanced protection principle is as follows: The forward voltage operation of the second protection circuit is similar to that of the reverse polarity protection circuit described above. During forward operation, MN5 is turned off, and the gate of T2 is shorted to the output terminal OUTPUT via R4. The second reverse polarity protection circuit is turned off, which does not affect the normal operation of the drive. During reverse polarity operation, the gate-drain voltage of MN1 is 0V, MN1 is turned on, and MN2 is turned on at the same time. R1 and R2 generate a voltage divider. By adjusting the ratio of R1 and R2, the gate-source voltage of MP1 can be controlled within the safe operating area, and MP1 and MP2 are turned on. The high voltage is transmitted to the VA node and the drain of MN6. At this time, the internal power supply fails, MN4 is turned off, MN6 is turned on, and the potential is transmitted to the gate of the power transistor T2. The power transistor T2 is turned on, forming a low-impedance path from the output terminal OUTPUT to VCC. The parasitic transistor Q1 will not malfunction. Note that the necessary condition for the implementation of the second reverse polarity protection circuit is that there is no push-pull structure similar to the drive of the main power transistor T1 near the power transistor T2.

[0072] In summary, during reverse polarity operation, node VA in the first-stage protection circuit goes high. This high level not only controls the fifth NMOS transistor MN5 to turn on the main power transistor T1, but also turns on the sixth NMOS transistor MN6. The high potential is transmitted to the gate of power transistor T2 through MN6 and the sixth diode D6, turning T2 on. T2 establishes a parallel low-impedance path between VCC and OUTPUT, effectively clamping the voltage at the output terminal, thereby suppressing the risk of false turn-on of parasitic transistors in the main power transistor drive circuit and ensuring the absolute reliability of the reverse polarity protection function. During normal polarity operation, node VA is low, the sixth NMOS transistor MN6 is off, and the gate of power transistor T2 is shorted to the output terminal OUTPUT through the fourth resistor R4, keeping T2 off and not affecting the normal operation of the system.

[0073] In the second technical solution of the present invention, Figure 7 , 8 9 is a structural schematic diagram provided according to an embodiment of a switch module of this technical solution, wherein... Figure 7 and Figure 8 These are schematic diagrams of positive and negative polarities, respectively. Figure 9 This is a schematic diagram of port multiplexing.

[0074] like Figure 7 and Figure 8 As shown, it includes: a power supply port VCC, an output port OUTPUT, an input port IN, an enable port SEN, a power supply circuit 110, an interface circuit 120, a control circuit 130, a main power transistor, and any of the above-described reverse polarity protection circuits 150.

[0075] The power supply circuit 110 is connected to the power supply port VCC, which is connected to the external system power supply VBAT and input to the switch module to form the internal power supply voltage VCC. The power supply circuit 110 is used to convert the internal power supply voltage VCC into the working voltage VINT0 and supply power to the interface circuit 120, the control circuit 130 and the reverse polarity protection circuit 150.

[0076] Meanwhile, the switch module has a grounding port GND, which is connected to the signal ground.

[0077] The power supply circuit is connected to the power supply port VCC. The power supply port VCC is used to connect to the external system power supply VBAT. The main function of the power supply circuit is to convert the unstable external voltage VBAT into a stable internal operating voltage VINT0, and to provide clean power and a stable internal ground GND_INT for the interface circuit, control circuit, and reverse polarity protection circuit. It should be noted that 140 in the diagram represents the internal ground node, which is the aforementioned internal ground GND_INT.

[0078] The input terminal of the interface circuit 120 is connected to the input port IN and the enable port SEN, and the output terminal of the interface circuit is connected to the input terminal of the control circuit 130. The interface circuit 120 is used to receive the input signal from the input port IN and the enable signal from the enable port SEN, specifically receiving the input signal and enable signal from an external controller (such as a microcontroller). The output terminal of the interface circuit is connected to the input terminal of the control circuit, transmitting the processed command signal to the control circuit.

[0079] The output terminal of the control circuit 130 is connected to the gate of the main power transistor, specifically, the gate of the main power transistor can be connected to a push-pull circuit. The control circuit 130 generates a trigger signal based on the input signal and an enable signal, which controls the main power transistor's on / off state. The control circuit generates a corresponding gate drive signal based on instructions from the interface circuit, and controls the main power transistor's on / off state through a push-pull circuit (e.g., composed of a PMOS transistor DMP1 and an NMOS transistor DMN1). The drain of the main power transistor is connected to the power supply port VCC, and the source is connected to the output port OUTPUT.

[0080] The input terminal of the reverse polarity protection circuit 150 is connected to the input control signal, and the output terminal is connected to the output port OUTPUT and the gate of the main power transistor.

[0081] The input terminal of the reverse polarity protection circuit is connected to an input control signal (such as GND or SEN), and its output terminal is connected to the output port OUTPUT and the gate of the main power transistor. When the power supply polarity is normal, the circuit does not operate; once a reverse power connection is detected, it immediately intervenes, forcibly turning on the main power transistor and performing the protection function.

[0082] The source of the main power transistor is connected to the output port OUTPUT, and the drain is connected to the power supply port VCC.

[0083] The input control signal is either the enable signal input to the enable port SEN or signal ground GND. Specifically, as shown below... Figure 7 and Figure 8 As shown, when the input control signal is signal ground (GND), the reverse polarity protection circuit 150 is connected to the signal ground (GND) interface, such as... Figure 9 As shown, when the input control signal is the enable signal input to the enable port SEN, the reverse polarity protection circuit 150 is connected to the enable port SEN.

[0084] In the third technical solution of the present invention, Figure 7 , 8 9 is a schematic diagram of an application circuit for a switching module according to this technical solution, as shown in Figure 1. Figure 7 , 8As shown in Figures 1 and 9, the device includes any of the aforementioned switch module 100, controller 200, and load 300.

[0085] The controller 200 is connected to the input port IN and the enable port SEN. The power supply port VCC is connected to the external system power supply VBAT. One end of the load 300 is connected to the output port OUTPUT, and the other end is connected to the signal ground.

[0086] The controller 200 can be a microcontroller (MCU). The output of the controller 200 is connected via a resistor to the input port IN and the enable port SEN of the switch module 100, used to send control commands to the switch module. The power supply port VCC of the switch module is connected to the external system power supply VBAT. Simultaneously, the external system power supply VBAT is grounded through a capacitor. One end of the load 300 is connected to the output port OUTPUT of the switch module, and the other end is connected to the system signal ground. Simultaneously, the grounding port is connected to the signal ground through a grounding resistor RGND.

[0087] In this application circuit, the switching module acts as an intelligent high-side switch, switching the load on and off under the command of the controller. When the system power supply is accidentally reversed, the reverse polarity protection circuit integrated inside the switching module automatically activates, protecting the switching module itself and the load from damage caused by high current and overheating, greatly improving the reliability and safety of the entire electronic system.

[0088] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A reverse polarity protection circuit, characterized in that, include: First NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, first diode D1, second diode D2, third diode D3, fourth diode D4, first resistor R1, second resistor R2, third resistor R3, fifth resistor R5, first PMOS transistor MP1, second PMOS transistor MP2; The drain of the first NMOS transistor MN1 is connected to the internal power supply voltage VCC, the gate is connected to the internal ground GND_INT, and the source is connected to the source of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 is connected to the internal ground GND_INT, and the drain is connected to one end of the second resistor R2 and the cathode of the fourth diode D4. The anode of the fourth diode D4 is connected to the internal ground GND_INT. The other end of the second resistor R2 is connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and one end of the first resistor R1. The sources of the first PMOS transistor MP1, the sources of the second PMOS transistor MP2, and the other end of the first resistor R1 are connected to the input control signal. The drain of the first PMOS transistor MP1 is connected to the source of the third NMOS transistor MN3, one end of the third resistor R3, and the fifth NMOS transistor MN4. The gate of the fifth NMOS transistor MN5 is connected to the gate of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to the source of the fifth NMOS transistor MN5. The gate of the third NMOS transistor MN3 is connected to the level signal. The drain of the third NMOS transistor MN3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the output port OUTPUT. The other end of the third resistor R3 is connected to the source of the fourth NMOS transistor MN4. The gate of the fourth NMOS transistor MN4 is connected to the operating voltage VINT0. The drain of the fourth NMOS transistor MN4 is connected to the internal ground GND_INT. The drain of the fifth NMOS transistor MN5 is connected to the anode of the third diode D3. The cathode of the third diode D3 is connected to the main power transistor.

2. The reverse polarity protection circuit as described in claim 1, characterized in that, The input control signal is an externally input enable signal or signal ground GND.

3. The reverse polarity protection circuit as described in claim 1, characterized in that, It also includes a second protection circuit, which includes: a sixth NMOS transistor MN6, a sixth diode D6, a fifth diode D5, a fourth resistor R4, and a power transistor T2. The source of the sixth NMOS transistor MN6 is connected to the negative terminal of the first diode D1. The gate of the sixth NMOS transistor MN6 is connected to one end of the third resistor R3. The drain of the sixth NMOS transistor MN6 is connected to the positive terminal of the sixth diode D6. The negative terminal of the sixth diode D6 is connected to the positive terminal of the fifth diode D5, one end of the fourth resistor R4, and the gate of the power transistor T2. The positive terminal of the fifth diode D5, the other end of the fourth resistor R4, and the source of the power transistor T2 are connected to the output port OUTPUT. The drain of the power transistor T2 is connected to the internal power supply voltage VCC.

4. The reverse polarity protection circuit as described in claim 1, characterized in that, When the supply voltage VCC is positive and the load is non-inductive, and when the supply voltage VCC is reversed, the level signal controls the third NMOS transistor MN3 to turn off. When the supply voltage VCC is positive and the load is inductive, the level signal controls the third NMOS transistor MN3 to turn on.

5. A switching module, characterized in that, include: The system includes a power supply port VCC, an output port OUTPUT, an input port IN, an enable port SEN, a power supply circuit (110), an interface circuit (120), a control circuit (130), a main power transistor, and a reverse polarity protection circuit (150) as described in any of claims 1-4. The power supply circuit (110) is connected to the power supply port VCC, which is connected to the external system power supply VBAT and input into the switch module to form the internal power supply voltage VCC. The power supply circuit (110) is used to convert the internal power supply voltage VCC into the working voltage VINT0 and supply power to the interface circuit (120), the control circuit (130) and the reverse polarity protection circuit (150). The input terminal of the interface circuit (120) is connected to the input port IN and the enable port SEN, and the output terminal of the interface circuit is connected to the input terminal of the control circuit (130). The interface circuit (120) is used to receive the input signal of the input port IN and the enable signal of the enable port SEN. The output terminal of the control circuit (130) is connected to the gate of the main power transistor. The control circuit (130) is used to generate a trigger signal according to the input signal and the enable signal. The trigger signal is used to control the opening and closing of the main power transistor. The input terminal of the reverse polarity protection circuit (150) is connected to the input control signal, and the output terminal is connected to the output port OUTPUT and the gate of the main power transistor. The source of the main power transistor is connected to the output port OUTPUT, and the drain is connected to the power supply port VCC.

6. The switching module as described in claim 5, characterized in that, The input control signal is either the enable signal input to the enable port SEN or the signal ground GND.

7. The switching module as described in claim 5, characterized in that, The gate of the main power transistor is connected to a push-pull circuit.

8. An application circuit for a switching module, characterized in that, Includes the switch module (100), controller (200), and load (300) as described in any one of claims 5-7. The controller (200) is connected to the input port IN and the enable port SEN. The power supply port VCC is connected to the external system power supply VBAT. One end of the load (300) is connected to the output port OUTPUT, and the other end is connected to the signal ground.

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