Cross-die communication apparatus

By setting up cross-die communication modules and link interfaces between dies, and implementing communication based on a non-high-speed transmission protocol, the problem of complex and unstable communication between dies is solved, and stable and reliable data transmission is achieved.

CN121722709BActive Publication Date: 2026-05-08沐曦集成电路(南京)有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
沐曦集成电路(南京)有限公司
Filing Date
2026-02-13
Publication Date
2026-05-08

AI Technical Summary

Technical Problem

In existing technologies, communication between dies is complex and unstable. Especially in non-high-speed data transmission scenarios, the link training process is complex and prone to errors, affecting chip functionality.

Method used

By employing a cross-die communication module and link interface based on a non-high-speed transmission protocol, an interconnection network is generated through link training, enabling the transmission of both non-high-speed and high-speed data. This simplifies the link training process and improves communication stability.

Benefits of technology

It reduces the complexity of cross-die communication and improves the stability and reliability of communication, making it particularly suitable for both low-speed and high-speed data transmission scenarios.

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Abstract

The present application relates to the technical field of integrated circuit chip design, and particularly relates to a cross-Die communication device, which comprises a first communication link and a second communication link; the first communication link comprises a first cross-Die communication module arranged in a first Die and a second cross-Die communication module arranged in a second Die, and the first cross-Die communication module and the second cross-Die communication module are interconnected based on a non-high-speed transmission protocol; the second communication link comprises a first link interface arranged in the first Die and a second link interface arranged in the second Die, and the first link interface and the second link interface are connected through an interconnection network generated by link training; the first communication link is used for transmitting non-high-speed data between the first Die and the second Die; and the second communication link is used for transmitting high-speed data between the first Die and the second Die. The present application reduces the complexity of cross-Die communication and improves the stability of cross-Die communication.
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Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip design technology, and more particularly to a cross-die communication device. Background Technology

[0002] In integrated circuit chip design, multiple dies (bare dies) packaged together can process tasks in parallel, thereby improving computing performance. Each die can handle different computational loads, especially for scenarios requiring high-concurrency computing such as machine learning and graphics processing. Dies typically communicate with each other using dedicated interconnect networks (such as Mesh, Ring Topologies, and NVLink). These dedicated interconnect networks require link training before connection; communication is only possible after successful link training. Link training involves initializing the interface (PHY), a complex configuration process that can lead to link failures. Furthermore, data errors can occur during use, causing chip malfunctions. Moreover, link training is particularly complex for cross-die access scenarios, especially for non-high-speed data transmission (such as register access). Therefore, providing a simple, fast, stable, and reliable cross-die communication device is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a cross-die communication device that reduces the complexity of cross-die communication and improves its stability.

[0004] According to a first aspect of the present invention, a cross-die communication device is provided, comprising a first communication link and a second communication link for implementing communication between a first die and a second die;

[0005] The first communication link includes a first cross-die communication module disposed in the first die and a second cross-die communication module disposed in the second die, wherein the first cross-die communication module and the second cross-die communication module are interconnected based on a non-high-speed transmission protocol.

[0006] The second communication link includes a first link interface disposed in the first die and a second link interface disposed in the second die, wherein the first link interface and the second link interface are connected through an interconnection network generated by link training.

[0007] The first communication link is used to transmit non-high-speed data between the first die and the second die, wherein the non-high-speed data is data with a corresponding clock rate of less than or equal to 1 GHz;

[0008] The second communication link is used to transmit high-speed data between the first die and the second die, wherein the high-speed data is data with a corresponding clock rate greater than 1 GHz.

[0009] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the cross-die communication device provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value, possessing at least the following beneficial effects:

[0010] This invention achieves cross-die communication by setting up a cross-die communication module in the die, eliminating the need for complex link training, reducing the complexity of cross-die communication, and improving the stability of cross-die communication. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a cross-die communication device provided in an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] This invention provides a cross-die communication device, such as... Figure 1As shown, the system includes a first communication link and a second communication link for enabling communication between a first die and a second die. The first communication link includes a first cross-die communication module disposed in the first die and a second cross-die communication module disposed in the second die, which are interconnected based on a non-high-speed transmission protocol. The second communication link includes a first link interface (Link PHY) disposed in the first die and a second link interface disposed in the second die, which are connected through an interconnection network generated by link training. The interconnection network generated by link training includes Mesh, Ring Topologies, Nvlink, etc. The first communication link is used to transmit non-high-speed data between the first die and the second die, wherein the non-high-speed data is data with a clock rate of less than or equal to 1 GHz. The second communication link is used to transmit high-speed data between the first die and the second die, wherein the high-speed data is data with a clock rate greater than 1 GHz.

[0015] The device further includes a first request processing module disposed in a first die and a second request processing module disposed in a second die; the first request processing module communicates with a first cross-die communication module based on a preset die intra-die data transmission protocol, and the second request processing module and the second cross-die communication module communicate with each other based on a preset die intra-die data transmission protocol; the first cross-die communication module and the second cross-die communication module communicate with each other based on a non-high-speed transmission protocol.

[0016] It should be noted that the first communication link is particularly suitable for non-high-speed data transmission scenarios, while the second communication link is also suitable for high-speed data transmission scenarios. The first link interface is interconnected with the first request processing module based on the preset intra-die data transmission protocol, and the second link interface is interconnected with the second request processing module based on the preset intra-die data transmission protocol. In the device, high-speed data between the first and second dies is transmitted using the first and second link interfaces, while non-high-speed data between the first and second dies is transmitted using the first and second cross-die communication modules. This structure can satisfy both the cross-die communication requirements for non-high-speed data (with data frequencies reaching up to 200Mbps or even higher) and the cross-die communication requirements for high-speed data.

[0017] As an example, the first request processing module and the second request processing module can specifically be configured as a register network. The preset intra-die data transmission protocol is AXI (Advanced eXtensible Interface) bus protocol, AHB (Advanced High-performance Bus) bus protocol, or RIB (Register Interface Bus) bus protocol, etc.

[0018] As an example, the non-high-speed transmission protocol is the default SPI (Serial Peripheral Interface) protocol.

[0019] The first request processing module is used to send an access request to the first cross-die communication module based on a preset intra-die data transmission protocol, wherein the access request follows the preset intra-die data transmission protocol.

[0020] The first cross-die communication module is used to convert the received access request into a request data packet, which follows a non-high-speed transmission protocol and is sent to the second cross-die communication module based on the non-high-speed transmission protocol.

[0021] The second cross-die communication module is used to convert the received request data packet into an access request and transmit it to the second request processing module based on a preset intra-die data transmission protocol.

[0022] The second request processing module is used to process the received access request, generate response information, and transmit it to the second cross-die communication module based on the preset intra-die data transmission protocol.

[0023] The second cross-die communication module is used to convert the response information into response data packets and transmit them to the first cross-die communication module based on a non-high-speed transmission protocol.

[0024] The first cross-die communication module is used to convert the response data packet into response information and send it to the first request processing module based on a preset intra-die data transmission protocol.

[0025] As one embodiment, the first cross-die communication module includes a first data packet generation module, a first sending module, and a first clock sending pin. Figure 1 The first request to send pin is represented as M2S_CLK. Figure 1 The first response transmission pin is represented as M2S_REQ. Figure 1 (represented as M2S_RESP), first receiving module, first unpacking module, first clock receiving pin ( Figure 1 The first request receive pin is represented as S2M_CLK. Figure 1 The first response receive pin (represented as S2M_REQ) and the second response receive pin ( Figure 1 The first sending module is connected to the first data packet generation module, the first clock sending pin, the first request sending pin, and the first response sending pin, respectively. The first receiving module is connected to the first unpacking module, the first clock receiving pin, the first request receiving pin, and the first response receiving pin, respectively.

[0026] The second cross-die communication module includes a second data packet generation module, a second sending module, and a second clock sending pin. Figure 1 The second request transmission pin is represented as M2S_CLK. Figure 1 The second response transmission pin is represented as M2S_REQ. Figure 1 (represented as M2S_RESP), second receiving module, second unpacking module, second clock receiving pin ( Figure 1 The second request receive pin is represented as S2M_CLK. Figure 1 The second response receive pin (represented as S2M_REQ) is shown in the middle. Figure 1 The second sending module is connected to the second data packet generation module, the second clock sending pin, the second request sending pin, and the second response sending pin, respectively. The second receiving module is connected to the second unpacking module, the second clock receiving pin, the second request receiving pin, and the second response receiving pin, respectively.

[0027] The first clock transmit pin is connected to the second clock receive pin, the first request transmit pin is connected to the second request receive pin, the first response transmit pin is connected to the second response receive pin, the first clock receive pin is connected to the second clock transmit pin, the first request receive pin is connected to the second request transmit pin, and the first response receive pin is connected to the second response transmit pin. These pins can be configured as general purpose input / output (GPIO) interfaces.

[0028] It should be noted that the first die and the second die can achieve cross-die communication through the above structure. The first die and the second die can both be set as master dies; the first die and the second die can both be set as slave dies; the first die can be set as master dies and the second die as slave dies; or the first die can be set as slave dies and the second die as master dies.

[0029] In one embodiment, the first die can act as a sender, and the second die as a receiver. The access request is transmitted through a data path composed of a first request processing module, a first data packet generation module, a first sending module, a first clock sending pin, a first request sending pin, a second clock receiving pin, a second request receiving pin, a second receiving module, a second unpacking module, and the second request processing module. It should be noted that the first clock sending pin and the second clock receiving pin are used to transmit clock signals, and the request data packet is transmitted between the first request sending pin and the second request receiving pin. After processing the access request, the second request processing module generates response information, which is transmitted through the data path composed of the second request processing module, the second data packet generation module, the second sending module, the second clock sending pin, the second response sending pin, the first clock receiving pin, the first response receiving pin, the first receiving module, the first unpacking module, and the first request processing module. It should be noted that the second clock sending pin and the first clock receiving pin are used to transmit clock signals, and the response data packet is transmitted between the first response sending pin and the second response receiving pin.

[0030] It is understandable that the second die can also be used as the sending end, and the first die as the receiving end. The access request is transmitted through a data path composed of the second request processing module, the second data packet generation module, the second sending module, the second clock sending pin, the second request sending pin, the first clock receiving pin, the first request receiving pin, the first receiving module, the first unpacking module, and the first request processing module. It should be noted that the second clock sending pin and the first clock receiving pin are used to transmit clock signals, and the second request sending pin and the first request receiving pin are used to transmit request data packets. After processing the access request, the first request processing module generates response information, which is transmitted through a data path composed of the first request processing module, the first data packet generation module, the first sending module, the first clock sending pin, the first response sending pin, the second clock receiving pin, the second response receiving pin, the second receiving module, the second unpacking module, and the second request processing module. The first clock sending pin and the second clock receiving pin are used to transmit clock signals, and the second response sending pin and the first response receiving pin are used to transmit response data packets.

[0031] The following explanation uses the example of the first die acting as the sender and the second die as the receiver. In one embodiment, the first data packet generation module obtains a start identifier, valid data packet transmission bits, source die identifier, destination die identifier, read / write request identifier, request data, and end identifier based on the access request, and concatenates them to generate a request data packet, which is then sent to the first sending module. The start identifier is used to set a start signal. Valid data transmission bits represent the number of valid data identifier bits in the information corresponding to the request data packet. The source die identifier, destination die identifier, read / write request identifier, and request data are all valid identifier bits. The source die identifier, destination die identifier, read / write request identifier, and request data can all be obtained from the access request. The source die identifier obtained from the access request refers to the die identifier that generated the access request, and the destination die identifier obtained from the access request refers to the die identifier that needs to execute the access request. The end identifier is used to set an end signal. If the read / write request identifier is a read identifier, the request data is information such as the read address and ground length that conform to a preset data transmission protocol within the die. If the read / write request is identified as a write identifier, the requested data will contain information such as the write address, write length, and write content that conform to the preset Die data transmission protocol.

[0032] To further improve the reliability of cross-die communication, as one embodiment, the first sending module, upon receiving a request data packet, generates a parity check code based on the data in the request data packet and adds it between the request data and the end identifier of the request data packet. Based on a preset edge of the clock signal transmitted via the first clock sending pin, it transmits the information in the request data packet to the second receiving module according to the transmission timing. The preset edge can specifically be set to a rising edge or a falling edge. Upon receiving the start identifier of the request data packet, the second receiving module generates a parity check code based on the data in the valid transmission bits of the request data packet and compares it with the parity check code in the request data packet. If they match, the receiving module sends the request data packet to the second unpacking module upon receiving the end identifier of the request data packet. If they do not match, the receiving module discards the currently transmitted request data packet and generates a prompt message. The second unpacking module parses the received request data packet, generates request information, and sends it to the second request processing module.

[0033] In one embodiment, the second data packet generation module is used to obtain the start identifier, data packet valid transmission bits, source die identifier, destination die identifier, response identifier, response data, and end identifier based on the response information, and concatenate them to generate a response data packet, which is then sent to the second sending module. The source die identifier obtained based on the response information refers to the die identifier that generates the response information, and the destination die identifier obtained based on the response information refers to the die identifier that receives the response information.

[0034] To further improve the reliability of cross-die communication, as one embodiment, the second sending module, upon receiving a response data packet, generates a parity check code based on the data in the response data packet and adds it between the response data and the end identifier of the response data packet. Based on a preset edge change of the clock signal transmitted via the second clock sending pin, it transmits the information in the response data packet to the first receiving module according to the transmission timing sequence via the second request sending pin. Upon receiving the start identifier of the response data packet, the first receiving module generates a parity check code based on the data in the valid transmission bits of the response data packet and compares it with the parity check code in the response data packet. If they match, the first receiving module sends the response data packet to the first unpacking module upon receiving the end identifier of the response data packet. If they do not match, the currently transmitted response data packet is discarded, and a prompt message is generated. The first unpacking module parses the received response data packet, generates response information, and sends it to the first request processing module. By adding a parity check code to the data packet, the reliability of data transmission is increased, thereby improving the reliability of cross-die communication.

[0035] This invention achieves cross-die communication by setting up a cross-die communication module in the die, eliminating the need for complex link training, reducing the complexity of cross-die communication, and improving the stability of cross-die communication.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A cross-die communication device, characterized in that, Includes a first communication link and a second communication link for enabling communication between the first die and the second die; The first communication link includes a first cross-die communication module disposed in the first die and a second cross-die communication module disposed in the second die, wherein the first cross-die communication module and the second cross-die communication module are interconnected based on a non-high-speed transmission protocol. The second communication link includes a first link interface disposed in the first die and a second link interface disposed in the second die, wherein the first link interface and the second link interface are connected through an interconnection network generated by link training. The first communication link is used to transmit non-high-speed data between the first die and the second die, wherein the non-high-speed data is data with a corresponding clock rate of less than or equal to 1 GHz; The second communication link is used to transmit high-speed data between the first die and the second die, wherein the high-speed data is data with a corresponding clock rate greater than 1 GHz; The first cross-die communication module includes a first data packet generation module, a first sending module, a first clock sending pin, a first request sending pin, and a first response sending pin. The first sending module is connected to the first data packet generation module, the first clock sending pin, the first request sending pin, and the first response sending pin, respectively. The second cross-die communication module includes a second receiving module, a second unpacking module, a second clock receiving pin, a second request receiving pin, and a second response receiving pin. The second receiving module is connected to the second unpacking module, the second clock receiving pin, the second request receiving pin, and the second response receiving pin, respectively. The first clock transmit pin is connected to the second clock receive pin, the first request transmit pin is connected to the second request receive pin, and the first response transmit pin is connected to the second response receive pin. The first cross-die communication module further includes a first receiving module, a first unpacking module, a first clock receiving pin, a first request receiving pin, and a first response receiving pin. The first receiving module is connected to the first unpacking module, the first clock receiving pin, the first request receiving pin, and the first response receiving pin, respectively. The second cross-die communication module further includes a second data packet generation module, a second sending module, a second clock sending pin, a second request sending pin, and a second response sending pin. The second sending module is connected to the second data packet generation module, the second clock sending pin, the second request sending pin, and the second response sending pin, respectively. The first clock receive pin is connected to the second clock transmit pin, the first request receive pin is connected to the second request transmit pin, and the first response receive pin is connected to the second response transmit pin.

2. The apparatus according to claim 1, characterized in that, The device further includes a first request processing module disposed in the first die and a second request processing module disposed in the second die; The first request processing module is used to send an access request to the first cross-die communication module based on a preset intra-die data transmission protocol. The first cross-die communication module is used to convert the received access request into a request data packet and send it to the second cross-die communication module based on a non-high-speed transmission protocol; The second cross-die communication module is used to convert the received request data packet into an access request and transmit it to the second request processing module based on a preset intra-die data transmission protocol; The second request processing module is used to process the received access request, generate response information, and transmit it to the second cross-die communication module based on the preset intra-die data transmission protocol. The second cross-die communication module is used to convert the response information into response data packets and transmit them to the first cross-die communication module based on a non-high-speed transmission protocol; The first cross-die communication module is used to convert the response data packet into response information and send it to the first request processing module based on a preset intra-die data transmission protocol.

3. The apparatus according to claim 1, characterized in that, The first data packet generation module is used to obtain the start identifier, data packet valid transmission bits, source die identifier, destination die identifier, read / write request identifier, request data, and end identifier based on the access request, and then concatenate them to generate a request data packet and send it to the first sending module. The first sending module is used to generate a parity verification code based on the data in the request data packet after receiving the request data packet, and add it between the request data and the end identifier of the request data packet. Based on the preset change edge of the clock signal transmitted by the first clock sending pin, the first request sending pin transmits the information in the request data packet to the second receiving module according to the transmission timing.

4. The apparatus according to claim 3, characterized in that, After receiving the start identifier of the request data packet, the second receiving module generates a parity verification code based on the data in the valid transmission bits of the request data packet and compares it with the parity verification code in the request data packet. If they are the same, the request data packet is sent to the second unpacking module after receiving the end identifier of the request data packet. If they are different, the currently transmitted request data packet is discarded and a prompt message is generated. The second unpacking module is used to parse the received request data packet, generate request information, and send it to the second request processing module.

5. The apparatus according to claim 1, characterized in that, The second data packet generation module is used to obtain the start identifier, data packet valid transmission bits, source die identifier, destination die identifier, response identifier, response data, and end identifier based on the response information, and then concatenate them to generate a response data packet, which is then sent to the second sending module. The second sending module is used to generate a parity verification code based on the data in the response data packet after receiving the response data packet, and add it between the response data and the end identifier of the response data packet. Based on the preset change edge of the clock signal transmitted by the second clock sending pin, the module transmits the information in the response data packet to the first receiving module through the second request sending pin in accordance with the transmission timing.

6. The apparatus according to claim 3, characterized in that, After receiving the start flag of the response data packet, the first receiving module generates a parity check code based on the data in the valid transmission bits of the response data packet and compares it with the parity check code in the response data packet. If they are the same, the first receiving module sends the response data packet to the first unpacking module after receiving the end flag of the response data packet. If they are different, the first receiving module discards the currently transmitted response data packet and generates a prompt message. The first unpacking module parses the received response data packet, generates response information, and sends it to the first request processing module.

7. The apparatus according to claim 2, characterized in that, Both the first request processing module and the second request processing module are register networks. The preset intra-die data transmission protocol includes the AXI bus protocol, the AHB bus protocol, and the RIB bus protocol. The non-high-speed transmission protocol is the preset SPI protocol.

8. The apparatus according to claim 1, characterized in that, The interconnected networks include Mesh, Ring Topologies, and Nvlink.

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