Memory, access control method thereof and electronic equipment

Abstract

The invention discloses a memory, an access control method thereof and electronic equipment. The memory comprises a plurality of memory arrays, a plurality of first word line gating sub-circuits and a plurality of first word line gating control lines, wherein the memory arrays are distributed on a substrate in the direction parallel to the substrate; the storage array comprises multiple layers of storage unit arrays and multiple common word lines, the storage unit arrays comprise multiple word lines extending in parallel, and the common word lines are connected with at least one word line; the common word line is connected with a word line driving end through a first word line gating sub-circuit; the same word line driving end is respectively connected with at least two common word lines of different storage arrays, and the first word line gating sub-circuit is configured to electrically connect or disconnect the word line driving end and the common word lines under the control of a first word line gating control line; wherein different common word lines of the same storage array are connected to different word line driving ends. According to the scheme provided by the embodiment of the invention, different memory arrays can share the word line driver, and the number of hybrid bonding pads can be reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a memory and its access control method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a memory and its access control method, as well as an electronic device, which can reduce the number of bonding pads.

[0006] This application provides a memory, comprising: a plurality of memory arrays distributed on a substrate along a direction parallel to the substrate, a plurality of first word line gating sub-circuits, and a plurality of first word line gating control lines; the memory arrays include a multilayer memory cell array stacked along a direction perpendicular to the substrate and a plurality of common word lines, the memory cell arrays including a plurality of memory cells and a plurality of word lines extending along a direction parallel to the substrate, the common word lines connecting to at least one word line; the common word lines are connected to a word line driver terminal through the first word line gating sub-circuits; the same word line driver terminal is connected to at least two of the common word lines through different first word line gating sub-circuits, and the common word lines connected to the same word line driver terminal belong to different memory arrays; the first word line gating sub-circuits are also connected to the first word line gating control lines; the first word line gating sub-circuits are configured to electrically connect or disconnect the word line driver terminal and the common word lines under the control of the first word line gating control lines; wherein, different common word lines of the same memory array are connected to different word line driver terminals.

[0007] In some embodiments, the same word line driver terminal is connected to two common word lines through different first word line gating sub-circuits, and the two common word lines connected to the same word line driver terminal belong to two adjacent memory arrays.

[0008] In some embodiments, the first word line gating sub-circuit connected to the common word line of the same memory cell array is connected to the same first word line gating control line, and the first word line gating sub-circuit connected to the common word line of different memory cell arrays is connected to different first word line gating control lines.

[0009] In some embodiments, the memory further includes: a plurality of second word line gating sub-circuits and a plurality of second word line gating control lines, wherein the common word line is also connected to the second word line gating sub-circuits, the second word line gating sub-circuits are also connected to a first preset voltage terminal and the second word line gating control lines, and the second word line gating sub-circuit is configured to electrically connect or disconnect the common word line and the first preset voltage terminal under the control of the second word line gating control lines.

[0010] In some embodiments, the second word line gating sub-circuit connected to the common word line of the same memory cell array is connected to the same second word line gating control line, and the second word line gating sub-circuit connected to the common word line of different memory cell arrays is connected to different second word line gating control lines.

[0011] In some embodiments, the signals of the first word line gating control line connected to the first word line gating sub-circuit connected to the same common word line and the second word line gating control line connected to the second word line gating sub-circuit connected to the same common word line are not simultaneously valid level signals; the signals of the two first word line gating control lines connected to the two first word line gating sub-circuits connected to the same word line driving terminal are not simultaneously valid level signals. When the signal of the first word line strobe control line connected to one of the memory cell arrays in the same memory array is an active level signal, the signals of the first word line strobe control lines connected to the other memory cell arrays in the same memory array are inactive level signals, and the signals of the first word line strobe control lines connected to the other memory arrays connected to the same word line driver terminal are also inactive level signals.

[0012] In some embodiments, the memory further includes: a plurality of first-line gating sub-circuits and a plurality of first-line gating control lines; The memory array further includes: a plurality of bit lines extending perpendicular to the substrate along a first direction parallel to the substrate and a second direction parallel to the substrate, and a plurality of common bit lines; the common bit lines connect to at least one bit line, and the common bit lines and the bit lines are connected through a first bit line gating sub-circuit; the first bit line gating sub-circuit is also connected to a first bit line gating control line; the first bit line gating sub-circuit is configured to electrically connect or disconnect the common bit lines and the bit lines under the control of the first bit line gating control line.

[0013] In some embodiments, the memory further includes: a plurality of second bit line gating sub-circuits and a plurality of second bit line gating control lines; The bit line is also connected to the second bit line gating sub-circuit, which is further connected to the second preset voltage terminal and the second bit line gating control line. The second bit line gating sub-circuit is configured to electrically connect or disconnect the bit line and the second preset voltage terminal under the control of the second bit line gating control line.

[0014] In some embodiments, the memory cell array includes a plurality of memory cells distributed along a first direction and a second direction parallel to the substrate, and the word line extends along the first direction; the word line connects a row of memory cells distributed along the first direction; Each column of bit lines distributed along the second direction corresponds to L common bit lines. Among the multiple bit lines in the same column, each L consecutively distributed bit lines are divided into a bit line group. The multiple bit lines in the same bit line group are respectively connected to different common bit lines in the L common bit lines corresponding to the column bit lines. The multiple first bit line gating sub-circuits connected to the multiple bit lines in the same bit line group are connected to the same first bit line gating control line. The multiple second bit line gating sub-circuits connected to the multiple bit lines in the same bit line group are connected to the same second bit line gating control line.

[0015] In some embodiments, the signals of the first bit line gating control line connected to the first bit line gating sub-circuit and the second bit line gating control line connected to the second bit line gating sub-circuit are not simultaneously valid level signals; When the first line gating control line connected to multiple first line gating sub-circuits of a bit line group in the same memory array has an active level signal, the first line gating control line connected to the other bit line groups of the memory array has an inactive level signal.

[0016] This disclosure provides an access control method applied to the aforementioned memory, comprising: During the data access phase, a valid level signal is applied to the first word line gating control line connected to the common word line to which the target memory cell is connected, an invalid level signal is applied to the first word line gating control line connected to the other memory cell arrays of the memory array to which the target memory cell is located, and an invalid level signal is applied to the first word line gating control line connected to all the first word line gating sub-circuits connected to the other memory arrays connected to the same word line driver terminal as the memory array to which the target memory cell is located.

[0017] In some embodiments, the method further includes loading an invalid level signal onto the second word line gating control line connected to the common word line connected to the target memory cell via the second word line gating sub-circuit; loading an valid level signal onto the second word line gating control line connected to other memory cell arrays in the memory array where the target memory cell is located; and loading valid level signals onto the second word line gating control lines connected to all second word line gating sub-circuits connected to other memory arrays connected to the same word line driver as the memory array where the target memory cell is located.

[0018] In some embodiments, the method further includes: A valid level signal is applied to the first bit line selection control line connected to the first bit line selection subcircuit of the bit line group to which the bit line connected to the target memory cell belongs; an invalid level signal is applied to the second bit line selection control line connected to the second bit line selection subcircuit of the bit line group to which the target memory cell belongs; an invalid level signal is applied to the first bit line selection control line connected to the first bit line selection subcircuit of the other bit line groups of the memory array where the target memory cell is located; and a valid level signal is applied to the second bit line selection control line connected to the second bit line selection subcircuit of the other bit line groups.

[0019] This disclosure provides an electronic device including the memory described in any of the above embodiments.

[0020] In some embodiments, the electronic device further includes a control circuit configured to access the memory using the access control method described in any of the above embodiments.

[0021] This application includes a memory, comprising: a plurality of memory arrays distributed on a substrate along a direction parallel to the substrate, a plurality of first word line gating sub-circuits, and a plurality of first word line gating control lines; the memory arrays include a multilayer memory cell array stacked along a direction perpendicular to the substrate and a plurality of common word lines, the memory cell arrays including a plurality of memory cells and a plurality of word lines extending along a direction parallel to the substrate, the common word lines connecting to at least one word line; the common word lines are connected to a word line driver terminal through the first word line gating sub-circuits; the same word line driver terminal is connected to at least two of the common word lines through different first word line gating sub-circuits, and the common word lines connected to the same word line driver terminal belong to different memory arrays; the first word line gating sub-circuits are also connected to the first word line gating control lines; the first word line gating sub-circuits are configured to electrically connect or disconnect the word line driver terminal and the common word lines under the control of the first word line gating control lines; wherein, different common word lines of the same memory array are connected to different word line driver terminals. The solution provided in this disclosure allows different memory arrays to share word line drivers, which can reduce the number of hybrid bonding pads used to connect multiple memory arrays and word line drivers, reduce the area occupied by hybrid bonding pads, shrink device area, and increase device density.

[0022] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0025] Figure 1 Schematic diagrams of the memory structure provided for some embodiments; Figure 2 for Figure 1 A partial equivalent circuit diagram of the provided word line gating circuit; Figure 3 A schematic diagram of common bit lines and bit line connections provided for some embodiments; Figure 4 Equivalent circuit diagrams of bit line gating circuits provided for other embodiments; Figure 5 Block diagrams of electronic devices provided for some embodiments. Detailed Implementation

[0026] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0027] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0028] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0029] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0030] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0031] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0032] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0033] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0034] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0035] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0036] Figure 1 This is a top view schematic diagram of a memory provided for an embodiment of this disclosure. Figure 2 Equivalent circuit diagrams of some sub-circuits in the word line gating circuit 100 provided in some embodiments.

[0037] like Figure 1 and Figure 2 As shown, this disclosure provides a memory that may include: a plurality of memory arrays (such as...) distributed along a direction parallel to the substrate. Figure 1 The first storage array MATk and the second storage array MATk+1 shown are shown. Figure 1The present invention discloses only two memory arrays, but is not limited to these; there may be more memory arrays. A word line gating circuit 100 is also included. The word line gating circuit 100 may include multiple first word line gating sub-circuits 21 and multiple first word line gating control lines HB_MAT_S. The memory array may include a multilayer memory cell array stacked perpendicular to the substrate direction and multiple common word lines CWL. The memory cell array may include multiple memory cells and multiple word lines WL extending parallel to the substrate direction. The common word line CWL connects to at least one word line WL. The common word line CWL is connected to a word line driver terminal HB_SWD through a first word line gating sub-circuit 21. The word line driver terminal HB_SWD can be connected to an external word line driver to load the signal generated by the word line driver onto the common word line CWL. The same word line driver terminal HB_SWD can be connected to at least two common word lines CWL (each common word line CWL is connected to one first word line select sub-circuit 21) through different first word line select sub-circuits 21, and the common word lines CWL connected to the same word line driver terminal HB_SWD belong to different memory arrays. The first word line select sub-circuit 21 is also connected to a first word line select control line HB_MAT_S; the first word line select sub-circuit 21 is configured to electrically connect or disconnect the word line driver terminal HB_SWD and the common word lines CWL under the control of the first word line select control line HB_MAT_S; wherein, different common word lines CWL of the same memory array are connected to different word line driver terminals HB_SWD.

[0038] The solution provided in this disclosure allows different memory arrays to share word line drivers, which can reduce the number of hybrid bonding pads used to connect multiple memory arrays and word line drivers, reduce the area occupied by hybrid bonding pads, shrink device area, and increase device density.

[0039] In some embodiments, the memory cell may be a 1T1C structure memory cell including a transistor and a capacitor. However, the embodiments disclosed herein are not limited to this, and may be memory cells with other structures.

[0040] In some embodiments, the memory cell array may include a plurality of memory cells distributed along a first direction X parallel to the substrate and a second direction Y parallel to the substrate. A word line WL may extend along the first direction X, and one word line WL connects a row of memory cells distributed along the first direction X. The first direction X and the second direction Y intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0041] In some embodiments, the memory array may further include: multiple bit lines BL extending perpendicular to the substrate direction and multiple common bit lines CBL distributed along a first direction X and a second direction Y; each of the common bit lines CBL is connected to at least one bit line BL.

[0042] In some embodiments, the same word line driver terminal HB_SWD can be connected to two common word lines CWL through different first word line gating sub-circuits 21, and the two common word lines CWL connected to the same word line driver terminal HB_SWD belong to two adjacent memory arrays. The two adjacent memory arrays can be, for example, two memory arrays adjacent along the first direction X. For example, such as... Figure 1 As shown, the first memory array MATk and the second memory array MATk+1 are two adjacent memory arrays. The first common word line CWL1_k of the first memory array MATk is connected to the first word line driver HB_SWD1 through a first word line selector circuit 21. The first common word line CWL1_k+1 of the second memory array MATk+1 is connected to the first word line driver HB_SWD1 through a first word line selector circuit 21. The second common word line CWL2_k of the first memory array MATk is connected to the second common word line driver HB_SWD1 through a first word line selector circuit 21. The second word line driver terminal HB_SWD2 is connected to the second word line driver terminal HB_SWD2 via a first word line gating sub-circuit 21; the third common word line CWL3_k of the first memory array MATk is connected to the third word line driver terminal HB_SWD3 via a first word line gating sub-circuit 21; the third common word line CWL3_k+1 of the second memory array MATk+1 is connected to the third word line driver terminal HB_SWD3 via a first word line gating sub-circuit 21; and so on.

[0043] In some embodiments, the first word line gating sub-circuit 21 connected to the common word line CWL of the same memory cell array is connected to the same first word line gating control line HB_MAT_S, and the first word line gating sub-circuit 21 connected to the common word line of different memory cell arrays is connected to different first word line gating control lines HB_MAT_S. Figure 2 The diagram shows the first word line gating sub-circuit 21 and the first word line gating control line HB_MAT_S connected to two memory cell arrays belonging to different memory arrays. Multiple first word line gating sub-circuits 21 connected to one memory cell array are all connected to the first first word line gating control line HB_MAT_S1, while multiple first word line gating sub-circuits 21 connected to the other memory cell array are connected to the second first word line gating control line HB_MAT_S2.

[0044] In some embodiments, the word line gating circuit may further include: a plurality of second word line gating sub-circuits 22 and a plurality of second word line gating control lines HB_MAT_Sb. The common word line CWL is also connected to the second word line gating sub-circuit 22. The second word line gating sub-circuit 22 is also connected to a first preset voltage terminal VSS and the second word line gating control line HB_MAT_Sb. The second word line gating sub-circuit 22 is configured to electrically connect or disconnect the common word line CWL and the first preset voltage terminal VSS under the control of the second word line gating control line HB_MAT_Sb. In some embodiments, the voltage of the first preset voltage terminal VSS may be a low-level voltage, such as zero voltage or a negative voltage. The solution provided by the embodiments of this disclosure can prevent the common word line CWL from being in a floating state when the first word line gating sub-circuit 21 connected to the common word line CWL is disconnected.

[0045] In some embodiments, the second word line gating sub-circuit 22 connected to the common word line CWL of the same memory cell array is connected to the same second word line gating control line HB_MAT_Sb, and the second word line gating sub-circuit 22 connected to the common word line CWL of different memory cell arrays is connected to different second word line gating control lines HB_MAT_Sb. For example... Figure 2 As shown, multiple second word line gating sub-circuits 22 connected to one memory cell array are all connected to the first second word line gating control line HB_MAT_Sb1, and multiple second word line gating sub-circuits 22 connected to another memory cell array are connected to the second second word line gating control line HB_MAT_Sb2.

[0046] In some embodiments, a common word line CWL can be connected to W word lines WL that are continuously distributed along the second direction Y. W can be, for example, 2, 3, 4, etc. Figure 1 The diagram shows a common word line CWL connected to four consecutively distributed word lines WL. However, this disclosure is not limited to this; a common word line CWL can be connected to multiple word lines WL spaced apart along the second direction Y.

[0047] In some embodiments, the common word line CWL can be led out through stepped electrodes and connected to the first word line gating sub-circuit 21 and the second word line gating sub-circuit 22.

[0048] In some embodiments, each column of bit lines BL distributed along the second direction Y can correspond to L common bit lines CBL. Among the multiple bit lines BL in the same column, each L consecutively distributed bit lines BL is divided into a bit line group. Multiple bit lines BL in the same bit line group are respectively connected to different common bit lines CBL among the L common bit lines CBL corresponding to that column of bit lines BL. L can be 2, 3, 4, etc. For example, ... Figure 3As shown, one column of bit lines BL can correspond to four common bit lines CBL. That is, four common bit lines CBL can be set in the area where a column of memory cells is located. Every four consecutively distributed bit lines BL are divided into a bit line group. The four bit lines BL in the same bit line group are connected to the first common bit line CBL1, the second common bit line CBL2, the third common bit line CBL3, and the fourth common bit line CBL4, respectively. The bit lines BL in adjacent bit line groups connected to the same common bit line CBL are separated by three bit lines BL. Figure 3 The connection method shown is for illustrative purposes only; other connection methods may be used.

[0049] In some embodiments, L can be equal to W. However, it is not limited to this, and L may not be equal to W. For example, two WLs distributed at intervals along the second direction Y can be connected to the same CWL, and every four consecutive BLs can be connected to four CBLs, and so on.

[0050] In some embodiments, the word lines WL connected to the memory cells of the same layer that are connected to the bit lines BL of the same bit line group are connected to the same common word line CWL. For example... Figure 3 As shown, the memory cells in the first row and first column of the bit lines BL1 to BL4 (connected to the first word line WL to the fourth word line WL) are connected to the same common word line CWL.

[0051] In other embodiments, such as Figure 4 As shown, a column of bit lines BL can correspond to two common bit lines CBL. That is, two common bit lines CBL can be set in the area where a column of memory cells is located. Every two consecutively distributed bit lines BL are divided into a bit line group. The two bit lines BL in the same bit line group are connected to the first common bit line CBL1 and the second common bit line CBL2, respectively.

[0052] In some embodiments, the memory may further include: a plurality of first bit line gating sub-circuits 31 and a plurality of first bit line gating control lines SL; and the common bit line CBL and the bit line BL are connected through the first bit line gating sub-circuit 31; the first bit line gating sub-circuit 31 is also connected to the first bit line gating control line SL; the first bit line gating sub-circuit 31 is configured to electrically connect or disconnect the common bit line CBL and the bit line BL under the control of the first bit line gating control line SL. The solution provided in this embodiment allows only the BL to be operated to be connected to the CBL, while the remaining BLs are disconnected, thereby reducing the capacitive reactance of the CBL, reducing power consumption, and increasing operating speed. Furthermore, when the capacitive reactance of the CBL is smaller, the voltage change ΔVBL on the BL is larger after charge sharing between the BL and the memory cell. Therefore, the CBL can connect to more bit lines, and the corresponding memory can use fewer CBLs. Also, since the CBL connects to the sensing amplifier, the number of CBLs is reduced, which correspondingly reduces the number of sensing amplifiers connected to the CBLs; thus, one CBL can connect to more BLs, reducing the number of CBLs and the number of sensing amplifiers.

[0053] In some embodiments, multiple first-line gating sub-circuits 31 connected by multiple bit lines BL in the same bit line group can be connected to the same first-line gating control line SL, and multiple first-line gating sub-circuits 31 connected by multiple bit lines BL in different bit line groups can be connected to different first-line gating control lines SL. For example, the first bit line BL1 and the second bit line BL2 form a bit line group, and the first-line gating sub-circuit 31 connected by the bit lines BL of this bit line group is connected to the first first-line gating control line SL1; the third bit line BL3 and the fourth bit line BL4 form a bit line group, and the first-line gating sub-circuit 31 connected by the bit lines BL of this bit line group is connected to the second first-line gating control line SL2; the fifth bit line BL5 and the sixth bit line BL6 form a bit line group, and the first-line gating sub-circuit 31 connected by the bit lines BL of this bit line group is connected to the third first-line gating control line SL3.

[0054] In some embodiments, the memory may further include: a plurality of second bit line gating sub-circuits 32 and a plurality of second bit line gating control lines PreC; The bit line BL is also connected to the second bit line gating sub-circuit 32, which is further connected to the second preset voltage terminal Vpre and the second bit line gating control line PreC. The second bit line gating sub-circuit 32 is configured to electrically connect or disconnect the bit line BL and the second preset voltage terminal Vpre under the control of the second bit line gating control line PreC. The solution provided in this embodiment, by setting the second bit line gating sub-circuit 32, can prevent non-target bit lines from floating when the first bit line gating sub-circuit 31 is turned off, and facilitates connecting non-target bit lines to the second preset voltage terminal Vpre, avoiding interference to the target bit line caused by voltage changes in the non-target bit line. However, this embodiment is not limited to this; in other embodiments, the second bit line gating sub-circuit 32 may not be provided.

[0055] In some embodiments, the voltage of the second preset voltage terminal Vpre can be the value between the voltage corresponding to logic data "0" (e.g., zero voltage) and the voltage VDD corresponding to logic data "1", such as 1 / 2VDD.

[0056] In some embodiments, multiple second bit line gating sub-circuits 32 connected to multiple bit lines of the same bit line group can be connected to the same second bit line gating control line PreC, and multiple second bit line gating sub-circuits 32 connected to multiple bit lines of different bit line groups can be connected to different second bit line gating control lines PreC. For example, the second bit line gating sub-circuit 32 connected to the bit line BL of the bit line group consisting of the first bit line BL1 and the second bit line BL2 is connected to the first second bit line gating control line PreC1; the second bit line gating sub-circuit 32 connected to the bit line BL of the bit line group consisting of the third bit line BL3 and the fourth bit line BL4 is connected to the second second bit line gating control line PreC2; and the second bit line gating sub-circuit 32 connected to the bit line BL of the bit line group consisting of the fifth bit line BL5 and the sixth bit line BL6 is connected to the third second bit line gating control line PreC3.

[0057] In some embodiments, the first word line gating sub-circuit 21 may include a first transistor T1, the gate electrode of the first transistor T1 is connected to the first word line gating control line HB_MAT_S, the first electrode is connected to the word line driving terminal HB_SWD, and the second electrode is connected to the common word line CWL. The second electrode can be connected to the common word line CWL by connecting to the stepped electrode node connected to the common word line CWL.

[0058] In some embodiments, the second word line gating sub-circuit 22 may include a second transistor T2, the gate electrode of the second transistor T2 being connected to the second word line gating control line HB_MAT_Sb, the first electrode being connected to the first preset voltage terminal VSS, and the second electrode being connected to the common word line CWL. The second electrode can be connected to the common word line CWL by connecting to a stepped electrode node connected to the common word line CWL.

[0059] In some embodiments, the first bit line gating sub-circuit 31 may include a third transistor T3, the gate electrode of which is connected to the first bit line gating control line SL, the first electrode of which is connected to the common bit line CBL, and the second electrode of which is connected to the bit line BL.

[0060] In some embodiments, the second bit line gating sub-circuit 32 may include a fourth transistor T4, the gate electrode of which is connected to the second bit line gating control line PreC, the first electrode of which is connected to the second preset voltage terminal Vpre, and the second electrode of which is connected to the bit line BL.

[0061] In some embodiments, the signals of the first word line gating control line HB_MAT_S connected to the first word line gating sub-circuit 21 connected to the same common word line CWL and the second word line gating control line HB_MAT_Sb connected to the second word line gating sub-circuit 22 connected to the same common word line CWL are not simultaneously valid level signals; wherein, a valid level signal is a signal that the corresponding gating sub-circuit is turned on, and an invalid level signal is a signal that the corresponding gating sub-circuit is turned off. That is, the first word line gating sub-circuit 21 and the second word line gating sub-circuit 22 connected to the same common word line CWL are not simultaneously turned on.

[0062] In some embodiments, the signals of the two first word line gating control lines HB_MAT_S connected to the two first word line gating sub-circuits 21 connected to the same word line driver terminal HB_SWD are not simultaneously valid level signals; that is, the signal of the same word line driver terminal HB_SWD is only loaded onto one of the multiple common word lines CWL connected at the same time.

[0063] In some embodiments, when the signal of the first word line strobe control line HB_MAT_S connected to one of the memory cell arrays in the same multi-layer memory cell array is an active level signal, the signals of the first word line strobe control lines HB_MAT_S connected to the other memory cell arrays in the same memory array are inactive level signals. Furthermore, the signals of the first word line strobe control lines HB_MAT_S connected to the other memory arrays connected to the same word line driver terminal HB_SWD are also inactive level signals. At any given time, only one word line driver terminal HB_SWD is loaded with an activation signal (the activation signal is the signal that the memory cell is turned on) when multiple word line driver terminals HB_SWD are connected to the same layer memory cell array. For example, the signal of the first word line gating control line HB_MAT_S connected to the first layer of the memory cell array of the first memory array MATk is an active level signal, while the signal of the second word line gating control line HB_MAT_Sb connected to the memory cell array of the same layer is an inactive level signal. The signals of the first word line gating control lines HB_MAT_S connected to the memory cell arrays of other layers of the first memory array MATk are inactive level signals, while the signals of the second word line gating control lines HB_MAT_Sb connected to the memory cell arrays of other layers of the first memory array MATk are active level signals. The signals of the first word line gating control lines HB_MAT_S connected to each layer of the memory cell array of the second memory array MATk+1 are inactive level signals, while the signals of the second word line gating control lines HB_MAT_Sb connected to each layer of the memory cell array of the second memory array MATk+1 are active level signals.

[0064] In some embodiments, the signals PreC of the first bit line gating control line SL connected to the first bit line gating sub-circuit 31 connected to the same bit line BL and the second bit line gating control line connected to the same bit line BL, respectively, are not simultaneously active. That is, the first bit line gating sub-circuit 31 and the second bit line gating sub-circuit 32 connected to the same bit line BL are not simultaneously turned on.

[0065] In some embodiments, when the signals of the first line gating control lines SL connected to the multiple first line gating sub-circuits 31 connected to multiple bit lines BL of one bit line group in the same memory array are active, the signals of the first line gating control lines SL connected to the remaining bit line groups of the memory array are inactive. For example, Figure 4For the common bit lines and bit lines in the first memory array MATk, when the first bit line gating control line SL1, which is connected to the bit line group composed of BL1 and BL2, is an active level signal, the second first bit line gating control line SL2, the third first bit line gating control line SL3, and other first bit line gating control lines in the first memory array MATk are all inactive level signals. The first second bit line gating control line PreC1 is an inactive level signal, while the second second bit line gating control line PreC2 and the third second bit line gating control line PreC3 are active level signals.

[0066] In some embodiments, the first word line select sub-circuit 21, the second word line select sub-circuit 22, the first bit line select sub-circuit 31, and the second bit line select sub-circuit 32 can be manufactured using non-CMOS processes, thereby enabling the first word line select sub-circuit 21, the second word line select sub-circuit 22, the first bit line select sub-circuit 31, and the second bit line select sub-circuit 32 to be located on the same die as the memory array.

[0067] In some embodiments, the bit line gating circuit 100 may be disposed between adjacent memory arrays along a first direction X.

[0068] This disclosure also provides an electronic device, including the memory described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0069] In some embodiments, the electronic device may further include a control circuit configured to access the memory according to any of the access control methods described above. The control circuit may include a word line driver that generates drive signals to the common word line, and drivers that generate control signals to the first word line gating control line, the second word line gating control line, the first bit line gating control line, and the second bit line gating control line, etc. The control circuit, together with a sense amplifier, etc., enables access to the memory. The control circuit and the sense amplifier may be located on a different die than the memory, and the die containing the control circuit and the die containing the memory may be connected via hybrid bonding pads. Figure 5 As shown, the control circuit can be located in the peripheral circuit die, and the memory can be located in the memory die, with the two connected by a hybrid bonding pad 200. The common bit line is connected to the sense amplifier through the hybrid bonding pad 200.

[0070] This disclosure provides an access control method applied to the aforementioned memory, which may include: During the data access phase, a valid level signal is applied to the first word line gating control line HB_MAT_S connected to the common word line CWL to which the target memory cell is connected, an invalid level signal is applied to the first word line gating control line HB_MAT_S connected to other memory cell arrays in the memory array where the target memory cell is located, and an invalid level signal is applied to the first word line gating control line HB_MAT_S connected to all the first word line gating sub-circuits 21 connected to other memory arrays connected to the same word line driver terminal as the memory array where the target memory cell is located.

[0071] The data access phase is the phase in which data is read from or written to the storage unit.

[0072] The solution provided in this disclosure embodiment can load the signal at the word line driver end into only one memory cell array.

[0073] In some embodiments, the method further includes loading an invalid level signal onto the second word line gating control line HB_MAT_Sb connected to the second word line gating sub-circuit 22 connected to the common word line CWL to which the target memory cell is connected; loading an valid level signal onto the second word line gating control line HB_MAT_Sb connected to other memory cell arrays in the memory array to which the target memory cell is located; and loading valid level signals onto the second word line gating control line HB_MAT_Sb connected to all second word line gating sub-circuits 22 connected to other memory arrays connected to the same word line driver terminal HB_SWD as the memory array to which the target memory cell is located. That is, the common word line connected to non-target memory cells is connected to a first preset voltage terminal to prevent floating.

[0074] In some embodiments, the method may further include: A valid level signal is applied to the first bit selection control line SL, which is connected to the first bit selection control line SL of the first bit selection sub-circuit 31 connected to the bit line group to which the bit line connected to the target memory cell belongs; an invalid level signal is applied to the second bit selection control line PreC, which is connected to the second bit selection control line PreC, which is connected to the second bit selection sub-circuit 32 connected to the bit line group to which the bit line connected to the target memory cell belongs; and an invalid level signal is applied to the first bit selection control line SL, which is connected to the first bit selection control line SL of the first bit selection sub-circuit 31 connected to the other bit line groups in the memory array where the target memory cell is located; and a valid level signal is applied to the second bit selection control line PreC, which is connected to the second bit selection control line PreC, which is connected to the second bit selection sub-circuit 32 connected to the other bit line groups. That is, the bit line connected to the target memory cell is connected to a common bit line, and the bit lines not connected to the target memory cell are connected to a second preset voltage terminal Vpre, so as to realize the reading and writing of the target memory cell and avoid the bit lines not connected to the target memory cell from floating.

[0075] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A memory, characterized in that, include: The substrate includes multiple memory arrays, multiple first word line gating sub-circuits, and multiple first word line gating control lines distributed along a direction parallel to the substrate. The memory arrays include multilayer memory cell arrays stacked along a direction perpendicular to the substrate and multiple common word lines. The memory cell arrays include multiple memory cells and multiple word lines extending along a direction parallel to the substrate. The common word lines connect at least one word line. The common word line is connected to a word line driver terminal via a first word line gating subcircuit; the same word line driver terminal is connected to at least two common word lines via different first word line gating subcircuit circuits, and the common word lines connected to the same word line driver terminal belong to different memory arrays; the first word line gating subcircuit circuit is also connected to a first word line gating control line; the first word line gating subcircuit circuit is configured to electrically connect or disconnect the word line driver terminal and the common word line under the control of the first word line gating control line; wherein, different common word lines of the same memory array are connected to different word line driver terminals.

2. The memory according to claim 1, characterized in that, The same word line driver terminal connects to two common word lines through different first word line gating sub-circuits, and the two common word lines connected to the same word line driver terminal belong to two adjacent memory arrays.

3. The memory according to claim 2, characterized in that, The first word line gating sub-circuit connected to the common word line of the same memory cell array is connected to the same first word line gating control line, and the first word line gating sub-circuit connected to the common word line of different memory cell arrays is connected to different first word line gating control lines.

4. The memory according to claim 3, characterized in that, The memory further includes: a plurality of second word line gating sub-circuits and a plurality of second word line gating control lines. The common word line is also connected to the second word line gating sub-circuit. The second word line gating sub-circuit is also connected to a first preset voltage terminal and a second word line gating control line. The second word line gating sub-circuit is configured to electrically connect or disconnect the common word line and the first preset voltage terminal under the control of the second word line gating control line.

5. The memory according to claim 4, characterized in that, The second word line gating sub-circuit connected to the common word line of the same memory cell array is connected to the same second word line gating control line, while the second word line gating sub-circuit connected to the common word line of different memory cell arrays is connected to different second word line gating control lines.

6. The memory according to claim 5, characterized in that, The signals of the first word line gating control line connected to the first word line gating sub-circuit connected to the same common word line and the second word line gating control line connected to the second word line gating sub-circuit connected to the same common word line are not simultaneously valid level signals; the signals of the two first word line gating control lines connected to the two first word line gating sub-circuits connected to the same word line driving terminal are not simultaneously valid level signals. When the signal of the first word line strobe control line connected to one of the memory cell arrays in the same memory array is an active level signal, the signals of the first word line strobe control lines connected to the other memory cell arrays in the same memory array are inactive level signals, and the signals of the first word line strobe control lines connected to the other memory arrays connected to the same word line driver terminal are also inactive level signals.

7. The memory according to any one of claims 1 to 6, characterized in that, The memory also includes: multiple first-line gating sub-circuits and multiple first-line gating control lines; The memory array further includes: a plurality of bit lines extending perpendicular to the substrate along a first direction parallel to the substrate and a second direction parallel to the substrate, and a plurality of common bit lines; the common bit lines connect to at least one bit line, and the common bit lines and the bit lines are connected through a first bit line gating sub-circuit; the first bit line gating sub-circuit is also connected to a first bit line gating control line; the first bit line gating sub-circuit is configured to electrically connect or disconnect the common bit lines and the bit lines under the control of the first bit line gating control line.

8. The memory according to claim 7, characterized in that, The memory also includes: multiple second bit line gating sub-circuits and multiple second bit line gating control lines; The bit line is also connected to the second bit line gating sub-circuit, which is further connected to the second preset voltage terminal and the second bit line gating control line. The second bit line gating sub-circuit is configured to electrically connect or disconnect the bit line and the second preset voltage terminal under the control of the second bit line gating control line.

9. The memory according to claim 8, characterized in that, The memory cell array includes a plurality of memory cells distributed along a first direction and a second direction parallel to the substrate, and the word line extends along the first direction; the word line connects a row of memory cells distributed along the first direction. Each column of bit lines distributed along the second direction corresponds to L common bit lines. Among the multiple bit lines in the same column, each L consecutively distributed bit lines are divided into a bit line group. The multiple bit lines in the same bit line group are respectively connected to different common bit lines in the L common bit lines corresponding to the column bit lines. The multiple first bit line gating sub-circuits connected to the multiple bit lines in the same bit line group are connected to the same first bit line gating control line. The multiple second bit line gating sub-circuits connected to the multiple bit lines in the same bit line group are connected to the same second bit line gating control line.

10. The memory according to claim 9, characterized in that, The signals of the first bit line gating control line connected to the first bit line gating sub-circuit and the second bit line gating control line connected to the second bit line gating sub-circuit are not simultaneously valid level signals; When the first line gating control line connected to multiple first line gating sub-circuits of a bit line group in the same memory array has an active level signal, the first line gating control line connected to the other bit line groups of the memory array has an inactive level signal.

11. An access control method, characterized in that, Applied to the memory as described in any one of claims 1 to 10, comprising: During the data access phase, a valid level signal is applied to the first word line gating control line connected to the common word line to which the target memory cell is connected, an invalid level signal is applied to the first word line gating control line connected to the other memory cell arrays of the memory array to which the target memory cell is located, and an invalid level signal is applied to the first word line gating control line connected to all the first word line gating sub-circuits connected to the other memory arrays connected to the same word line driver terminal as the memory array to which the target memory cell is located.

12. The access control method according to claim 11, characterized in that, The memory is the memory described in 5 or 6. The method further includes loading an invalid level signal onto the second word line gating control line connected to the second word line gating sub-circuit connected to the common word line connected to the target memory cell, loading an valid level signal onto the second word line gating control line connected to the other memory cell arrays of the memory array where the target memory cell is located, and loading valid level signals onto the second word line gating control lines connected to all the second word line gating sub-circuits connected to the other memory arrays connected to the same word line driver terminal as the memory array where the target memory cell is located.

13. The access control method according to claim 11, characterized in that, The memory is the memory as described in claim 9 or 10, and the method further includes: A valid level signal is applied to the first bit line selection control line connected to the first bit line selection subcircuit of the bit line group to which the bit line connected to the target memory cell belongs; an invalid level signal is applied to the second bit line selection control line connected to the second bit line selection subcircuit of the bit line group to which the target memory cell belongs; an invalid level signal is applied to the first bit line selection control line connected to the first bit line selection subcircuit of the other bit line groups of the memory array where the target memory cell is located; and a valid level signal is applied to the second bit line selection control line connected to the second bit line selection subcircuit of the other bit line groups.

14. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 10.

15. The electronic device according to claim 14, characterized in that, The electronic device further includes a control circuit configured to access the memory according to the access control method of any one of claims 11 to 13.

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