Novel heterogeneous integrated gallium oxide transistor and manufacturing method thereof
By designing heterogeneous integrated gallium oxide transistors, combining a heterogeneous semiconductor P-type channel layer with a gallium oxide N-type drift region to form a trench structure and a Schottky diode region, the problems of interface damage, low channel mobility, low breakdown voltage, and self-heating effect of β-Ga2O3 longitudinal field-effect transistors are solved, achieving efficient reverse freewheeling and enhanced breakdown voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-15
- Publication Date
- 2026-03-24
AI Technical Summary
Existing β-Ga2O3 longitudinal field-effect transistors suffer from problems such as interface damage, low channel mobility, high specific on-resistance, low breakdown voltage, lack of reverse freewheeling function, and severe self-heating effect.
A novel heterogeneous integrated gallium oxide transistor is designed by combining a heterogeneous semiconductor P-type channel layer with a gallium oxide N-type drift region to form a trench transistor region and a trench Schottky diode region. Through the design of the trench structure and Schottky anode metal, the device achieves enhancement characteristics and reverse freewheeling function, and utilizes SiC/Si materials to improve thermal conductivity.
It improves channel mobility, reduces specific on-resistance, enhances device withstand voltage, enables reverse freewheeling function, reduces system parasitic inductance and size, and avoids device degradation or failure caused by self-heating effect.
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Figure CN121728818A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of power semiconductors, and particularly relates to a novel hetero-integrated gallium oxide transistor and a manufacturing method. BACKGROUND
[0002] Gallium oxide (Ga2O3) based power devices gradually become a new favorite in the field of power devices due to their super-wide band gap (4.9eV), super-high critical breakdown field strength (8MV / cm) and the advantages of low cost, mass production and high-quality single crystal substrate growth. β-Ga2O3 is the only crystal structure that can be grown by melt method among many Ga2O3 crystal phases. Compared with traditional silicon-based and third-generation semiconductor materials such as gallium nitride and silicon carbide, β-Ga2O3 based power devices have the triple advantages of high breakdown voltage, low on-resistance and low cost, and have great application prospects in the fields of high voltage, high power and high efficiency energy saving. However, since β-Ga2O3 has not formed effective P-type doping, most of the current β-Ga2O3 vertical field effect transistors use nitrogen / magnesium ion implantation or thermal oxidation to form a high resistance layer to achieve a positive threshold and high voltage resistance. Nitrogen / magnesium ion implantation can easily cause interface damage, low channel mobility and large on-resistance. The thermal oxidation layer is difficult to effectively block the leakage current, and the device has low voltage resistance. At the same time, the traditional β-Ga2O3 field effect transistor lacks a parasitic diode, i.e. does not have a reverse current continuation function, and needs to be packaged into a module with a discrete diode in anti-parallel to realize reverse current continuation, which increases the difficulty of circuit system design, introduces parasitic inductance and increases the system volume. In addition, β-Ga2O3 has low thermal conductivity, and the device is prone to self-heating, which further increases the on-resistance of the device and causes thermal failure of the device. SUMMARY
[0003] In view of the above problems, the application provides a novel hetero-integrated gallium oxide transistor and a manufacturing method.
[0004] The technical scheme adopted by the application is:
[0005] A novel hetero-integrated gallium oxide transistor, which is sequentially stacked from bottom to top along the vertical direction of the device and comprises a drain metal 1, a gallium oxide N-type heavily doped substrate 2, a gallium oxide N-type drift region 3, a hetero-semiconductor P-type channel layer 4, a hetero-semiconductor N-type heavily doped layer 5 and a source metal 6.
[0006] The upper surface of the gallium oxide N-type drift region 3 has spaced distribution of groove transistor regions and groove Schottky diode regions along the lateral direction of the device, and the device cell is defined as the groove transistor region and the groove Schottky diode region with the line extending in the source metal 6 as the boundary; the groove transistor region has a gate groove structure penetrating through the source metal 6, the hetero-semiconductor N-type heavily doped layer 5 and the hetero-semiconductor P-type channel layer 4, and extending into the gallium oxide N-type drift region 3; the bottom and sidewall of the groove gate structure are covered with the insulating medium 7, and the insulating medium 7 laterally extends to cover the upper surface of the source metal 6 of the groove transistor region; the upper surface of the insulating medium 7 is covered with the gate metal 8, and the lateral coverage area of the gate metal 8 is smaller than that of the insulating medium 7, so that the gate metal 8 does not contact the groove Schottky diode region; the groove Schottky diode region has a deep groove structure penetrating through the source metal 6, the hetero-semiconductor N-type heavily doped layer 5 and the hetero-semiconductor P-type channel layer 4, and extending into the gallium oxide N-type drift region 3, and the bottom and sidewall of the deep groove structure are covered with the Schottky anode metal 9, and the Schottky anode metal 9 laterally extends to cover the upper surface of the source metal 6 of the Schottky diode region and forms contact with the source metal 6.
[0007] The hetero-semiconductor N-type heavily doped layer 5 and the hetero-semiconductor P-type channel layer 4 are the same kind of semiconductor material which is easy to be P-type doped or epitaxial, such as SiC, Si, etc. The drain metal 1 is a common ohmic contact metal which forms ohmic contact with the gallium oxide N-type heavily doped substrate 2, such as Ti / Au stack. The source metal 6 is an ohmic contact metal with large hardness and semiconductor etching selectivity, which forms ohmic contact with the hetero-semiconductor N-type heavily doped layer 5 and serves as a hard mask for self-aligned etching, such as Ti / Au / Ni stack. The gate metal 8 and the Schottky anode metal 9 are high work function metals, such as Ni, Cr, etc.
[0008] Further, the sidewall of the groove structure (i.e. the gate groove structure of the groove transistor region and the deep groove structure of the groove Schottky diode region) of the groove transistor region and the groove Schottky diode region has a certain inclination, and the corner of the groove bottom is an obtuse angle.
[0009] Further, the bottom corner and sidewall of the deep groove structure of the groove Schottky diode region are covered with the insulating medium 7, while the center of the groove bottom is not covered with the insulating medium 7, and the insulating medium 7 laterally extends to cover the upper surface of the source metal 6 of the groove transistor region; the Schottky anode metal 9 covers the upper surface of the insulating medium 7 and contacts the gallium oxide N-type drift region 3 at the center of the deep groove bottom, and the Schottky anode metal 9 contacts the source metal 6 to form contact at the periphery of the device.
[0010] Further, the groove structure (i.e. the gate groove structure of the groove transistor region and the deep groove structure of the groove Schottky diode region) of the groove transistor region and the groove Schottky diode region has a certain inclination angle, and the corner of the groove bottom is an obtuse angle; the bottom corner and the sidewall of the deep groove structure of the Schottky diode region are covered with the insulating medium 7, while the center of the groove bottom is not covered with the insulating medium 7, and the insulating medium 7 extends laterally to cover the upper surface of the source metal 6 of the groove transistor region; the Schottky anode metal 9 is covered on the upper surface of the insulating medium 7 and contacts with the gallium oxide N-type drift region 3 at the center of the deep groove bottom, and the Schottky anode metal 9 and the source metal 6 are interconnected to form a contact at the periphery of the device.
[0011] A feasible manufacturing method for the device of the present application comprises the following steps:
[0012] Step 1: epitaxially forming a gallium oxide N-type drift region 3 on a gallium oxide N-type heavily doped substrate 2;
[0013] Step 2: forming a hetero-semiconductor P-type channel layer 4 on the hetero-semiconductor N-type heavily doped layer 5 by epitaxy / ion implantation, and performing hydrogen (H + ) ion implantation;
[0014] Step 3: hetero-bonding the gallium oxide N-type drift region 3 and the hetero-semiconductor P-type channel layer 4;
[0015] Step 4: thinning and chemical mechanical polishing the bonded hetero-semiconductor N-type heavily doped layer 5;
[0016] Step 5: depositing the source metal 6 and the drain metal 1, and patterning the source metal 6 by a lift-off process, and annealing in an N2 atmosphere to form an ohmic contact;
[0017] Step 6: taking the source metal 6 as a hard mask, and forming the groove structure of the groove transistor region and the groove Schottky diode region by a self-aligned dry etching process, and then performing wet repair to remove etching damage;
[0018] Step 7: depositing the insulating medium 7, and patterning the insulating medium 7 by wet etching;
[0019] Step 8: depositing and lifting off to form the gate metal 8 and the Schottky anode metal 9.
[0020] The device of the present application is a novel hetero-integrated gallium oxide transistor, and the hetero-semiconductor P-type channel is used to realize an enhancement device. GS >V th , V DS(V GS <V th , V DS >0), the hetero-semiconductor P-type channel layer is inverted into an electron-conducting channel, the electron mobility in the channel is high, which is conducive to reducing the specific on-resistance and increasing the output current, and the hetero-semiconductor P-type channel is short-circuited by the Schottky anode metal and the source, thereby suppressing the transistor body effect. In the blocking state (V GS <V th , V DS <0), the Schottky diode is turned on, the device realizes reverse current flow function and has a low on-voltage drop, realizes the integration of field effect transistor and current flow diode in a single process, reduces the parasitic inductance and volume of the power integrated system. In addition, the current density concentrated channel layer adopts a hetero-semiconductor (SiC / Si) whose thermal conductivity is better than Ga2O3, which enhances the heat dissipation of the device and avoids degradation or failure of the device due to self-heating effect. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 is a structural schematic diagram of the device described in embodiment 1 of the present application;
[0022] Figure 2 is a structural schematic diagram of the device described in embodiment 2 of the present application;
[0023] Figure 3 is a structural schematic diagram of the device described in embodiment 3 of the present application;
[0024] Figure 4 is a structural schematic diagram of the device described in embodiment 4 of the present application;
[0025] Figure 5 is a feasible process flow diagram of the device described in embodiment 1 of the present application. DETAILED DESCRIPTION
[0026] The technical solutions of the present application will be described in detail below in combination with the drawings and embodiments:
[0027] Embodiment 1:
[0028] As Figure 1As shown, a novel hetero-integrated gallium oxide transistor is provided, which is vertically stacked from bottom to top with a drain metal 1, a gallium oxide N-type heavily doped substrate 2, a gallium oxide N-type drift region 3, a hetero-semiconductor P-type channel layer 4, a hetero-semiconductor N-type heavily doped layer 5, and a source metal 6.
[0029] In particular, the upper surface of the gallium oxide N-type drift region 3 has a plurality of spaced-apart groove transistor regions and groove Schottky diode regions in the lateral direction of the device, and the device cell is defined as the groove transistor region and the groove Schottky diode region by taking the center line of the source metal 6 as the boundary line; the groove transistor region has a gate groove structure penetrating through the source metal 6, the hetero-semiconductor N-type heavily doped layer 5, and the hetero-semiconductor P-type channel layer 4, and extending into the gallium oxide N-type drift region 3; the bottom and sidewall of the groove gate structure are covered with an insulating medium 7, and the insulating medium 7 laterally extends to cover the upper surface of the source metal 6 in the groove transistor region; the upper surface of the insulating medium 7 is covered with a gate metal 8, and the lateral coverage area of the gate metal 8 is smaller than that of the insulating medium 7, so that the gate metal 8 does not contact the groove Schottky diode region; the groove Schottky diode region has a deep groove structure penetrating through the source metal 6, the hetero-semiconductor N-type heavily doped layer 5, and the hetero-semiconductor P-type channel layer 4, and extending into the gallium oxide N-type drift region 3, and the bottom and sidewall of the deep groove structure are covered with a Schottky anode metal 9, and the Schottky anode metal 9 laterally extends to cover the upper surface of the source metal 6 in the Schottky diode region, and forms a contact with the source metal 6.
[0030] The hetero-semiconductor N-type heavily doped layer 5 and the hetero-semiconductor P-type channel layer 4 are the same kind of semiconductor material that is easy to be P-type doped or epitaxially grown, such as SiC, Si, etc. The drain metal 1 is a common ohmic contact metal, which forms an ohmic contact with the gallium oxide N-type heavily doped substrate 2, such as a Ti / Au stack. The source metal 6 is an ohmic contact metal with high hardness and high semiconductor etching selectivity, which forms an ohmic contact with the hetero-semiconductor N-type heavily doped layer 5 while serving as a hard mask for self-aligned etching, such as a Ti / Au / Ni stack. The gate metal 8 and the Schottky anode metal 9 are high work function metals, such as Ni, Cr, etc.
[0031] The working principle of the present example is as follows:
[0032] The device of the present application is a novel hetero-integrated gallium oxide transistor, which realizes an enhancement-mode device by using a hetero-semiconductor P-type channel. When the device is forward biased (V GS > th , V DS>0), the heterosemiconductor P-type channel layer 4 is inverted into an electron-conducting channel. The high electron mobility in the channel helps reduce specific on-resistance and increase output current. Furthermore, the heterosemiconductor P-type channel layer 4 is short-circuited to the source metal 6 via the Schottky anode metal 9, suppressing the transistor's bulk effect. In the blocking state (V... GS <V th V DS >0), the PN junction formed by the heterojunction P-type channel layer 4 and the gallium oxide N-type drift region 3 is reverse-biased, suppressing leakage current; and the deep trench structure of the trench transistor region and the trench Schottky diode region together pinch off the conductive path, shielding the high electric field, and the two work together to improve the device's breakdown voltage. In addition, the Schottky anode metal 9 is shorted to the source metal 6, and the Schottky junction is in a reverse-biased state during transistor operation, which does not affect the transistor's conduction and breakdown voltage characteristics. During reverse conduction (V GS <V th V DS When the voltage drop is less than 0, the Schottky diode, composed of the Schottky anode metal 9 and the gallium oxide N-type drift region 3, turns on. The device achieves reverse freewheeling function and has a low on-state voltage drop, enabling monolithic integration of the field-effect transistor and the freewheeling diode, reducing parasitic inductance and size in the power integrated system. Furthermore, the channel layer, where the current density is concentrated, uses a heterogeneous semiconductor (SiC / Si), which has better thermal conductivity than Ga2O3, enhancing device heat dissipation and preventing degradation or failure due to self-heating effects.
[0033] like Figure 5 Figures (a)-(h) show a feasible process flow diagram of the device described in Embodiment 1 of the present invention, which specifically includes the following steps:
[0034] Step 1: Epitaxially form a gallium oxide N-type drift region 3 on a gallium oxide N-type heavily doped substrate 2;
[0035] Step 2: Epitaxial growth is performed on the heavily doped N-type layer 5 of the heterosemiconductor. / Ion implantation was used to form a heterosemiconductor P-type channel layer 4, followed by hydrogen (H2O) implantation. + Ion implantation;
[0036] Step 3: Perform heterobonding on the gallium oxide N-type drift region 3 and the heterosemiconductor P-type channel layer 4;
[0037] Step 4: Thinning and chemical mechanical polishing of the bonded heterosemiconductor N-type heavily doped layer 5;
[0038] Step 5: Deposit source metal 6 and drain metal 1, and pattern the source metal 6 by a stripping process, and anneal in N2 atmosphere to form ohmic contacts;
[0039] Step 6: Using source metal 6 as a hard mask, a grooved structure of the grooved transistor region and the grooved Schottky diode region is formed by a self-aligned dry etching process, followed by wet repair to remove etching damage.
[0040] Step 7: Deposit insulating dielectric 7 and pattern the insulating dielectric 7 by wet etching;
[0041] Step 8: Deposit and strip to form gate metal 8 and Schottky anode metal 9.
[0042] Example 2:
[0043] like Figure 2 The diagram shown is a structural schematic of a novel heterogeneous integrated gallium oxide transistor in Example 2. The difference between this example and Example 1 is that the sidewalls of the groove structure of the groove transistor region and the groove Schottky diode region in this example have a certain tilt angle, and the bottom corner of the groove is an obtuse angle, which further weakens the electric field peak and improves the device withstand voltage. Its working principle is basically the same as that of Example 1.
[0044] The difference between this example and Example 1 is that in step 6, this example uses key parameters such as gas type, flow rate ratio, and gas pressure in the dry etching menu to etch a groove structure with an inclined sidewall.
[0045] Example 3:
[0046] like Figure 3 The diagram shown is a schematic of a novel heterogeneous integrated gallium oxide transistor (GaO) according to Embodiment 3. The difference between this embodiment and Embodiment 1 is that the bottom corners and sidewalls of the deep trench structure in the grooved Schottky diode region are covered with an insulating dielectric 7, while the center of the trench bottom is not covered. The insulating dielectric 7 extends laterally, covering the upper surface of the source metal 6 in the grooved transistor region. The Schottky anode metal 9 covers the upper surface of the insulating dielectric 7 and contacts the gallium oxide N-type drift region 3 at the center of the deep trench bottom. The Schottky anode metal 9 and the source metal 6 are interconnected at the device periphery to form a contact. This embodiment has a field plate structure in the grooved Schottky diode region, preventing the Schottky anode metal 9 from directly contacting the bottom corner of the deep trench, further weakening the electric field peak and improving the device's withstand voltage. Its working principle is basically the same as that of Embodiment 1.
[0047] The difference between this example and Example 1 is that in step 7, the layout is adjusted, and only the insulating medium 7 at the center of the deep trench bottom of the groove-type Schottky diode region is wet-etched.
[0048] Example 4:
[0049] like Figure 4The diagram shown is a structural schematic of a novel heterogeneous integrated gallium oxide transistor in Example 4. The difference between this example and Example 3 is that the sidewalls of the groove structure of the groove transistor region and the groove Schottky diode region in this example have a certain tilt angle, and the bottom corner of the groove is an obtuse angle, which further weakens the electric field peak and improves the device withstand voltage. Its working principle is basically the same as that of Example 1.
[0050] The difference between this example and Example 1 is that in step 6, by adjusting key parameters such as gas type, flow rate ratio, and gas pressure in the dry etching menu, a groove structure with inclined sidewalls is etched; in step 7, the layout is adjusted so that only the insulating medium 7 at the center of the bottom of the deep groove of the groove Schottky diode region is wet etched.
[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A novel heterogeneous integrated gallium oxide transistor, wherein a drain metal (1), a heavily doped gallium oxide N-type substrate (2), a gallium oxide N-type drift region (3), a heterogeneous semiconductor P-type channel layer (4), a heterogeneous semiconductor N-type heavily doped layer (5), and a source metal (6) are stacked sequentially from bottom to top along the vertical direction of the device. Its features are, Using the extension line of the source metal (6) as the dividing line, the structures on both sides of the device cell are defined as the slot transistor region and the slot Schottky diode region, respectively; the slot transistor region has a gate trench structure that extends through the source metal (6), the heterogeneous semiconductor N-type heavily doped layer (5) and the heterogeneous semiconductor P-type channel layer (4), and is embedded in the gallium oxide N-type drift region (3); the bottom and sidewalls of the slot gate structure are covered with an insulating dielectric (7), and the insulating dielectric (7) extends laterally to cover the upper surface of the source metal (6) of the slot transistor region; the upper surface of the insulating dielectric (7) is covered with a gate metal (8), and The lateral coverage area of the gate metal (8) is smaller than that of the lateral coverage area of the insulating dielectric (7), and the gate metal (8) does not contact the grooved Schottky diode region; the grooved Schottky diode region has a deep trench structure that penetrates the source metal (6), the heterogeneous semiconductor N-type heavily doped layer (5) and the heterogeneous semiconductor P-type channel layer (4) and extends into the gallium oxide N-type drift region (3). The bottom and sidewalls of the deep trench structure are covered with Schottky anode metal (9), and the Schottky anode metal (9) extends laterally to cover the upper surface of the source metal (6) of the Schottky diode region and forms contact with the source metal (6).
2. The novel heterogeneous integrated gallium oxide transistor according to claim 1, characterized in that, The gate trench structure of the trench transistor region and the deep trench structure of the trench Schottky diode region have a certain inclination angle on their sidewalls, and the bottom corner of the trench is an obtuse angle.
3. The novel heterogeneous integrated gallium oxide transistor according to claim 1, characterized in that, The bottom corners and sidewalls of the deep trench structure of the grooved Schottky diode are covered with an insulating medium (7), while the center of the bottom of the trench is not covered with an insulating medium (7), and the insulating medium (7) extends laterally to cover the upper surface of the source metal (6) of the grooved transistor region; the Schottky anode metal (9) covers the upper surface of the insulating medium (7) and contacts the gallium oxide N-type drift region (3) at the center of the bottom of the deep trench, and the Schottky anode metal (9) and the source metal (6) are interconnected at the periphery of the device to form a contact.
4. A novel heterogeneous integrated gallium oxide transistor according to claim 1, characterized in that, The gate trench structure of the slotted transistor region and the deep trench structure of the slotted Schottky diode region have a certain tilt angle on their sidewalls, and the bottom corner of the trench is an obtuse angle; the bottom corner and sidewall of the deep trench structure of the slotted Schottky diode region are covered with an insulating medium (7), while the center of the bottom of the trench is not covered with an insulating medium (7), and the insulating medium (7) extends laterally to cover the upper surface of the source metal (6) of the slotted transistor region; the Schottky anode metal (9) covers the upper surface of the insulating medium (7) and contacts the gallium oxide N-type drift region (3) at the center of the bottom of the deep trench, and the Schottky anode metal (9) and the source metal (6) are interconnected at the periphery of the device to form a contact.
5. A method for manufacturing a novel heterogeneous integrated gallium oxide transistor as described in claim 1, characterized in that, Includes the following steps: Step 1: Epitaxially form a gallium oxide N-type drift region (3) on a gallium oxide N-type heavily doped substrate (2); Step 2: Form a heterosemiconductor P-type channel layer (4) on the heterosemiconductor N-type heavily doped layer (5) by epitaxy / ion implantation, and perform hydrogen (H) injection. + Ion implantation; Step 3: Perform heterobonding on the gallium oxide N-type drift region (3) and the heterosemiconductor P-type channel layer (4); Step 4: Thinning and chemical mechanical polishing of the bonded heterosemiconductor N-type heavily doped layer (5); Step 5: Deposit source metal (6) and drain metal (1), and pattern the source metal (6) by a stripping process, and anneal in N2 atmosphere to form ohmic contacts; Step 6: Using the source metal (6) as a hard mask, a groove structure of the groove transistor region and the groove Schottky diode region is formed by self-aligned dry etching process. The groove depth and the groove sidewall tilt angle can be controlled by key parameters such as etching gas ratio and gas pressure. Then, wet repair is performed to remove etching damage. Step 7: Deposit insulating medium (7) and pattern the insulating medium (7) by wet etching; Step 8: Deposit and strip to form gate metal (8) and Schottky anode metal (9).
6. A feasible manufacturing method for a novel heterogeneous integrated gallium oxide transistor as described in claim 2, characterized in that, The manufacturing method is as follows: In step 6, by adjusting key parameters such as gas type, flow rate ratio, and gas pressure in the dry etching menu, a groove structure with inclined sidewalls is etched.
7. A feasible manufacturing method for a novel heterogeneous integrated gallium oxide transistor as described in claim 3, characterized in that, The manufacturing method is as follows: In step 7, the layout is adjusted so that only the insulating medium (7) at the center of the deep trench bottom of the groove Schottky diode region is wet-etched.
8. A feasible manufacturing method for a novel heterogeneous integrated gallium oxide transistor as described in claim 4, characterized in that, The manufacturing method is as follows: In step 6, by adjusting key parameters such as gas type, flow rate ratio, and gas pressure in the dry etching menu, a groove structure with inclined sidewalls is etched. In step 7, the layout is adjusted so that only the insulating medium (7) at the center of the deep trench bottom of the groove Schottky diode region is wet-etched.