Array substrate and display panel

Abstract

The invention relates to an array substrate and a display panel, two active layers are designed on one side of a substrate, and orthographic projections of the two active layers on the substrate are partially overlapped, so that transistors formed on the two active layers are arranged in a laminated manner in the thickness direction of the array substrate; the occupied area of the transistor formed by the upper active layer covers the occupied area of the transistor formed by the lower active layer. By means of the design, the transverse space and the longitudinal space of the array substrate can be saved to the maximum extent, the occupied area of a pixel circuit is reduced, and the pixel arrangement density is improved. Furthermore, the first transistor T1 and the second transistor T2 serve as a part of the pixel circuit, channels of the first transistor T1 and the second transistor T2 are designed to have a common end, and the common end is led out to form a common electrode to be connected with an anode, so that anode node sharing is achieved, the functions of anode resetting or driving light emitting and the like of a light-emitting element are achieved, the transverse occupied space of the pixel circuit is further reduced, and the pixel circuit is more compact. And higher pixel arrangement density can be realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of organic light-emitting diode (OLED) display panels is becoming more and more widespread, such as virtual reality (VR) and augmented reality (AR) display solutions, bringing users a brand-new visual experience.

[0003] However, existing OLED display panels suffer from low resolution, which cannot meet the application requirements of display solutions such as AR / VR. Summary of the Invention

[0004] Therefore, it is necessary to provide an array substrate and a display panel to address the aforementioned technical problems.

[0005] An array substrate, comprising:

[0006] Substrate;

[0007] The first active layer is located on one side of the substrate;

[0008] The second active layer is located on the side of the first active layer that is away from the substrate;

[0009] A first transistor and a second transistor, wherein the first transistor includes a first active portion and the second transistor includes a second active portion, and the first active portion and the second active portion are disposed on the first active layer;

[0010] A third transistor includes a third active portion disposed on the second active layer. The channel region of the third active portion is at least partially located within the orthogonal projection of the channel region of the first active portion onto the substrate, and the orthogonal projection of the channel region of the third active portion onto the substrate is located outside the orthogonal projection of the channel region of the second active portion onto the substrate.

[0011] In one embodiment, it further includes:

[0012] A first conductive layer is located between the first active layer and the second active layer;

[0013] The first electrode is located on the side of the second active layer that is away from the substrate;

[0014] The second electrode of the first transistor is connected to the second electrode of the second transistor to form a common electrode, the common electrode is located in the first conductive layer, and the common electrode is electrically connected to the first electrode.

[0015] In one embodiment, it further includes:

[0016] The second conductive layer is located between the first active layer and the first conductive layer;

[0017] The first transistor further includes a first gate located in the second conductive layer. The orthographic projection of the first gate onto the first active layer covers the channel region of the first active portion. The first gate is electrically connected to the second source-drain region of the third active portion.

[0018] The second transistor further includes a second gate located in the second conductive layer, and the orthogonal projection of the second gate onto the first active layer covers the channel region of the second active portion;

[0019] Preferably, a first gate insulating layer is provided between the second conductive layer and the first active layer, and a first insulating layer is provided between the first conductive layer and the second conductive layer. The common electrode is connected to the second source / drain region of the first active part and the second source / drain region of the second active part via a first via. The first via passes through the first insulating layer and the first gate insulating layer in sequence.

[0020] Preferably, the first transistor is a driving transistor used to transmit driving current to the light-emitting element;

[0021] Preferably, the second transistor is a reset transistor, used to reset the driving transistor and the light-emitting element;

[0022] Preferably, the array substrate further includes a first scan signal line, and the second gate is connected to the first scan signal line;

[0023] Preferably, the first electrode of the second transistor is located in the first conductive layer, and the first electrode of the second transistor is connected to the first source-drain region of the second active portion via the second via, and the second via sequentially penetrates the first insulating layer and the first gate insulating layer;

[0024] Preferably, the array substrate further includes a reset signal line, and the first terminal of the second transistor is connected to the reset signal line.

[0025] In one embodiment, it further includes:

[0026] The first connecting plate is located in the first conductive layer. The first connecting plate is connected to the first gate through a third via in the first insulating layer. The first gate is electrically connected to the second source / drain region of the third active part through the first connecting plate.

[0027] In one embodiment, it further includes:

[0028] The third conductive layer is located between the first conductive layer and the second active layer;

[0029] The fourth conductive layer is located between the third conductive layer and the second active layer;

[0030] A first capacitor and a second capacitor, the first capacitor and the second capacitor including a common electrode plate, the common electrode plate being located in the third conductive layer, the first connecting electrode plate serving as the other side electrode plate of the first capacitor, the second capacitor further including a second electrode plate, the second electrode plate being located in the fourth conductive layer, the orthographic projection of the first connecting electrode plate on the substrate being at least partially located within the orthographic projection of the common electrode plate on the substrate, and the orthographic projection of the second electrode plate on the substrate being at least partially located within the orthographic projection of the common electrode plate on the substrate;

[0031] Preferably, the orthographic projection of the common electrode plate onto the substrate is at least partially located within the orthographic projection of the first active portion onto the substrate;

[0032] Preferably, a second insulating layer is provided between the first conductive layer and the third conductive layer, a third insulating layer is provided between the third conductive layer and the fourth conductive layer, a fourth insulating layer is provided between the second active layer and the fourth conductive layer, and the first connecting plate is connected to the second source / drain region of the third active part through a fourth via, wherein the fourth via sequentially penetrates the fourth insulating layer, the third insulating layer and the second insulating layer;

[0033] Preferably, the filling material of the fourth via is the same as the material of the second active layer.

[0034] In one embodiment, it further includes:

[0035] The fifth conductive layer is located on the side of the second active layer that faces away from the substrate;

[0036] The third transistor is a dual-gate transistor, which includes a third top gate and a third bottom gate. The third top gate is located in the fifth conductive layer. The orthogonal projection of the third top gate onto the second active layer covers the channel region of the third active portion. The third bottom gate reuses the second electrode plate.

[0037] Preferably, the array substrate further includes a second scan signal line, and the third top gate is connected to the second scan signal line.

[0038] In one embodiment, it further includes:

[0039] A fourth transistor, the fourth transistor including a fourth active portion disposed on the second active layer, wherein the orthographic projection of the channel region of the fourth active portion on the substrate is located outside the orthographic projection of the channel region of the first active portion on the substrate;

[0040] The fourth transistor is a dual-gate transistor, which includes a fourth top gate and a fourth bottom gate. The fourth top gate is located in the fifth conductive layer, and the fourth bottom gate is located in the fourth conductive layer. The orthogonal projection of the fourth top gate and the fourth bottom gate on the second active layer covers the channel region of the fourth active portion. The second electrode of the fourth transistor is located in the third conductive layer.

[0041] Preferably, the second electrode of the fourth transistor is connected to the second source / drain region of the fourth active part via the fifth via, and the fifth via sequentially penetrates the fourth insulating layer and the third insulating layer;

[0042] Preferably, the filling material of the fifth via is the same as the material of the second active layer;

[0043] Preferably, the second electrode of the fourth transistor reuses the common electrode plate, and the orthographic projection of the fifth via on the substrate is located within the orthographic projection of the first connecting electrode plate on the substrate;

[0044] Preferably, the common electrode plate includes a first electrode plate portion, a connecting portion and a second electrode plate portion, the connecting portion connects the first electrode plate portion and the second electrode plate portion, and in a first direction, the first electrode plate portion, the fourth through hole and the second electrode plate portion are arranged sequentially, and in a second direction perpendicular to the first direction, the fourth through hole is located on one side of the connecting portion;

[0045] Preferably, the first electrode of the first transistor is located in the first conductive layer, and the first electrode of the first transistor is connected to the first source-drain region of the first active part through a sixth via, wherein the sixth via sequentially penetrates the first insulating layer and the first gate insulating layer.

[0046] Preferably, the array substrate further includes a power signal line, the second electrode plate and the fourth bottom gate are connected to the power signal line, the fourth bottom gate is connected to the first electrode of the first transistor through a seventh via, and the seventh via sequentially penetrates the third insulating layer and the second insulating layer;

[0047] Preferably, the array substrate further includes a sixth conductive layer located on the side of the fifth conductive layer opposite to the substrate, and the first electrode of the fourth transistor is located on the sixth conductive layer;

[0048] Preferably, a second gate insulating layer is provided between the second active layer and the fifth conductive layer, a fifth insulating layer is provided between the fifth conductive layer and the sixth conductive layer, and the first electrode of the fourth transistor is connected to the first source-drain region of the fourth active part through an eighth via, the eighth via sequentially penetrating the fifth insulating layer and the second gate insulating layer;

[0049] Preferably, the array substrate further includes a data signal line, and the first electrode of the fourth transistor is connected to the data signal line;

[0050] Preferably, the array substrate further includes a third scan signal line, and the fourth top gate is connected to the third scan signal line.

[0051] In one embodiment, it further includes:

[0052] The seventh conductive layer is located on the side of the sixth conductive layer that faces away from the substrate;

[0053] The second connection electrode is located in the seventh conductive layer and is connected to the common electrode and the anode, respectively.

[0054] Preferably, a sixth insulating layer is provided between the sixth conductive layer and the seventh conductive layer;

[0055] Preferably, the second connection electrode is connected to the common electrode via a ninth via, the ninth via extending from the sixth insulating layer to the second insulating layer along the thickness direction of the array substrate;

[0056] Preferably, the orthographic projection of the ninth via on the substrate is located within the orthographic projection of the first source / drain region of the third active portion on the substrate;

[0057] Preferably, the second connection electrode is connected to the first source / drain region of the third active part via a tenth via, and the first source / drain region of the third active part is connected to the common electrode via an eleventh via. The tenth via extends from the sixth insulating layer to the second active layer along the thickness direction of the array substrate, and the eleventh via extends from the fourth insulating layer to the first conductive layer along the thickness direction of the array substrate.

[0058] Preferably, the filling material of the eleventh via is the same as the material of the second active layer.

[0059] In one embodiment, the first active layer is a polycrystalline silicon active layer, and the second active layer is an oxide active layer.

[0060] In one embodiment, a display panel is provided, including the array substrate described in any of the above embodiments.

[0061] The aforementioned array substrate and display panel have two active layers, namely a first active layer and a second active layer, on one side of the substrate. The two active layers partially overlap in their orthogonal projections onto the substrate, causing the transistors formed on them to be stacked along the thickness direction of the array substrate. The area occupied by the transistors formed in the upper active layer covers the area occupied by the transistors formed in the lower active layer. This design maximizes the saving of horizontal and vertical space on the array substrate, reducing the area occupied by the pixel circuitry and increasing the pixel density. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a schematic cross-sectional view of the array substrate in one embodiment;

[0064] Figure 2 This is a schematic diagram of the cross-sectional structure of the array substrate in another embodiment;

[0065] Figure 3 This is a schematic diagram of a partial layout structure in one embodiment;

[0066] Figure 4 This is a schematic diagram of a partial layout structure in another embodiment;

[0067] Figure 5 This is a schematic diagram of a partial layout structure in another embodiment;

[0068] Figure 6 This is a schematic diagram of a partial layout structure in another embodiment;

[0069] Figure 7 This is a schematic diagram of a partial layout structure in another embodiment;

[0070] Figure 8 This is a schematic diagram of a partial layout structure in another embodiment;

[0071] Figure 9 This is a schematic diagram of a partial layout structure in another embodiment;

[0072] Figure 10 This is a schematic diagram of a partial layout structure in another embodiment;

[0073] Figure 11 This is a schematic diagram of a partial layout structure in another embodiment;

[0074] Figure 12 This is a schematic diagram of the cross-sectional structure of the array substrate in another embodiment;

[0075] Figure 13 This is a schematic diagram of the pixel circuit in one embodiment;

[0076] Figure 14 This is a schematic diagram of the control timing corresponding to the pixel circuit in one embodiment;

[0077] Figure 15 This is a schematic diagram of the structure of the display panel in one embodiment. Detailed Implementation

[0078] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0079] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0080] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0081] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0082] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0083] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0084] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0085] In recent years, with the continuous increase in shipments of VR (Virtual Reality) products, developing display panels with higher PPI (Pixel Per Inch) has become a major demand from users.

[0086] However, the inventors discovered that while mainstream silicon-based OLED (Organic Light Emitting Diode) solutions can achieve high PPI, their reliance on silicon-based backplanes for semiconductor processes results in high costs and limits screen size, becoming a major bottleneck for the widespread adoption of VR products. Compared to silicon-based OLEDs, glass-based OLEDs have lower costs, but as the PPI increases (≥800), the pixel area shrinks dramatically. Space constraints mean that only fewer TFTs (Thin Film Transistors) and signal lines can be used to achieve the pixel circuit compensation effect.

[0087] Based on this, this application provides an array substrate design scheme suitable for high PPI pixel circuits, with the aim of achieving a higher PPI to meet the display requirements of VR devices.

[0088] The display panel provided in the embodiments of this application will be described first below.

[0089] Figure 1 The diagram shown is a structural schematic of an array substrate provided in an embodiment of this application.

[0090] In one exemplary embodiment, see Figure 1The array substrate provided in this application includes: a substrate 100; a first active layer PSI1 located on one side of the substrate 100; a second active layer PSI2 located on the side of the first active layer PSI1 facing away from the substrate 100; a first transistor T1 and a second transistor T2, the first transistor T1 including a first active portion 110, the second transistor T2 including a second active portion 120, the first active portion 110 and the second active portion 120 being disposed on the first active layer PSI1; a third... Transistor T3 includes a third active portion 130, which is disposed on the second active layer PSI2. The channel region 131 of the third active portion 130 is at least partially located within the orthogonal projection of the channel region 111 of the first active portion 110 onto the substrate 100, and the orthogonal projection of the channel region 131 of the third active portion 130 onto the substrate 100 is located outside the orthogonal projection of the channel region 121 of the second active portion 120 onto the substrate 100.

[0091] Specifically, the first active layer PSI1 and the second active layer PSI2 are important film layers defining the conductive channel region of the transistor, and are actually semiconductor-like layers in thin-film transistors. In this application, the first active layer PSI1 is located on one side of the substrate 100, and the second active layer PSI2 is located on the side of the first active layer PSI1 facing away from the substrate 100; that is, the second active layer PSI2 is stacked on top of the first active layer PSI1. Furthermore, the orthographic projections of the two active layers onto the substrate 100 can be designed to partially overlap, allowing the transistors defined on them to be stacked and arranged in the thickness direction of the array substrate, thereby reducing the space occupied by the pixel circuitry.

[0092] It is understandable that, depending on the specific type of transistor to be formed, the first active layer PSI1 and the second active layer PSI2 can be made of different types of semiconductor materials, such as polysilicon, oxide semiconductor, or other semiconductor materials. Furthermore, they can be made of the same material or different materials, depending on the actual pixel circuit requirements.

[0093] In one example, the first active layer PSI1 is a polycrystalline silicon active layer, and the second active layer PSI2 is an oxide active layer. That is, in this embodiment, the transistor defined by the first active layer PSI1 is a polycrystalline silicon thin-film transistor, while the transistor defined by the second active layer PSI2 is an oxide thin-film transistor. Since the oxide active layer is disposed above the polycrystalline silicon active layer, and there are other films such as the first conductive layer M1 in between, the hydrogen, oxygen, and dopants generated during the fabrication of the polycrystalline silicon active layer will not diffuse into the oxide active layer, thus effectively ensuring the performance of the formed oxide thin-film transistor.

[0094] Correspondingly, the channel region and source / drain region of the first transistor T1 and the second transistor T2 can be defined in the first active layer PSI1. The first transistor T1 includes a first active portion 110, and the second transistor T2 includes a second active portion 120. The first active portion 110 and the second active portion 120 are disposed in the first active layer PSI1. The channel region and source / drain region of the third transistor T3 can be defined in the second active layer PSI2. The third transistor T3 includes a third active portion 130, and the third active portion 130 is disposed in the second active layer PSI2.

[0095] Most importantly, in this application, the orthographic projection of the channel region 131 of the third active portion 130 onto the substrate 100 is at least partially located within the orthographic projection of the channel region 111 of the first active portion 110 onto the substrate 100, and the orthographic projection of the channel region 131 of the third active portion 130 onto the substrate 100 is located outside the orthographic projection of the channel region 121 of the second active portion 120 onto the substrate 100. That is, the orthographic projection of the third transistor T3 onto the substrate overlaps with the orthographic projection of the first transistor T1 onto the substrate, and the two are stacked in the thickness direction of the array substrate. However, the orthographic projection of the third transistor T3 onto the substrate does not completely overlap with the orthographic projection of the second transistor T2 onto the substrate, and the two are staggered in the thickness direction of the array substrate. Ultimately, a first transistor T1, a second transistor T2, and a third transistor T3 are formed, stacked and staggered in the thickness direction of the array substrate, with the first transistor T1 and the second transistor T2 located at the bottom and the third transistor T3 located at the top. This maximizes the saving of horizontal and vertical space on the array substrate, which is beneficial for achieving a higher pixel density (PPI).

[0096] It is understandable that capacitors and other connection terminals of each transistor can be set between the first active layer PSI1 and the second active layer PSI2 to form a complete pixel circuit. By designing signal lines within the display area to control the array arrangement of the pixel circuit, the pixel circuit can drive the light-emitting elements to emit light, thereby realizing the pattern display on the display panel.

[0097] For example, the substrate 100 serves as a support base for the array substrate and is typically made of glass, polymer, or other insulating materials.

[0098] In this embodiment, two active layers, namely a first active layer and a second active layer, are designed on one side of the substrate. The two active layers partially overlap in their orthogonal projections onto the substrate, causing the transistors formed on them to be stacked in the thickness direction of the array substrate. The area occupied by the transistors formed in the upper active layer covers the area occupied by the transistors formed in the lower active layer. This design maximizes the saving of horizontal and vertical space on the array substrate, reducing the area occupied by the pixel circuit and increasing the pixel density. Furthermore, the first transistor T1 and the second transistor T2, as part of the pixel circuit, have their active parts designed to have a common terminal. This common terminal is led out to form a common electrode and connected to the first electrode (anode), realizing the sharing of the anode node. This enables functions such as anode reset or driving light emission of the light-emitting element, further reducing the horizontal space occupied by the pixel circuit and facilitating a higher pixel density.

[0099] Figure 2 The diagram shown is a cross-sectional structural schematic of an array substrate provided in an embodiment of this application. Figures 3 to 10 The diagram shown is a partial layout structure of an array substrate provided in several embodiments of this application. Figure 11 The diagram shown is a cross-sectional structural schematic of an array substrate provided in another embodiment of this application.

[0100] In one exemplary embodiment, reference is made to Figure 2 The array substrate further includes: a first conductive layer M1 located between the first active layer PSI1 and the second active layer PSI2; a first electrode located on the side of the second active layer PSI2 away from the substrate 100; and the second electrode of the first transistor T1 and the second electrode of the second transistor T2 connected to form a common electrode 21, which is located in the first conductive layer M1 and connected to the first electrode.

[0101] Specifically, the first electrode, which is the anode of the light-emitting element, is disposed on the side of the second active layer PSI2 away from the substrate 100. It is typically made of a transparent conductive material such as indium tin oxide (ITO) and is used as the anode electrode of the light-emitting element (such as an OLED). The first transistor T1 and the second transistor T2, as part of the pixel circuit, can be connected to the anode to realize functions such as anode reset or driving light emission of the light-emitting element.

[0102] In this design, based on the stacked and staggered arrangement of the first transistor T1, the second transistor T2, and the third transistor T3 along the thickness direction of the array substrate, to further save space, the first transistor T1 and the second transistor T2 can be designed to share a common anode node. Specifically, the first active portion 110 and the second active portion 120 can be designed to share a common source-drain region. This common source-drain region can be led out through vias to the first conductive layer M1 to form a common electrode 21. Then, through the common electrode 21 and the space where the second transistor T2 and the third transistor T3 are staggered, it connects upwards to the anode, achieving a shared anode node. This design can further reduce the lateral space occupied by the pixel circuit, which is beneficial for achieving a higher pixel density.

[0103] Furthermore, when either the first transistor T1 or the second transistor T2 is used as a driving transistor, the active parts of the two transistors are designed to have a common region, for example... Figure 1 The second source-drain region of the active part of the first transistor T1 is shared with the second source-drain region of the active part of the second transistor T2. This allows for a longer channel region design for the driving transistor, i.e., a longer distance between the source and drain of the driving transistor. This reduces the relative impact of process variations on transistor characteristics, improves the uniformity of the entire panel display, and makes the driving transistor's response to the control voltage smoother and more linear. It also allows for finer control of the driving current, enabling more and more accurate grayscale, improving color transitions, and effectively enhancing the display effect.

[0104] In one exemplary embodiment, reference is made to Figure 2 The array substrate further includes: a second conductive layer M2, located between the first active layer PSI1 and the first conductive layer M1; the first transistor T1 further includes a first gate G1, which is located in the second conductive layer M2, and the orthographic projection of the first gate G1 onto the first active layer PSI1 covers the channel region 111 of the first active portion 110, and the first gate G1 is electrically connected to the second source / drain region 143 of the fourth active portion 140; the second transistor T2 further includes a second gate G2, which is located in the second conductive layer M2, and the orthographic projection of the second gate G2 onto the first active layer PSI1 covers the channel region 121 of the second active portion 120.

[0105] Specifically, a second conductive layer M2 is disposed between the first active layer PSI1 and the first conductive layer M1, and a first gate G1 of the first transistor T1 is disposed on the second conductive layer M2. The first gate G1, projected onto the first active layer PSI1, covers the channel region 111 of the first active portion 110. When a suitable voltage is applied to the first gate G1, a conductive channel, i.e., the channel region 111, is induced on the corresponding surface of the first active portion 110, thereby controlling the flow of charge from the channel region 111 through an electric field. (Refer to...) Figure 3This can be understood as the channel region 111 being the area formed by the overlap of the first gate G1 and the first active portion 110 on the first conductive layer M1. It should be noted that the channel region is directional. When a suitable voltage is applied to the gate covering it, current is allowed to flow from the first source-drain region of the active portion through the channel region to the second source-drain region, so as to realize the flow of current between the source and drain of the first transistor T1.

[0106] The first gate G1 is electrically connected to the second source-drain region 143 of the fourth active part 140 of the third transistor T3, so that the gate of the first transistor T1 is connected to the drain of the third transistor T3, and the on / off state of the first transistor T1 can be controlled by the voltage of the drain of the third transistor T3.

[0107] Similarly, a second gate G2 of the second transistor T2 is also disposed on the second conductive layer M2, and the second gate G2, when projected onto the first active layer PSI1, covers the channel region 121 of the second active portion 120. (Refer to...) Figure 3 The channel region 121 can be understood as the region formed by the overlap of the second gate G2 and the second active portion 120 on the first conductive layer M1. When a suitable voltage is applied to the second gate G2, a conductive channel, namely the channel region 121, will be induced on the corresponding surface of the second active portion 120, allowing current to flow from the first source-drain region 122 to the second source-drain region 123 of the second active portion 120, so as to realize the flow of current between the source and drain of the second transistor T2.

[0108] For one example, please refer to... Figure 2 and Figure 4 A first gate insulating layer GI1 is provided between the second conductive layer M2 and the first active layer PSI1, and a first insulating layer CI1 is provided between the first conductive layer M1 and the second conductive layer M2. The common electrode 21 is connected to the second source / drain region 113 of the first active part 110 and the second source / drain region 123 of the second active part 120 through the first via ILD1. The first via ILD1 passes through the first insulating layer CI1 and the first gate insulating layer GI1 in sequence.

[0109] Specifically, a first gate insulating layer GI1 is provided between the second conductive layer M2 and the first active layer PSI1 for isolation, and a first insulating layer CI1 is also provided between the first conductive layer M1 and the second conductive layer M2 for isolation, so as to prevent the two layers from directly contacting each other and short-circuiting.

[0110] Furthermore, a first via ILD1 is provided through the first insulating layer CI1 and the first gate insulating layer GI1 so that the common electrode 21 can be connected to the second source / drain region 113 of the first active part 110 and the second source / drain region 123 of the second active part 120 through the through-through first via ILD1. This realizes that the first active part 110 and the second active part 120 are designed to have a common region, and the common region is led out to the first conductive layer M1 through the first via ILD1 to form the common electrode 21. Then, the common electrode 21 is connected to the first electrode (anode), so that the first transistor T1 and the second transistor T2 share the same anode node.

[0111] In this embodiment, when the first transistor T1 and the second transistor T2 share the same anode node, the connection structure between the first active part 110, the second active part 120 and the common electrode 21 is optimized by multiple insulating layers, which further reduces the lateral space occupied by the pixel circuit and is conducive to achieving a higher pixel arrangement density.

[0112] In one example, the first transistor T1 is a driving transistor, which plays the role of driving the light-emitting element in the pixel circuit.

[0113] In one example, the second transistor T2 is a reset transistor, which plays a role in resetting the driving transistor and the light-emitting element in the pixel circuit.

[0114] In one example, refer to Figure 3 The array substrate also includes a first scan signal line Scan1, and the second gate G2 of the second transistor T2 is connected to the first scan signal line Scan1. Specifically, the first scan signal line Scan1 is used to input the first scan signal S1 to the second gate G2 of the second transistor T2 so that the second transistor T2 is turned on during the effective period of the first scan signal S1. When the second transistor T2 is used as a reset transistor, it can introduce a reset voltage to the pixel circuit under the action of the first scan signal S1 to reset the gates of other transistors in the pixel circuit, and also to reset the anode of the light-emitting element.

[0115] For one example, please refer to... Figure 2 and Figure 4 The first electrode 22 of the second transistor T2 is located in the first conductive layer M1. The first electrode 22 of the second transistor T2 is connected to the first source-drain region 122 of the second active part 120 through the second via ILD2. The second via ILD2 passes through the first insulating layer CI1 and the first gate insulating layer GI1 in sequence.

[0116] Specifically, a second via ILD2 is also provided through the first insulating layer CI1 and the first gate insulating layer GI1, so that the first electrode 22 of the second transistor T2 is connected to the first source-drain region 122 of the second active part 120 through the through-hole ILD2. Based on this, the first via ILD1 through which the common electrode 21 passes is connected to the second source-drain region 123 of the second active part 120, thus realizing a current flow path in the second active part 120. The first electrode 22 of the second transistor T2 can serve as the source of the second transistor T2, and the common electrode 21 can serve as the drain of the second transistor T2. Furthermore, when a suitable voltage is applied to the second gate G2, current flows from the source of the second transistor T2 through the second active part 120 to the drain of the second transistor T2.

[0117] In one example, the array substrate also includes a reset signal line, with the first terminal 22 of the second transistor T2 connected to the reset signal line. Specifically, a reset voltage Vref is transmitted on the reset signal line. When the second transistor T2 is in the on state, the reset voltage Vref is introduced into the pixel circuit via the first terminal 22, the second active part 120, and the common terminal 21 of the second transistor T2 to achieve gate reset of other transistors in the pixel circuit, and can also achieve reset of the anode of the light-emitting element.

[0118] In one exemplary embodiment, please continue to refer to Figure 2 and Figure 4 The array substrate further includes: a first connecting plate 31 located in the first conductive layer M1, the first connecting plate 31 being connected to the first gate G1 via the third via ILD3 in the first insulating layer CI1, and the first gate G1 being connected to the second source / drain region 133 of the third active portion 130 via the first connecting plate 31.

[0119] Specifically, a first connecting plate 31 is provided on the first conductive layer M1, and a third via ILD3 is provided through the first insulating layer CI1. The first connecting plate 31 can be connected to the first gate G1 through the through third via ILD3, so that the first gate G1 is connected to the second source-drain region 133 of the third active part 130 of the third transistor T3 through the first connecting plate 31.

[0120] It is understandable that, since the second active layer PSI2 is stacked above the first active layer PSI1, and the two are further stacked with a second conductive layer M2, a first conductive layer M1, and other multiple insulating layers, when connecting the third active portion 130 disposed on the second active layer PSI2 to the first gate G1, the first gate G1 disposed on the second conductive layer M2 can be designed to be led up to the first conductive layer M1 through the third via ILD3, and the first connecting plate 31 can be used as the first gate G1 to connect with the second source / drain region 133 of the third active portion 130 of the third transistor T3. This design can reduce the drilling depth when the third active portion 130 of the second active layer PSI2 is connected to the first gate G1, avoiding the process problems of insufficient or over-etching caused by deep holes, and also making the subsequent hydrogen plasma treatment (conductivity) effect excellent, resulting in a higher quality, lower resistance, and better consistency of the formed conductive region.

[0121] In one exemplary embodiment, please continue to refer to Figure 2 The array substrate further includes: a third conductive layer M3 located between the first conductive layer M1 and the second active layer PSI2; a fourth conductive layer M4 located between the third conductive layer M3 and the second active layer PSI2; a first capacitor C1 and a second capacitor C2, the first capacitor C1 and the second capacitor C2 including a common electrode 32 located in the third conductive layer M3, a first connecting electrode 31 serving as the other electrode of the first capacitor C1, the second capacitor C2 further including a second electrode 33 located in the fourth conductive layer M4, the orthographic projection of the first connecting electrode 31 on the substrate 100 being at least partially located within the orthographic projection of the common electrode 32 on the substrate 100, and the orthographic projection of the second electrode 33 on the substrate 100 being at least partially located within the orthographic projection of the common electrode 32 on the substrate 100.

[0122] Specifically, a third conductive layer M3 is disposed between the first conductive layer M1 and the second active layer PSI2, and a fourth conductive layer M4 is also disposed between the third conductive layer M3 and the second active layer PSI2. A common electrode 32 is disposed on the third conductive layer M3, which can serve as one of the capacitor electrodes shared by the first capacitor C1 and the second capacitor C2. A second electrode 33 is disposed on the fourth conductive layer M4, serving as the other capacitor electrode of the second capacitor C2. (See also...) Figure 5 As shown, the orthographic projection of the second electrode 33 onto the substrate 100 is at least partially located within the orthographic projection of the common electrode 32 onto the substrate 100, so that the common electrode 32 and the second electrode 33 form a second capacitor C2. The capacitor electrode on the other side of the first capacitor C1 can be implemented using the first connecting electrode 31, and the orthographic projection of the first connecting electrode 31 onto the substrate 100 is at least partially located within the orthographic projection of the common electrode 32 onto the substrate 100, so that the first capacitor C1 is formed through the first connecting electrode 31 and the common electrode 32.

[0123] It is understandable that, under the above-described membrane structure design, the common electrode 32 sandwiched between the second electrode 33 and the first connecting electrode 31 can form a sandwich capacitor structure. The capacitance value of the sandwich capacitor structure is larger than that of a capacitor structure with only two electrode layers, greatly increasing the total storage capacitance.

[0124] For one example, please refer to... Figure 2 The orthographic projection of the common electrode 32 onto the substrate 100 is at least partially located within the orthographic projection of the first active part 110 onto the substrate 100.

[0125] Specifically, in the thickness direction of the array substrate, the common electrode plate 32 at least partially covers the first transistor T1, so that the first transistor T1, the first capacitor C1 and the second capacitor C2 are stacked in the thickness direction of the array substrate. The area occupied by the first capacitor C1 and the second capacitor C2 covers the area occupied by the first transistor T1, further reducing the lateral space occupied by the pixel circuit on the array substrate, which is conducive to achieving a higher pixel arrangement density.

[0126] For one example, please refer to... Figure 2 and Figure 6 A second insulating layer CI2 is provided between the first conductive layer M1 and the third conductive layer M3, a third insulating layer CI3 is provided between the third conductive layer M3 and the fourth conductive layer M4, and a fourth insulating layer CI4 is provided between the second active layer PSI2 and the fourth conductive layer M4. The first connecting electrode 31 is connected to the second source / drain region 133 of the third active part 130 through the fourth via ILD4. The fourth via ILD4 passes through the fourth insulating layer CI4, the third insulating layer CI3 and the second insulating layer CI2 in sequence.

[0127] Specifically, a second insulating layer CI2 is provided between the first conductive layer M1 and the third conductive layer M3 for isolation, a third insulating layer CI3 is provided between the third conductive layer M3 and the fourth conductive layer M4 for isolation, and a fourth insulating layer CI4 is provided between the second active layer PSI2 and the fourth conductive layer M4 for isolation, which can effectively prevent the two layers from directly contacting each other and short-circuiting.

[0128] Furthermore, a fourth via ILD4 is provided through the fourth insulating layer CI4, the third insulating layer CI3, and the second insulating layer CI2, so that the first connecting plate 31 can be connected to the second source-drain region 133 of the third active part 130 through the through-hole ILD4, realizing the connection between the first gate G1 of the first transistor T1 and the drain of the third transistor T3. Thus, the voltage at the drain of the third transistor T3 can be used to control the on / off state of the first transistor T1. At the same time, since the first connecting plate 31 also serves as one side plate of the first capacitor C1, and the first capacitor C1 and the second capacitor C2 are sandwich capacitors, the voltage at the drain of the third transistor T3 can also flow into the sandwich capacitor structure for storage.

[0129] For one example, please refer to... Figure 2 The filling material of the fourth via ILD4 is the same as that of the second active layer PSI2. Specifically, the fourth via ILD4 can be an inorganic via, using the same semiconductor material (such as IGZO) as the second active layer PSI2 to fabricate the via in the interlayer insulating layer. This design reduces the number of photomasks required for fabricating the array substrate, eliminating the need for a separate photomask step to fabricate the vias, significantly reducing cost and complexity, and improving production efficiency and yield. Furthermore, in terms of performance, the second active layer PSI2 and the via filling layer are physically a continuous, complete single-crystal or amorphous thin film, enabling lower resistance and more reliable electrical connections.

[0130] In one example, the array substrate also includes power signal lines, and the second electrode 33 is connected to the power signal lines. It can be understood that a positive power supply voltage VDD is applied to one electrode of the upper capacitor C2 in the aforementioned sandwich capacitor structure. When the voltage on the other side of capacitor C2 (common electrode 32) attempts to decrease due to leakage, the positive power supply voltage VDD provides a very stable voltage value to the common electrode 32 of the sandwich capacitor through capacitive coupling, thereby improving the stability of the voltage on the common electrode 32.

[0131] In one exemplary embodiment, please continue to refer to Figure 2 The array substrate also includes: a fifth conductive layer M5, located on the side of the second active layer PSI2 away from the substrate 100; the third transistor T3 is a dual-gate transistor, the third transistor T3 includes a third top gate TG3 and a third bottom gate BG3, the third top gate TG3 is located in the fifth conductive layer M5, the orthogonal projection of the third top gate TG3 covers the channel region 131 of the third active portion 130, and the third bottom gate BG3 reuses the second electrode plate 33.

[0132] In one exemplary embodiment, please continue to refer to Figure 2The array substrate further includes: a fourth transistor T4, which includes a fourth active portion 140 disposed on the second active layer PSI2. The orthographic projection of the channel region 141 of the fourth active portion 140 onto the substrate 100 is outside the orthographic projection of the channel region 111 of the first active portion 110 onto the substrate 100. The fourth transistor T4 is a dual-gate transistor, which includes a fourth top gate TG4 and a fourth bottom gate BG4. The fourth top gate TG4 is located on the fifth conductive layer M5, and the fourth bottom gate BG4 is located on the fourth conductive layer M4. The orthographic projection of the fourth top gate TG4 and the fourth bottom gate BG4 onto the second active layer PSI2 covers the channel region 141 of the fourth active portion 140.

[0133] Specifically, the channel region and source / drain region of the fourth transistor T4 can be defined in the second active layer PSI2. The fourth transistor T4 includes a fourth active portion 140, which is disposed in the second active layer PSI2. In this application, the orthographic projection of the channel region 141 of the fourth active portion 140 onto the substrate 100 is outside the orthographic projection of the channel region 111 of the first active portion 110 onto the substrate 100. That is, the orthographic projection of the fourth transistor T4 onto the substrate does not completely overlap with the orthographic projection of the first transistor T1 onto the substrate, and the two are staggered in the thickness direction of the array substrate. Ultimately, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are stacked and staggered in the thickness direction of the array substrate, with the first transistor T1 and the second transistor T2 located below, and the third transistor T3 and the fourth transistor T4 located above. This maximizes the saving of horizontal and vertical space on the array substrate, which is beneficial for achieving a higher pixel density (PPI).

[0134] Furthermore, a fifth conductive layer M5 is disposed on the side of the second active layer PSI2 facing away from the substrate 100. The third transistor T3 and the fourth transistor T4 are designed to be implemented using a dual-gate transistor structure, which has two independent gates, namely the top gate and the bottom gate. Both gates can be connected to an electric field to control the conduction and turn-off of the same channel.

[0135] The third transistor T3 may include a third top gate TG3 and a third bottom gate BG3. The third top gate TG3 is located in the fifth conductive layer M5, and the third bottom gate BG3 reuses the second electrode 33 and is located in the fourth conductive layer M4. The orthogonal projection of the third top gate TG3 onto the second active layer PSI2 covers the channel region 131 of the third active portion 130. (Refer to...) Figure 7The channel region 131 can be understood as the area formed by the overlap of the third top gate TG3 and the third active portion 130 on the fifth conductive layer M5. When a voltage is applied to either the third top gate TG3 or the third bottom gate BG3, a conductive channel, namely the channel region 131, will be induced on the corresponding surface of the third active portion 130, allowing current to flow from the first source-drain region 132 to the second source-drain region 133 of the third active portion 130, so as to realize the flow of current between the source and drain of the third transistor T3.

[0136] The fourth transistor T4 may include a fourth top gate TG4 and a fourth bottom gate BG4. The fourth top gate TG4 is located in the fifth conductive layer M5, and the fourth bottom gate BG4 is located in the fourth conductive layer M4. The orthogonal projection of the fourth top gate TG4 and the fourth bottom gate BG4 onto the second active layer PSI2 covers the channel region 141 of the fourth active portion 140. (Refer to...) Figure 7 The channel region 141 can be understood as the area formed by the overlap of the fourth top gate TG4 and the fourth active portion 140 on the fifth conductive layer M5. When a voltage is applied to either the fourth top gate TG4 or the fourth bottom gate BG4, a conductive channel, namely the channel region 141, will be induced on the corresponding surface of the fourth active portion 140, allowing current to flow from the first source-drain region 142 to the second source-drain region 143 of the fourth active portion 140, so as to realize the flow of current between the source and drain of the fourth transistor T4.

[0137] It should be noted that in this embodiment, the third bottom gate BG3 of the third transistor T3 is implemented using the second electrode plate 33. This can be understood as stacking the third transistor T3, the first capacitor C1, the second capacitor C2, and the first transistor T1 along the thickness direction of the array substrate. The area occupied by the third transistor T3 overlaps with the areas occupied by the first capacitor C1 and the second capacitor C2, further reducing the lateral space occupied by the pixel circuit on the array substrate, which is beneficial for achieving a higher pixel density.

[0138] After the third gate BG3 is implemented by multiplexing the second electrode plate 33, since the second electrode plate 33 is connected to the power signal line, the third gate BG3 is also connected to the power signal line. Since the fourth gate BG4 and the third gate BG3 are on the same film layer, the design can also connect the fourth gate BG4 to the power signal line, so that a fixed positive power supply voltage VDD is applied to the gates of the two dual-gate transistors.

[0139] This design serves two purposes. First, it ensures that the third transistor T3 and the fourth transistor T4 are reliably turned off during non-operating periods, eliminating brightness differences between pixels caused by inconsistent leakage current and improving uniformity. Second, when the transistors are turned on by the top gate's enable signal, a positive electric field can also be applied to the bottom gate, which is connected to the positive power supply voltage VDD. The two gates together "push" the charge carriers from both the top and bottom, forming a stronger conductive channel. This is especially important when rapid capacitor charging is required (such as during data writing) or when large currents need to be transferred, as it can shorten charging time and allow the pixel circuitry to operate normally at high refresh rates.

[0140] For one example, please refer to... Figure 2 and Figure 4 The first electrode 24 of the first transistor T1 is located in the first conductive layer M1. The first electrode 24 of the first transistor T1 is connected to the first source-drain region 112 of the first active part 110 through the sixth via ILD6. The sixth via ILD6 passes through the first insulating layer CI1 and the first gate insulating layer GI1 in sequence.

[0141] Specifically, a first electrode 24 of the first transistor T1 is disposed on the first conductive layer M1, and a sixth via ILD6 is disposed through the first insulating layer CI1 and the first gate insulating layer GI1, thereby connecting the first electrode 24 of the first transistor T1 to the first source-drain region 112 of the first active portion 110 via the through-hole ILD6. Furthermore, by connecting the first via ILD1 through which the common electrode 21 passes to the second source-drain region 113 of the first active portion 110, a current flow path can be realized in the first active portion 110. The first electrode 24 of the first transistor T1 can serve as the source of the first transistor T1, and the common electrode 21 of the first transistor T1 can serve as the drain of the first transistor T1. Furthermore, when a suitable voltage is applied to the first gate G1, current flows from the source of the first transistor T1 through the first active portion 110 to the drain of the first transistor T1.

[0142] In one example, refer to Figure 2 and Figure 5 The third bottom gate BG3 is connected to the first electrode 24 of the first transistor T1 via the seventh via ILD7. The seventh via ILD7 passes through the third insulating layer CI3 and the second insulating layer CI2 in sequence.

[0143] Specifically, a seventh via ILD7 is provided through the third insulating layer CI3 and the second insulating layer CI2, and the fourth bottom gate BG4 can be connected to the first electrode 24 of the first transistor T1 through the through seventh via ILD7.

[0144] This can be understood as follows: the fourth bottom gate BG4 is designed to connect to the power signal line to receive the positive power supply voltage VDD. Consequently, the first electrode 24 of the first transistor T1 also needs to be connected to the power signal line to obtain the positive power supply voltage VDD to drive the light-emitting element. Therefore, the position of the first electrode 24 of the first transistor T1 can be designed directly below the fourth bottom gate BG4, meaning the orthographic projection of the first electrode 24 of the first transistor T1 onto the substrate lies within the orthographic projection of the fourth bottom gate BG4 onto the substrate. Furthermore, a vertical hole can be drilled in the fourth bottom gate BG4 to input the positive power supply voltage VDD to the first electrode 24 of the first transistor T1.

[0145] Furthermore, from Figure 5 As can be seen, the fourth bottom gate BG4 extends along the first direction (Y) on the plane of the array substrate, while the first electrode 24 extends along the second direction (X) on the plane of the array substrate, and the first direction (Y) and the second direction (X) are two mutually perpendicular directions. This allows for the formation of a mesh of power signal lines within the display area. This not only saves space for the power signal lines, which is beneficial for pixel miniaturization and increasing pixel density, but also reduces the voltage difference of the positive power supply voltage in different areas of the display area, resulting in more uniform brightness of the display panel and effectively improving the display quality.

[0146] In one example, the third transistor T3 is a threshold compensation transistor that compensates for the threshold voltage of other transistors in the pixel circuit, thereby reducing the brightness difference between pixels and making the display panel display uniform.

[0147] In one example, refer to Figure 7 The array substrate also includes a second scan signal line Scan2, and the third top gate TG3 of the third transistor T3 is connected to the second scan signal line Scan2. Specifically, the second scan signal line Scan2 is used to input the second scan signal S2 to the third top gate TG3 of the third transistor T3 so that the third transistor T3 is turned on during the effective period of the second scan signal S2. When the third transistor T3 is used as a threshold compensation transistor, it can compensate for the threshold voltage of other transistors in the pixel circuit under the action of the second scan signal S2.

[0148] For one example, please refer to... Figure 2 and Figure 8 The second electrode 23 of the fourth transistor T4 is located in the third conductive layer M3. The second electrode 23 of the fourth transistor T4 is connected to the second source-drain region 143 of the fourth active part 140 through the fifth via ILD5. The fifth via ILD5 passes through the fourth insulating layer CI4 and the third insulating layer CI3 in sequence.

[0149] Specifically, the second electrode 23 of the fourth transistor T4 is disposed on the third conductive layer M3, and a fifth via ILD5 is disposed through the fourth insulating layer CI4 and the third insulating layer CI3, so that the second electrode 23 of the fourth transistor T4 can be connected to the second source-drain region 143 of the fourth active part 140 through the through fifth via ILD5.

[0150] In one example, refer to Figure 2 and Figure 8 The second electrode 23 of the fourth transistor T4 is multiplexed with the common electrode 32, and the orthographic projection of the fifth via ILD5 on the substrate 100 is located within the orthographic projection of the first connecting electrode 31 on the substrate 100.

[0151] Specifically, the first connecting plate 31 is the pole of the first gate G1 leading to the first conductive layer M1, and also serves as the lower plate of the sandwich capacitor structure. The common plate 32 is the middle plate of the sandwich capacitor structure. In this embodiment, the second pole 23 of the fourth transistor T4 is connected to the middle plate of the sandwich capacitor structure through the fifth via ILD5, and the orthogonal projection of the fifth via ILD5 onto the substrate 100 is located within the orthogonal projection of the first connecting plate 31 onto the substrate 100. This effectively increases the plate area of ​​the lower part of the capacitor (capacitor C1) in the sandwich capacitor structure, which is beneficial for forming a larger storage capacitor.

[0152] For an example, please refer to Figure 2 , Figure 8 and Figure 9 The common electrode plate 32 includes a first electrode plate portion 321, a connecting portion 322 and a second electrode plate portion 323. The connecting portion 322 connects the first electrode plate portion 321 and the second electrode plate portion 323. In the first direction, the first electrode plate portion 321, the fourth through hole IDL4 and the second electrode plate portion 323 are arranged sequentially. In the second direction perpendicular to the first direction, the fourth through hole IDL4 is located on one side of the connecting portion 322.

[0153] Specifically, refer to Figure 8 and 9 As shown, the first direction can be the Y direction, and the second direction can be the X direction. In the Y direction, the first electrode portion 321, the fourth through hole IDL4, and the second electrode portion 323 are sequentially arranged, and in the X direction, the fourth through hole IDL4 is located on one side of the connecting portion 322. From... Figure 9 As can be seen, a clearance region 324 is designed between the first electrode plate portion 321 and the second electrode plate portion 323, and the orthographic projection of the fourth via IDL4 on the substrate 100 is located within the orthographic projection of the clearance region 324 on the substrate 100.

[0154] This design allows the first connecting plate 31 to be connected to the second source / drain portion 133 of the third active portion 130 via the fourth via ILD4. This connection can be achieved by vertically punching holes in the clearance area 324 of the shared plate 32. This not only ensures that the capacitor C1 has a sufficiently large plate area, but also cleverly utilizes the vertical space to reduce the lateral space occupied by the pixel circuit on the array substrate, which is beneficial for achieving a higher pixel density.

[0155] In one example, the fourth transistor T4 is a data writing transistor, and the array substrate also includes a data signal line. The first terminal 25 of the fourth transistor T4 is connected to the data signal line. Specifically, a data voltage is transmitted on the data signal line to write the data voltage corresponding to the display data into the pixel circuit, thereby adjusting the voltage or current of the light-emitting element driven by the pixel circuit.

[0156] In one example, refer to Figure 7 The array substrate also includes a third scan signal line Scan3, and the fourth top gate TG4 of the fourth transistor T4 is connected to the third scan signal line Scan3. Specifically, the third scan signal line Scan3 is used to input the third scan signal S3 to the fourth top gate TG4 of the fourth transistor T4, so that the fourth transistor T4 is turned on during the effective period of the third scan signal S3. When the fourth transistor T4 is used as a data writing transistor, it can introduce a data voltage to the pixel circuit under the action of the third scan signal S3 to realize data writing to the pixel circuit.

[0157] It should be noted that when the fourth transistor T4 is used as a data write transistor, after the data voltage is introduced into the pixel circuit, since the second electrode 23 of the fourth transistor T4 is multiplexed using the common electrode 32, the input data voltage can be stored in the middle electrode (common electrode 32) of the sandwich capacitor structure. Furthermore, since a positive power supply voltage VDD is applied to the upper electrode (second electrode 33) of the sandwich capacitor structure, the input node of the data voltage will be sandwiched between the upper power signal line and the lower first gate G1 due to the sandwich capacitor structure. The data voltage will be strictly controlled between the two stable voltage reference layers to prevent it from being interfered with by other signals, ensuring that the voltage is stable from the beginning to the end of the frame, and that each pixel can emit light strictly according to the instructions, ultimately achieving uniform and stable display quality.

[0158] For one example, please refer to... Figure 2The filling material of the fifth via ILD5 is the same as that of the second active layer PSI2. Similar to the fourth via ILD4, the fifth via ILD5 is also an inorganic via, using the same semiconductor material (such as IGZO) as the second active layer PSI2 to fabricate the via in the interlayer insulating layer. This design reduces the number of photomasks required for array substrate fabrication, eliminating the need for a separate photomask step to fabricate the vias, significantly reducing cost and complexity, and improving production efficiency and yield. Furthermore, in terms of performance, the second active layer PSI2 and the via filling layer are physically a continuous, complete single-crystal or amorphous thin film, enabling lower resistance and more reliable electrical connections.

[0159] For one example, please refer to... Figure 2 and Figure 10 The array substrate also includes a sixth conductive layer M6, located on the side of the fifth conductive layer M5 facing away from the substrate 100. The first electrode 25 of the fourth transistor T4 is located in the sixth conductive layer M6. A second gate insulating layer GI2 is provided between the second active layer PSI2 and the fifth conductive layer M5, and a fifth insulating layer CI5 is provided between the fifth conductive layer M5 and the sixth conductive layer M6. The first electrode 25 of the fourth transistor T4 is connected to the first source / drain region 142 of the fourth active part 140 through an eighth via ILD8. The eighth via ILD8 passes through the fifth insulating layer CI5 and the second gate insulating layer GI2 in sequence.

[0160] Specifically, a sixth conductive layer M6 is disposed on the side of the fifth conductive layer M5 facing away from the substrate 100. A second gate insulating layer GI2 is disposed between the second active layer PSI2 and the fifth conductive layer M5, and a fifth insulating layer CI5 is disposed between the fifth conductive layer M5 and the sixth conductive layer M6. The first electrode 25 of the fourth transistor T4 is disposed on the sixth conductive layer M6. An eighth via ILD8 is disposed through the fifth insulating layer CI5 and the second gate insulating layer GI2, allowing the first electrode 25 of the fourth transistor T4 to be connected to the first source / drain region 142 of the fourth active portion 140 via the through-hole ILD8. Furthermore, by connecting the second electrode 23 of the fourth transistor T4 to the second source / drain region 143 of the fourth active portion 140 via the through-hole ILD5, a current flow path can be realized in the fourth active portion 140. The first electrode 25 of the fourth transistor T4 can serve as the source of the fourth transistor T4, and the second electrode 23 of the fourth transistor T4 can serve as the drain of the fourth transistor T4. Furthermore, when a suitable voltage is applied to the third top gate TG3, current flows from the source of the fourth transistor T4 through the fourth active part 140 to the drain of the fourth transistor T4.

[0161] In one exemplary embodiment, please continue to refer to Figure 2 and Figure 11The array substrate further includes: a seventh conductive layer M7, located on the side of the sixth conductive layer M6 facing away from the substrate 100; and a second connection electrode 26, located on the seventh conductive layer M7, which is connected to both the common electrode 21 and the anode. A sixth insulating layer CI6 is provided between the sixth conductive layer M6 and the seventh conductive layer M7. The second connection electrode 26 is connected to the common electrode 21 via a ninth via ILD9, which extends along the thickness direction of the array substrate from the sixth insulating layer CI6 to the second insulating layer CI2.

[0162] Specifically, a seventh conductive layer M7 is disposed on the side of the sixth conductive layer M6 facing away from the substrate 100, and a sixth insulating layer CI6 is disposed between the sixth conductive layer M6 and the seventh conductive layer M7. A ninth via ILD9 is disposed along the thickness direction of the array substrate, passing through the sixth insulating layer CI6, the fifth insulating layer CI5, the second gate insulating layer GI2, the fourth insulating layer CI4, the third insulating layer CI3, and the second insulating layer CI2. A second connection electrode 26 is disposed on the seventh conductive layer M7. The upper interface layer of the second connection electrode 26 is in contact with the anode, and the lower interface layer is connected to the common electrode 21 through the through-hole ninth via ILD9, thus connecting the common electrode 21 to the anode.

[0163] It can be understood that when the second transistor T2 is used as a reset transistor, it is connected to the anode through the common terminal 21, thus resetting the anode of the light-emitting element. When the first transistor T1 is used as a drive transistor, it is connected to the anode through the common terminal 21, thus outputting drive current to drive the light-emitting element to emit light.

[0164] For one example, please refer to... Figure 2 The orthographic projection of the ninth via ILD9 on the substrate 100 overlaps with the orthographic projection of the first source / drain region 132 of the third active portion 130 on the substrate 100.

[0165] Specifically, when the orthogonal projection of the ninth via ILD9 onto the substrate 100 is located within the orthogonal projection of the first source / drain region 132 of the third active portion 130 onto the substrate 100, the ninth via ILD9 can penetrate the second active layer PSI2 at the location of the first source / drain region 132 of the third active portion 130. Thus, while achieving the connection between the common electrode 21 and the anode, the sidewall overlap of the ninth via ILD9 on the third active portion 130 allows the common electrode 21 to connect with the first source / drain region 132 of the third active portion 130 of the third transistor T3. Furthermore, when the second transistor T2 is used as a reset transistor, the reset signal can be transmitted to the gate of the first transistor T1 (driving transistor) via the third transistor T3, thereby resetting the gate of the driving transistor.

[0166] In this embodiment, the reset signal resets the gate of the driving transistor and the anode of the light-emitting element by overlapping the sidewall of the second active layer PSI2 through the ninth via ILD9. The vertical space is cleverly used for wiring connection, reducing the lateral space occupied by the pixel circuit on the array substrate, which is conducive to achieving a higher pixel arrangement density.

[0167] For an example, please refer to Figure 12 The second connecting electrode 26 is connected to the first source / drain region 132 of the third active part 130 via the tenth via ILD10. The first source / drain region 132 of the third active part 130 is connected to the common electrode 21 via the eleventh via ILD11. The tenth via ILD10 extends from the sixth insulating layer CI6 to the second active layer PSI2 along the thickness direction of the array substrate. The eleventh via ILD11 extends from the fourth insulating layer CI4 to the first conductive layer M1 along the thickness direction of the array substrate.

[0168] It is understandable that the ninth via ILD9 designed in the previous embodiment is a deep via penetrating multiple layers. In etching technology, as the etching depth increases, the etching process is prone to drilling effect, that is, the bottom of the hole is etched normally, but the top entrance is also etched laterally, resulting in the final hole shape being larger at the top and smaller at the bottom. When the upper opening of the hole becomes too large due to drilling, the originally designed upper metal pattern may not be able to completely cover this enlarged opening, resulting in weak edge coverage or even breakage, also known as insufficient edge coverage.

[0169] Correspondingly, this embodiment can be decomposed into connecting the common electrode 21 and the anode through two shallow holes with relatively low difficulty, namely the tenth via ILD10 and the eleventh via ILD11. The tenth via ILD10 passes through the sixth insulating layer CI6, the fifth insulating layer CI5, and the second gate insulating layer GI2 to the second active layer PSI2, while the eleventh via ILD11 passes through the fourth insulating layer CI4, the third insulating layer CI3, and the second insulating layer CI2 to the first conductive layer M1. This achieves the following: firstly, the second connecting electrode 26 is connected to the first source / drain region 132 of the third active part 130 through the penetrating tenth via ILD10; then, the first source / drain region 132 of the third active part 130 is connected to the common electrode 21 through the penetrating eleventh via ILD11.

[0170] In one example, the filling material of the eleventh via ILD11 is the same as that of the second active layer PSI2. This can be understood as the eleventh via ILD11 being fabricated using the same semiconductor material (such as IGZO) as the second active layer PSI2.

[0171] In this embodiment, by decomposing the deep hole that penetrates multiple layers into two shallow holes with lower difficulty, and using a stable conductive layer (IGZO) as a transfer station, the inherent edge-wrapping deficiency in the deep hole processing technology is avoided, thereby achieving higher connection reliability and product yield.

[0172] Figure 13 The diagram shown is a schematic diagram of the pixel circuit provided in an embodiment of this application. Figure 14 As shown Figure 13 The provided control timing diagram corresponds to the pixel circuit.

[0173] The preferred embodiments of this application are as follows: Figure 13 The 4T2C pixel circuit shown is used as an example to illustrate the technical solution provided in this application. Of course, the array substrate provided in the embodiments of this application includes, but is not limited to, the 4T2C pixel circuit. (Refer to...) Figure 13 The pixel circuit includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and a light-emitting element OLED. The third transistor T3 and the fourth transistor T4 are implemented using dual-gate transistors.

[0174] Specifically, the source of driving transistor T1 and the first terminal of second capacitor C2 are connected to the positive power supply voltage VDD. The drains of driving transistor T1 and second transistor T2, the anode of the OLED, and the source of third transistor T3 are connected. The gate of driving transistor T1, the drain of third transistor T3, and the first terminal of first capacitor C1 are connected. The second terminal of first capacitor C1, the second terminal of second capacitor C2, and the drain of fourth transistor T4 are connected to form node N1. The source of fourth transistor T4 is connected to data voltage Data and input voltage Vini. The gate of second transistor T2 is connected to the first scan signal S1, the top gate of third transistor T3 is connected to the second scan signal S2, and the top gate of fourth transistor T4 is connected to the third scan signal S3. The bottom gates of both third transistor T3 and fourth transistor T4 are connected to the positive power supply voltage VDD. The cathode of the OLED is connected to the negative power supply voltage VSS.

[0175] Among them, the second transistor T2 is the reset transistor, the fourth transistor T4 is the data write transistor, and the third transistor T3 is the threshold compensation transistor. Combined with... Figure 13 and Figure 14 The specific working process of the pixel circuit provided in the embodiments of this application will be described. Its working process mainly includes a first reset stage t1, a threshold compensation stage t2, a data writing stage t3, a second reset stage t4, and a light emission stage t5.

[0176] It should be noted that the source of the fourth transistor T4 can be connected to the data signal line and the input signal line via a switching element SW, used to switch the input data voltage Data or the input voltage Vini. When the first switching signal SW-Vini is low, the source input of the fourth transistor T4 is the input voltage Vini; when the second switching signal SW-Data is low, the source input of the fourth transistor T4 is the data voltage Data.

[0177] During the first reset phase t1, the first scan signal S1 is low, while the second scan signal S2 and the third scan signal S3 are high. The second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned on. The first switch signal SW-Vini is low, and the source input of the fourth transistor T4 is the input voltage Vini. The reset voltage Vref resets the anode of the OLED element via the second transistor T2, and also resets the gate of the driving transistor T1 via the third transistor T3. The input voltage Vini is transmitted via the fourth transistor T4 and stored in the first capacitor C1.

[0178] During the threshold compensation stage t2, the first scan signal S1 goes high, and the second transistor T2 is turned off. The second scan signal S2 and the third scan signal S3 remain high, and both the third transistor T3 and the fourth transistor T4 are turned on. The first switch signal SW-Vini is low, and the source input of the fourth transistor T4 is the input voltage Vini. The input voltage Vini, which is pre-stored in the first capacitor C1, will couple and pull up the gate voltage of the driving transistor T1, causing the driving transistor T1 to turn on. The positive power supply voltage VDD will flow through the driving transistor T1 and the third transistor T3 to the gate of the driving transistor T1, continuously pulling up the capacitor voltage of the first capacitor C1 until the gate voltage of the driving transistor T1 rises to VDD+Vth, at which point the driving transistor T1 is turned off. At this time, the threshold voltage Vth of the driving transistor T1 is stored in the first capacitor C1, achieving continuous threshold compensation for the driving transistor T1 and ensuring the display quality of the display panel in subsequent display stages.

[0179] During the data writing phase t3, the first scan signal S1 is high, the second scan signal S2 is low, and the second transistor T2 and the fourth transistor T4 are turned off. The second switch signal SW-Data is low, and the source input of the fourth transistor T4 is the data voltage Data. The third scan signal S3 is low, enabling row-by-row writing of the data voltage Data to the gate of the driving transistor T1 through the fourth transistor T4, thus turning on the driving transistor T1 and generating the corresponding drive current.

[0180] In the second reset phase t4, the first scan signal S1 is switched to a low level, while the second scan signal S2 and the third scan signal S3 remain at a low level. The reset voltage Vref is used by the second transistor T2 to reset the anode of the OLED before it emits light, and to reset the anode potential that may be pulled up in the threshold compensation phase T2, so as to ensure the display effect in the light emission phase.

[0181] During the light-emitting stage t5, the first scan signal S1 is switched to a high level, and the negative power supply voltage VSS is pulled low, so that the driving path between the light-emitting element OLED and the driving transistor T1 is turned on, and light is emitted under the drive of the corresponding driving current.

[0182] In one exemplary embodiment, this application also provides a method for fabricating an array substrate, used to prepare an array substrate of any of the above embodiments, comprising the following steps:

[0183] A first active layer PSI1 is fabricated on a substrate 100, wherein a first active portion 110 of a first transistor T1 and a second active portion 120 of a second transistor T2 are disposed on the first active layer PSI1.

[0184] A first conductive layer M1 is fabricated on the first active layer PSI1, and a common electrode 21 is fabricated on the first conductive layer M1. The common electrode 21 is the second electrode of the first crystal T1 and the second electrode of the second transistor T2.

[0185] A second active layer PSI2 is fabricated on the first conductive layer M1, wherein the third active portion 130 of the third transistor T3 and the fourth active portion 140 of the fourth transistor T4 are disposed on the second active layer PSI2. The orthographic projection of the channel region 131 of the third active portion 130 onto the substrate 100 is at least partially located within the orthographic projection of the channel region 111 of the first active portion 110 onto the substrate. The orthographic projection of the channel region 131 of the third active portion 130 onto the substrate 100 is located outside the orthographic projection of the channel region 121 of the second active portion 120 onto the substrate. The orthographic projection of the channel region 140 of the fourth active portion 140 onto the substrate 100 is located outside the orthographic projection of the channel region 111 of the first active portion 110 onto the substrate.

[0186] A first electrode is fabricated on the second active layer PSI2, and the first electrode is connected to the common electrode 21.

[0187] In one specific embodiment, a method for fabricating an array substrate is provided with a specific photomask design, including the following steps:

[0188] PEP1: The first photomask is used to prepare the first active layer PSI1 on the substrate 100.

[0189] Specifically, the first active layer PSI1 is a P-type semiconductor layer, and the material selected is low-temperature polycrystalline silicon (LTPS). Then, a first gate insulating layer GI1 is deposited on the first active layer PSI1. The material of the first gate insulating layer GI1 can include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride, or their stacks, and can be achieved through chemical vapor deposition. Furthermore, before fabricating the first active layer PSI1 on the substrate, a first inorganic layer SI1 and a second inorganic layer SI2 can be sequentially fabricated on the substrate 100 to isolate water and oxygen.

[0190] The first active layer PSI1 can be used to form a first transistor T1 and a second transistor T2. The first active part 110 of the first transistor T1 and the second active part 120 of the second transistor T2 are disposed on the first active layer PSI1.

[0191] PEP2: The second photomask is used to fabricate the second conductive layer M2 on the first gate insulating layer GI1. The material of the second conductive layer M2 can be molybdenum (Mo). Then, the first insulating layer CI1, which can be silicon nitride (SiNx), is deposited on the second conductive layer M2.

[0192] PEP3: The third photomask is used to form multiple vias along the first insulating layer CI1 and the first gate insulating layer GI1 to achieve electrical connection with the first active layer PSI1 and the second conductive layer M2. For example, it may include forming ILD1, ILD2, ILD3 and ILD6 vias.

[0193] PEP4: The fourth photomask is used to prepare the first conductive layer M1 on the first insulating layer CI1. The material of the first conductive layer M1 can also be molybdenum (Mo). Then, the second insulating layer CI2 is deposited on the first conductive layer M1. The material can be silicon nitride (SiNx).

[0194] PEP5: The fifth photomask is used to fabricate the third conductive layer M3 on the second insulating layer CI2. The material of the third conductive layer M3 can also be molybdenum (Mo). Then, the third insulating layer CI3 is deposited on the third conductive layer M3, and the material can be silicon nitride (SiNx).

[0195] PEP6: The sixth photomask is used to form vias along the third insulating layer CI3 and the second insulating layer CI2 to achieve electrical connection with the first conductive layer M1, for example, to form the ILD7 via.

[0196] PEP7: The seventh photomask is used to fabricate the fourth conductive layer M4 on the third insulating layer CI3. The material of the fourth conductive layer M4 can also be molybdenum (Mo). Then, the fourth insulating layer CI4 is deposited on the fourth conductive layer M4, and the material can be silicon nitride (SiNx).

[0197] PEP8: The eighth photomask is used to form vias along the fourth insulating layer CI4, the third insulating layer CI3 and the second insulating layer CI2 to achieve electrical connection with the first conductive layer M1 and the third conductive layer M3, for example, to form vias ILD4 and ILD5.

[0198] PEP9: The ninth photomask is used to fabricate the second active layer PSI2 on the fourth insulating layer CI4. The material is IGZO (Indium Gallium Zinc Oxide). The filling material for the vias ILD4 and ILD5 can be the same as that of the second active layer PSI2. Then, the second gate insulating layer GI2 is deposited on the second active layer PSI2. The material of the second gate insulating layer GI2 can include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride, and their stacks, which can be achieved through chemical vapor deposition.

[0199] PEP10: The tenth photomask is used to fabricate the fifth conductive layer M5 on the second gate insulating layer GI2. The material of the fifth conductive layer M5 can also be molybdenum (Mo). Then, the fifth insulating layer CI5 is deposited on the fifth conductive layer M5, and the material can be silicon nitride (SiNx).

[0200] PEP11: The eleventh layer photomask is used to form vias along the fifth insulating layer CI5 and the second gate insulating layer GI2 to achieve electrical connection with the second active layer PSI2, for example, to form an ILD8 via.

[0201] PEP12: The twelfth photomask is used to fabricate the sixth conductive layer M6 on the fifth insulating layer CI5. The material of the sixth conductive layer M6 can be titanium (Ti) and aluminum (Al) or a composite material thereof. Then, the sixth insulating layer CI6 is deposited on the sixth conductive layer M6, and the material can be silicon nitride (SiNx).

[0202] PEP13: The thirteenth photomask is used to form vias along the sixth insulating layer CI6, the fifth insulating layer CI5, the second gate insulating layer GI2, the fourth insulating layer CI4, the third insulating layer CI3 and the second insulating layer CI2 to achieve electrical connection between the anode and the first conductive layer M1, for example, to form the ILD9 via.

[0203] PEP14: The fourteenth photomask is used to prepare the seventh conductive layer M7 on the sixth insulating layer CI6. The material of the seventh conductive layer M7 can also be titanium (Ti) and aluminum (Al) or their composite materials.

[0204] PEP15: The fifteenth photomask is used to form a planarization layer PLN on the seventh conductive layer M7, and to etch vias on it for electrical connections of subsequent electrodes or leads.

[0205] PEP16: The sixteenth photomask is used to fabricate transparent conductive ITO leads for signal transmission in pixel circuits (such as scan lines and data lines). The leads need to be connected to the PLN vias formed by PEP15 to transmit signals to each pixel unit.

[0206] PEP17: The seventeenth photomask is used to fabricate the anode of the OLED light-emitting element, providing a hole injection channel while ensuring electrical connection with the underlying structure. The material can be ITO / Ag / ITO.

[0207] PEP18: The eighteenth photomask is used to form the pixel definition layer (PDL). The light-emitting area of ​​each pixel is defined through the openings on the PDL. The material can be polyimide.

[0208] In one exemplary embodiment, a display panel is also provided, including the array substrate of any of the above embodiments. Therefore, the display panel also has the same beneficial effects as the array substrate described in any of the above embodiments. The similarities can be understood with reference to the explanation of the array substrate above. Figure 15 This is a schematic diagram of the structure of a display panel 200 provided in an embodiment of this application. In this embodiment, the display panel 200 includes any of the array substrates 100 provided in the above embodiments.

[0209] In one exemplary embodiment, a display device is also provided, including a display panel as described above. This display device includes any of the display panels provided in the above embodiments. Exemplarily, the display device includes a display panel. Therefore, this display device also has the beneficial effects of the display panel in the above embodiments; similarities can be understood with reference to the explanation of the display panel above, and will not be repeated below.

[0210] For example, the display device can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc., and the embodiments of this application do not make any special limitations on this.

[0211] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0212] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0213] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; The first active layer is located on one side of the substrate; The second active layer is located on the side of the first active layer that is away from the substrate; A first transistor and a second transistor, wherein the first transistor includes a first active portion and the second transistor includes a second active portion, and the first active portion and the second active portion are disposed on the first active layer; A third transistor includes a third active portion disposed on the second active layer. The channel region of the third active portion is at least partially located within the orthogonal projection of the channel region of the first active portion onto the substrate, and the orthogonal projection of the channel region of the third active portion onto the substrate is located outside the orthogonal projection of the channel region of the second active portion onto the substrate.

2. The array substrate according to claim 1, characterized in that, Also includes: The first conductive layer is located between the first active layer and the second active layer; The first electrode is located on the side of the second active layer that faces away from the substrate; The second electrode of the first transistor is connected to the second electrode of the second transistor to form a common electrode, the common electrode is located in the first conductive layer, and the common electrode is electrically connected to the first electrode.

3. The array substrate according to claim 2, characterized in that, Also includes: The second conductive layer is located between the first active layer and the first conductive layer; The first transistor further includes a first gate located in the second conductive layer. The orthographic projection of the first gate onto the first active layer covers the channel region of the first active portion. The first gate is electrically connected to the second source-drain region of the third active portion. The second transistor further includes a second gate located in the second conductive layer, and the orthogonal projection of the second gate onto the first active layer covers the channel region of the second active portion; Preferably, a first gate insulating layer is provided between the second conductive layer and the first active layer, and a first insulating layer is provided between the first conductive layer and the second conductive layer. The common electrode is connected to the second source / drain region of the first active part and the second source / drain region of the second active part via a first via. The first via passes through the first insulating layer and the first gate insulating layer in sequence. Preferably, the first transistor is a driving transistor used to transmit driving current to the light-emitting element; Preferably, the second transistor is a reset transistor, used to reset the driving transistor and the light-emitting element; Preferably, the array substrate further includes a first scan signal line, and the second gate is connected to the first scan signal line; Preferably, the first electrode of the second transistor is located in the first conductive layer, and the first electrode of the second transistor is connected to the first source-drain region of the second active portion via the second via, and the second via sequentially penetrates the first insulating layer and the first gate insulating layer; Preferably, the array substrate further includes a reset signal line, and the first terminal of the second transistor is connected to the reset signal line.

4. The array substrate according to claim 3, characterized in that, Also includes: The first connecting plate is located in the first conductive layer. The first connecting plate is connected to the first gate through a third via in the first insulating layer. The first gate is electrically connected to the second source / drain region of the third active part through the first connecting plate.

5. The array substrate according to claim 4, characterized in that, Also includes: The third conductive layer is located between the first conductive layer and the second active layer; The fourth conductive layer is located between the third conductive layer and the second active layer; A first capacitor and a second capacitor, the first capacitor and the second capacitor including a common electrode plate, the common electrode plate being located in the third conductive layer, the first connecting electrode plate serving as the other side electrode plate of the first capacitor, the second capacitor further including a second electrode plate, the second electrode plate being located in the fourth conductive layer, the orthographic projection of the first connecting electrode plate on the substrate being at least partially located within the orthographic projection of the common electrode plate on the substrate, and the orthographic projection of the second electrode plate on the substrate being at least partially located within the orthographic projection of the common electrode plate on the substrate; Preferably, the orthographic projection of the common electrode plate onto the substrate is at least partially located within the orthographic projection of the first active portion onto the substrate; Preferably, a second insulating layer is provided between the first conductive layer and the third conductive layer, a third insulating layer is provided between the third conductive layer and the fourth conductive layer, a fourth insulating layer is provided between the second active layer and the fourth conductive layer, and the first connecting plate is connected to the second source / drain region of the third active part through a fourth via, wherein the fourth via sequentially penetrates the fourth insulating layer, the third insulating layer and the second insulating layer; Preferably, the filling material of the fourth via is the same as the material of the second active layer.

6. The array substrate according to claim 5, characterized in that, Also includes: The fifth conductive layer is located on the side of the second active layer that faces away from the substrate; The third transistor is a dual-gate transistor, which includes a third top gate and a third bottom gate. The third top gate is located in the fifth conductive layer. The orthogonal projection of the third top gate onto the second active layer covers the channel region of the third active portion. The third bottom gate reuses the second electrode plate. Preferably, the array substrate further includes a second scan signal line, and the third top gate is connected to the second scan signal line.

7. The array substrate according to claim 6, characterized in that, Also includes: A fourth transistor, the fourth transistor including a fourth active portion disposed on the second active layer, wherein the orthographic projection of the channel region of the fourth active portion on the substrate is located outside the orthographic projection of the channel region of the first active portion on the substrate; The fourth transistor is a dual-gate transistor, which includes a fourth top gate and a fourth bottom gate. The fourth top gate is located in the fifth conductive layer, and the fourth bottom gate is located in the fourth conductive layer. The orthogonal projection of the fourth top gate and the fourth bottom gate on the second active layer covers the channel region of the fourth active portion. The second electrode of the fourth transistor is located in the third conductive layer. Preferably, the second electrode of the fourth transistor is connected to the second source / drain region of the fourth active part via the fifth via, and the fifth via sequentially penetrates the fourth insulating layer and the third insulating layer; Preferably, the filling material of the fifth via is the same as the material of the second active layer; Preferably, the second electrode of the fourth transistor reuses the common electrode plate, and the orthographic projection of the fifth via on the substrate is located within the orthographic projection of the first connecting electrode plate on the substrate; Preferably, the common electrode plate includes a first electrode plate portion, a connecting portion and a second electrode plate portion, the connecting portion connects the first electrode plate portion and the second electrode plate portion, and in a first direction, the first electrode plate portion, the fourth through hole and the second electrode plate portion are arranged sequentially, and in a second direction perpendicular to the first direction, the fourth through hole is located on one side of the connecting portion; Preferably, the first electrode of the first transistor is located in the first conductive layer, and the first electrode of the first transistor is connected to the first source-drain region of the first active part through a sixth via, wherein the sixth via sequentially penetrates the first insulating layer and the first gate insulating layer. Preferably, the array substrate further includes a power signal line, the second electrode plate and the fourth bottom gate are connected to the power signal line, the fourth bottom gate is connected to the first electrode of the first transistor through a seventh via, and the seventh via sequentially penetrates the third insulating layer and the second insulating layer; Preferably, the array substrate further includes a sixth conductive layer located on the side of the fifth conductive layer opposite to the substrate, and the first electrode of the fourth transistor is located on the sixth conductive layer; Preferably, a second gate insulating layer is provided between the second active layer and the fifth conductive layer, a fifth insulating layer is provided between the fifth conductive layer and the sixth conductive layer, and the first electrode of the fourth transistor is connected to the first source-drain region of the fourth active part through an eighth via, the eighth via sequentially penetrating the fifth insulating layer and the second gate insulating layer; Preferably, the array substrate further includes a data signal line, and the first electrode of the fourth transistor is connected to the data signal line; Preferably, the array substrate further includes a third scan signal line, and the fourth top gate is connected to the third scan signal line.

8. The array substrate according to claim 7, characterized in that, Also includes: The seventh conductive layer is located on the side of the sixth conductive layer that faces away from the substrate; The second connection electrode is located in the seventh conductive layer and is connected to the common electrode and the anode, respectively. Preferably, a sixth insulating layer is provided between the sixth conductive layer and the seventh conductive layer; Preferably, the second connection electrode is connected to the common electrode via a ninth via, the ninth via extending from the sixth insulating layer to the second insulating layer along the thickness direction of the array substrate; Preferably, the orthographic projection of the ninth via on the substrate is located within the orthographic projection of the first source / drain region of the third active portion on the substrate; Preferably, the second connection electrode is connected to the first source / drain region of the third active part via a tenth via, and the first source / drain region of the third active part is connected to the common electrode via an eleventh via. The tenth via extends from the sixth insulating layer to the second active layer along the thickness direction of the array substrate, and the eleventh via extends from the fourth insulating layer to the first conductive layer along the thickness direction of the array substrate. Preferably, the filling material of the eleventh via is the same as the material of the second active layer.

9. The array substrate according to any one of claims 1 to 8, characterized in that, The first active layer is a polycrystalline silicon active layer, and the second active layer is an oxide active layer.

10. A display panel, characterized in that, The array substrate includes any one of claims 1 to 9.

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