Display panel and electronic device including the same

Abstract

One embodiment of the present invention discloses a display panel comprising: a substrate in which a transmissive region, a dummy region surrounding the transmissive region, and a display region surrounding the dummy region are defined; a driving circuit disposed in the display area and including a transistor; a voltage line disposed in the display area and electrically connected to the driving circuit; an insulating layer on the voltage line; a first pixel electrode disposed on the insulating layer in the display area; a bank layer covering an edge of the first pixel electrode and defining a first opening overlapping the first pixel electrode; a light emitting layer overlapping the first pixel electrode; an opposite electrode disposed on the light emitting layer; and a dummy electrode layer disposed on the insulating layer in the dummy region, in which the bank layer extends toward the dummy region and defines a plurality of dummy openings overlapping the dummy electrode layer.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a display panel and an electronic device including the same. BACKGROUND

[0002] Recently, the use of display panels is diversifying. In addition, the thickness and weight of display panels are decreasing, and thus, the range of use of display panels is expanding.

[0003] As the area occupied by a display area in a display panel increases, various functions incorporated into the display panel or associated with the display panel are increasing. As a method of increasing various functions while expanding the area, research is continuing to use a portion of the display area for functions other than displaying images. SUMMARY

[0004] TECHNICAL PROBLEM

[0005] Embodiments provide a structure of a display panel including a transmissive area and an electronic device including the same.

[0006] Additional features will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings or can be learned by practice of the presented embodiments of the disclosure.

[0007] TECHNICAL SOLUTION

[0008] In an embodiment of the disclosure, a display panel includes a substrate in which a transmissive area, a dummy area surrounding the transmissive area, and a display area surrounding the dummy area are defined, a driving circuit disposed in the display area and including a transistor, a voltage line disposed in the display area and electrically connected to the driving circuit, an insulating layer on the voltage line, a first pixel electrode disposed on the insulating layer in the display area, a bank layer covering edges of the first pixel electrode and defining a first opening overlapping the first pixel electrode, an emission layer overlapping the first pixel electrode through the first opening of the bank layer, an opposite electrode disposed on the emission layer and overlapping the first pixel electrode and the emission layer, and a dummy electrode layer disposed on the insulating layer in the dummy area, wherein the bank layer extends toward the dummy area and defines a plurality of dummy openings overlapping the dummy electrode layer.

[0009] In an embodiment of the disclosure, an electronic device includes the above-described display panel and an assembly corresponding to the transmissive area of the display panel. The assembly can include a sensor or a camera.

[0010] In an embodiment, the display panel can further include a dummy transistor disposed below the dummy electrode layer, wherein the dummy electrode layer can be electrically insulated from the dummy transistor.

[0011] In an embodiment, the voltage line can extend toward the dummy area and a portion of the voltage line can overlap the dummy electrode layer, and the dummy electrode layer can be electrically connected to the voltage line.

[0012] In an embodiment, the voltage line can have a voltage level that is the same as a voltage level of the opposite electrode.

[0013] In an embodiment, the driving circuit can further include an initialization transistor electrically connected to the first pixel electrode and initializing the first pixel electrode, and the voltage line can be electrically connected to the initialization transistor.

[0014] In an embodiment, the plurality of dummy openings of the bank layer can include a first dummy opening, a second dummy opening, and a third dummy opening that respectively overlap different portions of the dummy electrode layer.

[0015] In an embodiment, the display panel can further include a second pixel electrode disposed on the insulating layer in the display area and adjacent to the first pixel electrode while being mutually separated from the first pixel electrode, and a third pixel electrode disposed on the insulating layer in the display area and adjacent to the first pixel electrode and the second pixel electrode while being mutually separated from the first pixel electrode and the second pixel electrode, wherein the bank layer can further define a second opening and a third opening, wherein the second opening overlaps the second pixel electrode and the third opening overlaps the third pixel electrode, the first opening and the second opening can be defined in the same column, and the third opening can be defined adjacent to the column of the first opening and the second opening, and the first dummy opening and the second dummy opening can be defined in the same column, and the third dummy opening can be defined adjacent to the column of the first dummy opening and the second dummy opening.

[0016] In an embodiment, a size of the first dummy opening and a size of the first opening can be substantially the same as each other, a size of the second dummy opening and a size of the second opening can be substantially the same as each other, and a size of the third dummy opening and a size of the third opening can be substantially the same as each other.

[0017] In an embodiment, a size and a shape of the first dummy opening can be different from a size and a shape of the first opening.

[0018] In an embodiment, a wiring area can be further defined between the transmission area and the dummy area in the substrate, and the wiring area can surround the transmission area, wherein the dummy electrode layer can extend toward the wiring area, and the bank layer can further define a fourth dummy opening, a fifth dummy opening, and a sixth dummy opening that respectively overlap different portions of the dummy electrode layer arranged in the wiring area.

[0019] In an embodiment, the size of the first dummy opening, the size of the second dummy opening, and the size of the third dummy opening can be different from each other, the size of the fourth dummy opening and the size of the first dummy opening can be substantially the same as each other, the size of the fifth dummy opening and the size of the second dummy opening can be substantially the same as each other, and the size of the sixth dummy opening and the size of the third dummy opening can be substantially the same as each other.

[0020] In an embodiment, in the wiring area, the dummy electrode layer can not overlap the transistor.

[0021] In an embodiment, the display panel can further include a signal line electrically connected to the driving circuit, wherein the signal line can be routed along an edge of the transmissive area in the wiring area, and the dummy electrode layer can overlap the routed portion of the signal line in the wiring area.

[0022] In an embodiment, the bank layer can include a light-blocking material.

[0023] Advantageous Effects

[0024] In an embodiment of the disclosure, when the display panel is not operated (turned off), a reflectance difference between the display area and the intermediate area can be reduced, and thus, when the display panel is not operated (turned off), the user can be prevented from distinguishably recognizing the display area and the intermediate area. Such an effect is merely an example, and the scope of the disclosure is not limited by the above effect. BRIEF DESCRIPTION OF DRAWINGS

[0025] The above and other features and advantages of illustrative embodiments of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference made to the accompanying drawings from which:

[0026] Figures la to lc FIG. 1 is a perspective view schematically illustrating an embodiment of an electronic device.

[0027] Figure 2 FIG. 2 is a cross-sectional view of an embodiment of the electronic device taken along line II-II' of FIG. 1. Figure lc

[0028] Figure 3 FIG. 4 is a plan view of an embodiment illustrating an excerpt of a portion of a display panel.

[0029] Figure 4 FIG. 6 is an equivalent circuit diagram schematically illustrating an embodiment of a light emitting diode disposed in a display area and a driving circuit electrically connected to the light emitting diode.

[0030] Figure 5 FIG. 8 is a cross-sectional view of an embodiment illustrating a portion of a display panel.

[0031] Figure 6 ​is a plan view showing an embodiment of a portion of the display panel, and shows Figure 3 Region III of FIG. 1.

[0032] Figure 7 is a plan view showing an embodiment of a portion of the display panel, and shows Figure 6 Region VII of FIG. 1.

[0033] Figure 8 is a cross-sectional view of the display panel taken along lines VIIIa-VIIIa' and lines VIIIb-VIIIb' of Figure 7

[0034] Figure 9 is a plan view showing an embodiment of a portion of the display panel, and shows Figure 3 Region III of FIG. 1.

[0035] Figure 10 is a plan view showing an embodiment of a portion of the display panel, and shows Figure 9 Region X of FIG. 1.

[0036] Figure 11 is a cross-sectional view of the embodiment of the display panel taken along lines XIa-XIa' and lines XIb-XIb' of Figure 10

[0037] Figure 12 is a plan view schematically showing an embodiment of the display panel.

[0038] Figure 13 is a plan view showing a portion of the display panel of Figure 12

[0039] Figure 14a and Figure 14b are cross-sectional views each showing an embodiment of a portion of the display panel in the embodiment taken along line XIV-IXV' of Figure 13

[0040] Figure 15 is a plan view schematically showing an embodiment of a portion of the display panel.

[0041] Figure 16 is a plan view showing a portion of the display panel of Figure 15

[0042] Figure 17 is a cross-sectional view of Region XVI of Figure 16 Figure 16

[0043] The most preferred embodiment of the present invention ​​​​​​​

[0044] In embodiments of this disclosure, a display panel includes: a substrate defining a transmissive region, a dummy region surrounding the transmissive region, and a display region surrounding the dummy region; a driving circuit disposed in the display region and including transistors; a voltage line disposed in the display region and electrically connected to the driving circuit; an insulating layer on the voltage line; a first pixel electrode disposed in the display region on the insulating layer; a dam layer covering the edge of the first pixel electrode and defining a first opening overlapping the first pixel electrode; an emission layer overlapping the first pixel electrode through the first opening of the dam layer; a counter electrode disposed on the emission layer and overlapping the first pixel electrode and the emission layer; and a dummy electrode layer disposed in the dummy region on the insulating layer, wherein the dam layer extends toward the dummy region and defines a plurality of dummy openings overlapping the dummy electrode layer.

[0045] In embodiments of this disclosure, the electronic device includes the aforementioned display panel and components corresponding to the transmissive area of ​​the display panel. The components may include sensors or cameras.

[0046] Embodiments of the present invention

[0047] This disclosure can have various modifications and implementations, and illustrative embodiments are shown in the accompanying drawings and described in detail in the detailed description. The effects and features of this disclosure, as well as methods for implementing this disclosure, will become apparent from the embodiments described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and can be implemented in various forms.

[0048] In the following description with reference to the accompanying drawings, the same reference numerals denote the same elements, and redundant descriptions thereof will be omitted.

[0049] In the following implementation, the terms "first" and "second" are not used in a limited sense and are used to distinguish one component from another.

[0050] In the following implementation, unless the meaning is clearly different in the context, the singular expression covers the plural expression.

[0051] In the following implementation, it will be further understood that the terms “comprise” and / or “comprising” as used herein specify the presence of the stated features or components, but do not exclude the presence or addition of one or more other features or components.

[0052] It will be understood that when a layer, region, or element is referred to as being "formed" on another layer, region, or element, it can be formed directly or indirectly on the other layer, region, or element. That is, for example, an intermediary layer, region, or element may exist.

[0053] In the accompanying drawings, the dimensions of components may be exaggerated or reduced for ease of description. In other words, because the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of interpretation, this disclosure is not necessarily limited thereto.

[0054] When the illustrative implementation can be carried out differently, a specific process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of the described sequence.

[0055] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0056] When a layer, region, component, etc., is connected to another layer, region, component, etc., the layer, region, component, etc., may be directly connected to it and / or may be indirectly connected to it, with an intermediary layer, region, component, etc., between them. For example, in this specification, when a layer, region, component, etc., is electrically connected to another layer, region, component, etc., the layer, region, component, etc., may be directly electrically connected to it and / or may be indirectly electrically connected to it, with an intermediary layer, region, component, etc., between them.

[0057] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system, but can be interpreted broadly to include all three axes. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0058] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term "substantially" as used herein includes the value and means within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art. The term "substantially" may mean within one or more standard deviations, or, for example, within ±5% of the value.

[0059] Figures la to lc This is a perspective view schematically showing an embodiment of electronic device 1.

[0060] refer to Figures la to lcElectronic device 1 is a device for displaying moving or still images and may include portable electronic devices such as mobile phones, smartphones, laptops, tablet computers, mobile communication terminals, e-notebooks, e-books, portable multimedia players (“PMPs”), navigation devices, or ultra-mobile personal computers (“UMPCs”). Electronic device 1 may be a display for televisions, billboards, or the Internet of Things (“IoT”). Electronic device 1 may be used in wearable devices such as smartwatches, smartwatch phones, glasses-type displays, or head-mounted displays (“HMDs”). Furthermore, electronic device 1 in the embodiments may be used as a vehicle panel, a central information display (“CID”) disposed on the center dashboard or instrument panel of a vehicle, an interior mirror display replacing the side mirrors of a vehicle, or a display disposed on the rear surface of the front seats as an entertainment device for the rear seats of a vehicle. Electronic device 1 may be flexible, foldable, or rollable.

[0061] In the planar view, electronic device 1 can have a quadrilateral shape, such as a rectangle. The corner where one side of electronic device 1 in the x-direction and the other side in the y-direction intersect can be formed as a right angle or rounded to have a predetermined curvature. The planar shape of electronic device 1 is not limited to a rectangle, and can also be another polygon, ellipse, or atypical shape.

[0062] Electronic device 1 may include a transmissive area. In one embodiment, such as... Figure la As shown, for example, electronic device 1 may include a first transmissive region TA1 and a display region DA surrounding the first transmissive region TA1. Electronic device 1 may include an intermediate region MA disposed between the first transmissive region TA1 and the display region DA, and an outer region PA surrounding the display region DA (e.g., an outer perimeter region PA surrounding the display region DA). The entire first transmissive region TA1 may be surrounded by the intermediate region MA, the entire intermediate region MA may be surrounded by the display region DA, and the entire display region DA may be surrounded by the outer perimeter region PA.

[0063] Light-emitting diodes (LEDs) are arranged in the display area DA. The display area DA can provide an image through the light emitted from the LEDs. The LEDs used for emitting light are not located in the first transmission area TA1, the intermediate area MA, and the peripheral area PA.

[0064] The first transmission region TA1 can be defined within the display region DA. In an embodiment, such as... Figure laAs shown, the first transmission region TA1 can be defined at the upper center of the display region DA. In the plan view of this specification, "left," "right," "up," and "down" indicate the directions when the electronic device 1 is viewed in a direction perpendicular to the electronic device 1. In an embodiment, for example, "left" represents the -x direction, "right" represents the +x direction, "up" represents the +y direction, and "down" represents the -y direction.

[0065] exist Figure la In one embodiment, a single transmission region is defined; however, in another embodiment, multiple transmission regions may exist. For example... Figure lb As shown, the electronic device 1 may include two transmission regions. In one embodiment, for example, the entirety of the first transmission region TA1 and the second transmission region TA2 may be surrounded by an intermediate region MA, and the entirety of the intermediate region MA and the first transmission region TA1 and the second transmission region TA2 within the intermediate region MA may be surrounded by a display region DA. In another embodiment, as... Figure lc As shown, the electronic device 1 may include three transmission regions. In one embodiment, for example, the entirety of the first transmission region TA1, the second transmission region TA2, and the third transmission region TA3 may be surrounded by an intermediate region MA, and the entirety of the intermediate region MA and the first transmission region TA1, the second transmission region TA2, and the third transmission region TA3 within the intermediate region MA may be surrounded by a display region DA. The size of one of the first transmission regions TA1 to the third transmission region TA3 may be different from the size of the others.

[0066] Figure 2 It is along Figure lc The line II-II' intercepted Figure lc A cross-sectional view of an embodiment of the electronic device 1.

[0067] refer to Figure 2 Electronic device 1 may include a display panel 10 and components disposed in a transmissive region of the display panel 10. Similar to electronic device 1, the display panel 10 may include a transmissive region, a central region MA, a display region DA, and a peripheral region PA. In an embodiment, in... Figure 2 In this embodiment, the display panel 10 includes three transmissive regions (e.g., first transmissive region TA1 to third transmissive region TA3), and the electronic device 1 includes three components, for example, a first component 71, a second component 72, and a third component 73 corresponding to the first transmissive region TA1 to the third transmissive region TA3, respectively. The display panel 10 and the first components 71 to the third components 73 can be housed in a housing HS.

[0068] The display panel 10 may include a display layer 20, an encapsulation layer 30, an input detection layer (also known as an input sensing layer) 40, an optical function layer 50, and a cover window 60.

[0069] The display layer 20 may include a light-emitting element and a driving circuit. The light-emitting element emits light to display an image, and the driving circuit is electrically connected to the light-emitting element and includes a transistor.

[0070] The encapsulation layer 30 can seal the display layer 20. The encapsulation layer 30 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In another embodiment, the encapsulation layer 30 may include a glass substrate.

[0071] The input detection layer 40 can obtain coordinate information based on external pressure (e.g., a touch event). The input detection layer 40 may include touch electrodes and signal lines (traces) connected to the touch electrodes. The input detection layer 40 may be disposed on the encapsulation layer 30. The input detection layer 40 can detect external input using mutual capacitance and / or self-capacitance methods.

[0072] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (external light) incident from the outside toward the display panel 10 through the cover window 60. The anti-reflective layer may include a retarder and a polarizer.

[0073] In another embodiment, the antireflective layer may include a black matrix and color filters. The color filters may be arranged to take into account the colors of light emitted from the display elements (e.g., light-emitting diodes) of the display layer 20. In another embodiment, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged in different layers. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can destructively interfere with each other, and therefore, the reflectivity of external light can be reduced.

[0074] The optical functional layer 50 may include a lens layer. The lens layer can improve the light output efficiency of light emitted from the display layer 20 or reduce color deviation. The lens layer may include a layer having a convex or concave lens shape and / or multiple layers with different refractive indices. The optical functional layer 50 may include both an anti-reflective layer and a lens layer, or one of an anti-reflective layer and a lens layer.

[0075] The opening 10OP can be confined within the display panel 10. In this respect, Figure 2 A display panel 10 is shown, including openings 10OP corresponding to a first transmission region TA1 and a third transmission region TA3, respectively. A display layer 20, an encapsulation layer 30, an input detection layer 40, and an optical functional layer 50 define openings 20OP, 30OP, 40OP, and 50OP that can overlap each other. The display layer 20, encapsulation layer 30, input detection layer 40, and optical functional layer 50 may not define an opening corresponding to a second transmission region TA2.

[0076] Cover window 60 may be disposed on optical functional layer 50. Cover window 60 may be bonded to optical functional layer 50 by an adhesive layer OCA (such as optically clear adhesive) disposed between cover window 60 and optical functional layer 50. Cover window 60 may comprise glass or plastic material. Plastic material may comprise polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0077] The cover window 60 may include a flexible window. In an embodiment, for example, the cover window 60 may include a polyimide window or an ultra-thin glass window.

[0078] The first transmission regions TA1 to the third transmission regions TA3 can be component regions of one type (e.g., sensor region, camera region, speaker region, etc.) in which first components 71 to third components 73 for providing various functions to electronic device 1 are disposed. The first components 71 to third components 73 can be arranged on the rear surface of display panel 10 in response to the first transmission regions TA1 to the third transmission regions TA3 respectively.

[0079] The first component 71 to the third component 73 may include electronic components. The first component 71 to the third component 73 may be electronic components that use light or sound, and the light or sound can pass through the first transmission region TA1 to the third transmission region TA3. For example, the electronic components may include a camera that captures images by receiving light, a sensor that measures distance by outputting and detecting light or sound, a sensor that identifies a part of the human body (such as an iris, fingerprint, or face), a relatively small lamp that outputs light, and a speaker that outputs sound. Electronic components using light may use light of various wavelength bands, such as visible light, infrared light, or ultraviolet light.

[0080] The first components 71 to the third components 73 may include electronic components that are different from each other. In an embodiment, one of the first components 71 to the third components 73 may be a camera for video conferencing or for taking images such as selfies. For example, one of the remaining two of the first components 71 to the third components 73 may be a transmitter that emits infrared light, and the other may be a receiver that receives infrared light to identify a part of the human body. As described above, the first components 71 to the third components 73 may be electronic components with different functions.

[0081] In another embodiment, when the electronic device 1 is used as a smartwatch or a vehicle dashboard, one of the first component 71 to the third component 73 may be a component including a clock hand or a pointer indicating predetermined information (e.g., vehicle speed). In this case, with Figure 2 As shown, the opening can be confined within the cover window 60, allowing components such as pointers to be exposed outwards.

[0082] Figure 2 Three transmission regions are shown, but this disclosure is not limited thereto. In another embodiment, as referenced above... Figure la and Figure lb As described, the electronic device 1 and / or display panel 10 may include one or two transmissive regions, or may include four or more transmissive regions. When the display panel 10 includes one transmissive region, an opening corresponding to one transmissive region may be defined in the display panel 10 or may not be defined in the display panel 10. When the display panel 10 includes two transmissive regions, the display panel 10 may include two openings corresponding to the two transmissive regions. In an alternative embodiment, an opening corresponding to one of the two transmissive regions may be defined in the display panel 10, and openings for the remaining transmissive regions may not be defined in the display panel 10.

[0083] Figure 3 This is a plan view showing a selected embodiment of a portion of the display panel 10. For ease of description, Figure 3 The display panel 10 is shown to include two transmissive areas, but as referenced above... Figures la to lc The number of transmission zones described can be varied.

[0084] refer to Figure 3 The display panel 10 may include a first transmissive region TA1 and a second transmissive region TA2 spaced apart from each other, an intermediate region MA surrounding the first transmissive region TA1 and the second transmissive region TA2, and a display region DA surrounding the intermediate region MA.

[0085] As referenced above Figure 2 As described, the first transmission region TA1 and the second transmission region TA2 are regions through which wavelengths (such as light) can pass, and can be of the type of non-display region in which no light-emitting diodes for displaying images are set.

[0086] The intermediate region MA is a non-display area that does not emit light and can surround the first transmission region TA1 and the second transmission region TA2. The intermediate region MA can include a wiring area and a dummy region DMA surrounding the wiring area. Wrapped portions of signal lines (e.g., wrapped portions of data lines DL and scan lines SL) can pass through the wiring area.

[0087] On this point, Figure 3A first wiring region RA1 surrounding a first transmission region TA1 and a second wiring region RA2 surrounding a second transmission region TA2 are shown. The first wiring region RA1 and the second wiring region RA2 may have closed-loop shapes surrounding the first transmission region TA1 and the second transmission region TA2, respectively. The first wiring region RA1 and the second wiring region RA2 may be spaced apart from each other, and a dummy region DMA may surround the first wiring region RA1 and the second wiring region RA2.

[0088] Light-emitting diodes (LEDs) emitting red, green, and blue light can be arranged in the display area DA. The red light emitted from the red-emitting LED, the green light emitted from the green-emitting LED, and the blue light emitted from the blue-emitting LED can respectively correspond to the light emitted from the red sub-pixel, the green sub-pixel, and the blue sub-pixel of the display panel 10. However, this disclosure is not limited to this, and the LEDs can emit various other colors.

[0089] Signal lines (e.g., scan lines SL and data lines DL) used to provide scan signals and data signals to transistors electrically connected to each light-emitting diode (LED) arranged in the display area DA can pass through the display area DA while bypassing the transmission area in the intermediate area MA. In an embodiment, for example, the scan lines SL and data lines DL can bypass the transmission area by extending along the edge of the transmission area in a wiring area (e.g., a first wiring area RA1 or a second wiring area RA2).

[0090] In an implementation, for example, a scan line SL may extend in the x-direction, bypassing the first transmission region TA1 above it and the second transmission region TA2 above it. Another scan line SL may extend in the x-direction, bypassing the first transmission region TA1 below it and the second transmission region TA2 below it. A data line DL may extend in the y-direction, bypassing the first transmission region TA1 to the left, and another data line DL may extend in the y-direction, bypassing the first transmission region TA1 to the right. Furthermore, another data line DL may extend in the y-direction, bypassing the second transmission region TA2 to the left, and another data line DL may extend in the y-direction, bypassing the second transmission region TA2 to the right.

[0091] Figure 4This is an equivalent circuit diagram schematically showing an embodiment of a light-emitting diode (LED) disposed in the display area and a driving circuit (PC) electrically connected to the LED.

[0092] The driver circuit PC can be electrically connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GIL for transmitting the second gate signal GI, the third gate line GRL for transmitting the third gate signal GR, the fourth gate line EML for transmitting the fourth gate signal EM, the fifth gate line EMBL for transmitting the fifth gate signal EMB, and the data line DL for transmitting the data signal DATA. The light emission of the LED is controlled by the fourth gate signal EM and the fifth gate signal EMB; therefore, the fourth gate signal EM and the fifth gate signal EMB can also be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL can also be referred to as emission control lines. The driver circuit PC can be electrically connected to the drive voltage line PL for transmitting the drive voltage ELVDD, the reference voltage line VRL for transmitting the reference voltage Vref, the first initialization voltage line VAL for transmitting the first initialization voltage Vaint, and the second initialization voltage line VIL for transmitting the second initialization voltage Vint.

[0093] In some embodiments, the plurality of transistors included in the driving circuit PC may be N-type oxide thin-film transistors. Oxide thin-film transistors may be low-temperature polycrystalline oxide (“LTPO”) thin-film transistors in which the semiconductor layer comprises oxide. However, this is merely an example, and the transistors of this disclosure are not limited thereto. In some embodiments, for example, the semiconductor layer included in the N-type transistor may comprise inorganic semiconductors (e.g., amorphous silicon or polycrystalline silicon) or organic semiconductors.

[0094] The driving circuit PC may include first transistors T1 to T7, a first capacitor C1, a second capacitor C2, and an auxiliary capacitor Ca. First transistor T1 may be a driving transistor that outputs a driving current corresponding to the data signal DATA, and second transistors T2 to T7 may be switching transistors that transmit signals. Depending on the voltage of the first terminal (or first electrode) and the second terminal (or second electrode), the first terminal and the second terminal of each of the first transistors T1 to T7 may be a source (or source electrode) or a drain (or drain electrode). In an embodiment, for example, depending on the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node to which the 1-1 gate of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as a second node N2.

[0095] The first transistor T1 can be connected to the drive voltage line PL and the light-emitting diode (LED). The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a gate (or gate electrode), a first terminal, and a second terminal connected to the second node N2. The first transistor T1 may include a 1-1 gate connected to the first node N1. The first transistor T1 may also include a 1-2 gate connected to the second terminal of the first transistor T1. The 1-1 gate and the 1-2 gate may be arranged facing each other in different layers. In an embodiment, for example, the 1-1 gate and the 1-2 gate of the first transistor T1 may face each other with a semiconductor layer between them. Hereinafter, the gate (or gate electrode) of the first transistor T1 may refer to the 1-1 gate involved in turning the first transistor T1 on or off.

[0096] The gate of the first transistor T1 (1-1) can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The gate of the first transistor T1 (1-2) can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the drive voltage line PL via the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the pixel electrode of the light-emitting diode (LED) via the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can control the amount of drive current flowing through the LED by receiving the data signal DATA according to the switching operation of the second transistor T2.

[0097] The second transistor T2 can be connected to the data line DL and the 1-1 gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the 1-1 gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 is turned on by a first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL and the first node N1, and can transmit the data signal DATA transmitted to the data line DL to the first node N1.

[0098] The third transistor T3 can be connected to the 1-1 gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the 1-1 gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 can be turned on by the third gate signal GR transmitted to the third gate line GRL to transmit the reference voltage Vref transmitted to the reference voltage line VRL to the first node N1.

[0099] A fourth transistor (also called an initialization transistor) T4 can be connected to the sixth transistor T6 and the first initialization voltage line VAL. The fourth transistor T4 can be connected between the light-emitting diode (LED) and the first initialization voltage line VAL. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the first initialization voltage line VAL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the LED. The fourth transistor T4 can be turned on by the second gate signal GI transmitted to the second gate line GIL to transmit the first initialization voltage Vaint transmitted to the first initialization voltage line VAL to the third node N3 and initialize the pixel electrode (e.g., the anode) of the LED.

[0100] The fifth transistor T5 can be connected to the drive voltage line PL and the first terminal of the first transistor T1. The fifth transistor T5 may include a gate connected to the fourth gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to the fourth gate signal EM transmitted to the fourth gate line EML.

[0101] The sixth transistor T6 can be connected to the first transistor T1 and the light-emitting diode (LED). The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the LED. The sixth transistor T6 can be turned on or off according to the fifth gate signal EMB transmitted to the fifth gate line EMBL.

[0102] A seventh transistor T7 can be connected between the first transistor T1 and the second initialization voltage line VIL. The seventh transistor T7 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VIL. The first terminal of the seventh transistor T7 can be connected to the second terminal of the first transistor T1, the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The seventh transistor T7 can be turned on by the second gate signal GI transmitted to the second gate line GIL to transmit the second initialization voltage Vint transmitted to the second initialization voltage line VIL to the second node N2.

[0103] A first capacitor C1 can be connected between the gate (1-1) of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 can be connected to the first node N1, and the second electrode of the first capacitor C1 can be connected to the second node N2. The first electrode of the first capacitor C1 can be connected to the gate (1-1) of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 can be connected to the second terminal and the gate (1-2) of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1, as a storage capacitor, can store a voltage corresponding to the data signal DATA and the threshold voltage of the first transistor T1.

[0104] When the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 can be turned on. When the voltage at the second terminal of the first transistor T1 drops to the difference Vref-Vth1 between the reference voltage Vref and the threshold voltage Vth1 of the first transistor T1, the first transistor T1 is turned off, and the voltage corresponding to the threshold voltage Vth1 of the first transistor T1 is stored in the first capacitor C1. Therefore, the threshold voltage Vth1 of the first transistor T1 can be compensated.

[0105] The second capacitor C2 can be connected between the drive voltage line PL and the second node N2. The first electrode of the second capacitor C2 can be connected to the drive voltage line PL. The second electrode of the second capacitor C2 can be connected to the second terminal and gate 1-2 of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6.

[0106] The capacitance of each of the first capacitor C1 and the second capacitor C2 can vary according to the color of the light emitted from the light-emitting diode (LED).

[0107] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the holding voltage line VSSL, and the pixel electrode of the light-emitting diode (LED). The auxiliary capacitor Ca can prevent increased black brightness when the sixth transistor T6 is turned off by storing and maintaining a voltage corresponding to the voltage difference between the pixel electrode of the LED and the holding voltage line VSSL.

[0108] A light-emitting diode (LED) can be connected to a first transistor T1 via a sixth transistor T6. The LED may include a pixel electrode (anode) connected to a third node N3 and a opposite electrode (cathode) facing the pixel electrode, and the opposite electrode may receive a common voltage ELVSS. In an embodiment, the opposite electrode (cathode) may extend in the display area to be electrically connected to a holding voltage line VSSL that provides the common voltage ELVSS. The drive current output through the first transistor T1 flows through the LED via a conducting fifth transistor T5 and a conducting sixth transistor T6, and the LED can emit light with a brightness corresponding to the magnitude of the drive current.

[0109] Figure 4 The illustrated drive circuit PC includes seven transistors, but this disclosure is not limited thereto. In another embodiment, the drive circuit PC may include six or fewer transistors, or eight or more transistors. Furthermore, the drive circuit PC may include two or fewer capacitors, or four or more capacitors.

[0110] Figure 5 This is a cross-sectional view showing a portion of the display panel 10. For ease of description, Figure 5 The display layer 20 and encapsulation layer 30 of the display panel 10 are shown, but as referenced Figure 2 As described, the encapsulation layer 30 may also include an input detection layer, an optical functional layer, and a cover window.

[0111] refer to Figure 5 The display panel 10 may include light-emitting diodes (LEDs) disposed in the display area DA. The LEDs are disposed on the substrate 100, and a driving circuit PC may be disposed on the substrate 100 between the LEDs. In this respect, Figure 5 The diagram shows a first transistor T1, a first capacitor C1, and a second capacitor C2, which are some components of the drive circuit PC.

[0112] Substrate 100 may comprise a glass material or a polymer resin. In one embodiment, substrate 100 may have an alternating stacked structure comprising a base layer of polymer resin and a barrier layer comprising an inorganic insulating material (such as silicon oxide or silicon nitride). The polymer resin may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate.

[0113] A first conductive layer CL1 may be disposed on the substrate 100. The first conductive layer CL1 may include a conductive material such as a metal. In an embodiment, for example, the first conductive layer CL1 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer or multi-layer structure comprising the conductive material.

[0114] A buffer layer 111 may be disposed on the first conductive layer CL1. The buffer layer 111 may include an inorganic insulating material, such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the inorganic insulating material.

[0115] The second conductive layer CL2 is disposed on the buffer layer 111 and may overlap with the first conductive layer CL1. In an embodiment, the first conductive layer CL1 may include the first electrode C21 of the second capacitor C2, and the second conductive layer CL2 may include the second electrode C22 of the second capacitor C2. The second conductive layer CL2 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer or multi-layer structure comprising the conductive material.

[0116] The first insulating layer 112 may be disposed on the second conductive layer CL2. The first insulating layer 112 may include inorganic insulating materials, such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure including inorganic insulating materials.

[0117] A semiconductor layer ACT1 may be disposed on the first insulating layer 112. The semiconductor layer ACT1 may include a channel region CH1 and a source region S1 and a drain region D1 respectively disposed on opposite sides of the channel region CH1. The semiconductor layer ACT1 may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In embodiments, for example, the semiconductor layer ACT1 may include an InSnZnO (“ITZO”) semiconductor layer or an InGaZnO (“IGZO”) semiconductor layer. A conductive process based on a plasma process may be performed on at least a portion of the semiconductor layer ACT1.

[0118] A third conductive layer CL3 may be disposed on the semiconductor layer ACT1 with a second insulating layer 113 therebetween. A portion of the third conductive layer CL3 may include a 1-1 gate electrode G11 overlapping the channel region CH1, and a portion of the second conductive layer CL2 may include a 1-2 gate electrode G12 overlapping the channel region CH1. The 1-1 gate electrode G11 and the 1-2 gate electrode G12 may overlap each other with the channel region CH1 therebetween. The second insulating layer 113 may include an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer or multi-layer structure including the inorganic insulating material.

[0119] The third insulating layer 114 may be disposed on the third conductive layer CL3. The third insulating layer 114 may include an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer or multi-layer structure including the inorganic insulating material.

[0120] The third conductive layer CL3 may include the first electrode C11 of the first capacitor C1, and the fourth conductive layer CL4 on the third insulating layer 114 may include the second electrode C12 of the first capacitor C1. The third conductive layer CL3 and the fourth conductive layer CL4 may each include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti), and may have a single-layer or multi-layer structure comprising conductive material.

[0121] The data line DL can be disposed on the third insulating layer 114. The data line DL may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure including the conductive material.

[0122] The fourth insulating layer 116 may be disposed on the data cable DL. The fourth insulating layer 116 may include an organic insulating material, such as acrylic acid, benzocyclobutene (“BCB”), polyimide, or hexamethyldisiloxane (“HMDSO”).

[0123] exist Figure 5 In this embodiment, the fourth conductive layer CL4 and the data line DL are arranged in the same layer, but this disclosure is not limited thereto. In another embodiment, an insulating layer may be further disposed between the fourth conductive layer CL4 and the data line DL, and the data line DL may be disposed on an additional insulating layer, and the fourth conductive layer CL4 may be disposed below the additional insulating layer.

[0124] The driving voltage line PL can be disposed on the fourth insulating layer 116 and covered by the fifth insulating layer 117. The driving voltage line PL can include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer or multi-layer structure including the conductive material. The fifth insulating layer 117 can include an organic insulating material.

[0125] Although not in Figure 5 As shown, for example, other voltage lines (e.g., Figure 4 The holding voltage line VSSL, Figure 4 The first initialization voltage line VAL and the second initialization voltage line VIL and Figure 4 The reference voltage line (VRL) can be arranged in the same layer as the drive voltage line PL on the fourth insulating layer 116.

[0126] A light-emitting diode (LED) may include a pixel electrode 210, an emitting layer 222, and a counter electrode 230.

[0127] Pixel electrode 210 may be disposed on fifth insulating layer 117. Pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any combination thereof. In another embodiment, pixel electrode 210 may also include a conductive oxide layer on and / or below the reflective layer. The conductive oxide layer may include indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (“IGO”), and / or aluminum zinc oxide (“AZO”). In an embodiment, pixel electrode 210 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0128] A dam layer 123 may be disposed on the pixel electrode 210. An opening 123OP overlapping the pixel electrode 210 may be defined in the dam layer 123, and the dam layer 123 may cover the edge of the pixel electrode 210. The dam layer 123 may include an organic insulating material. In embodiments, for example, the dam layer 123 may include an organic insulating material comprising a light-shielding material. In some embodiments, the dam layer 123 may include a polyimide (“PI”) based binder and therein mixed red, green, and blue pigments. In alternative embodiments, the dam layer 123 may include a cardo-based binder resin and a combination of lactam black and blue pigments. In alternative embodiments, the dam layer 123 may include carbon black. The dam layer 123 may enhance the contrast of the display panel 10.

[0129] Spacers 125 may be disposed on the dam layer 123. Spacers 125 may comprise a material different from that of the dam layer 123. In one embodiment, the dam layer 123 and spacers 125 may comprise materials different from each other; for example, the dam layer 123 may comprise a negatively photosensitive material, while the spacers 125 may comprise a positively photosensitive material and may be formed by a separate masking process. In another embodiment, spacers 125 may comprise the same material as the dam layer 123 and may be formed together with the dam layer 123 by the same masking process (e.g., a halftone masking process).

[0130] The emitting layer 222 may include a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a predetermined color. Depending on the light-emitting diode (LED), the emitting layer 222 may include a material that emits red, green, or blue light.

[0131] The functional layers may be further disposed below and / or on the emitter layer 222. In an embodiment, for example, a first functional layer 221 may be further disposed between the pixel electrode 210 and the emitter layer 222, and a second functional layer 223 may be further disposed between the emitter layer 222 and the opposing electrode 230 described below. The first functional layer 221 may include a hole transport layer and / or a hole injection layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer.

[0132] The counter electrode 230 may include a conductive material having a relatively low work function. In embodiments, for example, the counter electrode 230 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or any alloy thereof. The counter electrode 230 may also include a layer comprising ITO, IZO, ZnO, and / or In2O3 on top of a (semi-)transparent layer comprising such a material.

[0133] Unlike pixel electrodes 210 which are individually formed to correspond to light-emitting diodes (LEDs), the opposing electrode 230 can extend to correspond to multiple pixel electrodes 210. In an embodiment, for example, pixel electrodes 210 of one LED and pixel electrodes 210 of another LED can be separated and spaced apart from each other, but the opposing electrode 230, which overlaps with the multiple pixel electrodes 210, can extend to cover the multiple pixel electrodes 210.

[0134] The encapsulation layer 30 may be disposed on the display layer 20 and includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this embodiment, Figure 5 The encapsulation layer 30 is shown to include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0135] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic encapsulation layer selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or multiple layers comprising the above materials. The organic encapsulation layer 320 may include a polymer-based material. In embodiments, the polymer-based material may include acrylic resin, epoxy resin, polyimide, and polyethylene. In embodiments, the organic encapsulation layer 320 may include acrylate.

[0136] Figure 6 This is a plan view showing an embodiment of a portion of the display panel 10, and shows... Figure 3 Region III.

[0137] refer to Figure 6 The display area DA contains pixels that emit different lights (e.g., first pixel P1 to third pixel P3). In one embodiment, for example, first pixel P1 and second pixel P2 may be arranged in the same column, and third pixel P3 may be located in a column adjacent to the column in which first pixel P1 and second pixel P2 are arranged.

[0138] One of the first pixel P1 to the third pixel P3 can be a red pixel, another can be a green pixel, and the remaining pixel can be a blue pixel. The first pixel P1 to the third pixel P3 can correspond to the emission regions from which light is emitted by the respective light-emitting diodes. In an embodiment, for example, the first pixel P1 can correspond to the emission region of the light-emitting diode corresponding to the first pixel P1 (hereinafter, the first emission region EA1), the second pixel P2 can correspond to the emission region of the light-emitting diode corresponding to the second pixel P2 (hereinafter, the second emission region EA2), and the third pixel P3 can correspond to the emission region of the light-emitting diode corresponding to the third pixel P3 (hereinafter, the third emission region EA3).

[0139] The launch area can be limited to the above references. Figure 5 Description Figure 5 The opening of the embankment 123, for example, with Figure 5 The pixel electrodes 210 overlap Figure 5 The opening is 123OP. Therefore, Figure 6 The first launch area EA1 to the third launch area EA3 can respectively correspond to the first opening 123OP1 to the third opening 123OP3 of the dam 123.

[0140] refer to Figure 6 The embankment 123 can extend toward the intermediate region MA, and the dummy opening can be defined in the intermediate region MA within the embankment 123 in a predetermined pattern. In this respect, Figure 6 The diagram illustrates a first dummy opening DOP1 to a third dummy opening DOP3 defined within an intermediate region MA (e.g., a dummy region DMA). In some embodiments, the dummy openings may not be defined within a wiring region (e.g., as shown in the diagram). Figure 6 In the second wiring area RA2 shown.

[0141] The arrangement of the first dummy openings DOP1 to the third dummy openings DOP3 can be substantially the same as the arrangement of the first openings 123OP1 to the third openings 123OP3. The first dummy openings DOP1 and DOP2 can be defined in the same column, and the third dummy opening DOP3 can be defined in a column adjacent to the columns of the first dummy openings DOP1 and DOP2. The first dummy openings DOP1 and DOP2, as well as the first openings 123OP1 and 123OP2, can be defined in the same column, and the third dummy openings DOP3 and 123OP3 can be defined in the same column. The intervals between the first dummy openings DOP1 and DOP2, and between the first openings 123OP1 and 123OP2, can be substantially the same.

[0142] The dimensions of the first dummy openings DOP1 to DOP3 and the first opening 123OP1 to DOP3 can be substantially the same. In an embodiment, for example, the width in the x-direction and the length in the y-direction of the first dummy opening DOP1 can be substantially the same as the width in the x-direction and the length in the y-direction of the first opening 123OP1. The width in the x-direction and the length in the y-direction of the second dummy opening DOP2 can be substantially the same as the width in the x-direction and the length in the y-direction of the second opening 123OP2. The width in the x-direction and the length in the y-direction of the third dummy opening DOP3 can be substantially the same as the width in the x-direction and the length in the y-direction of the third opening 123OP3.

[0143] The dam layer 123 defines dummy openings (e.g., first dummy openings DOP1 to third dummy openings DOP3), and therefore, the reflectivity in the intermediate region MA and the reflectivity in the display region DA of the display panel 10 can be similar to each other. Specifically, the first dummy openings DOP1 to third dummy openings DOP3 of the dam layer 123 defined in the intermediate region MA have substantially the same arrangement and / or dimensions as the first openings 123OP1 to third openings 123OP3 as described above, and therefore, it is possible to effectively prevent the display region DA and the intermediate region MA from being identified differently by the user when the display panel 10 is in the off state (when the display panel 10 is not operating).

[0144] refer to Figure 6 A transmission region (e.g., a second transmission region TA2) and an opening (hereinafter, transmission opening 123OPT) overlapping the transmission region (e.g., the second transmission region TA2) may be defined in the embankment 123. The size of the transmission opening 123OPT may be substantially equal to or larger than the size of the second transmission region TA2.

[0145] Figure 6 The intermediate region MA and display region DA surrounding the second transmission region TA2 are shown, but this disclosure is not limited thereto. In another embodiment, the structure surrounding another transmission region (such as the first transmission region TA1) can be... Figure 6 The structures shown are the same.

[0146] Figure 7 This is shown as the display panel 10. Figure 6 A plan view of a selected implementation of region VII shown in the diagram, and Figure 8 It is along Figure 7A cross-sectional view of the display panel 10 taken by lines VIIIa-VIIIa' and VIIIb-VIIIb'.

[0147] refer to Figure 7 The display area DA may contain a first pixel electrode 210-1, a second pixel electrode 210-2, and a third pixel electrode 210-3, which may be arranged in the display area DA and spaced apart from each other. The first pixel electrode 210-1 and the second pixel electrode 210-2 may be arranged in the same column, and the third pixel electrode 210-3 may be arranged in a column adjacent to the column in which the first pixel electrode 210-1 and the second pixel electrode 210-2 are arranged.

[0148] refer to Figure 7 The display area DA and along Figure 8 The cross-sectional view taken by lines VIIIa-VIIIa' shows that the embankment 123 can cover the edges of the first pixel electrode 210-1, the second pixel electrode 210-2 and the third pixel electrode 210-3, and defines a first opening 123OP1 that overlaps with the first pixel electrode 210-1, a second opening 123OP2 that overlaps with the second pixel electrode 210-2 and a third opening 123OP3 that overlaps with the third pixel electrode 210-3.

[0149] The size (or area) of the opening in the dam layer 123 can correspond to the size (or area) of the light-emitting region and / or the size (or area) of the sub-pixel. In an embodiment, for example, the size (or area) of the first opening 123OP1 of the dam layer 123 can correspond to the light-emitting region emitted to the light-emitting diode including the first pixel electrode 210-1 (i.e., Figure 6 The size (or area) of the first launch region EA1 and / or Figure 6 The size (or area) of the first pixel P1. The size (or area) of the second opening 123OP2 of the embankment 123 can correspond to the emission area of ​​light emitted to the light-emitting diode including the second pixel electrode 210-2 (i.e., Figure 6 The size (or area) of the second launch area EA2 and / or Figure 6 The size (or area) of the second pixel P2. The size (or area) of the third opening 123OP3 of the embankment 123 can correspond to the emission area of ​​light emitted to the light-emitting diode including the third pixel electrode 210-3 (i.e., Figure 6 The size (or area) and / or of the third launch area (EA3) Figure 6 The size (or area) of the third pixel P3.

[0150] The first pixel electrode 210-1 to the third pixel electrode 210-3 and the first opening 123OP1 to the third opening 123OP3 of the embankment layer 123 can each overlap with a transistor. In this respect, Figure 8 The first capacitor C1 and the second capacitor C2, the first transistor T1 and the sixth transistor T6 of the driving circuit PC are shown, and the third pixel electrode 210-3 and the third opening 123OP3 of the embankment 123 overlap with the first transistor T1 and / or the sixth transistor T6 of the driving circuit PC.

[0151] Including the third pixel electrode 210-3 Figure 8 The detailed structure of the light-emitting diode (LED) is the same as the one mentioned above. Figure 5 The structure is identical to that described above, and the light-emitting diode (LED) can be encapsulated by the encapsulation layer 30. Except for the material of the emitting layer overlapping each of the first pixel electrode 210-1 to the third pixel electrode 210-3 through the first opening 123OP1 to the third opening 123OP3, the detailed structure of the LED including the first pixel electrode 210-1 and the second pixel electrode 210-2 is also as described above. Figure 5 As described.

[0152] refer to Figure 7 The dummy electrode layer DEL can be disposed in the intermediate region MA. The dummy electrode layer DEL may include a first part having a shape corresponding to the first pixel electrode 210-1, a second part having a shape corresponding to the second pixel electrode 210-2, and a third part having a shape corresponding to the third pixel electrode 210-3, and the first part to the third part may be integrally connected to each other.

[0153] The dam layer 123 may define a first dummy opening DOP1 to a third dummy opening DOP3 that overlap with the same dummy electrode layer DEL. The first dummy opening DOP1 may overlap with a first portion of the dummy electrode layer DEL, the second dummy opening DOP2 may overlap with a second portion of the dummy electrode layer DEL, and the third dummy opening DOP3 may overlap with a third portion of the dummy electrode layer DEL.

[0154] The arrangement of the first dummy openings DOP1 to the third dummy openings DOP3 can be substantially the same as the arrangement of the first openings 123OP1 to the third openings 123OP3. In an embodiment, for example, the first dummy openings DOP1 and the second dummy openings DOP2 can be defined in the same column, and the third dummy opening DOP3 can be defined in a column adjacent to the column defined by the first dummy openings DOP1 and the second dummy openings DOP2.

[0155] The first dummy opening DOP1 and the second dummy opening DOP2, as well as the first opening 123OP1 and the second opening 123OP2, can be defined in the same column, and the third dummy opening DOP3 and the third opening 123OP3 can be defined in the same column. The dimensions of the first dummy openings DOP1 to the third dummy openings DOP3 and the dimensions of the first openings 123OP1 to the third openings 123OP3 can be substantially the same. The intervals between the first dummy openings DOP1 and the second dummy openings DOP2 and the intervals between the first openings 123OP1 and the second openings 123OP2 can be substantially the same.

[0156] refer to Figure 7 The middle region MA and along Figure 8 A cross-sectional view taken by lines VIIIb-VIIIb', for example, Figure 8 As shown, the dummy electrode layer DEL can be disposed in the same layer as the first pixel electrode 210-1 to the third pixel electrode 210-3 on the fifth insulating layer 117. The dummy electrode layer DEL can include the same material as the first pixel electrode 210-1 to the third pixel electrode 210-3.

[0157] The dummy electrode layer DEL can be electrically connected to the voltage line CVL via contact holes CNTs passing through an insulating layer (e.g., fifth insulating layer 117) disposed between the dummy electrode layer DEL and the voltage line CVL. The voltage line CVL can be as described above. Figure 4 The described voltage line CVL is either a holding voltage line VSSL or a first initialization voltage line VAL. The voltage line CVL can extend in the display area DA towards the central area MA, and the dummy electrode layer DEL can be electrically connected to the voltage line CVL disposed beneath it. In the implementation, as... Figure 7 As shown in the diagram, in the plan view, the position of the contact hole CNT can be within a virtual triangle connecting the center of the first dummy opening DOP1, the center of the second dummy opening DOP2, and the center of the third dummy opening DOP3.

[0158] like Figure 8 As shown, the first dummy opening DOP1 to the third dummy opening DOP3 and the dummy electrode layer DEL can overlap with the dummy transistor below them. When the driving circuit PC is formed in the display area DA, a dummy driving circuit D-PC can also be formed in the intermediate area MA, and in this respect, Figure 8A dummy drive circuit D-PC is shown, comprising a first dummy transistor D-T1 and a sixth dummy transistor D-T6. The dummy electrode layer DEL and the first dummy openings DOP1 to DOP3 may overlap with the dummy transistors of the dummy drive circuit D-PC (e.g., the first dummy transistor D-T1 and / or the sixth dummy transistor D-T6). The dummy drive circuit D-PC is not electrically connected to the dummy electrode layer DEL. In other words, the dummy drive circuit D-PC is electrically insulated from the dummy electrode layer DEL.

[0159] like Figure 8 As shown, the first dummy emitter layer DML1 to the third dummy emitter layer DML3 overlap with the first to third portions of the dummy electrode layer DEL through the first dummy opening DOP1 to the third dummy opening DOP3 on the dummy electrode layer DEL, and the opposite electrode 230 can extend across the first dummy emitter layer DML1 to the third dummy emitter layer DML3. Similarly, the first functional layer 221 and the second functional layer 223 can also extend across the first dummy emitter layer DML1 to the third dummy emitter layer DML3. However, in an embodiment, when the voltage line CVL includes Figure 4 When the voltage line CVL is maintained, the dummy electrode layer DEL has the same voltage level as the opposing electrode 230, and therefore, light is not emitted from the stacked structure of the first to third portions of the dummy electrode layer DEL, the first dummy emission layer DML1 to the third dummy emission layer DML3, and the opposing electrode 230. In another embodiment, when the voltage line CVL includes Figure 4 During the first initialization voltage line VAL, the dummy electrode layer DEL has a higher voltage than... Figure 4 The sum of the common voltage ELVSS and the threshold voltage Vth of the light-emitting diode is a low voltage level, and therefore, light is not emitted from the stacked structure of the first to third portions of the dummy electrode layer DEL, the first to third dummy emission layers DML1 to DML3, and the opposite electrode 230. In other words, the stacked structure of the dummy electrode layer DEL, the first to third dummy emission layers DML1 to DML3, and the opposite electrode 230 corresponds to the type of dummy emission structure.

[0160] exist Figure 7 and Figure 8 The present invention describes a dummy electrode layer DEL electrically connected to a voltage line CVL, but this disclosure is not limited thereto. In another embodiment, the dummy electrode layer DEL may be in an electrically floating state without being electrically connected to the voltage line CVL. Figures 6 to 8 It shows the corresponding Figure 3 The intermediate region MA of region III is a portion surrounding the second transmission region TA2, but this disclosure is not limited thereto. The structure of the intermediate region MA, a portion surrounding the first transmission region TA1, can be similar to that of the referenced region.Figures 6 to 8 The structures of the described implementation methods are basically the same.

[0161] Figure 9 This is a plan view of an embodiment showing a portion of the display panel 10 in the embodiment, and shows... Figure 3 Region III.

[0162] Figure 9 The display panel 10 in the embodiment includes the above reference. Figure 6 The described structure. In the implementation, such as Figure 9 As shown, for example, the display panel 10 may include pixels (e.g., first pixels P1 to third pixels P3) that emit light of different colors in the display area DA, and dummy openings (e.g., first dummy openings DOP1 to third dummy openings DOP3) may be defined in the display panel 10 in the dummy area DMA. Furthermore, a transmission opening 123OPT of the dam layer 123 that overlaps with a transmission area (e.g., a second transmission area TA2) may be defined in the display panel 10. As described above, the first pixels P1 to third pixels P3 are emission areas of light emitted from a light-emitting diode, and correspond to first emission areas EA1 to third emission areas EA3, and the first emission areas EA1 to third emission areas EA3 correspond to the first openings 123OP1 to third openings 123OP3 of the dam layer 123.

[0163] exist Figure 9 In some implementations, additional dummy openings may be provided, defined within the wiring region (e.g., the second wiring region RA2 within the intermediate region MA). In this respect, Figure 9 The fourth dummy opening DOP4 to the sixth dummy opening DOP6 of the dam layer 123 are shown.

[0164] The arrangement of the fourth dummy opening DOP4 to the sixth dummy opening DOP6 can be substantially the same as the arrangement of the first dummy opening DOP1 to the third dummy opening DOP3 and / or the arrangement of the first opening 123OP1 to the third opening 123OP3. The fourth dummy opening DOP4 and the fifth dummy opening DOP5 can be defined in the same column, and the sixth dummy opening DOP6 can be defined in a column adjacent to the columns defined by the fourth dummy opening DOP4 and the fifth dummy opening DOP5. The fourth dummy opening DOP4 and the fifth dummy opening DOP5, the first dummy opening DOP1 and the second dummy opening DOP2, and the first opening 123OP1 and the second opening 123OP2 can be defined in the same column, and the sixth dummy opening DOP6, the third dummy opening DOP3, and the third opening 123OP3 can be defined in the same column. The intervals between the fourth dummy opening DOP4 and the fifth dummy opening DOP5, the intervals between the first dummy opening DOP1 and the second dummy opening DOP2, and the intervals between the first opening 123OP1 and the second opening 123OP2 can be substantially the same as each other.

[0165] The dimensions of the fourth dummy opening DOP4 to the sixth dummy opening DOP6 can be substantially the same as the dimensions of the first dummy opening DOP1 to the third dummy opening DOP3 and / or the dimensions of the first opening 123OP1 to the third opening 123OP3, respectively. In an embodiment, for example, the width in the x-direction and the length in the y-direction of the fourth dummy opening DOP4 can be substantially the same as the width in the x-direction and the length in the y-direction of the first dummy opening DOP1 and / or the width in the x-direction and the length in the y-direction of the first opening 123OP1. The width in the x-direction and the length in the y-direction of the fifth dummy opening DOP5 can be substantially the same as the width in the x-direction and the length in the y-direction of the second dummy opening DOP2 and / or the width in the x-direction and the length in the y-direction of the second opening 123OP2. The width in the x-direction and the length in the y-direction of the sixth dummy opening DOP6 can be substantially the same as the width in the x-direction and the length in the y-direction of the third dummy opening DOP3 and / or the width in the x-direction and the length in the y-direction of the third opening 123OP3.

[0166] The embankment 123 defines dummy openings (e.g., first dummy openings DOP1 to third dummy openings DOP3 and fourth dummy openings DOP4 to sixth dummy openings DOP6), and therefore, the reflectivity in the intermediate region MA of the display panel 10 and the reflectivity in the display region DA can be similar to each other. In an embodiment, for example, the first dummy openings DOP1 to third dummy openings DOP3 and fourth dummy openings DOP4 to sixth dummy openings DOP6 of the embankment 123 defined in the intermediate region MA have an arrangement and / or dimensions substantially the same as those of the first openings 123OP1 to third openings 123OP3 as described above, and therefore, it can be further effectively prevented that the display region DA and the intermediate region MA are identified differently by the user when the display panel 10 is in the off state (when the display panel 10 is not in operation).

[0167] Figure 9 The intermediate region MA and display region DA surrounding the second transmission region TA2 are shown, but this disclosure is not limited thereto. In another embodiment, the structure surrounding another transmission region (such as the first transmission region TA1) may be related to... Figure 9 The structures shown are the same.

[0168] Figure 10 This is shown as the display panel 10. Figure 9 A plan view of a selected implementation of region X, and Figure 11 It is along Figure 10 A cross-sectional view of the display panel taken by lines XIa-XIa' and XIb-XIb'.

[0169] Figure 10 and Figure 11 The structure of the display area DA and the dummy area DMA in the intermediate region MA is the same as the above reference. Figure 7 and Figure 8 The descriptions of those that are the same, and therefore the same in structure, will be explained by reference. Figure 7 and Figure 8 The description is replaced by [the description].

[0170] refer to Figure 10 The second wiring region RA2 in the intermediate region MA, and the dummy electrode layer DEL disposed in the dummy region DMA can extend toward the second wiring region RA2. In the second wiring region RA2, the fourth dummy opening DOP4 to the sixth dummy opening DOP6 overlapping with the dummy electrode layer DEL can be defined in the embankment layer 123 in a predetermined pattern.

[0171] The fourth dummy opening DOP4 can overlap with the fourth portion of the dummy electrode layer DEL, the fifth dummy opening DOP5 can overlap with the fifth portion of the dummy electrode layer DEL, and the sixth dummy opening DOP6 can overlap with the sixth portion of the dummy electrode layer DEL. The first dummy opening DOP1 can overlap with the first portion of the dummy electrode layer DEL, the second dummy opening DOP2 can overlap with the second portion of the dummy electrode layer DEL, and the third dummy opening DOP3 can overlap with the third portion of the dummy electrode layer DEL.

[0172] In the plan view, the portion of the dummy electrode layer DEL extending toward the wiring region (e.g., the second wiring region RA2) can have a shape substantially the same as the shape of the portion of the dummy electrode layer DEL disposed in the dummy region DMA, and can be integrally connected thereto. In an implementation, for example, the relative arrangement between the fourth to sixth portions of the dummy electrode layer DEL disposed in the second wiring region RA2 and the dimensions of each portion (e.g., width in the x direction and length in the y direction) can be the same as the relative arrangement between the first to third portions of the dummy electrode layer DEL disposed in the dummy region DMA and the dimensions of each portion (e.g., width in the x direction and length in the y direction).

[0173] In the dummy region DMA, the dummy electrode layer DEL can overlap with the dummy transistors of the dummy drive circuit D-PC below it, and can be electrically connected to the voltage line CVL extending toward the intermediate region MA. The voltage line CVL can be the reference mentioned above. Figure 4 The described holding voltage line VSSL or first initialization voltage line VAL. In this specification, when it is described as "A is set below B", A and B can be perpendicular to each other. Figure 11 The substrates 100 are arranged and / or overlap each other in the direction of A and B, and electrodes, components and / or layers may be disposed between A and B.

[0174] The transistor is not located in the wiring region (e.g., the second wiring region RA2). Therefore, in the second wiring region RA2, the dummy electrode layer DEL does not overlap with the transistor (e.g., the dummy transistor). Similarly, the fourth dummy opening DOP4 to the sixth dummy opening DOP6 do not overlap with the transistor.

[0175] In some implementations, the dummy electrode layer DEL extending toward the second wiring region RA2 and / or at least one selected from the fourth dummy opening DOP4 to the sixth dummy opening DOP6 may overlap with the bypass portion of the signal line disposed below it.

[0176] Reference along Figure 11A cross-sectional view taken from line XIb-XIb', a portion of the dummy electrode layer DEL extending toward the second wiring region RA2 and / or at least one selected from the fourth dummy opening DOP4 to the sixth dummy opening DOP6 may be in conjunction with... Figure 9 The second transmission region TA2 surrounds the data line winding portion DL-C and / or the scan line winding portion SL-C, which overlap. The data line winding portion DL-C and the scan line winding portion SL-C can be arranged in different layers with an insulating layer between them. As described above, the data line winding portion DL-C and / or the scan line winding portion SL-C correspond to providing a signal to drive as referenced above. Figure 3 The described settings are in the display area DA Figure 3 The data lines DL and scan lines SL of the light-emitting diode (LED) (e.g., the portion surrounding the line in the transmission area). Figures 9 to 11 It shows the corresponding Figure 3 The intermediate region MA of region III is a portion surrounding the second transmission region TA2, but this disclosure is not limited thereto. The structure of the intermediate region MA, a portion surrounding the first transmission region TA1, can be similar to that of the referenced region. Figures 9 to 11 The structures of the described implementation methods are basically the same.

[0177] Figure 12 This is a schematic plan view illustrating an embodiment of the display panel 10, and Figure 13 It is shown Figure 12 A plan view of a portion of the display panel 10 (e.g., a section of region XII).

[0178] As referenced above Figure 2 As described, the display panel 10 may include a cover window 60. The cover window 60 may include a light-transmitting portion and a light-shielding portion corresponding to the peripheral region PA. The light-transmitting portion of the cover window 60 may overlap with the first transmission region TA1 and the second transmission region TA2 of the display panel 10, and the display region DA. The light-shielding portion of the cover window 60 may overlap with the intermediate region MA and the peripheral region PA.

[0179] The cover window 60 may include a first light-transmitting portion 61 overlapping the display area DA, and a second light-transmitting portion 62 and a third light-transmitting portion 63 overlapping the first transmission area TA1 and the second transmission area TA2, respectively. The cover window 60 may also include a first light-shielding portion 64 overlapping the intermediate area MA and a second light-shielding portion 65 overlapping the peripheral area PA.

[0180] The area of ​​the first light-blocking portion 64 of the covering window 60 may not be the same as the area of ​​the intermediate region MA. In an embodiment, such as Figure 13As shown, for example, the first light-shielding portion 64 may have a shape similar to that of the intermediate region MA, and the area of ​​the first light-shielding portion 64 may be smaller than the area of ​​the intermediate region MA.

[0181] The first light-shielding portion 64 may include an outer edge 64OE defining the shape of the first light-shielding portion 64, and a first inner edge 64IE1 and a second inner edge 64IE2. The first inner edge 64IE1 and the second inner edge 64IE2 of the first light-shielding portion 64 may each have a closed curve shape surrounding the first transmission region TA1 and the second transmission region TA2. In a plan view, the outer edge 64OE of the first light-shielding portion 64 may have a closed curve shape surrounding the first inner edge 64IE1 and the second inner edge 64IE2.

[0182] The boundary between the first light-shielding portion 64 and the first light-transmitting portion 61 can be defined by the outer edge 64OE of the first light-shielding portion 64. The outer edge 64OE of the first light-shielding portion 64 can be set to be farther away from the display area DA than the boundary between the intermediate area MA and the display area DA.

[0183] Figure 14a and Figure 14b Each shows along Figure 13 A cross-sectional view of an embodiment of the display panel 10 taken by lines XIV-IXV'.

[0184] refer to Figure 14a and Figure 14b The first light-shielding portion 64 of the cover window 60 may overlap with a portion of the dummy electrode layer DEL disposed in the intermediate region MA, but may not overlap with another portion of the dummy electrode layer DEL. The first light-shielding portion 64 may overlap with at least one of the dummy openings DOP of the embankment layer 123 defined in the intermediate region MA, but may not overlap with some of the other dummy openings DOP. In an embodiment, for example, a dummy opening DOP of the embankment layer 123 that is relatively adjacent to the display area DA may not overlap with the first light-shielding portion 64 of the cover window 60, while a dummy opening DOP that is relatively distant from the display area DA may overlap with the first light-shielding portion 64 of the cover window 60.

[0185] The first light-transmitting portion 61 of the cover window 60 may overlap with the light-emitting diodes (LEDs) arranged in the display area DA and the opening 123OP of the embankment 123. The first light-transmitting portion 61 may overlap with a portion of the dummy electrode layer DEL that is arranged adjacent to the display area DA and some of the dummy opening DOP of the embankment 123.

[0186] The first light-shielding portion 64 of the cover window 60 may overlap with the bypass portion of the signal line passing through the intermediate region MA. In an embodiment, as...Figure 14a As shown, the data line bypass portion DL-C and the scan line bypass portion SL-C passing through the second wiring region RA2 can overlap with the first light-shielding portion 64 and the dam layer 123 (e.g., an organic material of the dam layer 123). In another embodiment, as... Figure 14b As shown, the data line bypass portion DL-C and the scan line bypass portion SL-C passing through the second wiring area RA2 can overlap with the first light-shielding portion 64 of the cover window 60, and at the same time overlap with the dummy opening DOP of the embankment 123.

[0187] Reference Figure 13 , Figure 14a and Figure 14b In the described embodiment, the first light-shielding portion 64 overlaps with the dummy opening DOP below it in the intermediate region MA, but this disclosure is not limited thereto. Figure 14a and Figure 14b It shows Figure 13 The second transmission region TA2 is a portion of the intermediate region MA surrounding the first transmission region TA1 and a portion of the display region DA, but this disclosure is not limited thereto. The structure of the portion of the intermediate region MA surrounding the first transmission region TA1 and the portion of the display region DA can be similar to that of the referenced region. Figure 14a and Figure 14b The structures of the described implementation methods are basically the same.

[0188] Figure 15 This schematically shows a portion of the display panel 10 (e.g., Figure 12 A plan view of the implementation method in area XII). Figure 16 It is shown Figure 15 A partial plan view of region XVI, and Figure 17 It is along Figure 16 The line XVII-XVII' intercepted Figure 16 A cross-sectional view of region XVI.

[0189] like Figure 15 As shown, the outer edge 64OE of the first light-shielding portion 64 is disposed in the middle region MA, but the dummy opening may not be limited to below the first light-shielding portion 64.

[0190] like Figure 16 and Figure 17 As shown, the dummy opening may not be below the first light-shielding portion 64. In an embodiment, for example, the dummy opening may not be on a portion of the dummy electrode layer DEL disposed below the first light-shielding portion 64. Figure 17 As shown, the dummy electrode layer DEL may include a covered portion (or a non-opening portion NOP) that is completely covered by the embankment layer 123.

[0191] A portion of the covered portion NOP of the dummy electrode layer DEL can overlap with the first light-shielding portion 64, and another portion of the covered portion NOP can overlap with the first light-transmitting portion 61, while not overlapping with the first light-shielding portion 64.

[0192] like Figure 16 As shown, the dummy openings overlapping the first light-transmitting portion 61 can be defined within the embankment 123, and the shapes of the dummy openings can be different from each other. In an embodiment, for example, a first dummy opening DOP1 can have a shape and size different from that of another first dummy opening DOP1, and a third dummy opening DOP3 can have a shape and size different from that of another third dummy opening DOP3.

[0193] like Figure 16 As shown, the shape of the dummy opening can define the dummy boundary 123BE of the embankment 123 that passes through the intermediate region MA. The dummy boundary 123BE of the embankment 123 can be defined by the edge of the dummy opening. In other words, the shape and size of the dummy opening through which the dummy boundary 123BE of the embankment 123 passes can be different from the shape and size of the dummy openings spaced apart from the dummy boundary 123BE of the embankment 123.

[0194] The shape of the first dummy opening DOP1 through which the virtual boundary 123BE of the embankment 123 passes may differ from the shape of another first dummy opening DOP1 in the intermediate region MA that is spaced apart from the virtual boundary 123BE of the embankment 123 and the shape of the first opening 123OP1 defined in the display region DA. The size of the first dummy opening DOP1 through which the virtual boundary 123BE of the embankment 123 passes may be smaller than the size of another first dummy opening DOP1 in the intermediate region MA that is spaced apart from the virtual boundary 123BE of the embankment 123, and smaller than the size of the first opening 123OP1 defined in the display region DA.

[0195] The shape and size of a first dummy opening DOP1 in the intermediate region MA, spaced apart from the virtual boundary 123BE of the embankment 123, can be the same as the shape and size of the first opening 123OP1 defined in the display region DA. The shape and size of the first dummy opening DOP1 through which the virtual boundary 123BE of the embankment 123 passes can be different from the shape and size of the first dummy opening DOP1. In an embodiment, for example, the size of the first dummy opening DOP1 through which the virtual boundary 123BE of the embankment 123 passes can be smaller than the size of the first dummy opening DOP1.

[0196] The shape and size of the second dummy opening DOP2 through which the virtual boundary 123BE of the embankment 123 passes may differ from the shape and size of the second dummy opening DOP2 defined in the display area DA. In an embodiment, for example, the size of the second dummy opening DOP2 through which the virtual boundary 123BE of the embankment 123 passes may be smaller than the size of the second dummy opening DOP2 defined in the display area DA. The shape of the second dummy opening DOP2 through which the virtual boundary 123BE of the embankment 123 passes may differ from the shape of another second dummy opening (not shown) in the intermediate area MA that is spaced apart from the virtual boundary 123BE of the embankment 123.

[0197] The shape and size of the third dummy opening DOP3 through which the virtual boundary 123BE of the dike layer 123 passes may differ from the shape and size of another third dummy opening DOP3 in the intermediate region MA that is spaced apart from the virtual boundary 123BE of the dike layer 123, and the shape and size of the third opening 123OP3 defined in the display region DA. The size of the third dummy opening DOP3 through which the virtual boundary 123BE of the dike layer 123 passes may be smaller than the size of another third dummy opening DOP3 in the intermediate region MA that is spaced apart from the virtual boundary 123BE of the dike layer 123, and smaller than the size of the third opening 123OP3 defined in the display region DA. The shape and size of the other third dummy opening DOP3 in the intermediate region MA that is spaced apart from the virtual boundary 123BE of the dike layer 123 may be the same as the shape and size of the third opening 123OP3 defined in the display region DA. Figure 16 and Figure 17 It shows the relationship with Figure 15 The region XVI corresponds to a portion of the intermediate region MA surrounding the second transmission region TA2 and a portion of the display region DA, but this disclosure is not limited thereto. The structure of a portion of the intermediate region MA surrounding the first transmission region TA1 and a portion of the display region DA can be similar to that of the referenced region. Figure 16 and Figure 17 The structures of the described implementation methods are basically the same.

[0198] It should be understood that the embodiments described herein should be interpreted in a descriptive sense only and not for limiting purposes. The description of features or advantages within each embodiment should generally be considered applicable to other similar features or advantages in other embodiments. Although embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. Display panel, including: A substrate, wherein a transmissive region, a dummy region surrounding the transmissive region, and a display region surrounding the dummy region are defined in the substrate; A driving circuit is disposed in the display area and includes transistors; A voltage line is provided in the display area and electrically connected to the drive circuit; Insulating layer on the voltage line; A first pixel electrode is disposed on the insulating layer in the display area; A dam layer covers the edge of the first pixel electrode, the dam layer defining a first opening that overlaps with the first pixel electrode; The emission layer overlaps with the first pixel electrode through the first opening in the dam layer; A relative electrode is disposed on the emission layer and overlaps with the first pixel electrode and the emission layer; as well as A dummy electrode layer is disposed on the insulating layer in the dummy region. The embankment extends toward the dummy region and defines a plurality of dummy openings that overlap with the dummy electrode layer.

2. The display panel according to claim 1 further includes a dummy transistor disposed below the dummy electrode layer. in, The dummy electrode layer is electrically insulated from the dummy transistor.

3. The display panel according to claim 1, wherein, The voltage line extends toward the dummy region and a portion of the voltage line overlaps with the dummy electrode layer. The dummy electrode layer is electrically connected to the voltage line.

4. The display panel according to claim 3, wherein, The voltage line has the same voltage level as the opposite electrode.

5. The display panel according to claim 3, wherein, The driving circuit further includes an initialization transistor electrically connected to the first pixel electrode and initializing the first pixel electrode. The voltage line is electrically connected to the initialization transistor.

6. The display panel according to claim 1, wherein, The plurality of dummy openings in the dam layer include a first dummy opening, a second dummy opening, and a third dummy opening that overlap with different portions of the dummy electrode layer, respectively.

7. The display panel according to claim 6, further comprising: The second pixel electrode is disposed on the insulating layer in the display area and is adjacent to the first pixel electrode while being separated from it. as well as A third pixel electrode is disposed on the insulating layer in the display area, and is adjacent to and separated from the first pixel electrode and the second pixel electrode. The embankment further defines a second opening and a third opening, wherein the second opening overlaps with the second pixel electrode, and the third opening overlaps with the third pixel electrode. The first opening and the second opening are defined in the same column, and the third opening is defined as being adjacent to the column of the first opening and the second opening. The first dummy opening and the second dummy opening are defined in the same column, and the third dummy opening is defined as being adjacent to the column of the first dummy opening and the second dummy opening.

8. The display panel according to claim 7, wherein, The size of the first illusory opening is substantially the same as the size of the first opening. The dimensions of the second illusory opening and the second opening are substantially the same, and The size of the third dummy opening and the size of the third opening are substantially the same.

9. The display panel according to claim 7, wherein, The size and shape of the first illusory opening are different from the size and shape of the first opening.

10. The display panel according to claim 6, wherein, A wiring region is further defined in the substrate between the transmissive region and the dummy region, and the wiring region surrounds the transmissive region. The dummy electrode layer extends toward the wiring area, and The embankment layer further defines a fourth dummy opening, a fifth dummy opening, and a sixth dummy opening, which overlap with different portions of the dummy electrode layer arranged in the wiring area.

11. The display panel according to claim 10, wherein, The dimensions of the first illusory opening, the second illusory opening, and the third illusory opening are different from each other. The size of the fourth dummy opening is substantially the same as the size of the first dummy opening. The dimensions of the fifth illusory opening and the second illusory opening are substantially the same as each other, and The size of the sixth dummy opening is substantially the same as the size of the third dummy opening.

12. The display panel according to claim 10, wherein, In the wiring region, the dummy electrode layer does not overlap with the transistor.

13. The display panel of claim 10, further comprising a signal line electrically connected to the driving circuit. in, The signal line travels along the edge of the transmission area in the wiring area, and The dummy electrode layer overlaps with the bypass portion of the signal line in the wiring area.

14. The display panel according to claim 1, wherein, The embankment layer includes light-blocking material.

15. Electronic devices, including: A display panel, defining a transmissive area, a dummy area surrounding the transmissive area, and a display area surrounding the dummy area, the display panel comprising: A driving circuit is disposed in the display area and includes transistors; A voltage line is provided in the display area and electrically connected to the drive circuit; Insulating layer on the voltage line; A first pixel electrode is disposed on the insulating layer in the display area; A dam layer covers the edge of the first pixel electrode and includes a first opening that overlaps with the first pixel electrode; The emission layer overlaps with the first pixel electrode through the first opening in the dam layer; A relative electrode is disposed on the emission layer and overlaps with the first pixel electrode and the emission layer; and A dummy electrode layer is disposed on the insulating layer in the dummy region; and The component overlaps with the transmissive area of ​​the display panel. The embankment extends toward the dummy region and includes a plurality of dummy openings that overlap with the dummy electrode layer.

16. The electronic device according to claim 15, wherein, The display panel also includes dummy transistors disposed below the dummy electrode layer. The dummy electrode layer is electrically insulated from the dummy transistor.

17. The electronic device according to claim 15, wherein, The voltage line extends toward the dummy region, and a portion of the voltage line overlaps with the dummy electrode layer. The dummy electrode layer is electrically connected to the voltage line.

18. The electronic device according to claim 17, wherein, The voltage line has the same voltage level as the opposite electrode.

19. The electronic device according to claim 17, wherein, The driving circuit includes an initialization transistor electrically connected to the first pixel electrode and initializing the first pixel electrode. The voltage line is electrically connected to the initialization transistor.

20. The electronic device according to claim 15, wherein, The plurality of dummy openings in the dam layer include a first dummy opening, a second dummy opening, and a third dummy opening that overlap with different portions of the dummy electrode layer, respectively.

21. The electronic device according to claim 20, wherein, The display panel also includes: A second pixel electrode is disposed on the insulating layer in the display area, and is adjacent to but separate from the first pixel electrode; and A third pixel electrode is disposed on the insulating layer in the display area, and is adjacent to and separated from the first pixel electrode and the second pixel electrode. The embankment further defines a second opening and a third opening, wherein the second opening overlaps with the second pixel electrode, and the third opening overlaps with the third pixel electrode. The first opening and the second opening are defined in the same column, and the third opening is defined as being adjacent to the column of the first opening and the second opening. The first dummy opening and the second dummy opening are defined in the same column, and the third dummy opening is defined as being adjacent to the column of the first dummy opening and the second dummy opening.

22. The electronic device according to claim 21, wherein, The size of the first illusory opening is substantially the same as the size of the first opening. The dimensions of the second illusory opening and the second opening are substantially the same, and The size of the third dummy opening and the size of the third opening are substantially the same.

23. The electronic device according to claim 21, wherein, The size and shape of the first illusory opening are different from the size and shape of the first opening.

24. The electronic device according to claim 20, wherein, A wiring area is further defined in the display panel between the transmissive area and the dummy area, and the wiring area surrounds the transmissive area. The dummy electrode layer extends toward the wiring area, and The embankment layer further defines a fourth dummy opening, a fifth dummy opening, and a sixth dummy opening, which overlap with different portions of the dummy electrode layer arranged in the wiring area.

25. The electronic device according to claim 24, wherein, The dimensions of the first illusory opening, the second illusory opening, and the third illusory opening are different from each other. The size of the fourth dummy opening is substantially the same as the size of the first dummy opening. The dimensions of the fifth illusory opening and the second illusory opening are substantially the same as each other, and The size of the sixth dummy opening is substantially the same as the size of the third dummy opening.

26. The electronic device according to claim 24, wherein, In the wiring region, the dummy electrode layer does not overlap with the transistor.

27. The electronic device of claim 24, further comprising a signal line electrically connected to the drive circuit. in, The signal line travels along the edge of the transmission area in the wiring area, and The dummy electrode layer overlaps with the bypass portion of the signal line in the wiring area.

28. The electronic device according to claim 15, wherein, The display panel also includes: Encapsulation layer, on the opposing electrode; and Cover window, on the encapsulation layer, The covering window includes a light-blocking portion and a light-transmitting portion. The light-blocking portion overlaps with at least one of the plurality of virtual openings defined in the virtual area, and the light-transmitting portion overlaps with at least one of the remaining virtual openings in the plurality of virtual openings.

29. The electronic device according to claim 15, wherein, The components include sensors or cameras.

30. The electronic device according to claim 15, wherein, The embankment layer includes light-blocking material.

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