Liquid ejecting apparatus and head unit

Abstract

The invention provides a liquid ejecting apparatus and a head unit which can reduce the possibility that the voltage of a driving signal is higher than the power supply voltage supplied to a head when a plurality of driving circuits are started. The liquid ejecting apparatus includes: a head having a first ejecting portion and a second ejecting portion; the first driving circuit outputs a first driving signal; the second driving circuit outputs a second driving signal; and a start-up control circuit that controls start-up of the first drive circuit and the second drive circuit, the first drive circuit outputting a signal that stops output of a head power supply signal from a power supply circuit when the head power supply signal is equal to or less than a predetermined voltage, and the second drive circuit outputting a signal that stops output of the head power supply signal from the power supply circuit when the head power supply signal is equal to or less than a predetermined voltage. The second drive circuit outputs a signal for stopping the output of the drive circuit power supply signal from the power supply circuit when the drive circuit power supply signal is equal to or less than a predetermined voltage, and the start-up control circuit starts the start-up timing of the second drive circuit after starting the start-up timing of the first drive circuit.

Description

Technical Field

[0001] This invention relates to a liquid ejection device and a head unit. Background Technology

[0002] In liquid ejection devices such as inkjet printers that print images and documents by ejecting ink, devices using piezoelectric elements, such as piezoelectric elements, are known. These piezoelectric elements are arranged in a head corresponding to multiple nozzles, each of which is driven according to a drive signal. Thus, a predetermined amount of liquid is ejected from the nozzles formed in the head at a predetermined time, forming dots on the printing medium.

[0003] In such liquid ejection devices, a high voltage of 42V is supplied as the power supply voltage to control the supply of the drive signal to the piezoelectric element. In this power supply voltage transmission path, the liquid ejection device may malfunction in the event of abnormalities such as overvoltage or overcurrent. To address this, Patent Document 1 proposes a liquid ejection device in which multiple drive circuits monitor the power supply voltage supplied to the device, and fuses are installed along the power supply voltage transmission wiring path.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2020-116867

[0005] However, if the voltage of the drive signal is higher than the high voltage supplied to the head, excessive current will flow from the drive signal wiring to the head power supply wiring through the parasitic diodes present in the head, potentially causing the head to malfunction. This situation is particularly prone to occur when multiple drive circuits are started. Summary of the Invention

[0006] One aspect of the liquid ejection device according to the present invention is characterized by comprising:

[0007] The head has a first ejection part and a second ejection part. The first ejection part includes a first driving part driven by a first driving signal and ejects liquid into the medium according to the driving of the first driving part. The second ejection part includes a second driving part driven by a second driving signal and ejects liquid into the medium according to the driving of the second driving part.

[0008] The conveying unit conveys the medium;

[0009] The first driving circuit outputs the first driving signal;

[0010] The second driving circuit outputs the second driving signal; and

[0011] The start-up control circuit controls the start-up of the first drive circuit and the second drive circuit.

[0012] In the liquid ejection device,

[0013] Supply a head power signal to the head.

[0014] Power signals are supplied to the first driving circuit and the second driving circuit.

[0015] When the head power signal is below a specified voltage, the first driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit.

[0016] When the power supply signal of the drive circuit is below a specified voltage, the second drive circuit outputs a signal that stops the output of the power supply signal from the power supply circuit.

[0017] The startup control circuit starts the startup sequence of the second drive circuit after starting the startup sequence of the first drive circuit.

[0018] One aspect of the head unit according to the present invention is characterized by comprising:

[0019] The head has a first ejection part and a second ejection part. The first ejection part includes a first driving part driven by a first driving signal and ejects liquid into the medium according to the driving of the first driving part. The second ejection part includes a second driving part driven by a second driving signal and ejects liquid into the medium according to the driving of the second driving part.

[0020] The first driving circuit outputs the first driving signal;

[0021] The second driving circuit outputs the second driving signal; and

[0022] The start-up control circuit controls the start-up of the first drive circuit and the second drive circuit.

[0023] In the head unit,

[0024] Supply a head power signal to the head.

[0025] Power signals are supplied to the first driving circuit and the second driving circuit.

[0026] When the head power signal is below a specified voltage, the first driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit.

[0027] When the power supply signal of the drive circuit is below a specified voltage, the second drive circuit outputs a signal that stops the output of the power supply signal from the power supply circuit.

[0028] The startup control circuit starts the startup sequence of the second drive circuit after starting the startup sequence of the first drive circuit. Attached Figure Description

[0029] Figure 1 This is a perspective view showing the simplified structure of the liquid ejection device.

[0030] Figure 2 This is a block diagram showing the electrical configuration of the liquid ejection device.

[0031] Figure 3 This is a diagram illustrating an example of the drive signal COM.

[0032] Figure 4 This is a block diagram showing the electrical configuration of the drive signal selection circuit.

[0033] Figure 5 This is a circuit diagram showing the electrical configuration of the selection circuit.

[0034] Figure 6 This is a diagram showing the decoded content in the decoder.

[0035] Figure 7 This is a diagram used to illustrate the operation of the drive signal selection circuit.

[0036] Figure 8 This is a cross-sectional view showing a simplified configuration of the ejector section.

[0037] Figure 9 This is a block diagram showing the circuit configuration of the drive circuit board in the first embodiment.

[0038] Figure 10 This is a diagram showing an example of the configuration of an overcurrent protection circuit.

[0039] Figure 11 This is a block diagram showing the configuration of the drive circuit.

[0040] Figure 12 This is a diagram illustrating an example of the startup timing of a drive circuit.

[0041] Figure 13 This is a block diagram showing the circuit configuration of the drive circuit board in the second embodiment.

[0042] Figure 14 This is a block diagram showing the circuit configuration of the drive circuit board in the third embodiment.

[0043] Figure 15 This is a block diagram showing the circuit configuration of the drive circuit board in the fourth embodiment.

[0044] Explanation of reference numerals in the attached figures

[0045] 1: Liquid ejection device; 2: Moving body; 3: Moving mechanism; 4: Conveying mechanism; 10: Control unit; 20: Head unit; 21, 21a, 21b, 21c, 21d: Liquid ejection module; 22: Print head; 24: Carriage; 31: Carriage motor; 32: Carriage guide shaft; 33: Timing belt; 40: Imprint plate; 41: Conveyor motor; 42: Conveyor roller; 50: Drive circuit board; 51, 51a, 51b, 51c, 51d: Drive circuit; 52, 53, 54: Resistors; 60, 60a, 60b, 60c, 60d: Piezoelectric element; 70, 70a, 70b, 70c: Overcurrent protection circuit; 7 1a, 71b, 71c, 71d: Logic circuits; 72, 73, 74: Resistors; 75a, 75b, 75c: Power supply wiring; 76a, 76b, 76c: Capacitors; 77: Fuse; 80: Startup control circuit; 90: Power supply circuit; 91: Oscillator circuit; 100: Control circuit; 190: Cable; 200, 200a, 200b, 200c, 200d: Drive signal selection circuit; 210: Selection control circuit; 212: Shift register; 214: Latch circuit; 216: Decoder; 230: Selection circuit; 232: Inverter; 234: Transmission gate; 235, 236: Transistors; 4 00: Voltage generation circuit; 410: Oscillator circuit; 420: Clock selection circuit; 430: Anomaly detection circuit; 431: Oscillator anomaly detection unit; 432: Operation anomaly detection unit; 433: Power supply voltage anomaly detection unit; 440: Register control circuit; 441: Timing register; 442: Status register; 443: Register control unit; 450: Drive signal discharge circuit; 460: Reference voltage signal output circuit; 470: VHV control signal output circuit; 471: Transistor; 480: Status signal input / output circuit; 490: Error signal input / output circuit; 500: Integrated circuit; 501: Drive signal generation circuit. 502: Amplification control signal generation circuit; 510: DAC interface; 520: DAC section; 530: Modulation section; 540: Gate drive section; 550: Drive signal amplification circuit; 551, 552: Transistor; 553: Coil; 554: Capacitor; 555, 556: Resistor; 600, 600a, 600b, 600c, 600d: Ejector section; 601: Piezoelectric element; 611, 612: Electrode; 621: Vibrating plate; 631: Cavity; 632: Nozzle plate; 641: Liquid reservoir; 651: Nozzle; 661: Supply port; 700: Electronic fuse IC; 701, 702: Resistor. Detailed Implementation

[0046] The preferred embodiments of the present invention will now be described using the accompanying drawings. The drawings are provided for ease of explanation. It should be noted that the embodiments described below do not unduly limit the scope of the invention as defined in the claims. Furthermore, not all elements described below are essential components of the present invention.

[0047] 1. First Implementation Method

[0048] 1-1. Composition of the liquid ejection device

[0049] As an example of the liquid ejection device involved in this embodiment, the printing device is an inkjet printer. The inkjet printer ejects ink according to image data input from an external host, thereby forming dots on a printing medium such as paper, and printing images including text, graphics, etc., corresponding to the image data.

[0050] Figure 1 This is a perspective view showing a simplified configuration of the liquid ejection device 1. Figure 1 The diagram illustrates the direction X of the transport medium P, the direction Y intersecting direction X and in which the moving body 2 reciprocates, and the direction Z of the ink ejection. It should be noted that in this embodiment, directions X, Y, and Z are described as mutually orthogonal axes, but the arrangement is not limited to various configurations of the liquid ejection device 1 arranged orthogonally. Furthermore, in the following description, the direction Y in which the moving body 2 moves is sometimes referred to as the main scanning direction.

[0051] like Figure 1 As shown, the liquid ejection device 1 includes a movable body 2 and a moving mechanism 3 that moves the movable body 2 back and forth in the direction Y. The moving mechanism 3 includes a carriage motor 31 that serves as the drive source for the movable body 2, a carriage guide shaft 32 fixed at both ends, and a timing belt 33 that extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0052] The carriage 24 included in the movable body 2 is supported on the carriage guide shaft 32 in a reciprocating manner and fixed to a portion of the timing belt 33. Then, by driving the timing belt 33 via the carriage motor 31, the carriage 24 is guided by the carriage guide shaft 32 to reciprocate in the direction Y. Additionally, a head unit 20 with multiple nozzles is provided in the portion of the movable body 2 opposite to the medium P. Control signals are input to the head unit 20 via cable 190. Based on the input control signals, the head unit 20 ejects ink, for example a liquid, from the nozzles.

[0053] The liquid ejection device 1 includes a conveying mechanism 4 for conveying medium P on the printing plate 40 in the direction X. The conveying mechanism 4 includes a conveying motor 41 as a drive source and a conveying roller 42 that rotates by the conveying motor 41 to convey medium P in the direction X.

[0054] In the liquid ejection device 1 configured as described above, ink is ejected through the head unit 20 at the timing when the medium P is conveyed by the conveying mechanism 4, thereby forming an image on the surface of the medium P.

[0055] 1-2. Electrical Configuration of the Liquid Ejection Device

[0056] Figure 2 This is a block diagram showing the electrical configuration of the liquid ejection device 1. (As shown) Figure 2 As shown, the liquid ejection device 1 has a control unit 10 and a head unit 20. The control unit 10 and the head unit 20 are electrically connected by a cable 190 such as a flexible flat cable (FFC).

[0057] The control unit 10 includes a control circuit 100, a power supply circuit 90, and an oscillation circuit 91. Furthermore, the control circuit 100 generates multiple control signals for controlling various configurations based on image data input from the host computer and outputs them to the head unit 20.

[0058] Specifically, the control circuit 100 outputs clock signal SCK, printing data signals SIa, SIb, SIc, SId, latch signals LATa, LATb, LATc, LATd, change signals CHA, CHb, CHc, CHd, and drive data signals DATAa, DATAb, DATAc, DATAd to the head unit 20.

[0059] Additionally, although the diagram is omitted, the control circuit 100 controls the carriage motor 31 and the conveyor motor 41. Thus, it controls... Figure 1 The movement of the carriage 24 shown in the Y direction, Figure 1 The movement of medium P in the direction X shown.

[0060] The power supply circuit 90 generates, for example, DC 42V voltages VHV_H, VHV_A1, and VHV_A2. Then, the power supply circuit 90 supplies voltages VHV_H, VHV_A1, and VHV_A2 to the head unit 20.

[0061] The oscillator circuit 91 outputs a clock signal MCK. The clock signal MCK output from the oscillator circuit 91 is input to the head unit 20. It should be noted that the oscillator circuit 91 can be as follows: Figure 2 The configuration shown is independent of the control circuit 100, but it can also be configured inside the control circuit 100.

[0062] The head unit 20 includes a print head 22 and a drive circuit board 50. The drive circuit board 50 is connected to the print head 22.

[0063] The drive circuit board 50 includes drive circuits 51a, 51b, 51c, and 51d. The drive circuits 51a, 51b, 51c, and 51d drive the liquid ejection modules 21a, 21b, 21c, and 21d included in the printhead 22, respectively.

[0064] Drive circuit 51a generates drive signal COMA and reference voltage signal VBSa based on voltage VHV_A1, drive data signal DATAa, and clock signal MCK, and outputs them to liquid ejection module 21a. Drive circuit 51b generates drive signal COMb and reference voltage signal VBSb based on voltage VHV_A1, drive data signal DATAb, and clock signal MCK, and outputs them to liquid ejection module 21b. Drive circuit 51c generates drive signal COMc and reference voltage signal VBSc based on voltage VHV_A2, drive data signal DATAc, and clock signal MCK, and outputs them to liquid ejection module 21c. Drive circuit 51d generates drive signal COMd ​​and reference voltage signal VBSd based on voltage VHV_A2, drive data signal DATAd, and clock signal MCK, and outputs them to liquid ejection module 21d. Here, reference voltage signals VBSa, VBSb, VBSc, and VBSd are constant voltage signals, such as ground potential, DC 5V, DC 6V, etc.

[0065] It should be noted that, in Figure 2 The diagrams are omitted here to avoid making the process more complicated. However, the drive circuit board 50 also includes circuits other than drive circuits 51a, 51b, 51c, and 51d. Details about the circuit configuration and operation of the drive circuit board 50 will be described below.

[0066] The printhead 22 includes liquid ejection modules 21a, 21b, 21c, and 21d. Each liquid ejection module 21a has a drive signal selection circuit 200a and multiple ejection sections 600a. Each ejection section 600a also includes a piezoelectric element 60a. A clock signal SCK, a print data signal SIa, a latch signal LATa, a change signal CHa, a drive signal COMA, and a voltage VHV_H are input to the drive signal selection circuit 200a. The drive signal selection circuit 200a then generates a drive signal VOUTa by selecting or not selecting the drive signal COMA based on the clock signal SCK, the print data signal SIa, the latch signal LATa, the change signal CHa, and the voltage VHV_H.

[0067] A drive signal VOUTa is supplied to one end of the piezoelectric element 60a included in each of the plurality of ejection sections 600a. A reference voltage signal VBSa is supplied to the other end of the piezoelectric element 60a. Then, the piezoelectric element 60a is driven according to the potential difference between the drive signal VOUTa and the reference voltage signal VBSa, thereby ejecting ink from the ejection section 600a. That is, the liquid ejection module 21a has a piezoelectric element 60a driven by a drive signal COMA, and a drive signal selection circuit 200a that controls the supply of the drive signal COMA to the piezoelectric element 60a.

[0068] The liquid ejection module 21b includes a drive signal selection circuit 200b and multiple ejection sections 600b. Each ejection section 600b also includes a piezoelectric element 60b. A clock signal SCK, a print data signal SIb, a latch signal LATb, a change signal CHb, a drive signal COMb, and a voltage VHV_H are input to the drive signal selection circuit 200b. Then, the drive signal selection circuit 200b generates a drive signal VOUTb by selecting or not selecting the drive signal COMb based on the clock signal SCK, the print data signal SIb, the latch signal LATb, the change signal CHb, and the voltage VHV_H.

[0069] A drive signal VOUTb is supplied to one end of the piezoelectric element 60b included in each of the plurality of ejection sections 600b. A reference voltage signal VBSb is supplied to the other end of the piezoelectric element 60b. Then, the piezoelectric element 60b is driven according to the potential difference between the drive signal VOUTb and the reference voltage signal VBSb, thereby ejecting ink from the ejection section 600b. That is, the liquid ejection module 21b has a piezoelectric element 60b driven by a drive signal COMb, and a drive signal selection circuit 200b that controls the supply of the drive signal COMb to the piezoelectric element 60b.

[0070] The liquid ejection module 21c includes a drive signal selection circuit 200c and multiple ejection sections 600c. Each ejection section 600c includes a piezoelectric element 60c. A clock signal SCK, a print data signal SIc, a latch signal LATc, a change signal CHc, a drive signal COMc, and a voltage VHV_H are input to the drive signal selection circuit 200c. The drive signal selection circuit 200c then generates a drive signal VOUTc by selecting or not selecting the drive signal COMc based on the clock signal SCK, the print data signal SIc, the latch signal LATc, the change signal CHc, and the voltage VHV_H.

[0071] A drive signal VOUTc is supplied to one end of the piezoelectric element 60c included in each of the plurality of ejection sections 600c. A reference voltage signal VBSc is supplied to the other end of the piezoelectric element 60c. Then, the piezoelectric element 60c is driven according to the potential difference between the drive signal VOUTc and the reference voltage signal VBSc, thereby ejecting ink from the ejection section 600c. That is, the liquid ejection module 21c has a piezoelectric element 60c driven by a drive signal COMc, and a drive signal selection circuit 200c that controls the supply of the drive signal COMc to the piezoelectric element 60c.

[0072] The liquid ejection module 21d includes a drive signal selection circuit 200d and multiple ejection sections 600d. Each ejection section 600d includes a piezoelectric element 60d. A clock signal SCK, a print data signal SId, a latch signal LATd, a change signal CHd, a drive signal COMd, and a voltage VHV_H are input to the drive signal selection circuit 200d. The drive signal selection circuit 200d then generates a drive signal VOUTd by selecting or not selecting the drive signal COMd ​​based on the clock signal SCK, the print data signal SId, the latch signal LATd, the change signal CHd, and the voltage VHV_H.

[0073] A drive signal VOUTd is supplied to one end of the piezoelectric element 60d included in each of the plurality of ejection sections 600d. A reference voltage signal VBSd is supplied to the other end of the piezoelectric element 60d. Then, the piezoelectric element 60d is driven according to the potential difference between the drive signal VOUTd and the reference voltage signal VBSd, thereby ejecting ink from the ejection section 600d. That is, the liquid ejection module 21d has a piezoelectric element 60d driven by a drive signal COMd, and a drive signal selection circuit 200d that controls the supply of the drive signal COMd ​​to the piezoelectric element 60d.

[0074] It should be noted that in the following description, drive circuits 51a, 51b, 51c, and 51d have the same configuration and are sometimes referred to as drive circuit 51 unless otherwise specified. Furthermore, the various signals input to drive circuit 51 are referred to as voltage VHV, drive data signal DATA, and clock signal MCK. Additionally, the various signals output from drive circuit 51 are referred to as drive signal COM and reference voltage signal VBS.

[0075] Furthermore, liquid ejection modules 21a, 21b, 21c, and 21d have the same configuration and are sometimes referred to as liquid ejection module 21 unless otherwise specified. The liquid ejection module 21 will be described as having a drive signal selection circuit 200 and multiple ejection sections 600, each including a piezoelectric element 60. In this case, the various signals input to the liquid ejection module 21 will be referred to as clock signal SCK, printing data signal SI, latch signal LAT, change signal CH, drive signal COM, reference voltage signal VBS, and voltage VHV_H. The signal supplied to the piezoelectric element 60 will be referred to as drive signal VOUT.

[0076] 1-3. Composition and Operation of the Liquid Ejection Module

[0077] Next, the structure and operation of the drive signal selection circuit 200 will be explained. In explaining the structure and operation of the drive signal selection circuit 200, firstly, using... Figure 3 An example of the drive signal COM input to the drive signal selection circuit 200 will be explained. Next, using... Figures 4 to 7 The structure and operation of the drive signal selection circuit 200 are explained.

[0078] Figure 3 This is a diagram illustrating an example of the drive signal COM. Figure 3 The diagram shows the period T1 from the rise of the latch signal LAT to the rise of the change signal CH, the period T2 after period T1 until the next rise of the change signal CH, and the period T3 after period T2 until the rise of the latch signal LAT. Furthermore, the period T1, T2, and T3 constitutes the period Ta for forming a new point on the medium P. That is, as shown... Figure 3 As shown, the latch signal LAT is a signal that specifies the period for forming a new point on the medium P, and the change signal CH is a signal that specifies the switching timing of the waveform included in the drive signal COM.

[0079] like Figure 3As shown, the drive circuit 51 generates a trapezoidal waveform Adp during period T1. When the trapezoidal waveform Adp is supplied to the piezoelectric element 60, a predetermined amount, specifically a moderate amount, of ink is ejected from the corresponding ejection section 600. Additionally, the drive circuit 51 generates a trapezoidal waveform Bdp during period T2. When the trapezoidal waveform Bdp is supplied to the piezoelectric element 60, a small amount of ink, less than the predetermined amount, is ejected from the corresponding ejection section 600. Furthermore, the drive circuit 51 generates a trapezoidal waveform Cdp during period T3. When the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, the piezoelectric element 60 is driven to prevent ink from being ejected from the corresponding ejection section 600. Therefore, when the trapezoidal waveform Cdp is supplied to the piezoelectric element 60, no dots are formed on the medium P. This trapezoidal waveform Cdp is a waveform used to cause micro-vibration of the ink near the nozzle opening of the ejection section 600 to prevent an increase in ink viscosity. In the following description, the degree to which the piezoelectric element 60 is driven to prevent ink from being ejected from the ejection section 600 in order to prevent the ink viscosity from increasing is referred to as "micro-vibration".

[0080] Here, the start and end timing voltage values ​​of trapezoidal waveforms Adp, Bdp, and Cdp are all shared voltage Vc. That is, trapezoidal waveforms Adp, Bdp, and Cdp are waveforms that begin and end with voltage Vc. Therefore, the drive circuit 51 outputs a drive signal COM representing the continuous waveforms of trapezoidal waveforms Adp, Bdp, and Cdp within the period Ta. It should be noted that... Figure 3 The waveform of the drive signal COM shown is an example; the waveform of the drive signal COM can also be different. Furthermore, drive circuits 51a and 51b can also generate and output drive signals COM with different waveforms.

[0081] Figure 4 This is a block diagram showing the electrical configuration of the drive signal selection circuit 200. During periods T1, T2, and T3, the drive signal selection circuit 200 generates and outputs a drive signal VOUT supplied to the piezoelectric element 60 in period Ta by switching whether to select the trapezoidal waveforms Adp, Bdp, and Cdp included in the drive signal COM. Figure 4 As shown, the drive signal selection circuit 200 includes a selection control circuit 210 and multiple selection circuits 230.

[0082] The selection control circuit 210 is supplied with a clock signal SCK, a printing data signal SI, a latch signal LAT, a change signal CH, and a voltage VHV_H. In the selection control circuit 210, groups of shift registers 212 (S / R), latch circuits 214, and decoders 216 are respectively provided corresponding to the ejection section 600. That is, the head unit 20 has the same number of groups of shift registers 212, latch circuits 214, and decoders 216 as the total number n of the ejection sections 600.

[0083] Shift register 212 temporarily holds the 2 bits of printing data [SIH, SIL] included in the printing data signal SI for each corresponding ejector 600. Specifically, shift registers 212 of the corresponding stages to ejector 600 are cascaded together, and the serially supplied printing data signal SI is sequentially transmitted to the next stage according to the clock signal SCK. It should be noted that in... Figure 4 In order to distinguish shift register 212, it is sequentially labeled as level 1, level 2, ..., level n, starting from the upstream side of the supplying printed data signal SI.

[0084] Each of the n latching circuits 214 latches the printed data [SIH, SIL] held by the corresponding shift register 212 when the latching signal LAT rises. Each of the n decoders 216 decodes the 2-bit printed data [SIH, SIL] latched by the corresponding latching circuit 214 to generate a selection signal S, which is then supplied to the selection circuit 230.

[0085] The selection circuits 230 are respectively provided corresponding to the ejector sections 600. That is, the number of selection circuits 230 in one head unit 20 is the same as the total number n of ejector sections 600 included in the head unit 20. The selection circuits 230 control the supply of drive signal COM to the piezoelectric element 60 based on the selection signal S supplied from the decoder 216.

[0086] Figure 5 This is a circuit diagram showing the electrical configuration of a selection circuit 230 corresponding to an ejector section 600. (Example:) Figure 5 As shown, the selection circuit 230 includes an inverter 232 and a transmission gate 234. Furthermore, the transmission gate 234 includes a transistor 235, which is an NMOS transistor, and a transistor 236, which is a PMOS transistor.

[0087] A selection signal S is supplied from decoder 216 to the gate terminal of transistor 235. Additionally, the selection signal S is logically inverted by inverter 232 and also supplied to the gate terminal of transistor 236. The drain terminal of transistor 235 and the source terminal of transistor 236 are connected to terminal TG-In, which is one end of the transistor. A drive signal COM is input from terminal TG-In. Then, by controlling transistors 235 and 236 to be on or off according to the selection signal S, a drive signal VOUT is output from terminal TG-Out, which is the other end shared by the source terminal of transistor 235 and the drain terminal of transistor 236. Terminal TG-Out is electrically connected to electrode 611 of piezoelectric element 60, which will be described below. It should be noted that in the following description, the condition where transistors 235 and 236 are controlled to be in a conducting state is sometimes referred to as "on," and the condition where transistors 235 and 236 are controlled to be in a non-conducting state is sometimes referred to as "off."

[0088] Next, use Figure 6 The decoding content of decoder 216 is explained. Figure 6 This diagram illustrates the decoded content in decoder 216. Two bits of printed data [SIH, SIL], a latch signal LAT, and a change signal CH are input to decoder 216. Then, for example, if the printed data [SIH, SIL] is [1, 0] with a defined "midpoint," decoder 216 outputs a selection signal S at levels H, L, and L during periods T1, T2, and T3. Here, the logic level of the selection signal S is converted to a high-amplitude logic based on voltage VHV_H by a level converter (not shown).

[0089] Figure 7 This is a diagram used to illustrate the operation of the drive signal selection circuit 200. For example... Figure 7 As shown, the printing data signal SI is supplied serially to the drive signal selection circuit 200 in sync with the clock signal SCK, and is sequentially transferred in the shift register 212 corresponding to the ejector section 600. Then, if the supply of the clock signal SCK is stopped, the shift register 212 holds the printing data [SIH, SIL] corresponding to the ejector section 600. It should be noted that the printing data signal SI is supplied in the order corresponding to the final n-stage, ..., 2-stage, and 1-stage ejector sections 600 in the shift register 212.

[0090] Here, if the latch signal LAT rises, the latch circuit 214 latches the printed data [SIH, SIL] held in the corresponding shift register 212 together. Figure 7The LT1, LT2, ..., LTn shown are printed data [SIH, SIL] latched by latch circuits 214 corresponding to shift registers 212 of level 1, level 2, ..., level n.

[0091] Decoder 216 outputs the data according to the size of the dots specified by the latched print data [SIH, SIL] during periods T1, T2, and T3, respectively. Figure 6 The logic level selection signal S for the content shown.

[0092] When the printed data [SIH, SIL] is [1, 1], the selection circuit 230 selects the trapezoidal waveform Adp during period T1, selects the trapezoidal waveform Bdp during period T2, and does not select the trapezoidal waveform Cdp during period T3, according to the selection signal S. As a result, it generates... Figure 7 The large dots shown correspond to the drive signal VOUT. Therefore, a moderate amount of ink and a small amount of ink are ejected from the ejector 600. Thus, through this ink bonding, large dots are formed on the medium P. Furthermore, when the printing data [SIH, SIL] is [1, 0], the selection circuit 230 selects the trapezoidal waveform Adp during period T1, does not select the trapezoidal waveform Bdp during period T2, and does not select the trapezoidal waveform Cdp during period T3, according to the selection signal S. As a result, a large dot is generated... Figure 7 The drive signal VOUT corresponds to the midpoint shown. Therefore, a moderate amount of ink is ejected from the ejector 600. Thus, a midpoint is formed on the medium P. Furthermore, when the printing data [SIH, SIL] is [0, 1], the selection circuit 230, according to the selection signal S, does not select the trapezoidal waveform Adp during period T1, selects the trapezoidal waveform Bdp during period T2, and does not select the trapezoidal waveform Cdp during period T3. As a result, a midpoint is generated... Figure 7 The small dots shown correspond to the drive signal VOUT. Therefore, a small amount of ink is ejected from the ejector section 600. Thus, small dots are formed on the medium P. Furthermore, when the printing data [SIH, SIL] is [0, 0], the selection circuit 230, according to the selection signal S, does not select the trapezoidal waveform Adp during period T1, does not select the trapezoidal waveform Bdp during period T2, and selects the trapezoidal waveform Cdp during period T3. As a result, a dot is generated... Figure 7 The micro-vibration shown corresponds to the drive signal VOUT. Therefore, no ink is ejected from the ejection section 600, resulting in micro-vibration.

[0093] Here, use Figure 8 The structure and operation of the ejection section 600, including the piezoelectric element 60, will be explained. Figure 8 This is a cross-sectional view showing a simplified configuration of the ejector section 600 when the liquid ejection module 21 is cut off, including the ejector section 600.

[0094] like Figure 8 As shown, the liquid ejection module 21 includes an ejection section 600 and a reservoir 641. Ink is introduced into the reservoir 641 from the supply port 661. Furthermore, the reservoir 641 is configured for each color of ink.

[0095] The ejection section 600 includes a piezoelectric element 60, a vibrating plate 621, a cavity 631, and a nozzle 651. The vibrating plate 621 is disposed between the cavity 631 and the piezoelectric element 60. Furthermore, the vibrating plate 621 is displaced by being driven by the piezoelectric element 60 disposed on its upper surface. That is, the vibrating plate 621 functions as a diaphragm that expands / contracts the internal volume of the cavity 631 through displacement. The cavity 631 is filled with ink. Additionally, the cavity 631 functions as a pressure chamber whose internal volume changes due to the drive of the piezoelectric element 60. The nozzle 651 is an opening disposed on a nozzle plate 632 and communicating with the cavity 631.

[0096] The piezoelectric element 60 is a structure consisting of a piezoelectric body 601 sandwiched between a pair of electrodes 611 and 612. A drive signal VOUT is supplied to electrode 611, and a reference voltage signal VBS is supplied to electrode 612. The piezoelectric element 60 with this structure is driven according to the potential difference between electrodes 611 and 612. Furthermore, as the piezoelectric element 60 is driven, electrodes 611 and 612 and the central portion of the vibrating plate 621 are displaced in the vertical direction relative to the two end portions. Moreover, the internal volume of the cavity 631 changes with the displacement of the vibrating plate 621, causing the ink filled inside the cavity 631 to be ejected from the nozzle 651.

[0097] Here, as described above, the drive signal VOUTa is a signal that selects at least a portion of the waveform of the drive signal COMA. The drive signal COMA drives the piezoelectric element 60a, and the ejector unit 600a ejects ink into the medium P according to the drive of the piezoelectric element 60a. Similarly, the drive signal VOUTb is a signal that selects at least a portion of the waveform of the drive signal COMA. The drive signal COMA drives the piezoelectric element 60b, and the ejector unit 600b ejects ink into the medium P according to the drive of the piezoelectric element 60b. Similarly, the drive signal VOUTc is a signal that selects at least a portion of the waveform of the drive signal COMA. The drive signal COMA drives the piezoelectric element 60c, and the ejector unit 600c ejects ink into the medium P according to the drive of the piezoelectric element 60c. Similarly, the drive signal VOUTd is a signal that selects at least a portion of the waveform of the drive signal COMA. The drive signal COMA drives the piezoelectric element 60d, and the ejector unit 600d ejects ink into the medium P according to the drive of the piezoelectric element 60d.

[0098] 1-4. Circuit structure and operation of the drive circuit board

[0099] Next, the circuit configuration and operation of the drive circuit board 50 will be explained. Figure 9 This is a block diagram showing the circuit configuration of the drive circuit board 50. (Example) Figure 9 As shown, the drive circuit board 50 includes overcurrent protection circuits 70a, 70b, and 70c, logic circuits 71a, 71b, 71c, and 71d, resistors 72, 73, and 74, power supply wiring 75a, 75b, and 75c, capacitors 76a, 76b, and 76c, and a start-up control circuit 80.

[0100] Power cable 75a is a connection Figure 2 The wiring between the power supply circuit 90 and the print head 22 shows that voltage VHV_H is supplied to the print head 22 via power supply wiring 75a. Power supply wiring 75b connects the power supply circuit 90 to the drive circuits 51a and 51b, supplying voltage VHV_A1 to the drive circuits 51a and 51b via power supply wiring 75b. Power supply wiring 75c connects the power supply circuit 90 to the drive circuits 51c and 51d, supplying voltage VHV_A2 to the drive circuits 51c and 51d via power supply wiring 75c.

[0101] In this embodiment, the voltage VHV_A1 supplied to the drive circuits 51a and 51b is a different signal from the voltage VHV_H supplied to the print head 22, and is not supplied to the print head 22. Similarly, the voltage VHV_A2 supplied to the drive circuits 51c and 51d is a different signal from the voltage VHV_H supplied to the print head 22, and is not supplied to the print head 22.

[0102] Capacitor 76a is connected between power supply line 75a and ground. Capacitor 76b is connected between power supply line 75b and ground. Capacitor 76c is connected between power supply line 75c and ground. Capacitors 76a, 76b, and 76c are stabilizing capacitors. Since drive circuits 51a, 51b, 51c, and 51d need to charge and discharge multiple piezoelectric elements 60 simultaneously, the capacitance of capacitor 76b connected to power supply line 75b (which transmits the power supply voltage VHV_A1 for drive circuits 51a and 51b) and the capacitance of capacitor 76c connected to power supply line 75c (which transmits the power supply voltage VHV_A2 for drive circuits 51c and 51d) are larger than the capacitance of capacitor 76a connected to power supply line 75a (which transmits the power supply voltage VHV_H for the printhead 22).

[0103] An overcurrent protection circuit 70a is provided on the power supply wiring 75a, and has a conduction mode that enables the power supply circuit 90 and the print head 22 to be in a conducting state, and a non-conducting mode that enables the power supply circuit 90 and the print head 22 to be in a non-conducting state. Furthermore, the overcurrent protection circuit 70a outputs an operation mode signal MD_H indicating whether the operation mode is in a conducting or non-conducting state. In this embodiment, when the operation mode signal MD_H is at level H, the operation mode is in a conducting mode; when the operation mode signal MD_H is at level L, the operation mode is in a non-conducting mode.

[0104] In the on-mode, if the current flowing through the power supply wiring 75a exceeds a specified value, the overcurrent protection circuit 70a switches from the on-mode to the non-on-mode. If the current flowing through the power supply wiring 75a exceeds a specified value, the overcurrent protection circuit 70a switches from the on-mode to the non-on-mode, thus stopping the supply of voltage VHV_H from the power supply circuit 90 to the print head 22, and the operation mode signal MD_H changes from H level to L level.

[0105] Furthermore, in the on-mode, if the voltage VHV_H output from the power supply circuit 90 is below a specified value, the overcurrent protection circuit 70a can also switch from the on-mode to the non-on-mode. If the voltage VHV_H is below the specified value, the overcurrent protection circuit 70a switches from the on-mode to the non-on-mode, thus stopping the supply of voltage VHV_H from the power supply circuit 90 to the print head 22, and the operation mode signal MD_H changes from H level to L level.

[0106] An overcurrent protection circuit 70b is provided on the power supply wiring 75b, and has a conduction mode that enables the power supply circuit 90 and the drive circuits 51a and 51b to be in a conducting state, and a non-conducting mode that enables the power supply circuit 90 and the drive circuits 51a and 51b to be in a non-conducting state. Furthermore, the overcurrent protection circuit 70b outputs an operation mode signal MD_A1 indicating whether the operation mode is in a conducting mode or a non-conducting mode. In this embodiment, when the operation mode signal MD_A1 is at a high level (H), the operation mode is in a conducting mode; when the operation mode signal MD_A1 is at a low level (L), the operation mode is in a non-conducting mode.

[0107] In the on-mode, if the current flowing through the power supply wiring 75b exceeds a specified value, the overcurrent protection circuit 70b switches from the on-mode to the non-on-mode. If the current flowing through the power supply wiring 75b exceeds a specified value, the overcurrent protection circuit 70b switches from the on-mode to the non-on-mode, thus stopping the supply of voltage VHV_A1 from the power supply circuit 90 to the drive circuits 51a and 51b, and the operation mode signal MD_A1 changes from H level to L level.

[0108] Furthermore, in the on-mode, if the voltage VHV_A1 output from the power supply circuit 90 is below a specified value, the overcurrent protection circuit 70b can also switch from the on-mode to the non-on-mode. If the voltage VHV_A1 is below the specified value, the overcurrent protection circuit 70b switches from the on-mode to the non-on-mode, thus stopping the supply of voltage VHV_A1 from the power supply circuit 90 to the drive circuits 51a and 51b, and the operation mode signal MD_A1 changes from H level to L level.

[0109] Logic circuit 71a receives operation mode signals MD_H and MD_A1 as inputs and outputs a VHV abnormality signal VERa. Specifically, when both operation mode signals MD_H and MD_A1 are at a high level (H), logic circuit 71a outputs a low-level (L) VHV abnormality signal VERa, indicating that both voltages VHV_H and VHV_A1 are normal. When at least one of the operation mode signals MD_H and MD_A1 is at a low level (L), logic circuit 71a outputs a high-level (H) VHV abnormality signal VERa, indicating that at least one of the voltages VHV_H and VHV_A1 is abnormal. That is, logic circuit 71a is implemented using a two-input NAND circuit. The VHV abnormality signal VERa output from logic circuit 71a is input to driver circuit 51a as an error signal ERRAO.

[0110] When the error signal ERa is at level H, the drive circuit 51a stops outputting the drive waveform of the drive signal COMa. Furthermore, when the error signal ERa is at level L, the drive circuit 51a outputs an enable signal ENa to the overcurrent protection circuits 70a and 70b; when the error signal ERa is at level H, it stops outputting the enable signal ENa to the overcurrent protection circuits 70a and 70b. Therefore, when the overcurrent protection circuit 70a switches from the on mode to the off mode, the drive circuit 51a stops outputting the enable signal ENa to both the overcurrent protection circuit 70a and 70b. Similarly, when the overcurrent protection circuit 70b switches from the on mode to the off mode, the drive circuit 51a stops outputting the enable signal ENa to both the overcurrent protection circuit 70b and 70a.

[0111] In this embodiment, the enable signal ENa is a high-level control signal VHV_CNTa output from the drive circuit 51a. The drive circuit 51a stops outputting the enable signal ENa by outputting the low-level control signal VHV_CNTa. When the enable signal ENa is input, the overcurrent protection circuits 70a and 70b become either in a conducting mode or a non-conducting mode depending on the current flowing through the power supply wirings 75a and 75b, respectively. When no enable signal ENa is input, they become non-conducting. Therefore, by switching from the conducting mode to the non-conducting mode through the overcurrent protection circuit 70a, even when the output of the enable signal ENa from the drive circuit 51a stops, the overcurrent protection circuit 70b also switches from the conducting mode to the non-conducting mode. Similarly, by switching from the conducting mode to the non-conducting mode through the overcurrent protection circuit 70b, even when the output of the enable signal ENa from the drive circuit 51a stops, the overcurrent protection circuit 70a also switches from the conducting mode to the non-conducting mode. Furthermore, when the overcurrent protection circuits 70a and 70b are not enabled by the input enable signal ENA, they will not enter the conduction mode even if the current flowing through the power supply wirings 75a and 75b is less than the specified value.

[0112] Furthermore, the overcurrent protection circuit 70a can switch from a non-conducting mode to a conducting mode. Specifically, the overcurrent protection circuit 70a switches from a non-conducting mode to a conducting mode by receiving a specified signal. For example, the specified signal can be the enable signal ENa output from the drive circuit 51a. That is, the overcurrent protection circuit 70a can also switch from a non-conducting mode to a conducting mode by switching the control signal VHV_CNTa output from the drive circuit 51a from a low level to a high level. Alternatively, the drive circuit 51a can continue to output a low-level control signal VHV_CNTa after switching the control signal VHV_CNTa from a high level to a low level, as long as it is not reset, and switch the control signal VHV_CNTa from a low level to a high level when it is reset. In this case, the specified signal is a reset signal (not shown).

[0113] The logic circuit 71b receives the operating mode signal MD_A1 as input and outputs a VHV abnormality signal VERb. Specifically, when the operating mode signal MD_A1 is at a high level (H), the logic circuit 71b outputs a VHV abnormality signal VERb at a low level (L), indicating that the voltage VHV_A1 is normal; when the operating mode signal MD_A1 is at a low level (L), the logic circuit 71b outputs a VHV abnormality signal VERb at a high level (H). That is, the logic circuit 71b is implemented using a NOT circuit. The VHV abnormality signal VERb output from the logic circuit 71b is input to the driver circuit 51b as an error signal ERRb.

[0114] When the error signal ERRb is at level H, the drive circuit 51b stops outputting the drive waveform of the drive signal COMb. Additionally, when the error signal ERRb is at level L, the drive circuit 51b outputs an enable signal ENb to the overcurrent protection circuit 70b; when the error signal ERRb is at level H, it stops outputting the enable signal ENb to the overcurrent protection circuit 70b. Therefore, when the overcurrent protection circuit 70b switches from the on mode to the off mode, the drive circuit 51b stops outputting the enable signal ENb to the overcurrent protection circuit 70b.

[0115] In this embodiment, the enable signal ENb is a high-level control signal VHV_CNTb output from the drive circuit 51b. The drive circuit 51b stops outputting the enable signal ENb by outputting the low-level control signal VHV_CNTb. When the enable signal ENb is input, the overcurrent protection circuit 70b becomes either in a conducting mode or a non-conducting mode depending on the current flowing through the power supply wiring 75b. When the enable signal ENb is not input, it becomes a non-conducting mode. Furthermore, when the enable signal ENb is not input, the overcurrent protection circuit 70b will not become in a conducting mode even if the current flowing through the power supply wiring 75b is less than a specified value.

[0116] Furthermore, the overcurrent protection circuit 70b can switch from a non-conducting mode to a conducting mode. Specifically, the overcurrent protection circuit 70b switches from a non-conducting mode to a conducting mode by receiving a specified signal. For example, the specified signal can be the enable signals ENa and ENb output from the drive circuits 51a and 51b. That is, the overcurrent protection circuit 70b can also switch from a non-conducting mode to a conducting mode by both the control signals VHV_CNTa and VHV_CNTb output from the drive circuits 51a and 51b becoming H level. Alternatively, after switching the control signals VHV_CNTa and VHV_CNTb from H level to L level, the drive circuits 51a and 51b can continue to output L level control signals VHV_CNTa and VHV_CNTb as long as they are not reset, and switch the control signals VHV_CNTa and VHV_CNTb from L level to H level when reset. In this case, the specified signal is a reset signal (not shown).

[0117] An overcurrent protection circuit 70c is provided on the power supply wiring 75c, and has a conduction mode that enables the power supply circuit 90 and the drive circuits 51c and 51d to be in a conducting state, and a non-conducting mode that enables the power supply circuit 90 and the drive circuits 51c and 51d to be in a non-conducting state. Furthermore, the overcurrent protection circuit 70c outputs an operation mode signal MD_A2 indicating whether the operation mode is in a conducting or non-conducting state. In this embodiment, when the operation mode signal MD_A2 is at a high level (H), the operation mode is in a conducting mode; when the operation mode signal MD_A2 is at a low level (L), the operation mode is in a non-conducting mode.

[0118] In the on-mode, if the current flowing through the power supply wiring 75c exceeds a specified value, the overcurrent protection circuit 70c switches from the on-mode to the non-on-mode. If the current flowing through the power supply wiring 75c exceeds a specified value, the overcurrent protection circuit 70c switches from the on-mode to the non-on-mode, thus stopping the supply of voltage VHV_A2 from the power supply circuit 90 to the drive circuits 51c and 51d, and the operation mode signal MD_A2 changes from H level to L level.

[0119] Furthermore, in the on-mode, if the voltage VHV_A2 output from the power supply circuit 90 is below a specified value, the overcurrent protection circuit 70c can also switch from the on-mode to the non-on-mode. If the voltage VHV_A2 is below the specified value, the overcurrent protection circuit 70c switches from the on-mode to the non-on-mode, thus stopping the supply of voltage VHV_A2 from the power supply circuit 90 to the drive circuits 51c and 51d, and the operation mode signal MD_A2 changes from H level to L level.

[0120] The logic circuit 71c receives the operating mode signal MD_A2 as input and outputs a VHV abnormality signal VERc. Specifically, when the operating mode signal MD_A2 is at a high level (H), the logic circuit 71c outputs a VHV abnormality signal VERc at a low level (L), indicating that the voltage VHV_A2 is normal; when the operating mode signal MD_A2 is at a low level (L), the logic circuit 71c outputs a VHV abnormality signal VERc at a high level (H). That is, the logic circuit 71c is implemented using a NOT circuit. The VHV abnormality signal VERc output from the logic circuit 71c is input to the driver circuit 51c as an error signal ERRc.

[0121] When the error signal ERRc is at level H, the drive circuit 51c stops outputting the drive waveform of the drive signal COMc. Additionally, when the error signal ERRc is at level L, the drive circuit 51c outputs an enable signal ENc to the overcurrent protection circuit 70c; when the error signal ERRc is at level H, it stops outputting the enable signal ENc to the overcurrent protection circuit 70c. Therefore, when the overcurrent protection circuit 70c switches from the on mode to the off mode, the drive circuit 51c stops outputting the enable signal ENc to the overcurrent protection circuit 70c.

[0122] In this embodiment, the enable signal ENc is a high-level control signal VHV_CNTc output from the drive circuit 51c. The drive circuit 51c stops outputting the enable signal ENc by outputting the low-level control signal VHV_CNTc. When the enable signal ENc is input, the overcurrent protection circuit 70c enters either a conducting or non-conducting mode depending on the current flowing through the power supply wiring 75c. When the enable signal ENc is not input, it enters a non-conducting mode. Furthermore, when the enable signal ENc is not input, the overcurrent protection circuit 70c will not enter a conducting mode even if the current flowing through the power supply wiring 75c is less than a specified value.

[0123] The logic circuit 71d receives the operating mode signal MD_A2 as input and outputs a VHV abnormality signal VERd. Specifically, when the operating mode signal MD_A2 is at a high level (H), the logic circuit 71d outputs a VHV abnormality signal VERd at a low level (L), indicating that the voltage VHV_A2 is normal; when the operating mode signal MD_A2 is at a low level (L), the logic circuit 71d outputs a VHV abnormality signal VERd at a high level (H), indicating that the voltage VHV_A2 is abnormal. That is, the logic circuit 71d is implemented using a NOT circuit. The VHV abnormality signal VERd output from the logic circuit 71d is input to the driver circuit 51d as an error signal ERRd.

[0124] When the error signal ERRd is at level H, the drive circuit 51d stops outputting the drive waveform of the drive signal COMd. Additionally, when the error signal ERRd is at level L, the drive circuit 51d outputs an enable signal ENd to the overcurrent protection circuit 70c; when the error signal ERRd is at level H, it stops outputting the enable signal ENd to the overcurrent protection circuit 70c. Therefore, when the overcurrent protection circuit 70c switches from the on mode to the off mode, the drive circuit 51d stops outputting the enable signal ENd to the overcurrent protection circuit 70c.

[0125] In this embodiment, the enable signal ENd is a high-level control signal VHV_CNTd output from the drive circuit 51d. The drive circuit 51d stops outputting the enable signal ENd by outputting the low-level control signal VHV_CNTd. When the enable signal ENd is input, the overcurrent protection circuit 70c becomes either in a conducting mode or a non-conducting mode depending on the current flowing through the power supply wiring 75c. When the enable signal ENd is not input, it becomes a non-conducting mode. Furthermore, when the enable signal ENd is not input, the overcurrent protection circuit 70c will not become in a conducting mode even if the current flowing through the power supply wiring 75c is less than a specified value.

[0126] Furthermore, the overcurrent protection circuit 70c can switch from a non-conducting mode to a conducting mode. Specifically, the overcurrent protection circuit 70c switches from a non-conducting mode to a conducting mode by receiving a specified signal. For example, the specified signal can be the enable signals ENc and End output from the drive circuits 51c and 51d. That is, the overcurrent protection circuit 70c can also switch from a non-conducting mode to a conducting mode by both the control signal VHV_CNTc output from the drive circuit 51c and the control signal VHV_CNTd output from the drive circuit 51d becoming H level. Alternatively, after switching the control signals VHV_CNTc and VHV_CNTd from H level to L level, the drive circuits 51c and 51d can continue to output L level control signals VHV_CNTc and VHV_CNTd as long as they are not reset, and switch the control signals VHV_CNTc and VHV_CNTd from L level to H level when reset. In this case, the specified signal is a reset signal, which is not shown in the diagram.

[0127] It should be noted that, as Figure 9As shown, the terminals of the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd output by the drive circuits 51a, 51b, 51c, and 51d are electrically connected to each other. Furthermore, instead of outputting the low-level control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd, the drive circuits 51a, 51b, 51c, and 51d set each terminal to high impedance (Hi-Z), and use pull-down resistors 72 to make the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd low-level. Additionally, if at least one of the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd is high-level, a common enable signal is input to the overcurrent protection circuits 70a, 70b, and 70c. On the other hand, if the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd all become L level, then the input of the enable signal to the overcurrent protection circuits 70a, 70b, and 70c will stop.

[0128] Since overcurrent protection circuits 70a, 70b, and 70c have the same configuration, they are referred to as overcurrent protection circuit 70, and an example of its configuration will be described. It should be noted that in the description of the configuration example of overcurrent protection circuit 70, voltages VHV_H, VHV_A1, and VHV_A2 are referred to as voltages VHV, operating mode signals MD_H, MD_A1, and MD_A2 are referred to as operating mode signals MD, and control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd are referred to as control signals VHV_CNT.

[0129] Figure 10 This is a diagram showing an example of the configuration of an overcurrent protection circuit 70. (As shown...) Figure 10 As shown, the overcurrent protection circuit 70 includes an electronic fuse IC700 and resistors 701 and 702. The electronic fuse IC700 has Vin, Vout, UVLO, P-Good, and EN terminals. The Vin terminal is the voltage input terminal, and the Vout terminal is the voltage output terminal. The UVLO terminal is used to detect a decrease in the input voltage, and the P-Good terminal is the output terminal indicating the state of the input voltage. The EN terminal is the enable terminal.

[0130] The electronic fuse IC700 operates when the EN terminal is at a low (L) level and the control signal VHV_CNT is at a high (H) level. When the current flowing through the Vin terminal is above a specified value, the electronic fuse IC700 de-connects the Vin and Vout terminals and outputs an L-level signal from the P-Good terminal. Conversely, when the voltage input to the UVLO terminal is below a specified value, the electronic fuse IC700 de-connects the Vin and Vout terminals and outputs an L-level signal from the P-Good terminal. Finally, when the current flowing through the Vin terminal is less than a specified value and the voltage input to the UVLO terminal is higher than a specified value, the electronic fuse IC700 connects the Vin and Vout terminals and outputs an H-level signal from the P-Good terminal.

[0131] A control signal VHV_CNT is input to the EN terminal. The Vin terminal is connected to the power circuit 90 via a power supply line, and the Vout terminal is connected to the print head 22 or the drive circuit 51 via a power supply line. A voltage VHV is input to the Vin terminal. Resistors 701 and 702 are connected in series between the Vin terminal and ground, and the connection point of resistors 701 and 702 is connected to the UVLO terminal. Therefore, the voltage VHV input to the UVLO terminal is the voltage after being divided by resistors 701 and 702. The above function is achieved through the overcurrent protection circuit 70 configured in this way.

[0132] return Figure 9 The drive circuit 51a monitors the voltage VHV_H supplied to the printhead 22 via power supply wiring 75a. Then, the drive circuit 51a outputs an L-level error signal ERRa when the voltage VHV_H is higher than a specified voltage, and outputs an H-level error signal ERRa when the voltage VHV_H is lower than the specified voltage, and stops the output of the drive waveform of the drive signal COMi. Furthermore, the H-level error signal ERRa is a signal that stops the output of the voltage VHV_H from the power supply circuit 90; the power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRa is H-level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by the drive circuit 51a is lower than the specified voltage, therefore the drive circuit 51a outputs an H-level error signal ERRa. The drive circuit 51a can also output an H-level error signal ERRa when the voltage VHV_H is lower than the specified voltage, and output an L-level control signal VHV_CNTa.

[0133] Additionally, drive circuit 51b monitors the voltage VHV_A1 supplied to drive circuits 51a and 51b via power supply wiring 75b. Then, drive circuit 51b outputs an L-level error signal ERRb when VHV_A1 is higher than a specified voltage, and outputs an H-level error signal ERRb when VHV_A1 is lower than the specified voltage, and stops the output of the drive waveform of drive signal COMb. Furthermore, the H-level error signal ERRb is a signal that stops the output of voltage VHV_A1 from power supply circuit 90; power supply circuit 90 stops the output of voltage VHV_A1 when the error signal ERRb is H-level. For example, if overcurrent protection circuit 70b switches from on mode to off mode, the voltage VHV_A1 monitored by drive circuit 51b is lower than the specified voltage, therefore drive circuit 51b outputs the H-level error signal ERRb. The drive circuit 51b can also output an H-level error signal ERRb and an L-level control signal VHV_CNTb when the voltage VHV_A1 is below the specified voltage.

[0134] Additionally, drive circuit 51c monitors the voltage VHV_A2 supplied to drive circuits 51c and 51d via power supply wiring 75c. Then, drive circuit 51c outputs an L-level error signal ERRc when VHV_A2 is higher than a specified voltage, and outputs an H-level error signal ERRc when VHV_A2 is lower than the specified voltage, and stops outputting the drive waveform of drive signal COMc. Similarly, drive circuit 51d monitors the voltage VHV_A2 supplied to drive circuits 51c and 51d via power supply wiring 75c. Then, drive circuit 51d outputs an L-level error signal ERRd when VHV_A2 is higher than a specified voltage, and outputs an H-level error signal ERRd when VHV_A2 is lower than the specified voltage, and stops outputting the drive waveform of drive signal COMd. Furthermore, the H-level error signals ERRc and ERRd are signals that stop the output of voltage VHV_A2 from the power supply circuit 90. The power supply circuit 90 stops the output of voltage VHV_A2 when at least one of the error signals ERRc and ERRd is at the H level. For example, if the overcurrent protection circuit 70c switches from the on mode to the off mode, the voltage VHV_A2 monitored by the drive circuits 51c and 51d is below the specified voltage. Therefore, the drive circuits 51c and 51d output H-level error signals ERRc and ERRd, respectively. The drive circuits 51c and 51d can also output H-level error signals ERRc and ERRd, respectively, and L-level control signals VHV_CNTc and VHV_CNTd, respectively, when the voltage VHV_A2 is below the specified voltage.

[0135] It should be noted that, as Figure 9 As shown, the terminals of the drive circuits 51a, 51b, 51c, and 51d that output error signals ERRra, ERRb, ERRc, and ERRd are electrically connected to each other. Furthermore, instead of outputting L-level error signals ERRra, ERRb, ERRc, and ERRd, the drive circuits 51a, 51b, 51c, and 51d set each terminal to Hi-Z, and use pull-down resistors 73 to make the error signals ERRra, ERRb, ERRc, and ERRd L-level. Additionally, if all error signals ERRra, ERRb, ERRc, and ERRd are L-level, the error signal input to the power supply circuit 90 becomes L-level. On the other hand, if at least one of the error signals ERRra, ERRb, ERRc, and ERRd becomes H-level, the error signal input to the power supply circuit 90 becomes H-level, and the power supply circuit 90 stops outputting voltages VHV_H, VHV_A1, and VHV_A2.

[0136] Furthermore, the terminal of the output error signal ERRA of the drive circuit 51a is also an input terminal. If the voltage at this terminal switches from L level to H level, the drive circuit 51a stops outputting the drive waveform of the drive signal COMa and outputs an L level control signal VHV_CNTa. Similarly, the terminal of the output error signal ERRb of the drive circuit 51b is also an input terminal. If the voltage at this terminal switches from L level to H level, the drive circuit 51b stops outputting the drive waveform of the drive signal COMb and outputs an L level control signal VHV_CNTb. Likewise, the terminal of the output error signal ERRc of the drive circuit 51c is also an input terminal. If the voltage at this terminal switches from L level to H level, the drive circuit 51c stops outputting the drive waveform of the drive signal COMc and outputs an L level control signal VHV_CNTc. Similarly, the terminal of the drive circuit 51d that outputs the error signal ERRd is also an input terminal. If the voltage at this terminal switches from L level to H level, the drive circuit 51d stops outputting the drive waveform of the drive signal COMd ​​and outputs the L level control signal VHV_CNTd. Therefore, when all error signals ERRa, ERRb, ERRc, and ERRd are at L level, if at least one of the error signals ERRa, ERRb, ERRc, and ERRd switches from L level to H level, the output of the drive waveforms of drive signals COMa, COMb, COMc, and COMd ​​to the print head 22 stops, and the control signals VHV_CNTa, VHV_CNTb, VHV_CNTc, and VHV_CNTd all become L level. As a result, the overcurrent protection circuits 70a, 70b, and 70c all become non-conducting.

[0137] Additionally, drive circuit 51a outputs a status signal BUSYa indicating its operating state. Similarly, drive circuit 51b outputs a status signal BUSYb indicating its operating state. Similarly, drive circuit 51c outputs a status signal BUSYc indicating its operating state. Similarly, drive circuit 51d outputs a status signal BUSYd indicating its operating state. Drive circuits 51a, 51b, 51c, and 51d output H-level status signals BUSYa, BUSYb, BUSYc, and BUSYd respectively when in a specified state, and L-level status signals BUSYa, BUSYb, BUSYc, and BUSYd respectively when not in a specified state. The status signals BUSYa, BUSYb, BUSYc, and BUSYd are output to the control circuit 100 of control unit 10, and control circuit 100 determines the state of drive circuits 51a, 51b, 51c, and 51d based on the status signals BUSYa, BUSYb, BUSYc, and BUSYd.

[0138] It should be noted that, as Figure 9 As shown, the terminals of the drive circuits 51a, 51b, 51c, and 51d that output status signals BUSYa, BUSYb, BUSYc, and BUSYd are electrically connected to each other. Furthermore, instead of outputting L-level status signals BUSYa, BUSYb, BUSYc, and BUSYd, the drive circuits 51a, 51b, 51c, and 51d set each terminal to Hi-Z, and use pull-down resistors 74 to make the status signals BUSYa, BUSYb, BUSYc, and BUSYd L-level. Additionally, if all status signals BUSYa, BUSYb, BUSYc, and BUSYd are L-level, the status signal input to the control circuit 100 becomes L-level. On the other hand, if at least one of the status signals BUSYa, BUSYb, BUSYc, and BUSYd becomes H-level, the status signal input to the control circuit 100 becomes H-level, and the control circuit 100 determines the state of the drive circuits 51a, 51b, 51c, and 51d based on this status signal.

[0139] Here, assuming that while the drive signals COMa, COMb, COMc, and COMd ​​are being supplied to the print head 22, if the supply of voltage VHV_H to the print head 22 is stopped, or if the voltage VHV_H decreases, then inside the print head 22, through the parasitic diodes between the drive signal wirings that transmit the drive signals COMa, COMb, COMc, and COMd ​​and the power supply wiring that transmits the voltage VHV_H, excessive current will flow from the drive signal wirings to the power supply wiring, and the print head 22 may malfunction.

[0140] During the monitoring of voltage VHV_H by drive circuit 51a, if voltage VHV_H decreases, the output of drive waveforms of drive signals COMa, COMb, COMc, and COMd ​​to printhead 22 is immediately stopped by outputting an error signal ERa at level H. Therefore, the possibility of printhead 22 malfunctioning is low. Conversely, if voltage VHV_H decreases and at least one drive waveform of drive signals COMa, COMb, COMc, and COMd ​​is output to printhead 22 before drive circuit 51a starts monitoring voltage VHV_H, printhead 22 may malfunction. Therefore, in this embodiment, drive circuit board 50 includes a startup control circuit 80 that controls the startup of drive circuits 51a, 51b, 51c, and 51d. When head unit 20 is started, startup control circuit 80 causes drive circuit 51a, which monitors voltage VHV_H, to start first among drive circuits 51a, 51b, 51c, and 51d. That is, the start control circuit 80 starts the start timing of the drive circuits 51b, 51c, and 51d after the start timing of the start drive circuit 51a.

[0141] In this embodiment, the start-up control circuit 80 receives the drive data signals DATAa, DATAb, DATAc, and DATAd output by the input control circuit 100, and outputs data signals DATAXa, DATAXb, DATAXc, and DATAXd corresponding to each of the drive data signals DATAa, DATAb, DATAc, and DATAd. That is, the start-up control circuit 80 converts the drive data signals DATAa, DATAb, DATAc, and DATAd into data signals DATAXa, DATAXb, DATAXc, and DATAXd that conform to the input specifications of the drive circuits 51a, 51b, 51c, and 51d, respectively, and outputs them. The data signals DATAXa, DATAXb, DATAXc, and DATAXd are then input to the drive circuits 51a, 51b, 51c, and 51d, respectively. As described above, the driving data signals DATAa, DATAb, DATAc, and DATAd are used to generate the driving signals COMa, COMb, COMc, and COMd. However, the driving circuits 51a, 51b, 51c, and 51d actually generate the driving signals COMa, COMb, COMc, and COMd ​​based on the data signals DATAXa, DATAXb, DATAXc, and DATAXd, respectively.

[0142] Additionally, the drive data signals DATAa, DATAb, DATAc, and DATAd are also used as commands to indicate the start of drive circuits 51a, 51b, 51c, and 51d. For example, the control circuit 100 can also output a command to indicate the start of drive circuit 51a as drive data signal DATAa, and after a predetermined time, output commands to indicate the start of drive circuits 51b, 51c, and 51d as drive data signals DATAb, DATAc, and DATAd. In this case, if the control circuit 100 only converts the format of drive data signals DATAa, DATAb, DATAc, and DATAd and outputs data signals DATAXa, DATAXb, DATAXc, and DATAXd, then the start-up timing of drive circuit 51a begins before the start-up timing of drive circuits 51b, 51c, and 51d. Alternatively, if at least one of the commands indicating the start of drive circuit 51b, 51c, and 51d is input as drive data signals DATAb, DATAc, and DATAd before the command instructing drive circuit 51a to start is input as drive data signal DATAa, the control circuit 100 may also keep the outputs of data signals DATAxb, DATAxc, and DATAxd in standby until the command instructing drive circuit 51a to start is input as drive data signal DATAa and the data signal DATAxa is output. Thus, the start-up timing of drive circuit 51a begins before the start-up timing of drive circuits 51b, 51c, and 51d.

[0143] It should be noted that if the format of the driving data signals DATAa, DATAb, DATAc, and DATAd conforms to the input specifications of the driving circuits 51a, 51b, 51c, and 51d, the start control circuit 80 may output the data signals DATAXa, DATAXb, DATAXc, and DATAXd without format conversion. The driving circuit board 50 may also not include the start control circuit 80, and the control circuit 100 may function as the start control circuit 80.

[0144] 1-5. Composition of the drive circuit

[0145] Next, use Figure 11 The configuration of drive circuits 51a, 51b, 51c, and 51d will be explained. Figure 11 In this document, drive circuits 51a and 51b are not distinguished, and are described as drive circuit 51. Figure 11 This is a block diagram showing the configuration of the drive circuit 51. The drive circuit 51 includes an integrated circuit 500, a drive signal amplifier circuit 550, and resistors 555 and 556.

[0146] Integrated circuit 500 includes an amplification control signal generation circuit 502, a voltage generation circuit 400, an oscillation circuit 410, a clock selection circuit 420, an abnormality detection circuit 430, a register control circuit 440, a drive signal discharge circuit 450, a reference voltage signal output circuit 460, a VHV control signal output circuit 470, a status signal input / output circuit 480, and an error signal input / output circuit 490.

[0147] The voltage generation circuit 400 generates a voltage GVDD based on the voltage VHV. The voltage GVDD is, for example, a 7.5V DC voltage signal, and is input to various configurations of the integrated circuit 500, including the gate drive unit 540, which will be described below.

[0148] The amplification control signal generation circuit 502 generates amplification control signals Hgd and Lgd based on the data signal of the drive signal COM included in the drive data signal DATAX input from the DATA-In terminal. The amplification control signal generation circuit 502 includes a DAC interface (DAC_I / F: Digital to Analog Converter Interface) 510, a DAC section 520, a modulation section 530, and a gate drive section 540.

[0149] The DAC interface 510 receives a drive data signal DATAX supplied from the DATA-In terminal and a clock signal MCK supplied from the MCK-In terminal. The DAC interface 510 accumulates the drive data signal DATAX based on the clock signal MCK and generates, for example, 10-bit drive data dA, specifying the waveform of the drive signal COM. The drive data dA is then input to the DAC section 520. The DAC section 520 converts the input drive data dA into a base drive signal aA of an analog signal. This base drive signal aA is the target signal before amplification of the drive signal COM. The base drive signal aA is input to the modulation section 530. The modulation section 530 outputs a modulated signal Ms after pulse width modulation of the base drive signal aA. Voltages VHV and GVDD, and the modulation signal Ms are input to the gate drive section 540. The gate drive unit 540 amplifies the input modulation signal Ms based on voltage GVDD and generates an amplified control signal Hgd, whose level is converted to high amplitude logic based on voltage VHV, and an amplified control signal Lgd, which inverts the logic level of the input modulation signal Ms and amplifies it based on voltage GVDD. That is, the amplified control signal Hgd and the amplified control signal Lgd are mutually exclusive H-level signals. The amplified control signal Hgd is output from the integrated circuit 500 via terminal Hg-Out and input to the drive signal amplification circuit 550. Similarly, the amplified control signal Lgd is output from the integrated circuit 500 via terminal Lg-Out and input to the drive signal amplification circuit 550.

[0150] The drive signal amplifier circuit 550 operates based on amplified control signals Hgd and Lgd to output a drive signal COM. The drive signal amplifier circuit 550 includes transistors 551 and 552, a coil 553, and a capacitor 554. It should be noted that transistors 551 and 552 are, for example, N-channel FETs (Field Effect Transistors).

[0151] A voltage VHV is supplied to the drain terminal of transistor 551. An amplification control signal Hgd is supplied to the gate terminal of transistor 551 via terminal Hg-Out. The source terminal of transistor 551 is electrically connected to the drain terminal of transistor 552. Additionally, an amplification control signal Lgd is supplied to the gate terminal of transistor 552 via terminal Lg-Out. The source electrode of transistor 552 is grounded. Transistor 551, connected as described above, operates according to the amplification control signal Hgd, and transistor 552 operates according to the amplification control signal Lgd. That is, transistors 551 and 552 are exclusively turned on. Thus, an amplified modulation signal, based on voltage VHV, is generated at the connection point between the source terminal of transistor 551 and the drain terminal of transistor 552.

[0152] One end of coil 553 is connected to a common ground with the source terminal of transistor 551 and the drain terminal of transistor 552. The other end of coil 553 is connected to one end of capacitor 554. The other end of capacitor 554 is grounded. That is, coil 553 and capacitor 554 constitute a low-pass filter. Then, by supplying an amplified modulation signal to this low-pass filter, the amplified modulation signal is demodulated, and a drive signal COM is generated. Then, drive circuit 51 outputs the drive signal COM generated as described above.

[0153] In the following description, the configuration of the amplified control signal generation circuit 502 and the drive signal amplification circuit 550 included in the integrated circuit 500 is sometimes referred to as the drive signal generation circuit 501 that generates the drive signal COM based on the drive data signal DATAX.

[0154] The oscillation circuit 410 generates and outputs a clock signal LCK that determines the timing of the operation of the integrated circuit 500. The clock signal LCK is input to the clock selection circuit 420 and the fault detection circuit 430.

[0155] Clock signals MCK, LCK, and a clock selection signal CSW are input to the clock selection circuit 420. The clock selection circuit 420 switches between outputting clock signal MCK as clock signal RCK to the register control circuit 440, or outputting clock signal LCK as clock signal RCK, based on the logic level of the clock selection signal CSW. It should be noted that in this embodiment, the clock selection circuit 420 outputs clock signal MCK as clock signal RCK to the register control circuit 440 when the clock selection signal CSW is at a high level (H), and outputs clock signal LCK as clock signal RCK to the register control circuit 440 when the clock selection signal CSW is at a low level (L).

[0156] The abnormality detection circuit 430 includes an oscillation abnormality detection unit 431, an action abnormality detection unit 432, and a power supply voltage abnormality detection unit 433.

[0157] The clock signal LCK output by the oscillation circuit 410 is input to the oscillation anomaly detection unit 431. The oscillation anomaly detection unit 431 detects whether the input clock signal LCK is normal and outputs a clock selection signal CSW and an error signal NES based on the detection result and a logic level. For example, the oscillation anomaly detection unit 431 detects at least one of the frequency and voltage level of the clock signal LCK. Then, if at least one of the frequency and voltage level of the clock signal LCK is abnormal, the oscillation anomaly detection unit 431 outputs the H-level clock selection signal CSW to the clock selection circuit 420 and the H-level error signal NES to the register control circuit 440. Alternatively, if both the frequency and voltage level of the clock signal LCK are normal, the oscillation anomaly detection unit 431 outputs the L-level clock selection signal CSW to the clock selection circuit 420 and the L-level error signal NES to the register control circuit 440.

[0158] An operation status signal ASS, representing the operation state of various configurations of the drive circuit 51, is input to the operation anomaly detection unit 432. Based on the logic level of the input operation status signal ASS, the operation anomaly detection unit 432 detects whether the various configurations of the drive circuit 51 are operating normally. In this embodiment, if any of the various configurations of the drive circuit 51 malfunctions, a high-level operation status signal ASS is input to the operation anomaly detection unit 432. Then, when a high-level operation status signal ASS is input, the operation anomaly detection unit 432 outputs a high-level error signal NES to the register control circuit 440.

[0159] A voltage VHV is input to the power supply voltage anomaly detection unit 433. Then, the power supply voltage anomaly detection unit 433 detects the voltage value of VHV. Based on the voltage value of VHV, the power supply voltage anomaly detection unit 433 checks whether the voltage level of the voltage VHV supplied to the liquid ejection module 21 is normal. In this embodiment, if it is determined that the voltage level of VHV supplied to the liquid ejection module 21 is abnormal, the power supply voltage anomaly detection unit 433 outputs an H-level error signal FES to the register control circuit 440.

[0160] The register control circuit 440 includes a timing register 441, a status register 442, and a register control unit 443. The timing register 441 and status register 442 synchronously hold the operation information input as the drive data signal DATAX, in sync with the clock signal MCK. Then, the register control unit 443 synchronously generates and outputs control signals CNT1 to CNT6 based on the information held in the timing register 441 and status register 442, in sync with the clock signal RCK. This controls the operation of the drive circuit 51.

[0161] The control signal CNT1 is input to the drive signal discharge circuit 450. The drive signal discharge circuit 450 controls the output of the drive signal COM from the drive circuit 51. When the low-level control signal CNT1 is input to the drive signal discharge circuit 450, the drive signal discharge circuit 450 releases the charge accumulated in the terminal Com-Dis. On the other hand, when the high-level control signal CNT1 is input to the drive signal discharge circuit 450, the drive signal discharge circuit 450 does not release the charge accumulated in the terminal Com-Dis.

[0162] The control signal CNT2 is input to the reference voltage signal output circuit 460. The reference voltage signal output circuit 460 generates and outputs a reference voltage signal VBS to the piezoelectric element 60. The reference voltage signal VBS is a signal with a constant voltage value based on the voltage GVDD. When the H-level control signal CNT2 is input to the reference voltage signal output circuit 460, the reference voltage signal VBS with a constant voltage value is output from the VBS-Out terminal. On the other hand, when the L-level control signal CNT2 is input to the reference voltage signal output circuit 460, the reference voltage signal VBS with a ground potential is output. In other words, when the L-level control signal CNT2 is input to the reference voltage signal output circuit 460, the output of the reference voltage signal VBS stops.

[0163] The control signal CNT3 is input to the VHV control signal output circuit 470. The VHV control signal output circuit 470 outputs the control signal VHV_CNT. When the low-level control signal CNT3 is input to the VHV control signal output circuit 470, a voltage GVDD is supplied to the terminal VHV_CNT-Out. That is, the high-level control signal VHV_CNT is output. On the other hand, when the high-level control signal CNT3 is input to the VHV control signal output circuit 470, the terminal VHV_CNT-Out becomes Hi-Z.

[0164] The control signal CNT4 is input to the status signal input / output circuit 480. The status signal input / output circuit 480 outputs a status signal BUSY indicating the operating state of the drive circuit 51. Based on the control signal CNT4 output from the register control circuit 440, the status signal input / output circuit 480 outputs the status signal BUSY from the terminal BUSY-Out, and inputs the signal input to the terminal BUSY-Out to the register control circuit 440. When the L-level control signal CNT4 is input to the status signal input / output circuit 480, a voltage GVDD is supplied to the terminal BUSY-Out. That is, the H-level status signal BUSY is output. On the other hand, when the H-level control signal CNT4 is input to the status signal input / output circuit 480, the terminal BUSY-Out becomes Hi-Z.

[0165] The control signal CNT5 is input to the error signal input / output circuit 490. The error signal input / output circuit 490 outputs an error signal ERR indicating whether an abnormality has occurred in the drive circuit 51. Based on the control signal CNT5 output from the register control circuit 440, the error signal input / output circuit 490 outputs the error signal ERR from the terminal ERR-Out and inputs the signal to the terminal ERR-Out to the register control circuit 440. When a low-level control signal CNT5 is input to the error signal input / output circuit 490, a voltage GVDD is supplied to the terminal ERR-Out. That is, a high-level error signal ERR is output. On the other hand, when a high-level control signal CNT5 is input to the error signal input / output circuit 490, the terminal ERR-Out becomes Hi-Z.

[0166] The control signal CNT6 is input to the amplified control signal generation circuit 502. When the control signal CNT6 is input to the amplified control signal generation circuit 502, the waveform of the drive signal COM generated by the drive signal generation circuit 501 is defined by the control signal CNT6, independent of the drive data signal DATAX. Specifically, the drive signal generation circuit 501 generates a drive signal COM that is constant at a predetermined voltage value based on the control signal CNT6. Alternatively, the drive signal generation circuit 501 can also generate a drive signal COM that is constant at a ground potential based on the control signal CNT6.

[0167] In the drive circuit 51 configured as described above, operation information, input as a drive data signal DATAX synchronously with the clock signal MCK, is maintained in the timing register 441. This operation information includes information corresponding to a command instructing the drive circuit 51 to start. Then, the register control unit 443 executes timing control of the drive circuit 51 based on the operation information maintained in the timing register 441. Then, by executing various timing controls including the aforementioned start timing control, information indicating the operation mode accompanying the execution of the timing control is maintained in the status register 442. The register control circuit 440 controls the output of control signals CNT1 to CNT6 based on the information indicating the operation mode maintained in the status register 442. Thus, various signals output from the drive circuit 51 are controlled. For example, the register control circuit 440 may also control the output of control signals CNT1, CNT2, CNT3, and CNT5 based on the error signal FES and the signal input to the terminal ERR-Out.

[0168] 1-6. Startup timing of the drive circuit

[0169] Next, use Figure 12 The startup timing sequence of drive circuits 51a, 51b, 51c, and 51d is explained in detail. Figure 12 This is a diagram illustrating an example of the startup timing sequence of drive circuits 51a, 51b, 51c, and 51d. (See diagram for example.) Figure 12 As shown, among the drive circuits 51a, 51b, 51c, and 51d, drive circuit 51a executes the startup sequence first.

[0170] Before starting the startup sequence, the drive circuit 51a sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMA. First, at time t1, the drive circuit 51a receives a startup command from the startup control circuit 80 as a data signal DATAXa and begins the startup sequence (step S11). Next, the drive circuit 51a outputs a control signal VHV_CNTa at level H and uses it as the drive signal COMA to begin constant voltage output (step S12). Then, the drive circuit 51a waits for charging to complete until the voltage VHV_H reaches the desired voltage (step S13), and at time t2, it begins monitoring the voltage VHV_H (step S14). Next, the drive circuit 51a ends the constant voltage output as the drive signal COMA (step S15). Finally, the drive circuit 51a begins outputting the drive waveform of the drive signal COMA and ends the startup sequence (step S16).

[0171] Before starting the startup sequence, the drive circuit 51b sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMb. First, at time t3 after time t2, the drive circuit 51b receives a startup command from the startup control circuit 80 as a data signal DATAXb and begins the startup sequence (step S21). Next, the drive circuit 51b outputs a high-level control signal VHV_CNTb and begins constant-voltage output as the drive signal COMb (step S22). Then, the drive circuit 51b begins monitoring the voltage VHV_A1 (step S24). Next, the drive circuit 51b ends the constant-voltage output as the drive signal COMb (step S25). Finally, the drive circuit 51b begins outputting the drive waveform of the drive signal COMb and ends the startup sequence (step S26).

[0172] Before starting the startup sequence, the drive circuit 51c sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMc. First, at time t4 after time t3, the drive circuit 51c receives a startup command from the startup control circuit 80 as a data signal DATAXc and begins the startup sequence (step S31). Next, the drive circuit 51c outputs a high-level control signal VHV_CNTc and uses it as the drive signal COMc to begin constant-voltage output (step S32). Next, the drive circuit 51c begins monitoring the voltage VHV_A2 (step S34). Next, the drive circuit 51c uses the drive signal COMc to end the constant-voltage output (step S35). Finally, the drive circuit 51c begins outputting the drive waveform of the drive signal COMc and ends the startup sequence (step S36).

[0173] Before starting the startup sequence, the drive circuit 51d sets terminals ERR-Out and VHV_CNT-Out to Hi-Z and stops outputting the drive waveform of the drive signal COMd. First, at time t5 after time t4, the drive circuit 51d receives a startup command from the startup control circuit 80 as a data signal DATAXd and begins the startup sequence (step S41). Next, the drive circuit 51d outputs a high-level control signal VHV_CNTd as the drive signal COMd ​​to begin constant-voltage output (step S42). Next, the drive circuit 51d begins monitoring the voltage VHV_A2 (step S44). Next, the drive circuit 51d ends the constant-voltage output as the drive signal COMd ​​(step S45). Finally, the drive circuit 51d begins outputting the drive waveform of the drive signal COMd ​​and ends the startup sequence (step S46).

[0174] It should be noted that the start times t3, t4, and t5 of the drive circuits 51b, 51c, and 51d can be later than the start time t1 of the drive circuit 51a, but preferably after the start time t2 of the drive circuit 51a when it starts monitoring the voltage VHV_H.

[0175] It should be noted that the conveying mechanism 4 is an example of a "conveyor section". Furthermore, the printhead 22 is an example of a "head". Additionally, voltage VHV_H is an example of a "head power signal", and voltage VHV_A1 is an example of a "drive circuit power signal". Furthermore, drive circuit 51a is an example of a "first drive circuit", drive circuit 51b is an example of a "second drive circuit", and drive circuit 51c is an example of a "third drive circuit". Furthermore, drive signal COMA is an example of a "first drive signal", drive signal COMb is an example of a "second drive signal", and drive signal COMc is an example of a "third drive signal". Additionally, ejection section 600a is an example of a "first ejection section", ejection section 600b is an example of a "second ejection section", and ejection section 600c is an example of a "third ejection section". Furthermore, piezoelectric element 60a is an example of a "first driving unit", piezoelectric element 60b is an example of a "second driving unit", and piezoelectric element 60c is an example of a "third driving unit".

[0176] 1-7. Effects

[0177] As explained above, in the liquid ejection device 1 of the first embodiment, the drive circuit 51a that monitors the voltage VHV_H supplied to the print head 22 starts its startup timing before the drive circuit 51b that monitors the voltage VHV_A1 supplied to the drive circuits 51a and 51b, and the drive circuits 51c and 51d that monitor the voltage VHV_A2 supplied to the drive circuits 51c and 51d. Therefore, the drive circuit 51a starts monitoring the voltage VHV_H before the drive circuits 51b, 51c, and 51d start outputting drive signals COMb, COMc, and COMd ​​to the print head 22, respectively. Furthermore, the drive circuit 51a starts monitoring the voltage VHV_H before it starts outputting drive signal COMa to the print head 22. Then, when the drive circuit 51a detects a decrease in the voltage VHV_H, the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, the liquid ejection device 1 according to the first embodiment can reduce the possibility that the drive signals COMa, COMb, COMc, and COMd ​​are higher than the voltage VHV_H, not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, thus reducing the possibility of head failure.

[0178] However, when the supply of voltages VHV_H, VHV_A1, and VHV_A2 to the printhead 22 is stopped, the voltage VHV_H decreases faster than VHV_A1 and VHV_A2 because the capacitance values ​​of the stabilizing capacitors 76b and 76c are larger than that of capacitor 76a. Sometimes, the voltages of the drive signals COMa, COMb, COMc, and COMd ​​are higher than VHV_H. Furthermore, sometimes overshoot occurs in the drive signals COMa, COMb, COMc, and COMd ​​due to the inductance of the transmission path, causing their voltages to be higher than VHV_H. As a result, excessive current flows from the drive signal wirings transmitting drive signals COMa, COMb, COMc, and COMd ​​to the power supply wiring 75a transmitting voltage VHV_H through the parasitic diodes inside the printhead 22, making the possibility of printhead 22 malfunctioning non-zero.

[0179] Assuming that the current flowing through the power supply wiring 75a exceeds a specified value due to a printhead 22 malfunction, the overcurrent protection circuits 70a, 70b, and 70c switch from a conducting mode to a non-conducting mode, thus protecting various circuits and electronic components, such as the drive circuits 51a, 51b, 51c, and 51d, included in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that blow due to high current, and since they can switch from a non-conducting mode to a conducting mode, they can be reused. Therefore, according to the liquid ejection device 1 of the first embodiment, in the head unit 20, it is not necessary to replace the drive circuit board 50 in the event of a printhead 22 malfunction, thus reducing repair time and costs.

[0180] Furthermore, according to the liquid ejection device 1 of the first embodiment, when the overcurrent protection circuits 70a, 70b, and 70c switch from the on mode to the non-on mode, the input of the enable signal stops, thus maintaining the non-on mode. As long as a specified signal is not input, it will not switch from the non-on mode to the on mode, thereby reducing the possibility of accidentally returning to the on mode.

[0181] 2. Second Implementation Method

[0182] Hereinafter, with respect to the second embodiment, the same reference numerals will be used to mark the same constituent elements as in the first embodiment, and descriptions that are repeated in the first embodiment will be omitted or simplified. The description will mainly focus on the contents that are different from the first embodiment.

[0183] The circuit configuration and operation of the drive circuit board 50 of the liquid ejection device 1 in the second embodiment are different from those of the liquid ejection device 1 in the first embodiment. Figure 13 This is a block diagram showing the circuit configuration of the drive circuit board 50 in the second embodiment.

[0184] like Figure 13As shown, in the second embodiment, the drive circuit 51c monitors the voltage VHV_H instead of VHV_A2. Then, the drive circuit 51c outputs an L-level error signal ERRc when the voltage VHV_H is higher than a specified voltage, and outputs an H-level error signal ERRc when the voltage VHV_H is lower than the specified voltage, and stops outputting the drive waveform of the drive signal COMc. Furthermore, the H-level error signal ERRc is a signal that stops the output of the voltage VHV_H from the power supply circuit 90; the power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRc is H-level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by the drive circuit 51c is lower than the specified voltage, therefore the drive circuit 51c outputs an H-level error signal ERRc. The drive circuit 51c may also output an H-level error signal ERRc and an L-level control signal VHV_CNTc when the voltage VHV_H is lower than the specified voltage. Thus, drive circuit 51c operates in the same way as drive circuit 51a. That is, in the second embodiment, the two drive circuits 51a and 51c monitor the voltage VHV_H.

[0185] Then, when the head unit 20 starts, the start control circuit 80 causes at least one of the drive circuits 51a and 51c that monitors the voltage VHV_H in the drive circuits 51a, 51b, 51c, and 51d to start first. That is, the start control circuit 80 starts the start timing of drive circuits 51b and 51d after the start timing of at least one of the drive circuits 51a and 51c. For example, the start control circuit 80 may start the start timing of drive circuits 51b, 51c, and 51d after the start timing of drive circuit 51a, after the start timing of drive circuit 51c, or after the start timing of drive circuits 51b and 51d simultaneously. It should be noted that the preferred start-up timing of drive circuits 51b and 51d is after the start-up timing of at least one of drive circuits 51a and 51c.

[0186] The other circuit configurations of the drive circuit board 50 in the second embodiment are the same as those in the second embodiment. Figure 9 The drive circuit board 50 shown in the first embodiment is the same, so its description is omitted. Furthermore, the other configurations and functions of the liquid ejection device 1 in the second embodiment are the same as those in the first embodiment, so their description is omitted.

[0187] In the liquid ejection device 1 of the second embodiment described above, at least one of the drive circuits 51a and 51c that monitors the voltage VHV_H supplied to the print head 22 starts its startup timing before drive circuit 51b that monitors the voltage VHV_A1 supplied to drive circuits 51a and 51b, and drive circuit 51d that monitors the voltage VHV_A2 supplied to drive circuits 51c and 51d. Therefore, at least one of the drive circuits 51a and 51c starts monitoring the voltage VHV_H before drive circuits 51b and 51d start outputting drive signals COMb and COMd ​​to the print head 22, respectively. Furthermore, drive circuits 51a and 51c start monitoring the voltage VHV_H before they start outputting drive signals COMa and COMc to the print head 22. Then, if at least one of the drive circuits 51a and 51b detects a decrease in voltage VHV_H, the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, according to the liquid ejection device 1 of the second embodiment, not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, the possibility that the drive signals COMa, COMb, COMc, and COMd ​​are higher than voltage VHV_H can be reduced, thus reducing the possibility of print head malfunction.

[0188] Assuming that the current flowing through the power supply wiring 75a exceeds a specified value due to a printhead 22 malfunction, the overcurrent protection circuits 70a, 70b, and 70c switch from the conducting mode to the non-conducting mode, thus protecting various circuits and electronic components, such as the drive circuits 51a, 51b, 51c, and 51d, included in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that blow due to high current, and since they can switch from the non-conducting mode to the conducting mode, they can be reused. Therefore, according to the liquid ejection device 1 of the second embodiment, in the head unit 20, it is not necessary to replace the drive circuit board 50 in the event of a printhead 22 malfunction, thus reducing repair time and costs.

[0189] Furthermore, according to the liquid ejection device 1 of the second embodiment, when the overcurrent protection circuits 70a, 70b, and 70c switch from the on mode to the non-on mode, the input of the enable signal stops, thus maintaining the non-on mode. As long as a specified signal is not input, it will not switch from the non-on mode to the on mode, thereby reducing the possibility of accidentally returning to the on mode.

[0190] 3. Third Implementation Method

[0191] Hereinafter, regarding the third embodiment, the same reference numerals are used to mark the same constituent elements as in the first or second embodiment, and descriptions that are repeated in the first or second embodiment are omitted or simplified. The description mainly focuses on the contents that are different from the first and second embodiments.

[0192] The circuit configuration and operation of the drive circuit board 50 of the liquid ejection device 1 in the third embodiment are different from those of the liquid ejection device 1 in the first or second embodiment. Figure 14 This is a block diagram showing the circuit configuration of the drive circuit board 50 in the third embodiment.

[0193] like Figure 14 As shown, in the third embodiment, the drive circuit board 50 includes a fuse 77. The fuse 77 is disposed on the power supply wiring 75a that supplies voltage VHV_H to the print head 22. Specifically, one end of the fuse 77 is connected to the output terminal of the overcurrent protection circuit 70a, and the other end is connected to the print head 22. Therefore, voltage VHV_H is supplied to the print head 22 from the other end of the fuse 77.

[0194] The drive circuit 51a monitors the voltage VHV_H transmitted between the fuse 77 and the printhead 22 in the power supply wiring 75a. When the voltage VHV_H is below a specified voltage, it outputs an H-level error signal ERRa and stops the output of the drive waveform of the drive signal COMA. Furthermore, the H-level error signal ERRa is a signal that stops the output of the voltage VHV_H from the power supply circuit 90. The power supply circuit 90 stops the output of the voltage VHV_H when the error signal ERRa is at an H level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by the drive circuit 51a is below a specified voltage, therefore the drive circuit 51a outputs an H-level error signal ERRa. The drive circuit 51a can also output an H-level error signal ERRa and an L-level control signal VHV_CNTa when the voltage VHV_H is below a specified voltage.

[0195] Then, when the head unit 20 starts, the start control circuit 80 causes the drive circuit 51a, which monitors the voltage VHV_H among the drive circuits 51a, 51b, 51c, and 51d, to start first. That is, the start control circuit 80 starts the start sequence of drive circuits 51b, 51c, and 51d after drive circuit 51a starts. It should be noted that, preferably, the start time of drive circuits 51b, 51c, and 51d starts after the time when drive circuit 51a starts monitoring the voltage VHV_H.

[0196] The other circuit configurations of the drive circuit board 50 in the third embodiment are the same as those in the third embodiment. Figure 9The drive circuit board 50 shown in the first embodiment is the same, so its description is omitted. Furthermore, the other configurations and functions of the liquid ejection device 1 in the third embodiment are the same as those in the first embodiment, so their description is omitted.

[0197] It should be noted that, in the third embodiment, it is also related to... Figure 13 Similarly, in the second embodiment of the drive circuit board 50 shown, drive circuits 51a and 51c can also monitor the voltage VHV_H transmitted between the fuse 77 of the power supply wiring 75a and the printhead 22. In this case, when the head unit 20 is started, the start-up control circuit 80 causes at least one of the drive circuits 51a and 51c that monitors the voltage VHV_H to start first. That is, the start-up control circuit 80 starts the start-up sequence of drive circuits 51b and 51d after the start-up sequence of at least one of the drive circuits 51a and 51c. For example, the startup control circuit 80 can start the startup sequence of drive circuits 51b, 51c, and 51d after the startup sequence of drive circuit 51a, or after the startup sequence of drive circuit 51c, or simultaneously start the startup sequence of drive circuits 51b and 51d. It should be noted that, preferably, the startup sequence of drive circuits 51b and 51d begins after the moment when at least one of drive circuits 51a and 51c begins monitoring voltage VHV_H.

[0198] It should be noted that, as a component used to electrically disconnect the power supply circuit 90 from the print head 22, the drive circuit board 50 may also include other components such as ferrite beads to replace the fuse 77.

[0199] In the liquid ejection device 1 of the third embodiment described above, similarly to the liquid ejection device 1 of the first embodiment, the drive circuit 51a begins monitoring the voltage VHV_H before the drive circuits 51b, 51c, and 51d start outputting drive signals COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, according to the liquid ejection device 1 of the third embodiment, not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, the possibility that the drive signals COMa, COMb, COMc, and COMd ​​are higher than the voltage VHV_H can be reduced, thus reducing the possibility of print head malfunction.

[0200] Furthermore, according to the liquid ejection device 1 of the third embodiment, when an overcurrent flows through the power supply wiring 75a that supplies voltage VHV_H to the print head 22, the fuse 77 blows, thus further reducing the possibility of print head 22 malfunctioning.

[0201] Furthermore, according to the liquid ejection device 1 of the third embodiment, when the overcurrent protection circuits 70a, 70b, and 70c switch from the on mode to the non-on mode, the input of the enable signal stops, thus maintaining the non-on mode. As long as a specified signal is not input, it will not switch from the non-on mode to the on mode, thereby reducing the possibility of accidentally returning to the on mode.

[0202] 4. Fourth Implementation Method

[0203] Hereinafter, with respect to the fourth embodiment, the same reference numerals will be used to mark any of the same constituent elements as in the first to third embodiments, and descriptions that are repeated in the first to third embodiments will be omitted or simplified. The description will mainly focus on the contents that are different from the first to third embodiments.

[0204] The circuit configuration and operation of the drive circuit board 50 of the liquid ejection device 1 in the fourth embodiment are different from those of the liquid ejection device 1 in the first to third embodiments. Figure 15 This is a block diagram showing the circuit configuration of the drive circuit board 50 in the fourth embodiment.

[0205] like Figure 15 As shown, in the fourth embodiment, the voltage VHV_H supplied to the print head 22 and the voltage VHV_A1 supplied to the drive circuits 51a and 51b are shared voltages.

[0206] Drive circuits 51a and 51b monitor the voltage VHV_H. When VHV_H is higher than a specified voltage, drive circuits 51a and 51b output low-level error signals ERa and ERRb, respectively. When VHV_H is lower than the specified voltage, they output high-level error signals ERa and ERRb, respectively, and stop the output of the drive waveforms of drive signals COMa and COMb, respectively. Furthermore, the high-level error signals ERa and ERRb are signals that stop the output of the voltage VHV_H from the power supply circuit 90. The power supply circuit 90 stops the output of the voltage VHV_H when at least one of the error signals ERa and ERRb is at a high level. For example, if the overcurrent protection circuit 70a switches from the on mode to the off mode, the voltage VHV_H monitored by drive circuits 51a and 51b is lower than the specified voltage; therefore, drive circuits 51a and 51b output high-level error signals ERa and ERRb, respectively. The drive circuits 51a and 51b can also output H-level error signals ERRa and ERRb respectively when the voltage VHV_H is below the specified voltage, and output L-level control signals VHV_CNTa and VHV_CNTb respectively.

[0207] Then, when the head unit 20 starts, the start control circuit 80 causes at least one of the drive circuits 51a and 51b that monitors the voltage VHV_H in the drive circuits 51a, 51b, 51c, and 51d to start first. That is, the start control circuit 80 starts the start timing of drive circuits 51c and 51d after the start timing of at least one of the drive circuits 51a and 51b. For example, the start control circuit 80 may start the start timing of drive circuits 51b, 51c, and 51d after the start timing of drive circuit 51b, or it may start the start timing of drive circuits 51a, 51c, and 51d after the start timing of drive circuit 51b, or it may start the start timing of drive circuits 51c and 51d simultaneously. It should be noted that the preferred start-up timing of drive circuits 51c and 51d is after the start-up timing of at least one of drive circuits 51a and 51b.

[0208] The other circuit configurations of the drive circuit board 50 in the fourth embodiment are the same as those in the fourth embodiment. Figure 9 The drive circuit board 50 shown in the first embodiment is the same, so its description is omitted. Furthermore, the other configurations and functions of the liquid ejection device 1 in the fourth embodiment are the same as those in the first embodiment, so their description is omitted.

[0209] It should be noted that, in the fourth embodiment, it is also related to... Figure 14Similarly, the drive circuit board 50 of the third embodiment shown may also include a fuse 77 disposed on the power supply line 75a that supplies voltage VHV_H to the print head 22, and drive circuits 51a and 51b monitor the voltage VHV_H transmitted between the fuse 77 in the power supply line 75a and the print head 22.

[0210] In the liquid ejection device 1 of the fourth embodiment described above, at least one of the drive circuits 51a and 51b that monitors the voltage VHV_H (VHV_A1) supplied to the print head 22 and the drive circuits 51a and 51b begins its startup timing before monitoring the voltage VHV_A2 supplied to the drive circuits 51c and 51d. Therefore, at least one of the drive circuits 51a and 51b begins monitoring the voltage VHV_H (VHV_A1) before the drive circuits 51c and 51d begin outputting drive signals COMc and COMd ​​to the print head 22, respectively. Furthermore, the drive circuits 51a and 51b begin monitoring the voltage VHV_H (VHV_A1) before they begin outputting drive signals COMa and COMb to the print head 22. Then, if at least one of the drive circuits 51a and 51b detects a drop in voltage VHV_H (VHV_A1), the drive circuits 51a, 51b, 51c, and 51d immediately stop outputting drive signals COMa, COMb, COMc, and COMd ​​to the print head 22, respectively. Therefore, according to the liquid ejection device 1 of the fourth embodiment, not only when the drive circuits 51a, 51b, 51c, and 51d are operating stably, but also when the drive circuits 51a, 51b, 51c, and 51d are started, the possibility that drive signals COMa, COMb, COMc, and COMd ​​are higher than voltage VHV_H (VHV_A1) can be reduced, thus reducing the possibility of print head malfunction.

[0211] Assuming that the current flowing through the power supply wiring 75a exceeds a specified value due to a printhead 22 malfunction, the overcurrent protection circuits 70a, 70b, and 70c switch from the conducting mode to the non-conducting mode, thus protecting various circuits and electronic components, such as the drive circuits 51a, 51b, 51c, and 51d, included in the drive circuit board 50. Furthermore, the overcurrent protection circuits 70a, 70b, and 70c are not fuses that blow due to high current, and since they can switch from the non-conducting mode to the conducting mode, they can be reused. Therefore, according to the liquid ejection device 1 of the fourth embodiment, in the head unit 20, it is not necessary to replace the drive circuit board 50 in the event of a printhead 22 malfunction, thus reducing repair time and costs.

[0212] Furthermore, according to the liquid ejection device 1 of the fourth embodiment, when the overcurrent protection circuits 70a, 70b, and 70c switch from the on mode to the non-on mode, the input of the enable signal stops, thus maintaining the non-on mode. As long as a specified signal is not input, it will not switch from the non-on mode to the on mode, thereby reducing the possibility of accidentally returning to the on mode.

[0213] 5. Variations

[0214] This invention is not limited to this embodiment, and various modifications can be made within the scope of the spirit of this invention.

[0215] For example, in the above embodiments, the drive circuit substrate 50 includes four drive circuits 51, but the number of drive circuits 51 included in the drive circuit substrate 50 may also be two, three, or more than five. Similarly, the drive circuit substrate 50 includes three overcurrent protection circuits 70, but the number of overcurrent protection circuits 70 included in the drive circuit substrate 50 may also be two, four, or more than five.

[0216] In addition, in the above embodiments, the VHV abnormal signals VERa, VERb, VERc, and VERd output from logic circuits 71a, 71b, 71c, and 71d are respectively input to drive circuits 51a, 51b, 51c, and 51d as error signals ERRa, ERRb, ERRc, and ERRd. However, the VHV abnormal signal VERa output from logic circuit 71a can also be input to drive circuits 51a, 51b, 51c, and 51d in a common manner as error signals ERRa, ERRb, ERRc, and ERRd.

[0217] Furthermore, in the above embodiments, a so-called serial inkjet printer is described in which the liquid ejection device 1 is a liquid ejection module 21 that ejects ink and is mounted on a carriage 24, and the printing is performed by the carriage 24 moving back and forth on the medium P. However, it is also possible to describe a so-called line inkjet printer in which the liquid ejection module 21 is arranged in the width direction of the medium P and the printing is performed by transporting the medium P.

[0218] The embodiments have been described above, but the present invention is not limited to these embodiments and can be implemented in various ways without departing from its spirit. For example, the above embodiments can also be appropriately combined.

[0219] This invention includes configurations that are substantially the same as those described in the embodiments, such as configurations with the same function, method, and result, or configurations with the same purpose and effect. Additionally, this invention includes configurations that replace non-essential parts of the configurations described in the embodiments. Furthermore, this invention includes configurations that achieve the same effect as those described in the embodiments or that can achieve the same purpose. Additionally, this invention includes configurations that incorporate known technology into the configurations described in the embodiments.

[0220] The following content is derived from the above implementation method.

[0221] One aspect of the liquid ejection device is characterized by comprising:

[0222] The head has a first ejection part and a second ejection part. The first ejection part includes a first driving part driven by a first driving signal and ejects liquid into the medium according to the driving of the first driving part. The second ejection part includes a second driving part driven by a second driving signal and ejects liquid into the medium according to the driving of the second driving part.

[0223] The conveying unit conveys the medium;

[0224] The first driving circuit outputs the first driving signal;

[0225] The second driving circuit outputs the second driving signal; and

[0226] The start-up control circuit controls the start-up of the first drive circuit and the second drive circuit.

[0227] In the liquid ejection device,

[0228] Supply a head power signal to the head.

[0229] Power signals are supplied to the first driving circuit and the second driving circuit.

[0230] When the head power signal is below a specified voltage, the first driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit.

[0231] When the power supply signal of the drive circuit is below a specified voltage, the second drive circuit outputs a signal that stops the output of the power supply signal from the power supply circuit.

[0232] The startup control circuit starts the startup sequence of the second drive circuit after starting the startup sequence of the first drive circuit.

[0233] In this liquid ejection device, the first drive circuit, which monitors the voltage of the head power signal, starts its startup sequence before the second drive circuit, which monitors the voltage of the head power signal. Therefore, the first drive circuit begins monitoring the head power signal voltage before the second drive circuit begins outputting the second drive signal to the head. Consequently, this liquid ejection device reduces the likelihood that the voltage of the second drive signal will be higher than the voltage of the head power signal when the first and second drive circuits are started, thus reducing the possibility of head malfunction.

[0234] One aspect of the liquid ejection device may also include:

[0235] The third ejection section includes a third drive unit driven by a third drive signal, and ejects liquid into the medium according to the drive of the third drive unit; and

[0236] The third driving circuit outputs the third driving signal.

[0237] When the head power signal is below a specified voltage, the third driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit.

[0238] The startup control circuit starts the startup timing of the second drive circuit after starting the startup timing of at least one of the first drive circuit and the third drive circuit.

[0239] In this liquid ejection device, at least one of the first and third drive circuits that monitors the voltage of the head power signal starts its startup sequence before the second drive circuit that monitors the voltage of the drive circuit power signal. Therefore, before the second drive circuit starts outputting the second drive signal to the head, at least one of the first and third drive circuits begins monitoring the voltage of the drive circuit power signal. Consequently, according to this liquid ejection device, the possibility that the voltage of the second drive signal is higher than the voltage of the head power signal when the first, second, and third drive circuits are started can be reduced, thus reducing the possibility of head malfunction.

[0240] In one aspect of the liquid ejection device, it may also be that...

[0241] The power supply signal for the drive circuit is a different signal from the power supply signal for the head and is not supplied to the head.

[0242] One aspect of the liquid ejection device can also be,

[0243] The liquid ejection device includes a fuse, which is disposed on the power wiring that supplies power signals to the head.

[0244] When the power supply signal for the head transmitted through the portion of the power supply wiring between the fuse and the head is below the specified voltage, the first driving circuit outputs a signal that stops the output of the power supply signal for the head from the power supply circuit.

[0245] According to this liquid ejection device, when an overcurrent flows through the power wiring that supplies power to the head, the fuse blows, thus further reducing the possibility of head failure.

[0246] One aspect of the head unit is characterized by having:

[0247] The head has a first ejection part and a second ejection part. The first ejection part includes a first driving part driven by a first driving signal and ejects liquid into the medium according to the driving of the first driving part. The second ejection part includes a second driving part driven by a second driving signal and ejects liquid into the medium according to the driving of the second driving part.

[0248] The first driving circuit outputs the first driving signal;

[0249] The second driving circuit outputs the second driving signal; and

[0250] The start-up control circuit controls the start-up of the first drive circuit and the second drive circuit.

[0251] In the head unit,

[0252] Supply a head power signal to the head.

[0253] Power signals are supplied to the first driving circuit and the second driving circuit.

[0254] When the head power signal is below a specified voltage, the first driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit.

[0255] When the power supply signal of the drive circuit is below a specified voltage, the second drive circuit outputs a signal that stops the output of the power supply signal from the power supply circuit.

[0256] The startup control circuit starts the startup sequence of the second drive circuit after starting the startup sequence of the first drive circuit.

[0257] In this head unit, the first drive circuit that monitors the voltage of the head power signal starts its startup timing before the second drive circuit that monitors the voltage of the drive circuit power signal. Therefore, the first drive circuit starts monitoring the voltage of the head power signal before the second drive circuit starts outputting the second drive signal to the head. Consequently, according to this head unit, the possibility that the voltage of the second drive signal is higher than the voltage of the head power signal when the first and second drive circuits start can be reduced, thus reducing the possibility of head failure.

[0258] One aspect of the head unit may also be:

[0259] The third ejection section includes a third drive unit driven by a third drive signal, and ejects liquid into the medium according to the drive of the third drive unit; and

[0260] The third driving circuit outputs the third driving signal.

[0261] When the head power signal is below a specified voltage, the third driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit.

[0262] The startup control circuit starts the startup timing of the second drive circuit after starting the startup timing of at least one of the first drive circuit and the third drive circuit.

[0263] In this head unit, at least one of the first and third drive circuits that monitors the voltage of the head power signal starts its startup timing before the second drive circuit that monitors the voltage of the drive circuit power signal. Therefore, before the second drive circuit starts outputting the second drive signal to the head, at least one of the first and third drive circuits begins monitoring the voltage of the drive circuit power signal. Consequently, according to this head unit, the possibility that the voltage of the second drive signal is higher than the voltage of the head power signal when the first, second, and third drive circuits start can be reduced, thus reducing the possibility of head failure.

[0264] In one aspect of the head unit, it could also be that...

[0265] The power supply signal for the drive circuit is a different signal from the power supply signal for the head and is not supplied to the head.

[0266] One aspect of the head unit can also be,

[0267] The head unit includes a fuse, which is disposed on the power supply wiring that supplies power signals to the head.

[0268] When the power supply signal for the head transmitted through the portion of the power supply wiring between the fuse and the head is below the specified voltage, the first driving circuit outputs a signal that stops the output of the power supply signal for the head from the power supply circuit.

[0269] According to this head unit, the fuse blows when an overcurrent flows through the power wiring that supplies the head with the head power signal, thus further reducing the possibility of head failure.

Claims

1. A liquid ejection device, characterized in that, have: The head has a first ejection part and a second ejection part. The first ejection part includes a first driving part driven by a first driving signal and ejects liquid into the medium according to the driving of the first driving part. The second ejection part includes a second driving part driven by a second driving signal and ejects liquid into the medium according to the driving of the second driving part. The conveying unit conveys the medium; The first driving circuit outputs the first driving signal; The second driving circuit outputs the second driving signal; as well as The start-up control circuit controls the start-up of the first drive circuit and the second drive circuit. In the liquid ejection device, Supply a head power signal to the head. Power signals are supplied to the first driving circuit and the second driving circuit. When the head power signal is below a specified voltage, the first driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit. When the power supply signal of the drive circuit is below a specified voltage, the second drive circuit outputs a signal that stops the output of the power supply signal from the power supply circuit. The startup control circuit starts the startup sequence of the second drive circuit after starting the startup sequence of the first drive circuit.

2. The liquid ejection device according to claim 1, characterized in that, The liquid ejection device includes: The third ejection section includes a third drive section driven by a third drive signal, and ejects liquid into the medium according to the drive of the third drive section; as well as The third driving circuit outputs the third driving signal. When the head power signal is below a specified voltage, the third driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit. The startup control circuit starts the startup timing of the second drive circuit after starting the startup timing of at least one of the first drive circuit and the third drive circuit.

3. The liquid ejection device according to claim 1, characterized in that, The power supply signal for the drive circuit is a different signal from the power supply signal for the head and is not supplied to the head.

4. The liquid ejection device according to claim 1, characterized in that, The liquid ejection device includes a fuse, which is disposed on the power wiring that supplies power signals to the head. When the power supply signal for the head transmitted through the portion of the power supply wiring between the fuse and the head is below the specified voltage, the first driving circuit outputs a signal that stops the output of the power supply signal for the head from the power supply circuit.

5. A head unit, characterized in that, have: The head has a first ejection part and a second ejection part. The first ejection part includes a first driving part driven by a first driving signal and ejects liquid into the medium according to the driving of the first driving part. The second ejection part includes a second driving part driven by a second driving signal and ejects liquid into the medium according to the driving of the second driving part. The first driving circuit outputs the first driving signal; The second driving circuit outputs the second driving signal; as well as The start-up control circuit controls the start-up of the first drive circuit and the second drive circuit. In the head unit, Supply a head power signal to the head. Power signals are supplied to the first driving circuit and the second driving circuit. When the head power signal is below a specified voltage, the first driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit. When the power supply signal of the drive circuit is below a specified voltage, the second drive circuit outputs a signal that stops the output of the power supply signal from the power supply circuit. The startup control circuit starts the startup sequence of the second drive circuit after starting the startup sequence of the first drive circuit.

6. The head unit according to claim 5, characterized in that, have: The third ejection section includes a third drive section driven by a third drive signal, and ejects liquid into the medium according to the drive of the third drive section; as well as The third driving circuit outputs the third driving signal. When the head power signal is below a specified voltage, the third driving circuit outputs a signal that stops the output of the head power signal from the power supply circuit. The startup control circuit starts the startup timing of the second drive circuit after starting the startup timing of at least one of the first drive circuit and the third drive circuit.

7. The head unit according to claim 5, characterized in that, The power supply signal for the drive circuit is a different signal from the power supply signal for the head and is not supplied to the head.

8. The head unit according to claim 5, characterized in that, The head unit includes a fuse, which is disposed on the power supply wiring that supplies power signals to the head. When the power supply signal for the head transmitted through the portion of the power supply wiring between the fuse and the head is below the specified voltage, the first driving circuit outputs a signal that stops the output of the power supply signal for the head from the power supply circuit.

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