Instruction execution method and device, processor and related products thereof

Abstract

The embodiment of the invention relates to an instruction execution method and device, a processor and a related product, an MIMD framework is adopted in a GPU, a first SIMT stack and a second SIMT stack are configured for managing execution information of different branch basic blocks in the same thread bundle, and on the basis, the execution information of the different branch basic blocks in the same thread bundle can be managed through the first SIMT stack and the second SIMT stack. According to the method, the state of at least one of a first SIMT stack and a second SIMT stack is updated according to a basic block to be executed, and under the condition that the updated first SIMT stack and the updated second SIMT stack are both non-empty, instructions in all branch basic blocks are taken out respectively according to execution information of the first SIMT stack and execution information of the second SIMT stack and transmitted to an MIMD for concurrent execution. According to the method, when the execution channels of the MIMD concurrently execute the branch instructions, the resource utilization rate of the ALU can be improved, and therefore the running performance of a GPU program is improved.

Description

Technical Field

[0001] This application relates to the field of high-performance computing technology, and in particular to an instruction execution method, apparatus, processor and related products. Background Technology

[0002] With the rapid proliferation of graphics processing units (GPUs) in computationally intensive applications, they have become a major force in high-performance computing and artificial intelligence. The technology that utilizes GPUs for general-purpose computing is called general-purpose computing on graphics processing units (GPGPU).

[0003] In related technologies, GPUs often employ a Single Instruction Multiple Threads (SIMT) model for instruction processing. SIMT divides threads into different thread bundles for execution on Single Instruction Multiple Data (SIMD) hardware. When executing branch instructions within the same thread bundle, some SIMD resources are typically masked, causing some threads within the bundle to execute branch instructions at different times. This leads to reduced resource utilization of the GPU's arithmetic logic units, severely impacting the performance of GPU programs. Summary of the Invention

[0004] This application provides an instruction execution method, apparatus, processor, and related products, which can be used to improve the resource utilization of arithmetic logic units in a GPU, thereby improving the running performance of GPU programs.

[0005] In a first aspect, embodiments of this application provide an instruction execution method applied to a GPU, wherein the GPU employs MIMD and is configured with a first SIMT stack and a second SIMT stack; the first SIMT stack and the second SIMT stack are respectively used to manage execution information of different branch basic blocks within the same thread bundle; the method includes:

[0006] Update the stack state based on the basic block to be executed; the stack state includes at least one of the first SIMT stack and the second SIMT stack.

[0007] If both the updated first SIMT stack and the second SIMT stack are not empty, the instructions in each branch basic block are retrieved and transferred to MIMD for concurrent execution according to the execution information of the first SIMT stack and the second SIMT stack.

[0008] In one embodiment, the execution information includes instruction addresses, which are stored in the program counter (PC) register. Instructions from each branch basic block are fetched and transferred to the MIMD for concurrent execution according to the execution information of the first SIMT stack and the second SIMT stack, including:

[0009] Fetch the first instruction from the first branch basic block according to the instruction address in the PC register of the first SIMT stack, and fetch the second instruction from the second branch basic block according to the instruction address in the PC register of the second SIMT stack;

[0010] The first and second instructions are transmitted to the MIMD, so that the MIMD can execute the first and second instructions concurrently.

[0011] In one embodiment, the execution information further includes a thread mask; the process of MIMD concurrently executing the first instruction and the second instruction includes:

[0012] MIMD controls the execution channel corresponding to the thread indicated by the first thread mask to execute the first instruction according to the first thread mask of the first instruction; and controls the execution channel corresponding to the thread indicated by the second thread mask to execute the second instruction according to the second thread mask of the second instruction.

[0013] In one embodiment, a predicate mask is configured in the MIMD, which includes three state values: a first state value, a second state value, and a third state value.

[0014] The first state value indicates that the execution channel in MIMD is closed, the second state value indicates that the execution channel in MIMD is executing the instructions in the first branch basic block, and the third state value indicates that the execution channel in MIMD is executing the instructions in the second branch basic block.

[0015] In one embodiment, the GPU is further configured with a first instruction cache and a second instruction cache; fetching a first instruction from a first branch basic block according to the instruction address of the first SIMT stack, and fetching a second instruction from a second branch basic block according to the instruction address of the second SIMT stack, includes:

[0016] The first instruction is fetched from the first instruction cache according to the instruction address of the first SIMT stack, and the second instruction is fetched from the second instruction cache according to the instruction address of the second SIMT stack.

[0017] In one embodiment, the method further includes:

[0018] If the updated target SIMT stack is not empty, the instructions in the target basic block managed by the target SIMT stack are retrieved according to the execution information of the target SIMT stack and transferred to MIMD for execution; wherein, the target SIMT stack is either the first SIMT stack or the second SIMT stack.

[0019] In one embodiment, instructions from the target basic block managed by the target SIMT stack are retrieved according to the execution information of the target SIMT stack and transferred to the MIMD for execution, including:

[0020] According to the instruction address in the PC register of the target SIMT stack, the instruction in the target basic block is retrieved from the instruction cache corresponding to the target SIMT stack and passed to MIMD for execution.

[0021] In one embodiment, updating the stack state based on the basic block to be executed includes:

[0022] If the basic block to be executed is the top basic block, the execution information of the top basic block is pushed onto the first SIMT stack.

[0023] In one embodiment, the execution information includes instruction addresses and thread masks, and the execution information of the top basic block is pushed onto the first SIMT stack, including:

[0024] Obtain the instruction address and thread mask of the top basic block;

[0025] Push the instruction address of the top basic block into the PC register of the first SIMT stack, and push the thread mask of the top basic block into the predicate register of the first SIMT stack.

[0026] In one embodiment, the GPU is also configured with an RPC stack that updates the stack state based on the base block to be executed, including:

[0027] If the basic block to be executed is not the top basic block, the stack state is updated according to the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack.

[0028] In one embodiment, the stack state is updated based on the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack, including:

[0029] If the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack both point to the same jump, and the jump address is the same as the head node of the RPC stack, then the first SIMT stack, the second SIMT stack and the RPC stack are popped simultaneously, and the jump address is pushed back onto the first SIMT stack.

[0030] In one embodiment, the stack state is updated based on the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack, including:

[0031] If the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump, and the jump address is different from the head node of the RPC stack, the SIMT stack pointing to the unified jump is popped from the stack, and the jump address is pushed back onto the SIMT stack pointing to the unified jump.

[0032] In one embodiment, the method further includes:

[0033] If the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump, and the jump address is the same as the head node of the RPC stack, then instruction fetching of the SIMT stack pointing to the unified jump is suspended until both the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack point to the unified jump.

[0034] In one embodiment, the stack state is updated based on the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack, including:

[0035] If the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a divergent jump, obtain the two branch basic blocks of the divergence.

[0036] The execution information of the two branch basic blocks is pushed into the first SIMT stack and the second SIMT stack respectively, and the direct common post-dominant node of the two branch basic blocks is pushed into the RPC stack.

[0037] Secondly, embodiments of this application provide a processor that adopts a MIMD architecture and is configured with a first SIMT stack and a second SIMT stack; the first SIMT stack and the second SIMT stack are respectively used to manage the execution information of different branch basic blocks within the same thread bundle;

[0038] The scheduling unit in the processor is used to retrieve instructions from each branch basic block and transmit them to the MIMD for concurrent execution, according to the execution information of the first SIMT stack and the second SIMT stack, when both the first SIMT stack and the second SIMT stack are not empty.

[0039] In one embodiment, the processor is also configured with an RPC stack; the RPC stack is used for the direct common post-dominant node of different branch basic blocks.

[0040] In one embodiment, both the first SIMT stack and the second SIMT stack include a PC register and a predicate register. The PC register is used to store the instruction address of the basic block to be executed, and the predicate register is used to store the thread mask of the basic block to be executed.

[0041] In one embodiment, the processor is further configured with a first instruction cache and a second instruction cache, the first instruction cache being used to store instructions in a branch basic block managed by a first SIMT stack, and the second instruction cache being used to store instructions in a branch basic block managed by a second SIMT stack.

[0042] In one embodiment, the processor further includes an instruction fetch unit for fetching corresponding instructions from the storage subsystem into a first instruction cache and a second instruction cache.

[0043] In one embodiment, a predicate mask is configured in the MIMD, which includes three state values: a first state value, a second state value, and a third state value.

[0044] The first state value indicates that the execution channel in MIMD is closed, the second state value indicates that the execution channel in MIMD is executing the instructions in the first branch basic block, and the third state value indicates that the execution channel in MIMD is executing the instructions in the second branch basic block.

[0045] In one embodiment, the processor is a general-purpose graphics processor.

[0046] Thirdly, embodiments of this application provide an instruction execution apparatus, the apparatus comprising:

[0047] The stack state update module is used to update the stack state based on the basic block to be executed; the stack state includes at least one of the first SIMT stack and the second SIMT stack;

[0048] The instruction execution module is used to extract instructions from each branch basic block and transmit them to the MIMD for concurrent execution, based on the execution information of the first and second SIMT stacks, when both the updated first and second SIMT stacks are not empty.

[0049] Fourthly, embodiments of this application provide an instruction execution device, which includes a memory, a general-purpose graphics processor, and a computer program; the computer program is stored in the memory.

[0050] A general-purpose graphics processor is used to run computer programs to perform the steps of the instruction execution method of any of the embodiments of the first aspect described above.

[0051] Fifthly, embodiments of this application provide a computing system, which includes the instruction execution device, general interconnect interface, and other processing devices provided in the fourth aspect; the instruction execution device interacts with the other processing devices to jointly complete the computing operation specified by the user.

[0052] In a sixth aspect, embodiments of this application provide a readable storage medium storing a computer program, which, when executed by a processor, is used to implement the steps of the instruction execution method of any of the embodiments of the first aspect described above.

[0053] In a seventh aspect, embodiments of this application provide a computer program product, wherein when the computer program is executed by a processor, it implements the steps of the instruction execution method of any of the embodiments in the first aspect described above.

[0054] The instruction execution method, apparatus, processor, and related products provided in this application employ a MIMD architecture in the GPU, configured with a first SIMT stack and a second SIMT stack for managing execution information of different branch basic blocks within the same thread bundle. Based on this, by updating the state of at least one of the first and second SIMT stacks according to the basic block to be executed, and ensuring that both the updated first and second SIMT stacks are not empty, instructions from each branch basic block are retrieved according to the execution information of the first and second SIMT stacks and transmitted to the MIMD for concurrent execution. In this method, because different SIMT stacks independently manage the execution information of each branch instruction, and combined with the fact that different processing modules in the MIMD architecture can asynchronously execute different instructions, the scheduling unit can send different branch instructions from the same thread bundle to the MIMD for concurrent execution, achieving asynchronous execution of branch instructions within the same thread bundle and achieving the effect of parallel processing of branch instructions. Since each execution channel in the MIMD has its own ALU, the concurrent execution of branch instructions by different execution channels in the MIMD naturally improves the resource utilization of the ALU, thereby enhancing the running performance of the GPU program. Attached Figure Description

[0055] Figure 1This is an application environment diagram of an instruction execution method provided in one embodiment;

[0056] Figure 2 This is a schematic diagram of the internal architecture of a GPU provided in one embodiment;

[0057] Figure 3 A schematic diagram of the internal architecture of a GPU is provided in another embodiment;

[0058] Figure 4 A schematic diagram of the internal architecture of a GPU is provided in another embodiment;

[0059] Figure 5 A schematic diagram of the internal architecture of a GPU is provided in another embodiment;

[0060] Figure 6 This is a flowchart illustrating an instruction execution method provided in one embodiment;

[0061] Figure 7 This is a schematic diagram of a basic block control flow provided in one embodiment;

[0062] Figure 8 This is a flowchart illustrating an instruction execution method provided in another embodiment;

[0063] Figure 9 This is a flowchart illustrating an instruction execution method provided in another embodiment;

[0064] Figure 10 This is a schematic diagram of a basic block control flow provided in another embodiment;

[0065] Figure 11 This is a schematic block diagram of an instruction execution device provided in one embodiment;

[0066] Figure 12 This is a schematic diagram of the internal structure of a computing system provided in one embodiment. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.

[0068] First, before introducing the technical solutions of the embodiments of this application in detail, we will first introduce the technical background or technical evolution on which the embodiments of this application are based.

[0069] Typically, when a graphics processing unit (GPU) uses a Single Instruction Multiple Threads (SIMT) model for instruction processing, multiple threads can execute independently within the same thread bundle. Essentially, each thread within a SIMT thread bundle has its own execution unit; each unit executes different data but the commands are the same. Furthermore, threads within a SIMT thread bundle do not have their own independent instruction cache or program counter (PC) register; the same command is broadcast simultaneously to all threads from a shared instruction cache.

[0070] In GPU programming, branching statements are commonly used to implement different computational logic and control flows. They are a type of program control structure that determines the program's execution path based on the truth value of a condition. Common branching statements in GPUs include if statements, switch statements, and ternary operators, among others.

[0071] When a GPU program encounters a branch instruction during execution, a conditional jump in control flow occurs, forming a diverging branch instruction. Typically, GPU branch instructions diverge into two-branch instructions. The GPU needs to execute different control flows sequentially to achieve the execution of these diverging branch instructions. In practice, a portion of the threads within the same thread bundle are active to execute one of the branch instructions. At this time, the other portion of the threads within the same thread bundle is masked using predicate masks and must wait for the first portion of threads to finish executing. Therefore, not all threads are active when each branch instruction within the same thread bundle is being executed; even if some threads are not working on a particular branch instruction, they must still wait for all branch instructions to complete.

[0072] Correspondingly, in related technologies, to simplify the control of SIMT threads in GPUs, the actual hardware implementation often uses a Single Instruction Multiple Data (SIMD) execution unit. The width of the SIMD unit is the number of threads that can be processed within one cycle. Therefore, when encountering branch instructions, predicate masks are used to dynamically shield some resources of the SIMD, allowing the SIMD to execute different branch instructions. The implementation of SIMD relies on the Arithmetic Logic Unit (ALU), as the ALU is the hardware unit responsible for performing specific operations, including arithmetic and logical operations. Data in the SIMD registers can be processed in the ALU, performing operations such as addition, subtraction, and multiplication, or logical operations such as AND, OR, and NOT. Therefore, in related technologies, shielding some SIMD resources through predicate masks to enable some threads to be active within a thread bundle during branch instruction execution in the GPU leads to low ALU resource utilization, thus affecting the GPU's computational performance.

[0073] Furthermore, GPUs are designed for high-performance computing, and their configurations often include more computing units, with fewer features like branch prediction and instruction prefetching. In such cases, to fill the program's pipeline and compensate for the ALU's wasted resources, it's necessary to switch threads from other thread bundles to fill the gaps, allowing the ALU to process other threads while waiting for them. However, this back-and-forth thread switching consumes time and resources, and also introduces latency for individual threads. Therefore, this approach also leads to poor single-threaded performance in GPUs.

[0074] In summary, given the significant impact of branch instructions on GPU program execution performance, there is still a lack of effective technical solutions to mitigate this performance degradation. Therefore, this application provides an instruction execution method, apparatus, processor, and related products that enable concurrent execution of two branch instructions within the same thread bundle, greatly improving the resource utilization of the GPU's ALU and thus enhancing GPU program performance. Of course, the technical solution provided in this application is not limited to solving the above-mentioned problems and also offers other technical effects, which can be found in the following embodiments.

[0075] Before describing the embodiments of this application, the application scenarios involved in the embodiments of this application will be described first.

[0076] The instruction execution method provided in this application can be implemented inside the processor in practical applications. Therefore, the instruction execution method provided in this application can be applied to, for example... Figure 1 In the application environment shown, the application environment may include an instruction execution device, which can be a computer device with computing capabilities, such as a personal computer, laptop, smartphone, tablet, server, and portable wearable device, etc. The instruction execution device includes a processor and a storage subsystem, which are connected in communication, allowing the processor to retrieve the program file corresponding to the instruction from the storage subsystem when executing an instruction.

[0077] Optionally, the processor may include, but is not limited to, a GPU, CPU, neural network processor, and other devices with processing capabilities.

[0078] Furthermore, to clearly and intuitively explain the instruction execution method of the technical solution of this application, the following will be combined with... Figure 1 The internal architecture of the processor involved in the technical solution of this application will be introduced first.

[0079] like Figure 2 As shown, in one embodiment, the processor in the technical solution of this application adopts a MIMD architecture and is configured with a first SIMT stack and a second SIMT stack; the processor includes a scheduling unit; the scheduling unit is used to, when both the first SIMT stack and the second SIMT stack are not empty, retrieve the instructions in each branch basic block and transmit them to the MIMD for concurrent execution according to the execution information of the first SIMT stack and the second SIMT stack.

[0080] Taking a GPU as an example, the GPU architecture in this embodiment adopts a Multiple Instruction Multiple Data (MIMD) architecture. An MIMD architecture typically consists of multiple independent processing modules, each with its own control unit, ALU, and local memory. These modules can asynchronously execute different instruction streams and data streams, thus achieving a high degree of parallel processing capability. Therefore, the GPU in this technical solution, implemented using an MIMD architecture, can concurrently execute two-branch instructions within the same thread bundle, achieving asynchronous execution of branch instructions within the same thread bundle and thus parallel processing of branch instructions.

[0081] For example, suppose there are 8 execution lanes in MIMD, and each lane has its own ALU, which corresponds to one thread in the execution thread bundle. In the same cycle, the 8 lanes can execute two different instructions concurrently. For example, lanes 1, 3, 5, and 7 execute the add instruction, while lanes 2, 4, 6, and 8 execute the mul instruction.

[0082] Given the characteristics of the MIMD architecture, this embodiment of the application also configures two SIMT stacks in the GPU. Different SIMT stacks manage the execution information of different branch basic blocks within the same thread bundle. This allows the ALUs of different lanes in the MIMD to concurrently execute the instructions in the corresponding branch basic blocks based on the execution information of the branch basic blocks indicated in the two SIMT stacks when facing branch instructions.

[0083] In this context, a basic block refers to a sequential sequence of statements in a program. Each basic block has only one entry statement and one exit statement. The operations within the block are executed sequentially without any branching. Since the technical solution of this application aims to improve the processing efficiency of branch instructions, the basic block is used as the smallest instruction unit. That is, each branch basic block in this application refers to the smallest sequential sequence of statements in the path containing a branch instruction.

[0084] For example, execution information may include the instruction address, address length, and thread mask of the instructions in the basic block.

[0085] Optionally, the instruction address can be the starting address in the basic block, and the address length represents the length between the starting address and the end instruction address in the basic block.

[0086] Here, `mask` indicates the thread that executes the basic block within the thread bundle. The mask is in binary form, where 1 indicates the corresponding thread is active, and 0 indicates the thread is inactive. The length of the mask is equal to the size of the thread bundle, and the number of threads executing in parallel within the bundle is the size of the thread bundle. For example, the size of the thread bundle can be 16, 32, or 64 parallel threads. For simplicity, let's assume the thread bundle size is 4 parallel threads. If the mask of a basic block S is 1100, it means that the first and second threads in that thread bundle execute the instructions in basic block S, while the third and fourth threads do not.

[0087] The two SIMT stacks in this embodiment include a first SIMT stack and a second SIMT stack. The first SIMT stack and the second SIMT stack can be randomly determined or determined according to a certain rule to manage the execution information of which basic block of different branch basic blocks.

[0088] This rule can be to assign the branch with shorter thread switching time to the first SIMT stack and the branch with longer thread switching time to the second SIMT stack. For example, suppose that after the instructions in basic block B are executed, they diverge into branch basic blocks C and D. If the time required for a thread to switch from the end instruction of basic block B to the first instruction in branch basic block C is shorter than the time required to switch from the end instruction of basic block B to the first instruction in branch basic block B, then the first SIMT stack can be configured to manage the execution information of branch basic block C, and the second SIMT stack can manage the execution information of branch basic block D.

[0089] The GPU is equipped with a scheduling unit, which can be understood as an instruction scheduler. When executing instructions, the scheduling unit can fetch instructions based on the latest state of the first and second SIMT stacks and hand them over to MIMD for concurrent execution.

[0090] Specifically, when both the first SIMT stack and the second SIMT stack are not empty, the scheduling unit retrieves the instructions from each branch basic block according to the execution information of the first SIMT stack and the second SIMT stack, and transmits them to the MIMD for concurrent execution.

[0091] The first and second SIMT stacks can be either empty or non-empty. If both the first and second SIMT stacks are non-empty, it indicates that the current basic block to be executed is a two-branch basic block. Accordingly, the first SIMT stack contains the execution information for one of the two branch basic blocks, while the second SIMT stack contains the execution information for the other branch basic block. Therefore, the scheduling unit can retrieve the instructions from the two branch basic blocks based on the execution information in the first and second SIMT stacks and send them to MIMID. Because MIMD allows different threads in the same thread bundle to execute different instructions, after receiving instructions from two different branch basic blocks, MIMD controls the corresponding execution channel to execute the instructions according to the mask in the execution information of each branch basic block, thereby achieving concurrent execution of instructions from different branch basic blocks.

[0092] In one embodiment, the MIMD of this application is configured with a predicate mask, which includes three state values: a first state value, a second state value, and a third state value.

[0093] The first state value indicates that the execution channel in MIMD is closed, the second state value indicates that the execution channel in MIMD is executing the instructions in the first branch basic block, and the third state value indicates that the execution channel in MIMD is executing the instructions in the second branch basic block.

[0094] For example, the predicate mask includes three state values: 0, 1, and 2. 0 indicates that the corresponding lane (execution channel) in the MIMD is closed, 1 indicates that the corresponding lane in the MIMD executes the instructions in the first branch basic block managed by the first SIMT stack, and 2 indicates that the corresponding lane in the MIMD executes the instructions in the branch basic block managed by the second SIMT stack.

[0095] Furthermore, in the execution information maintained in the first SIMT stack and the second SIMT stack, if the state value of the predicate mask is 1, the bit corresponding to the mask field in the execution information of the first SIMT stack is 1, and the remaining bits are 0; if the state value of the predicate mask is 2, the bit corresponding to the mask field in the execution information of the second SIMT stack is 1, and the remaining bits are 0.

[0096] In this way, by setting the state value of the predicate mask to three state values, the predicate masks corresponding to threads executing different branch basic blocks in the same thread bundle are distinguished by different state values, which facilitates the differentiated management of the two, greatly reduces the probability of confusion and errors, and thus increases the convenience of independent management of threads corresponding to dual-branch instructions.

[0097] In this embodiment, the processor adopts a MIMD architecture and is configured with dual SIMT stacks to manage the execution information of different branch basic blocks within the same thread bundle. When the processor encounters a branch basic block (i.e., a branch instruction) during instruction execution, the execution information of each branch instruction is independently managed in different SIMT stacks. Combined with the fact that different processing modules in the MIMD architecture can asynchronously execute different instructions, the scheduling unit can assign different branch instructions from the same thread bundle to the MIMD for concurrent execution. This achieves asynchronous execution of branch instructions within the same thread bundle, resulting in parallel processing of branch instructions. Since each execution channel in the MIMD has its own ALU, the concurrent execution of branch instructions across different execution channels in the MIMD naturally improves the ALU resource utilization, thereby enhancing the performance of the GPU program.

[0098] like Figure 3 As shown, in one embodiment, the processor is also configured with an RPC stack; the RPC stack is used for the direct common post-dominant node of different branch basic blocks.

[0099] The direct common dominating node between two branch instructions can be understood in conjunction with the dominating tree in programming. Nodes in the dominating tree represent basic blocks in the program, and edges indicate the direction of control flow. In the dominating tree, if basic block Y will always pass through basic block X during execution, then basic block X dominates basic block Y.

[0100] Therefore, in the control flow of a program, if there are two branch instructions (i.e. two branch basic blocks) that have a common follow-up node, and this follow-up node is located after the two branch instructions in the program flow, then it means that the follow-up node jointly dominated by the two branch instructions is called the direct common follow-up node of the two branch instructions.

[0101] To address this, the technical solution of this application includes a dedicated RPC stack, which stores the direct common post-dominant node of the two branch basic blocks. In this embodiment, setting up the RPC stack allows for certain constraints on branch instruction jumps based on the head node maintained in the RPC stack during the execution of branch basic blocks, enabling the two branch instructions to reconverge at the convergence point and ensuring the correct execution of each basic block in each control flow.

[0102] Furthermore, the internal entries of the first SIMT stack and the second SIMT stack are described. In one embodiment, both the first SIMT stack and the second SIMT stack include a PC register and a predicate register. The PC register is used to store the instruction address of the basic block to be executed, and the predicate register is used to store the thread mask of the basic block to be executed.

[0103] Specifically, please see Figure 4 As shown, Figure 4 The diagram illustrates the first SIMT stack, which includes a first PC register (PC1) and a first thread mask (mask1), and the second SIMT stack, which includes a second PC register (PC2) and a second thread mask (mask2).

[0104] The PC register is used to store the address of the next instruction. In this embodiment, the basic block to be executed refers to the program instruction to be executed next, so the PC register stores the instruction address of the basic block to be executed. That is, the instruction address in the execution information mentioned in the previous embodiment is the instruction address stored in the PC register here.

[0105] In practical applications, the PC register in the SIMT stack is crucial, ensuring that the program can execute each instruction in the correct order.

[0106] The predicate register is a key component in GPUs for implementing efficient branch instructions. Each thread has its own predicate register, and each bit in the predicate register represents whether the corresponding thread is valid or invalid.

[0107] Similarly, see the explanation of the thread mask in the execution information above.

[0108] The settings of the PC register and predicate register in the two SIMT stacks in this embodiment enable effective, correct and convenient management of the execution information of each basic block to be executed in the dual-branch instruction, ensuring that the branch basic blocks in the same thread bundle are correctly executed concurrently.

[0109] Please continue reading Figure 4 As shown, in conjunction with the purpose of concurrent execution of dual-branch instructions in the embodiments of this application, in one embodiment, the processor is further configured with a first instruction cache and a second instruction cache. The first instruction cache is used to store instructions in the branch basic block managed by the first SIMT stack, and the second instruction cache is used to store instructions in the branch basic block managed by the second SIMT stack.

[0110] Two different branch instructions need to be executed asynchronously and concurrently by different threads in the same thread bundle. Therefore, not only does the MIMD architecture in the backend execution unit ensure that the two branch instructions can be executed independently and concurrently, but the instruction cache required for independent concurrent execution of the two branch instructions also needs to be configured separately. In this way, different instruction caches are set for different instruction branches to facilitate instruction retrieval for different branch instructions.

[0111] In one embodiment, see Figure 5 As shown, the processor also includes an instruction fetch unit, which is used to fetch the corresponding instructions from the storage subsystem into the first instruction cache and the second instruction cache.

[0112] The storage subsystem can be understood as a storage unit used to store program instruction code files, while the instruction fetch unit is a hardware unit in the GPU used to fetch the instructions to be executed from the storage subsystem. The instruction fetch unit stores the fetched instructions in the instruction cache unit, waiting for the scheduling unit to perform subsequent scheduling and issuance of the instructions from the instruction cache unit, so as to dispatch the instructions to the MIMD for execution.

[0113] For example, the instruction fetch unit may fetch the instruction to be executed from the memory subsystem based on the instruction address, which may be the address of the next instruction or multiple instructions recorded in the PC register in the GPU. This application embodiment does not limit this.

[0114] The above description of the GPU architecture only introduces some of the functions or modules within the GPU. It is understood that, in addition to the structures mentioned above, the GPU may include other structural units, such as register files (where the ALU stores the results of operations performed according to instructions), video encoding / decoding, or other processing cores, which are not shown in the accompanying drawings and can be added based on actual needs. Regardless of the specific type, in this embodiment, by implementing concurrent execution of different branch instructions within the same thread bundle, the pipeline flushing overhead caused by serial execution within the thread bundle is reduced, resulting in higher execution efficiency during scheduling within the thread bundle and thus improving ALU resource utilization.

[0115] The above describes the internal structure of the GPU involved in the technical solution of this application from a structural perspective. Based on the internal architecture of the GPU, the technical solutions involved in the execution process of branch instructions in the GPU are introduced through specific embodiments.

[0116] It should be noted that the execution of each branch instruction in the technical solution of this application is the process of running program instructions inside the GPU. Therefore, the execution subject of each branch instruction execution method described below is the scheduling unit in the GPU. It should also be noted that the GPU architecture on which the instruction execution methods below are based and some corresponding configurations in the GPU can be found in the descriptions in the previous embodiments. The descriptions in the previous embodiments can be applied to or combined with any embodiment of the instruction execution methods below. For clarity and brevity, repeated details will not be repeated hereafter.

[0117] Please see Figure 6 As shown, in one embodiment, this application provides an instruction execution method, which includes the following steps:

[0118] S101, Update the stack state according to the basic block to be executed; the stack state includes at least one of the first SIMT stack and the second SIMT stack.

[0119] In this application's embodiments, the term "to be executed basic block" refers to any basic block within the control flow. For example, considering a thread executing a loop program whose control flow includes multiple basic blocks, please refer to [link to relevant documentation]. Figure 7 As shown, assuming that the control flow of a thread bundle execution includes seven basic blocks A, B, C, D, E, F and G, the basic block to be executed can be any one or more of A, B, C, D, E, F and G.

[0120] Before executing any basic block, the scheduling unit must update the stack state. This is because whenever an instruction in a basic block is executed in the GPU, the instruction address and thread mask of that basic block are pushed onto the corresponding stack. Therefore, updating the stack is to ensure that the instructions in the basic block can correctly access and manipulate the resources and data they need when they are executed.

[0121] In this application's technical solution, two SIMT stacks are set up in the GPU. The first SIMT stack and the second SIMT stack respectively manage the execution information of different branch basic blocks.

[0122] Based on this, for different basic blocks to be executed, updating the stack state may only update the state of the first SIMT stack, or it may update the state of the second SIMT stack, or it may update the state of both the first and second SIMT stacks.

[0123] Updating the stack state includes, but is not limited to, updating the entries in the stack. Optionally, the operation of updating the stack state includes, but is not limited to, pushing and popping operations.

[0124] In an exemplary embodiment, the stack state can be updated based on the conditional jumps before and after the basic block, updating the states of the first SIMT stack and the second SIMT stack. For example, updates can be performed according to preset rules. These preset rules can be set based on the instruction jump type of the end instruction of the basic block preceding the basic block to be executed. This instruction jump type includes, but is not limited to, uniform jumps or divergent jumps.

[0125] Among them, unified redirect is unifom redirect, and divergent redirect is divergence redirect.

[0126] S102, if both the updated first SIMT stack and the second SIMT stack are not empty, according to the execution information of the first SIMT stack and the second SIMT stack, the instructions in each branch basic block are retrieved and transferred to MIMD for concurrent execution.

[0127] If both the first and second SIMT stacks are not empty, it indicates that the basic block to be executed is a two-branch basic block. Accordingly, the first SIMT stack contains the execution information of one of the two-branch basic blocks, while the second SIMT stack contains the execution information of the other-branch basic block.

[0128] Therefore, the scheduling unit can extract the instructions from the two branch basic blocks based on the execution information in the first SIMT stack and the second SIMT stack, respectively, and give them to MIMID. Since MIMD allows different threads in the same thread bundle to execute different instructions, after MIMD receives the instructions from the two different branch basic blocks, it controls the corresponding execution channel to execute the instructions according to the mask in the execution information of each branch basic block, thereby realizing the concurrent execution of instructions in different branch basic blocks.

[0129] In this embodiment, a MIMD architecture is employed in the GPU, configured with a first SIMT stack and a second SIMT stack to manage execution information of different branch basic blocks within the same thread bundle. Based on this, the state of at least one of the first and second SIMT stacks is updated according to the basic block to be executed. When both the updated first and second SIMT stacks are not empty, instructions from each branch basic block are retrieved according to the execution information of the first and second SIMT stacks and transmitted to the MIMD for concurrent execution. In this method, because different SIMT stacks independently manage the execution information of each branch instruction, and the various processing modules in the MIMD architecture can execute different instructions asynchronously, the scheduling unit can send different branch instructions from the same thread bundle to the MIMD for concurrent execution, achieving asynchronous execution of branch instructions within the same thread bundle and achieving parallel processing of branch instructions. Since each execution channel in the MIMD has its own ALU, the concurrent execution of branch instructions by each execution channel in the MIMD naturally improves the resource utilization of the ALU, thereby enhancing the running performance of the GPU program.

[0130] Based on the foregoing embodiments, the following provides some embodiments to illustrate the process of retrieving instructions from each branch basic block and transmitting them to MIMD for concurrent execution when both the updated first SIMT stack and the second SIMT stack are not empty, according to the execution information of the first SIMT stack and the second SIMT stack.

[0131] like Figure 8 As shown, in one embodiment, S102 above includes the following steps:

[0132] S201, fetch the first instruction from the first branch basic block according to the instruction address in the PC register of the first SIMT stack, and fetch the second instruction from the second branch basic block according to the instruction address in the PC register of the second SIMT stack.

[0133] The execution information managed in the SIMT stack includes instruction addresses, which are stored in the PC register within the SIMT stack. This instruction address refers to the address of the instruction within the basic block managed by the SIMT.

[0134] Because the two SIMT stacks manage different branch basic blocks respectively, the first instruction in the first branch basic block is fetched according to the instruction address in the PC register of the first SIMT stack, and the second instruction in the second branch basic block is fetched according to the instruction address in the PC register of the second SIMT stack.

[0135] S202, the first instruction and the second instruction are transmitted to the MIMD, so that the MIMD can execute the first instruction and the second instruction concurrently.

[0136] Both types of instructions taken from the two different branch basic blocks are handed over to MIMD so that MIMD can execute the first and second instructions concurrently.

[0137] Since a basic block is a program sequence, instructions can be fetched one by one from the two branch basic blocks. Each cycle fetches one instruction from each branch basic block and sends it to the MIMD until all instructions in the basic block have been fetched. Then, the cycle jumps to the next basic block according to the end instruction.

[0138] In this embodiment, the first instruction in the first branch basic block is fetched according to the instruction address in the PC register of the first SIMT stack, and the second instruction in the second branch basic block is fetched according to the instruction address in the PC register of the second SIMT stack. Then, the first and second instructions are transferred to the MIMD, allowing the MIMD to execute the first and second instructions concurrently. Since instruction fetching for different branch basic blocks is based on the execution information in their respective SIMT stacks, the instructions in each branch basic block can be executed concurrently.

[0139] The scheduling unit may fetch instructions from the instruction cache. In one embodiment, fetching a first instruction from a first branch basic block according to the instruction address of the first SIMT stack, and fetching a second instruction from a second branch basic block according to the instruction address of the second SIMT stack, includes: fetching the first instruction from the first instruction cache according to the instruction address of the first SIMT stack, and fetching the second instruction from the second instruction cache according to the instruction address of the second SIMT stack.

[0140] The GPU is also configured with a first instruction cache and a second instruction cache. Different instruction caches allow instructions in different branch basic blocks to be managed independently, ensuring that they are executed asynchronously by MIMD independently.

[0141] In one embodiment, the process of concurrently executing dual-branch instructions within the same thread bundle in the MIMD includes the MIMD controlling the execution channel corresponding to the thread indicated by the first thread mask to execute the first instruction according to the first thread mask of the first instruction; and controlling the execution channel corresponding to the thread indicated by the second thread mask to execute the second instruction according to the second thread mask of the second instruction.

[0142] As mentioned earlier, each lane (execution channel) in MIMD has its own ALU, corresponding to a thread in the execution thread bundle. Execution information also includes a thread mask, which is located in the SIMT stack. For each instruction, the thread mask is pre-push onto the SIMT stack containing its branch basic block. This thread mask indicates which lane in MIMD will execute the instruction. Therefore, MIMD only needs to control the execution of the lane corresponding to the thread of the instruction to be executed according to the thread mask of the instruction to be executed.

[0143] For example, the thread mask in the SIMT stack can be transmitted to the MIMD by the scheduling unit along with the instruction, or it can be requested by the MIMD from the scheduling unit. This application embodiment does not limit the implementation process.

[0144] Accordingly, a predicate mask is configured in the MIMD, which includes three state values: a first state value, a second state value, and a third state value. The first state value indicates that the execution channel in the MIMD is closed, the second state value indicates that the execution channel in the MIMD executes the instructions in the first branch basic block, and the third state value indicates that the execution channel in the MIMD executes the instructions in the second branch basic block.

[0145] The predicate masking process can also be found in the previous examples, and will not be repeated here.

[0146] In this embodiment, by setting the state value of the predicate mask to three different state values, the predicate masks corresponding to threads executing different branch basic blocks in the same thread bundle are distinguished by different state values. This facilitates the differentiated management of the two, greatly reduces the probability of confusion and errors, and thus increases the convenience of independently managing the threads corresponding to dual-branch instructions.

[0147] The above embodiments describe the process of the scheduling unit fetching instructions and assigning them to the MIMD for execution when both the updated first and second SIMT stacks are not empty. However, in practical applications, the updated first and second SIMT stacks may also be empty. This embodiment does not consider the case where both stacks are empty, so it describes the case where one of the two stacks is empty and the other is not empty.

[0148] In one embodiment, the method further includes: if the updated target SIMT stack is not empty, retrieving instructions from the target basic block managed by the target SIMT stack according to the execution information of the target SIMT stack and transferring them to the MIMD for execution.

[0149] The target SIMT stack is either the first SIMT stack or the second SIMT stack.

[0150] If one of the first SIMT stack and the second SIMT stack is empty while the other is not empty, it indicates that no branch basic block has occurred. In this case, the instructions in the target basic block managed by the target SIMT stack are retrieved according to the execution information of the target SIMT stack and transferred to MIMD for execution.

[0151] For example, if the target SIMT stack is the first SIMT stack, then the instructions in the basic block managed by the first SIMT stack are transferred to MIMD for execution. Since the instructions themselves are within a basic block, MIMD does not need to execute them concurrently and directly executes the instructions in that basic block.

[0152] It should be noted that, in cases where no branch basic block appears, the execution information (instruction address and thread mask) of the basic block is usually pushed onto the first SIMT stack. Therefore, in one embodiment, the target SIMT stack is the first stack.

[0153] In one embodiment, the process of retrieving instructions from the target basic block managed by the target SIMT stack and transferring them to the MIMD for execution according to the execution information of the target SIMT stack includes: retrieving instructions from the target basic block from the instruction cache corresponding to the target SIMT stack according to the instruction address in the PC register of the target SIMT stack and transferring them to the MIMD for execution.

[0154] When one of the first SIMT stack and the second SIMT stack is empty and the other is not empty, instructions are fetched from the instruction cache corresponding to the target SIMT stack.

[0155] For example, if the target SIMT stack is the first SIMT stack, then the instruction cache corresponding to the target SIMT stack is the first instruction cache in the GPU; if the target SIMT stack is the second SIMT stack, then the instruction cache corresponding to the target SIMT stack is the second instruction cache in the GPU.

[0156] In this embodiment, if there is no branch block, it means that the same instruction is being executed in the same thread bundle. Therefore, in this embodiment, the execution information is pushed into the first SIMT stack, and the instruction is fetched from the first instruction cache, which ensures the correct execution of the instruction.

[0157] Based on any of the above embodiments, the process of updating the stack state according to the basic block to be executed will be described below through several embodiments.

[0158] When updating the stack state based on the basic block to be executed, if the basic block to be executed is the top basic block, the stack push operation is performed directly. However, if the basic block to be executed is not the top basic block, the stack state update needs to be performed in conjunction with the jump type of the end instruction of the previous basic block.

[0159] The top basic block can participate in the aforementioned Figure 6 The basic block A in the middle, naturally, in Figure 6 In this context, all basic blocks except for the basic A are non-top basic blocks.

[0160] In one embodiment, S101 includes: if the basic block to be executed is the top basic block, pushing the execution information of the top basic block into the first SIMT stack.

[0161] The SIMT stack stores execution information for basic blocks.

[0162] For the top basic block, both the first and second SIMT stacks are empty because the basic block has not yet been executed. Furthermore, the top basic block is a basic block without branches, so the execution information of the top basic block is pushed onto the first SIMT stack. By pushing the execution information of the top basic block onto the first SIMT stack, it is treated as a case without branch instructions, ensuring that the instructions in the top basic block can be executed correctly.

[0163] like Figure 9 As shown, in one embodiment, the process of pushing the execution information of the top basic block into the first SIMT stack includes the following steps:

[0164] S301, obtain the instruction address and thread mask of the top basic block.

[0165] Execution information includes instruction addresses and thread masks. Therefore, to push the execution information of the top basic block onto the first SIMT stack, the instruction addresses and thread masks of the top basic block must first be obtained.

[0166] For example, the instruction address of the top basic block can be the instruction address of the first instruction in the top basic block plus the length of the instruction addresses in the top basic block. This allows the scheduling unit to accurately identify each instruction in the top basic block when fetching instructions.

[0167] For example, the thread mask in the top basic block can be determined based on the bit for each thread in the predicate register. For instance, if the thread bundle has 4 threads, the thread mask of that thread is 1 if the bit in the predicate register is 1, and the thread mask of that thread is 0 if the corresponding bit in the predicate register is 0.

[0168] This application does not limit the instruction address and thread mask for obtaining the top basic block in the embodiments.

[0169] S301, push the instruction address of the top basic block into the PC register of the first SIMT stack, and push the thread mask of the top basic block into the predicate register of the first SIMT stack.

[0170] In this embodiment, both the first and second SIMT stacks have a PC register to store the instruction address of the basic block to be executed. Similarly, both the first and second SIMT stacks have a predicate register to store the thread mask of the basic block to be executed. Based on this, when the top basic block is the basic block to be executed, the instruction address of the top basic block is pushed into the PC register of the first SIMT stack. The thread mask of the top basic block is pushed into the predicate register of the first SIMT stack.

[0171] For example, see Figure 10 The diagram shows the control flow graph of a common loop program, containing multiple nested branch instructions. Boxes represent basic blocks, numbers within the boxes represent the thread masks of the basic blocks, and arrows indicate the jump direction of jump instructions. Figure 10 The top basic block is basic block A. The GPU starts executing this program from basic block A. At this point, there are no branches in the program, so the second SIMT stack is empty. The scheduling unit can only fetch instructions from the registers of the first SIMT stack. At this time, the stack state of basic block A is updated, as shown in Table 1 below:

[0172] Table 1

[0173]

[0174] In Table 1 above, PC1 represents the register of the first SIMT stack, mask1 represents the thread mask of the basic block in the first SIMT stack, PC2 represents the register of the second SIMT stack, mask2 represents the thread mask of the basic block in the second SIMT stack, and RPC represents the stack used to store the dominant node after the two branch basic blocks directly share the same data. Subsequent stack state tables are similar and will not be described in detail.

[0175] In this embodiment, before the instructions in the top basic block are executed, the instruction address and thread mask of the top basic block are pushed into the first SIMT stack, so that the scheduling unit can correctly execute the instructions in the top basic block from the execution information of the top basic block managed by the first SIMT stack.

[0176] For non-top basic blocks, the stack state is updated as follows.

[0177] In one embodiment, updating the stack state based on the basic block to be executed includes: if the basic block to be executed is not the top basic block, updating the stack state based on the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack.

[0178] As previously explained, the GPU is also configured with an RPC stack. In practical applications, updating the stack state also includes updating the RPC stack state. When the basic block to be executed is not the top basic block, it means that the instructions in at least one basic block have already been executed, and naturally, the state information in each stack has also been updated.

[0179] Then, the stack state required for the execution of the basic block can be updated based on the contents of the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack.

[0180] This application embodiment can set rule conditions for the relationship between the values ​​of the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack. Different stack update operations are performed under each rule condition. The specific stack update operation can be determined according to the set rule conditions before the specific instruction is executed.

[0181] The following continues in conjunction with the above. Figure 10 ,according to Figure 10 The execution order of basic blocks in the code is explained, and several cases of determining specific stack update operations based on set rules and conditions are introduced.

[0182] If the next basic blocks to be executed are B and F, then in one embodiment, determining the specific stack update operation based on the set rules includes: if the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a divergent jump, then obtain the two divergent branch basic blocks. Push the execution information of the two branch basic blocks into the first SIMT stack and the second SIMT stack respectively, and push the direct common post-dominant node of the two branch basic blocks into the RPC stack.

[0183] In this context, divergence jumps are called diversity jumps. That is, PC1 or PC2 points to a diversity jump, and the scheduling unit pushes the two branches onto the first SIMT stack and the second SIMT stack respectively, and pushes the direct common post-dominant node of the two branches onto the RPC stack.

[0184] Table 1 above is the stack state table for the basic block A to be executed. The execution of instructions in basic block A is naturally based on the stack state in Table 1. After basic block A finishes execution, since the end instruction of basic block A branches out into two basic blocks B and F, the instruction address of basic block A is still in the PC register of the first SIMT stack. Therefore, it belongs to the PC1 pointing to diversity jump instruction, satisfying the rule condition that PC1 or PC2 points to diversity jump.

[0185] Therefore, after the GPU executes basic block A, it encounters a divergence jump instruction. The branches target basic blocks B and F, respectively. At this time, the stack state update operation is as follows: the first SIMT stack is popped directly, and basic blocks B and F are pushed onto the first SIMT stack and the second SIMT stack, respectively. The direct common dominator node G of basic blocks B and F is pushed onto the RPC stack. The state of the SIMT stack at this time is shown in Table 2 below:

[0186] Table 2

[0187]

[0188] Based on the updated stack state in Table 2, the instructions in branch basic blocks B and F need to be executed concurrently. Specifically, since neither the first SIMT stack nor the second SIMT stack is empty at this time, and both are divergent branch basic blocks, their masks1 and mask2 must not overlap. Therefore, each cycle of the scheduling unit can take one instruction from branch basic block B pointed to by PC1 and one instruction from branch basic block F pointed to by PC2 and give them to MIMD for concurrent execution.

[0189] The next basic blocks to be executed are C and D. In one embodiment, the method further includes: if the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump, and the jump address is the same as the head node of the RPC stack, then the instruction fetching of the SIMT stack pointing to the unified jump is suspended until both the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack point to the unified jump.

[0190] The rule in this embodiment is: PC1 or PC2 points to a uniform jump, and the jump address is the same as the header node of the RPC. At this time, the instruction fetching of the corresponding SIMT stack is suspended until the end instruction of the basic block in the PC register of the first SIMT stack and the end instruction of the basic block in the PC register of the second SIMT stack both point to the same jump.

[0191] Please continue reading Figure 10 After the instructions in the aforementioned branch basic blocks B and F are executed, the end instruction of branch basic block F is a uniform jump to basic block G, and the top element (head node) of the RPC stack is also G (see Table 2 for the latest stack state table). Therefore, the second SIMT stack is blocked by the RPC and cannot be popped immediately. The end instruction of the other branch basic block B is a divergence jump to basic blocks C and D, which is different from the top element of the RPC stack. Therefore, it is not blocked by the top element of the RPC stack and can jump and be popped. Thus, the stack state update operation for the basic blocks C and D to be executed is: push basic blocks C and D onto the first SIMT stack and the second SIMT stack respectively, and push the direct common next dominator node E of C and D onto the RPC stack. The state of the SIMT stack at this time is shown in Table 3 below.

[0192] Table 3

[0193]

[0194] Based on the updated stack state in Table 3, instructions in branch basic blocks C and D need to be executed concurrently. Specifically, since neither the first SIMT stack nor the second SIMT stack is empty at this time, and both are divergent branch basic blocks, their masks1 and mask2 must not overlap. Therefore, each cycle of the scheduling unit can take one instruction from branch basic block C pointed to by PC1 and one instruction from branch basic block D pointed to by PC2 and give them to MIMD for concurrent execution.

[0195] If the next basic block to be executed is E, then in one embodiment, for the basic block to be executed E, the specific stack update operation is determined according to the set rules and conditions, including: if the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack both point to the same jump, and the jump address is the same as the head node of the RPC stack, then the first SIMT stack, the second SIMT stack and the RPC stack are popped simultaneously, and the jump address is pushed back into the first SIMT stack.

[0196] In this context, "uniform jump" refers to a jump where both PC1 and PC2 point to a uniform jump, and the jump addresses are the same as the RPC header. This triggers a SIMT stack merge, where the first SIMT stack, the second SIMT stack, and the RPC stack are popped simultaneously, and the jump addresses are pushed back onto the first SIMT stack.

[0197] When the execution information of basic block C is in the first SIMT stack and the execution information of basic block D is in the second SIMT stack, the instructions in basic block C and basic block D need to be executed in the manner described in the previous embodiment when both stacks are not empty. After the execution of basic block C and basic block D is completed, the end instructions of basic block C and basic block D are checked. It is found that both of them point to uniform jumps, and the addresses pointing to uniform jumps are the addresses of basic block E. At this time, the head node in the RPC stack is also basic block E. Therefore, the re-merging of PC1 and PC2 is triggered. The stack update operation performed at this time is: the first SIMT stack, the second SIMT stack, and the RPC stack are popped simultaneously, and basic block E is pushed into the first SIMT stack. The updated stack state is as shown in Table 4 below:

[0198] Table 4

[0199]

[0200] Based on the updated stack state in Table 4, the instructions in branch basic blocks E and F need to be executed concurrently. Specifically, since neither the first SIMT stack nor the second SIMT stack is empty at this time, and both are divergent branch basic blocks, their mask1 and mask2 must not overlap. Therefore, each cycle of the scheduling unit can take one instruction from branch basic block E pointed to by PC1 and one instruction from branch basic block F pointed to by PC2 and give them to MIMD for concurrent execution.

[0201] If the next basic block to be executed is G, then in one embodiment, for the basic block to be executed E, the specific stack update operation is determined according to the set rules and conditions, including: if the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump, and the jump address is different from the head node of the RPC stack, then the SIMT stack pointing to the unified jump is popped from the stack, and the jump address is pushed back into the SIMT stack pointing to the unified jump.

[0202] In this embodiment, the rule condition is that PC1 or PC2 points to a uniform jump, and the jump address is different from the RPC header node. At this time, the corresponding SIMT stack is popped and the jump address is pushed back onto the corresponding stack.

[0203] The end instructions for basic blocks E and F are both jump instructions with target address G, and the header node of the RPC is G. Therefore, PC1 and PC2 will be merged. At this time, the first SIMT stack, the second SIMT stack, and the RPC stack are popped simultaneously, and basic block G is pushed onto the first SIMT stack. The state of the SIMT stack at this time is shown in Table 5 below:

[0204] Table 5

[0205]

[0206] Based on the updated stack state in Table 5, the instructions in basic block G need to be executed. Specifically, since the second SIMT stack is empty at this time, the scheduling unit can only take one instruction from the branch basic block G pointed to by PC1 and hand it over to MIMD for execution in each cycle.

[0207] After basic block G is executed, the end instruction of basic block G is an unconditional jump to the target address A. Since the head node of RPC in Table 5 is not A, the stack update operation is as follows: the first SIMT stack is popped directly, and basic block A is pushed onto the first SIMT stack. The GPU stack returns to the initial state of program execution, and the basic block to be executed returns to the top basic block A, starting the next round of loop, as shown in Table 6 below:

[0208] Table 6

[0209]

[0210] The above describes the process of updating the stack state based on the basic block to be executed in this embodiment. By setting rules for stack state updates and executing instructions, the two branch basic blocks can be executed concurrently, greatly alleviating the performance degradation caused by branch instructions and significantly improving the utilization of the ALU in divergent branch scenarios, thereby improving GPU program performance. Moreover, this embodiment maintains source code-level compatibility while requiring only a small increase in chip area, greatly improving the applicability of various scenarios.

[0211] In one embodiment, the present application also provides a branch instruction execution method, which can be found in the foregoing embodiment. Figure 10 Tables 1-6, including the following procedures:

[0212] S1, obtain the instruction address of the program instruction in basic block A.

[0213] S2, push the instruction address and thread mask of basic block A into the first SIMT stack;

[0214] S3, according to the instruction address in the first SIMT stack, transfer the program instructions in the basic block A to the MIMD for execution;

[0215] S4, if the address pointed to by the end instruction in the program instructions in basic block A is a divergence jump to basic blocks B and F, then pop the first SIMT stack, push the instruction address and thread mask of basic block B onto the first SIMT stack, push the instruction address and thread mask of basic block F onto the second SIMT stack, and push the direct common post-dominant node G of basic blocks B and F onto the RPC stack;

[0216] S5, read the instruction addresses of the first SIMT stack and the second SIMT stack;

[0217] S6: According to the instruction addresses of the first SIMT stack and the second SIMT stack, fetch one instruction from the instruction cache and pass it to MIMD for concurrent execution;

[0218] S7, the end instruction of basic block B is a divergence jump to basic blocks C and D, then pop the first SIMT stack, push the instruction address and thread mask of basic block C into the first SIMT stack, push the instruction address and thread mask of basic block D into the second SIMT stack, and push the direct common post-dominant node E of basic blocks C and D into the RPC stack.

[0219] S8, read the instruction addresses of the first SIMT stack and the second SIMT stack;

[0220] S9: According to the instruction addresses of the first SIMT stack and the second SIMT stack, fetch one instruction from the instruction cache and pass it to MIMD for concurrent execution;

[0221] S10, the address pointed to by the end instruction of basic blocks C and D is a uniform jump to E, and the head node of RPC is also E, then the re-merging of PC1 and PC2 is triggered. At this time, the first SIMT stack, the second SIMT stack, and the RPC stack are popped simultaneously, and basic block E is pushed onto the first SIMT stack.

[0222] S11, read the instruction addresses of the first SIMT stack and the second SIMT stack;

[0223] S12, according to the instruction addresses of the first SIMT stack and the second SIMT stack, fetch one instruction from each instruction cache and pass them to MIMD for concurrent execution;

[0224] S13, the end instructions of basic blocks E and F point to uniform jumps to G, and the head node of RPC is G, thus triggering the re-merging of PC1 and PC2. At this time, SIMT stacks 1 and 2 and the RPC stack are popped simultaneously, and basic block G is pushed onto SIMT stack 1.

[0225] S14, read the instruction addresses of the first SIMT stack and the second SIMT stack;

[0226] S15, if the second SIMT stack is empty, then fetch instructions from the instruction cache according to the first SIMT stack and pass them to MIMD for execution;

[0227] S16, the end instruction of basic block G is unconditionally jumped to address A, and the head node of RPC is not A, so the 1st SIMT stack is popped and basic block A is pushed into the 1st SIMT stack.

[0228] S17, the GPU's SIMT stack returns to the initial state of program execution and begins the next loop.

[0229] The implementation principle of each step in this embodiment is the same as that in the previous embodiments, and will not be repeated here.

[0230] It should be understood that although the steps in the flowchart above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the above embodiments may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0231] In one embodiment, such as Figure 11 As shown, an instruction execution device 110 is provided, including: a stack state update module 1101 and an instruction execution module 1102, wherein:

[0232] The stack state update module 1101 is used to update the stack state according to the basic block to be executed; the stack state includes at least one of the first SIMT stack and the second SIMT stack.

[0233] The instruction execution module 1102 is used to extract the instructions from each branch basic block and transmit them to the MIMD for concurrent execution, according to the execution information of the first SIMT stack and the second SIMT stack, when both the updated first SIMT stack and the second SIMT stack are not empty.

[0234] In one embodiment, the execution information includes an instruction address, which is stored in the PC register; the instruction execution module 1102 includes an instruction fetch unit and an instruction transfer unit, wherein:

[0235] The first instruction fetch unit is used to fetch the first instruction in the first branch basic block according to the instruction address in the PC register of the first SIMT stack, and to fetch the second instruction in the second branch basic block according to the instruction address in the PC register of the second SIMT stack.

[0236] The instruction transmission unit is used to transmit the first instruction and the second instruction to the MIMD, so that the MIMD can execute the first instruction and the second instruction concurrently.

[0237] In one embodiment, the execution information further includes a thread mask; an instruction transmission unit, configured to control the execution channel corresponding to the thread indicated by the first thread mask to execute the first instruction according to the first thread mask of the first instruction; and to control the execution channel corresponding to the thread indicated by the second thread mask to execute the second instruction according to the second thread mask of the second instruction.

[0238] In one embodiment, a predicate mask is configured in the MIMD, and the predicate mask includes three state values: a first state value, a second state value, and a third state value.

[0239] The first state value indicates that the execution channel in MIMD is closed, the second state value indicates that the execution channel in MIMD is executing the instructions in the first branch basic block, and the third state value indicates that the execution channel in MIMD is executing the instructions in the second branch basic block.

[0240] In one embodiment, the GPU is further configured with a first instruction cache and a second instruction cache; the first instruction fetch unit includes: an instruction fetch subunit, configured to fetch a first instruction from the first instruction cache according to the instruction address of the first SIMT stack, and to fetch a second instruction from the second instruction cache according to the instruction address of the second SIMT stack.

[0241] In one embodiment, the apparatus further includes: an instruction fetching module, configured to fetch instructions from a target basic block managed by the target SIMT stack and transmit them to the MIMD for execution, according to the execution information of the target SIMT stack, when the updated target SIMT stack is not empty; wherein the target SIMT stack is a first SIMT stack or a second SIMT stack.

[0242] In one embodiment, the instruction fetching module includes: a second instruction fetching unit, configured to fetch instructions from the instruction cache corresponding to the target basic block according to the instruction address in the PC register of the target SIMT stack and pass them to the MIMD for execution.

[0243] In one embodiment, the stack state update module 1101 includes: an information push unit, used to push the execution information of the top basic block into the first SIMT stack when the basic block to be executed is the top basic block.

[0244] In one embodiment, the execution information includes instruction address and thread mask, and the information push unit includes:

[0245] The information acquisition subunit is used to obtain the instruction address and thread mask of the top basic block;

[0246] The information push stack subunit is used to push the instruction address of the top basic block into the PC register of the first SIMT stack, and to push the thread mask of the top basic block into the predicate register of the first SIMT stack.

[0247] In one embodiment, the GPU is also configured with an RPC stack, and the stack state update module 1101 includes: a stack update unit, used to update the stack state according to the PC register of the first SIMT stack, the PC register of the second SIMT stack and the head node of the RPC stack when the basic block to be executed is not the top basic block.

[0248] In one embodiment, the stack update unit includes: a first stack update subunit, configured to pop the first SIMT stack, the second SIMT stack, and the RPC stack simultaneously, and push the jump address back onto the first SIMT stack, when both the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack point to the same jump and the jump address is the same as the head node of the RPC stack.

[0249] In one embodiment, the stack update unit includes a second stack update subunit, configured to pop the SIMT stack pointing to the unified jump and push the jump address back onto the SIMT stack pointing to the unified jump when either the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump and the jump address is different from the head node of the RPC stack.

[0250] In one embodiment, the apparatus further includes a stack update stop subunit, configured to pause instruction fetching of the SIMT stack pointing to the unified jump when either the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump, and the jump address is the same as the head node of the RPC stack, until both the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack point to the unified jump.

[0251] In one embodiment, the stack update unit includes: a third stack update subunit, configured to, when the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a divergent jump, obtain two divergent branch basic blocks; push the execution information of the two branch basic blocks into the first SIMT stack and the second SIMT stack respectively, and push the direct common post-dominant node of the two branch basic blocks into the RPC stack.

[0252] For specific limitations regarding the instruction execution device, please refer to the limitations on instruction execution methods above, which will not be repeated here. Each module in the aforementioned instruction execution device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the instruction processing device, or stored in software in the memory of the instruction processing device, so that the processor can invoke and execute the operations corresponding to each module.

[0253] It should be noted that the division of modules, units, and sub-units in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0254] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application.

[0255] It should be noted that the apparatus provided in this application embodiment can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Here, the parts that are the same as those in the method embodiment and the beneficial effects will not be described in detail.

[0256] In addition, this application provides an instruction execution device, which includes a memory, a general-purpose graphics processor, and a computer program; the computer program is stored in the memory; the general-purpose graphics processor is used to run the computer program to execute the steps of the instruction execution method of any of the above embodiments.

[0257] like Figure 12 As shown in the figure, this application provides a computing system, which includes an instruction execution device, a general interconnect interface, and other processing devices; the instruction execution device interacts with the other processing devices to jointly complete the computing operations specified by the user.

[0258] Other processing devices include one or more processor types such as central processing units (CPUs), graphics processing units (GPUs), and neural network processors. There is no limit to the number of processors included in other processing devices. These other processing devices serve as interfaces between the instruction execution device and external data and control, including data transfer and basic control of the instruction execution device; they can also collaborate with the instruction execution device to complete computational tasks. A general interconnect interface is used to transmit data and control instructions between the instruction execution device and other processing devices. The instruction execution device can obtain the required input data from other processing devices and write it to its shared memory; it can obtain control instructions from other processing devices and write them to its machine learning components; it can also read data from the shared memory of the instruction execution device and transmit it to other processing devices.

[0259] The aforementioned computing system may further include a storage device, which is connected to the instruction execution device and other processing devices. The storage device is used to store data stored in the instruction execution device and other processing devices, and is particularly suitable for data that cannot be fully stored in the internal storage of the instruction execution device or other processing devices, requiring computation.

[0260] This computing system can serve as a System-on-a-Chip (SoC) for devices such as mobile phones, robots, drones, and video surveillance equipment, effectively reducing the core area of ​​the control unit, increasing processing speed, and lowering overall power consumption. In this case, the computing system's general-purpose interconnect interface connects to certain components of the device, such as cameras, monitors, mice, keyboards, network cards, and Wi-Fi interfaces.

[0261] In one embodiment, this application also provides a chip that includes the aforementioned computing system.

[0262] In one embodiment, this application also provides a chip packaging structure that includes the aforementioned chip.

[0263] In one embodiment, this application also provides a board that includes the above-described chip packaging structure.

[0264] In one embodiment, a readable storage medium is also provided, which stores a computer program that, when executed by a processor, is used to implement the steps of the instruction execution method of any of the above embodiments. The readable storage medium can be any available medium or data storage device accessible to the processor, including but not limited to magnetic storage (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND flash), solid-state drives (SSDs)).

[0265] In one embodiment, a computer program product is also provided, which, when executed by a processor, implements the steps of the instruction execution method of any of the above embodiments. The computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, some or all of the above methods can be implemented, wholly or partially, according to the processes or functions described in the embodiments of this application.

[0266] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0267] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0268] The above-described embodiments are merely illustrative of several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims

1. A method for executing instructions, characterized in that, It is applied to a graphics processing unit (GPU), wherein the GPU adopts multiple instruction multiple data (MIMD) and is configured with a first single instruction multiple thread (SIMT) stack and a second SIMT stack; The first SIMT stack and the second SIMT stack are respectively used to manage the execution information of different branch basic blocks within the same thread bundle; the method includes: Update the stack state based on the basic block to be executed; the stack state includes at least one of the first SIMT stack and the second SIMT stack. If both the updated first SIMT stack and the second SIMT stack are not empty, the instructions in each branch basic block are retrieved and transmitted to MIMD for concurrent execution according to the execution information of the first SIMT stack and the second SIMT stack.

2. The method according to claim 1, characterized in that, The execution information includes instruction addresses, which are stored in the program counter (PC) register; the step of retrieving instructions from each branch basic block and transferring them to the MIMD for concurrent execution according to the execution information of the first SIMT stack and the second SIMT stack includes: Fetch the first instruction from the first branch basic block according to the instruction address in the PC register of the first SIMT stack, and fetch the second instruction from the second branch basic block according to the instruction address in the PC register of the second SIMT stack; The first instruction and the second instruction are transmitted to the MIMD, so that the MIMD executes the first instruction and the second instruction concurrently.

3. The method according to claim 2, characterized in that, The execution information also includes a thread mask; the process by which the MIMD performs concurrent execution of the first instruction and the second instruction includes: The MIMD controls the execution channel corresponding to the thread indicated by the first thread mask to execute the first instruction according to the first thread mask of the first instruction; and controls the execution channel corresponding to the thread indicated by the second thread mask to execute the second instruction according to the second thread mask of the second instruction.

4. The method according to claim 3, characterized in that, The MIMD is configured with a predicate mask, which includes three state values: a first state value, a second state value, and a third state value. The first state value indicates that the execution channel in the MIMD is closed, the second state value indicates that the execution channel in the MIMD is executing the instructions in the first branch basic block, and the third state value indicates that the execution channel in the MIMD is executing the instructions in the second branch basic block.

5. The method according to claim 2, characterized in that, The GPU is also configured with a first instruction cache and a second instruction cache; the step of retrieving the first instruction from the first branch basic block according to the instruction address of the first SIMT stack, and retrieving the second instruction from the second branch basic block according to the instruction address of the second SIMT stack, includes: The first instruction is fetched from the first instruction cache according to the instruction address of the first SIMT stack, and the second instruction is fetched from the second instruction cache according to the instruction address of the second SIMT stack.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: If the updated target SIMT stack is not empty, the instructions in the target basic block managed by the target SIMT stack are retrieved according to the execution information of the target SIMT stack and transferred to MIMD for execution; wherein the target SIMT stack is the first SIMT stack or the second SIMT stack.

7. The method according to claim 6, characterized in that, The step of retrieving instructions from the target basic block managed by the target SIMT stack according to the execution information of the target SIMT stack and transferring them to MIMD for execution includes: According to the instruction address in the PC register of the target SIMT stack, the instruction in the target basic block is retrieved from the instruction cache corresponding to the target SIMT stack and passed to the MIMD for execution.

8. The method according to any one of claims 1-5, characterized in that, The step of updating the stack state based on the basic block to be executed includes: If the basic block to be executed is the top basic block, the execution information of the top basic block is pushed onto the first SIMT stack.

9. The method according to claim 8, characterized in that, The execution information includes instruction addresses and thread masks. Pushing the execution information of the top basic block into the first SIMT stack includes: Obtain the instruction address and thread mask of the top basic block; The instruction address of the top basic block is pushed into the PC register of the first SIMT stack, and the thread mask of the top basic block is pushed into the predicate register of the first SIMT stack.

10. The method according to any one of claims 1-5, characterized in that, The GPU is also configured with an RPC stack, and updating the stack state based on the base block to be executed includes: If the basic block to be executed is not the top basic block, the stack state is updated according to the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack.

11. The method according to claim 10, characterized in that, The step of updating the stack state based on the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack includes: If the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack both point to the same jump, and the jump address is the same as the head node of the RPC stack, then the first SIMT stack, the second SIMT stack and the RPC stack are popped simultaneously, and the jump address is pushed back onto the first SIMT stack.

12. The method according to claim 10, characterized in that, The step of updating the stack state based on the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack includes: If the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump, and the jump address is different from the head node of the RPC stack, the SIMT stack pointing to the unified jump is popped from the stack, and the jump address is pushed back onto the SIMT stack pointing to the unified jump.

13. The method according to claim 12, characterized in that, The method further includes: If the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a unified jump, and the jump address is the same as the head node of the RPC stack, then instruction fetching of the SIMT stack pointing to the unified jump is suspended until both the basic block end instruction in the PC register of the first SIMT stack and the basic block end instruction in the PC register of the second SIMT stack point to the unified jump.

14. The method according to claim 10, characterized in that, The step of updating the stack state based on the PC register of the first SIMT stack, the PC register of the second SIMT stack, and the head node of the RPC stack includes: If the basic block end instruction in the PC register of the first SIMT stack or the basic block end instruction in the PC register of the second SIMT stack points to a divergent jump, obtain the two branch basic blocks of the divergence. The execution information of the two branch basic blocks is pushed into the first SIMT stack and the second SIMT stack, respectively, and the direct common post-dominant node of the two branch basic blocks is pushed into the RPC stack.

15. A processor, characterized in that, The processor adopts a MIMD architecture and is configured with a first SIMT stack and a second SIMT stack; the first SIMT stack and the second SIMT stack are respectively used to manage the execution information of different branch basic blocks within the same thread bundle; The scheduling unit in the processor is used to, when both the first SIMT stack and the second SIMT stack are not empty, retrieve the instructions from each branch basic block according to the execution information of the first SIMT stack and the second SIMT stack, and transmit them to the MIMD for concurrent execution.

16. The processor according to claim 15, characterized in that, The processor is also configured with an RPC stack; the RPC stack is used for the direct common post-dominant node of different branch basic blocks.

17. The processor according to claim 15 or 16, characterized in that, Both the first SIMT stack and the second SIMT stack include a PC register and a predicate register. The PC register is used to store the instruction address of the basic block to be executed, and the predicate register is used to store the thread mask of the basic block to be executed.

18. The processor according to claim 15 or 16, characterized in that, The processor is also configured with a first instruction cache and a second instruction cache, wherein the first instruction cache is used to store instructions in the branch basic blocks managed by the first SIMT stack, and the second instruction cache is used to store instructions in the branch basic blocks managed by the second SIMT stack.

19. The processor according to claim 18, characterized in that, The processor further includes an instruction fetch unit, which is used to fetch corresponding instructions from the storage subsystem into the first instruction cache and the second instruction cache.

20. The processor according to claim 15 or 16, characterized in that, The MIMD is configured with a predicate mask, which includes three state values: a first state value, a second state value, and a third state value. The first state value indicates that the execution channel in the MIMD is closed, the second state value indicates that the execution channel in the MIMD is executing the instructions in the first branch basic block, and the third state value indicates that the execution channel in the MIMD is executing the instructions in the second branch basic block.

21. The processor according to claim 15 or 16, characterized in that, The processor is a general-purpose graphics processor.

22. An instruction execution device, characterized in that, The device includes: A stack state update module is used to update the stack state based on the basic block to be executed; the stack state includes at least one of a first SIMT stack and a second SIMT stack. The instruction execution module is used to, when both the updated first SIMT stack and the second SIMT stack are not empty, retrieve the instructions from each branch basic block according to the execution information of the first SIMT stack and the second SIMT stack, and transmit them to the MIMD for concurrent execution.

23. An instruction execution device, characterized in that, The instruction execution device includes a memory, a general-purpose graphics processor, and a computer program; the computer program is stored in the memory. The general-purpose graphics processor is used to run the computer program to perform the steps of the instruction execution method according to any one of claims 1 to 14.

24. A computing system, characterized in that, The computing system includes the instruction execution device as described in claim 23, a general interconnect interface, and other processing devices; the instruction execution device interacts with the other processing devices to jointly complete the computational operation specified by the user.

25. A readable storage medium, characterized in that, The readable storage medium stores a computer program, which, when executed by a processor, is used to implement the steps of the instruction execution method according to any one of claims 1 to 14.

26. A computer program product, characterized in that, When the computer program is executed by a processor, it implements the steps of the instruction execution method according to any one of claims 1 to 14.

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