Sampling delay control method based on adjustable trigger period and sampling system

Abstract

The invention relates to the technical field of electronic measurement, in particular to a sampling delay control method based on an adjustable trigger period and a sampling system, and aims to design a method capable of stably, accurately and flexibly controlling equivalent sampling delay. The method includes determining a linear work interval of the programmable delay line. In the linear working interval, the fixed voltage stepping amount of the digital-to-analog converter is set, so that the programmable delay line generates uniform basic delay stepping amount. The digital-to-analog converter is controlled to progressively increase the output voltage at a fixed time interval, the pulse generator is controlled to generate a trigger pulse, and the period of the trigger pulse is integer multiples of the fixed time interval. Sampling pulses are output through the programmable delay line, and the delay increment between the adjacent sampling pulses is an integral multiple of the basic delay stepping amount.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement technology, and in particular to a sampling delay control method and sampling system based on an adjustable trigger period. Background Technology

[0002] In the field of electronic measurement, especially for the measurement and analysis of high-frequency repetitive signals, sequential equivalent sampling technology is widely used in instruments such as sampling oscilloscopes. The core of this technology lies in generating a series of sampling pulses with precise and uniform delay steps to achieve high-precision reconstruction of the signal waveform. Traditional implementations typically use a digital-to-analog converter (DAC) to directly control the operating voltage of the programmable delay line: by adjusting the voltage step size of the DAC output, the delay step size of the delay line is controlled, thereby obtaining the desired sampling pulse sequence.

[0003] However, this traditional method suffers from two significant technical bottlenecks. First, the system's delay accuracy and resolution are directly limited by the DAC's performance parameters, such as its resolution and linearity. To achieve high-precision delay control, it is often necessary to use a high-performance, high-cost digital-to-analog converter (DAC). Second, when the traditional method changes the delay step by adjusting the DAC's output voltage step size, the core parameters of the DAC need to be reconfigured. In some scenarios, it may even require adjusting the hardware circuitry or calibration procedures, making the operation complex and time-consuming. It also makes it impossible to quickly switch between different delay levels according to actual measurement needs, resulting in poor system adaptability. Summary of the Invention

[0004] The purpose of this invention is to provide a sampling delay control method and sampling system based on an adjustable trigger period, aiming to design a method that can stably, accurately and flexibly control the equivalent sampling delay.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: This invention provides a sampling delay control method based on an adjustable trigger period, comprising: S1: determining the linear operating range of a programmable delay line; S2: within the linear operating range, setting a fixed voltage step of the digital-to-analog converter to generate a uniform base delay step of the programmable delay line; S3: controlling the digital-to-analog converter to increase the output voltage at fixed time intervals, and controlling a pulse generator to generate trigger pulses, the period of which is an integer multiple of the fixed time interval; S4: outputting sampling pulses through the programmable delay line, wherein the delay increment between adjacent sampling pulses is an integer multiple of the base delay step. In step S3, the period of the trigger pulse is configured by the digital control unit to be an integer multiple of a fixed time interval. The digital control unit can be any one of a programmable logic device, a microprocessor, or a digital signal processor.

[0006] The sampling delay control method based on adjustable trigger period also includes an extension step for the nonlinear operating region: measuring the actual delay of the programmable delay line at different voltage points and establishing a voltage-delay characteristic lookup table; adjusting the voltage step sequence of the digital-to-analog converter in the nonlinear region according to the lookup table to keep the step delay of the programmable delay line in the nonlinear region uniform.

[0007] The trigger pulse is strictly synchronized with the synchronization clock signal, which is derived from the signal being measured.

[0008] This invention also provides a sampling system for implementing the above-described equivalent sampling delay control method based on an adjustable trigger period. The equivalent sampling system includes: a digital control unit, a digital-to-analog converter module, a pulse generator, and a programmable delay line; wherein the digital control unit coordinates system timing; the digital-to-analog converter module generates a fixed voltage step sequence; the pulse generator generates a trigger pulse with an adjustable period; and the programmable delay line outputs sampling pulses with precise step delays.

[0009] The digital control unit connects to the digital-to-analog converter module and the pulse generator via a digital interface to achieve timing synchronization control.

[0010] The system also includes a sampler and an analog-to-digital converter. The sampler samples the input signal under the drive of the sampling pulse, and the analog-to-digital converter digitizes the sampled signal under the control of the synchronous acquisition signal.

[0011] The digital control unit is also used to generate a synchronous acquisition signal for the analog-to-digital converter. The synchronous acquisition signal is driven by a synchronous pulse signal fed back from the pulse generator to ensure strict synchronization between sampling and delay.

[0012] The digital control unit is also used to store and execute the pre-calibrated voltage-delay characteristic lookup table to support uniform step control of the programmable delay line in the nonlinear region.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention first locks the linear operating range of the programmable delay line and sets a fixed digital-to-analog converter voltage step within this range, thereby ensuring that the programmable delay line generates a uniform and stable base delay step. Then, the trigger pulse period is configured as an integer multiple by the digital control unit, and a defined proportional relationship is established between this period and the voltage update period of the digital-to-analog converter, thereby expanding the base delay step to the actual required system delay increment in integer multiples. This method essentially achieves flexible and precise adjustment of the equivalent sampling delay step while maintaining the original hardware operating point through a digital timing control strategy, significantly improving the flexibility and system repeatability of controlling the delay increment of adjacent sampling pulses.

[0014] 2. This invention allows for flexible adjustment of the sampling pulse delay increment by adjusting the integer multiple relationship between the trigger pulse period and the digital-to-analog converter step period in a purely digital manner, without the need to reconfigure the voltage step parameters of the digital-to-analog converter or modify the hardware circuit. The configuration operation of the digital control unit is intuitive and precise, and different delay increment modes can be quickly switched according to actual measurement needs, which greatly improves the system's adaptability and ease of operation.

[0015] 3. This invention coordinates the working timing of the digital-to-analog converter, pulse generator, programmable delay line, and analog-to-digital converter through a digital control unit, ensuring that the trigger pulse is strictly synchronized with the synchronous clock signal from the measured signal. At the same time, the synchronous acquisition signal of the analog-to-digital converter is driven by the synchronous pulse fed back by the pulse generator, realizing precise linkage between sampling action and delay control, reducing the impact of timing deviation and external interference on measurement, and improving the overall stability of the system and the reliability of sampling data. Attached Figure Description

[0016] Figure 1 This is a flowchart of a sampling delay control method based on an adjustable trigger period provided in an embodiment of this application; Figure 2 This is a timing diagram provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] This application provides a sampling delay control method based on an adjustable trigger period, for example, as shown in the embodiments below. Figure 1 As shown. The method includes: S1: Determine the linear operating range of the programmable delay line.

[0019] For example, the AD9500 programmable delay line was selected as the core delay device, with a voltage operating range of 0-5V. Experimental testing yielded its voltage-delay characteristic curve: within the 1V-3.5V voltage range, for every 0.1V change in voltage, the corresponding delay change fluctuated by no more than ±1ps, meeting the linearity criterion of "uniform delay output." Therefore, 1V-3.5V was determined as the linear operating range for this programmable delay line. However, within the 0-1V and 3.5V-5V ranges, the non-linear relationship between voltage and delay deviated by more than 5ps, thus classifying it as a non-linear operating region.

[0020] S2: Within the linear operating range, set the fixed voltage step of the digital-to-analog converter to produce a uniform base delay step for the programmable delay line.

[0021] For example, a fixed voltage step of the digital-to-analog converter (DAC) is set to ΔV, causing the programmable delay line to produce a uniform base delay step of ΔT_base.

[0022] More specifically, a 12-bit resolution digital-to-analog converter was selected, and its fixed voltage step was set to 0.1V within the aforementioned linear operating range (1V-3.5V). Through actual testing, this voltage step applied to the AD9500 programmable delay line produced a stable base delay step. After multiple measurements, the average value of this base delay step was 10ps, with a fluctuation range ≤ ±0.5ps, meeting the uniformity requirements.

[0023] S3: Controls the digital-to-analog converter to increase the output voltage at fixed time intervals, and controls the pulse generator to generate trigger pulses. The period of the trigger pulses is an integer multiple of the fixed time interval.

[0024] For example, the DAC is controlled to increase the output voltage by a fixed voltage step ΔV at fixed time intervals T_step, and the pulse generator is controlled to generate a trigger pulse, the period of which T_trigger is N times the fixed time interval T_step.

[0025] As one possible implementation, in step S3, the period T_trigger of the trigger pulse is configured by the digital control unit to be an integer multiple of a fixed time interval T_step. The digital control unit can be any one of a field-programmable logic device (FPGA), a microprocessor, or a digital signal processor. Field-programmable logic devices are suitable for high timing precision scenarios, microprocessors are suitable for low-cost miniaturized systems, and digital signal processors are suitable for complex algorithm processing scenarios, thus improving the system's compatibility and practicality.

[0026] For example, the digital control unit uses a Xilinx Artix-7 series field-programmable logic device and connects to the digital-to-analog converter and pulse generator via an SPI digital interface. The digital control unit outputs a control signal with a fixed time interval of 10μs, driving the digital-to-analog converter to increase the output voltage in fixed voltage steps of 0.1V. The digital-to-analog converter maintains a stable output voltage within each fixed time interval of 10μs, forming a standard stepped wave signal.

[0027] Meanwhile, the digital control unit configures the trigger pulse period of the pulse generator according to the measurement requirements: when the minimum delay step is required, the trigger pulse period is configured to 10μs (i.e., 1 time interval, N=1); when the delay increment is required, the trigger pulse period is configured to 20μs (i.e., 2 times the fixed time interval, N=2), and so on, with the trigger pulse period always remaining an integer multiple of the fixed time interval. Furthermore, the trigger pulse is strictly synchronized with the synchronization clock signal, which is obtained by frequency division of the measured high-frequency periodic signal to ensure the timing consistency between the trigger action and the measured signal.

[0028] S4: Outputs adjacent sampling pulses through a programmable delay line, where the delay increment between adjacent sampling pulses is an integer multiple of the base delay step.

[0029] For example, the delay increment between adjacent sampling pulses is ΔT_sys, which is N times the base delay step ΔT_base, that is, ΔT_sys = N × ΔT_base.

[0030] For example, the programmable delay line receives the stepped voltage signal from the digital-to-analog converter and the trigger pulse signal from the pulse generator, and outputs a sampling pulse based on the synergistic effect of the two. When N=1, the delay increment between adjacent sampling pulses is equal to the basic delay step of 10ps; when N=2, the delay increment between adjacent sampling pulses is twice the basic delay step, i.e., 20ps. This achieves the goal of flexibly controlling the delay increment by adjusting the integer multiple coefficient N, and in multiple cyclic tests, the repeatability error of the delay increment is ≤±0.3ps.

[0031] For example, the sampling delay control method based on adjustable trigger period also includes an extension step for the nonlinear operating region: measuring the actual delay of the programmable delay line at different voltage points and establishing a voltage-delay characteristic lookup table; adjusting the voltage step sequence of the digital-to-analog converter in the nonlinear region according to the lookup table so that the step delay of the programmable delay line in the nonlinear region remains uniform.

[0032] For example, when the measurement requirement exceeds the linear operating range (1V-3.5V), a nonlinear operating range extension process is initiated. This process is divided into a pre-calibration stage and an actual operating stage. In the pre-calibration stage, within the full voltage range (0-5V) of the programmable delay line, the actual delay corresponding to each voltage point is measured at 0.05V intervals. For example, 0.5V corresponds to a delay of 8ps, 3.8V corresponds to a delay of 36ps, and 4.5V corresponds to a delay of 48ps, etc. A total of 100 sets of voltage-delay data are obtained, and a voltage-delay characteristic lookup table is established. This lookup table is stored in the non-volatile memory of the digital control unit.

[0033] In practical operation, when a uniform 10ps delay increment needs to be output in the nonlinear region (e.g., 3.6V-4.0V), the digital control unit calls the voltage-delay characteristic lookup table to obtain the voltage step sequence required to achieve the 10ps delay increment: 3.6V corresponds to a delay of 32ps, 3.67V corresponds to a delay of 42ps, 3.75V corresponds to a delay of 52ps, etc. The voltage output of the digital-to-analog converter is dynamically adjusted so that the programmable delay line can still output a uniform 10ps step delay in the nonlinear region, with a uniformity error ≤ ±0.8ps, which meets the requirements of precision measurement.

[0034] As one possible implementation, the trigger pulse is strictly synchronized with the synchronization clock signal, which originates from the signal under test. The signal under test refers to the target signal that the user needs to measure and analyze. The signal under test is both the measurement target and the source of the system's synchronization reference. The design principle of synchronization from the same source helps improve sampling accuracy and avoid timing deviations.

[0035] As one possible implementation, the output voltage of the digital-to-analog converter (DAC) remains stable within each step cycle, forming a stepped wave signal. Maintaining a stable output voltage within each fixed time interval, forming a standard stepped wave signal, avoids delay jitter caused by voltage fluctuations and further improves the stability of delay control.

[0036] This application also provides a sampling system for implementing the above-described sampling delay control method based on an adjustable trigger period. The sampling system includes: a digital control unit, a digital-to-analog converter module, a pulse generator, and a programmable delay line. The digital control unit coordinates system timing; the digital-to-analog converter module generates a fixed voltage step sequence; the pulse generator generates a periodically adjustable trigger pulse; and the programmable delay line outputs sampling pulses with precise step delays.

[0037] In some embodiments, the digital control unit is connected to the digital-to-analog converter module and the pulse generator via a digital interface to achieve timing synchronization control.

[0038] In some embodiments, the sampling system further includes a sampler and an analog-to-digital converter, wherein the sampler samples the input signal under the drive of a sampling pulse, and the analog-to-digital converter digitizes the sampled signal under the control of a synchronous acquisition signal.

[0039] As one possible implementation, the digital control unit is also used to generate a synchronous acquisition signal for the analog-to-digital converter. The synchronous acquisition signal is driven by a synchronous pulse signal fed back from the pulse generator, ensuring strict synchronization between sampling and delay.

[0040] The digital control unit (DCU) sends voltage step control signals to the analog-to-digital converter (ADC) module and trigger period configuration signals to the pulse generator via a digital interface, coordinating their timing synchronization. The ADC module outputs a stepped voltage signal to the programmable delay line (PDL), and the pulse generator outputs a periodically adjustable trigger pulse to the PDL. Based on the voltage signal and the trigger pulse, the PDL outputs a sampling pulse with precise step delay, driving the sampler to sample the input high-frequency measured signal. The DCU generates a synchronization acquisition signal for the ADC, driven by a synchronization pulse signal fed back from the pulse generator, ensuring strict synchronization between the ADC's acquisition action and the sampler's sampling action. Under the control of the synchronization acquisition signal, the ADC digitizes the sampled signal and outputs digital sampled data, completing the entire sampling process.

[0041] For example, the equivalent sampling system also includes a synchronization clock, which provides a system timing reference and provides a synchronization signal for the pulses.

[0042] Reference Figure 2 The implementation method of this application is based on the linear operating region of the programmable delay line. First, the linear operating region of the programmable delay line is determined by testing, and a fixed voltage step ΔV is selected within the linear operating region. The base delay step ΔT_base corresponding to this voltage step is the base delay accuracy of the equivalent sampling system.

[0043] Figure 2 The timing diagram for the sampling system based on an adjustable trigger period visually illustrates the timing coordination relationship between the digital-to-analog converter (DAC) output signal, the synchronization pulse signal, and the delay pulses (sampling pulses) corresponding to different integer multiples N: The DAC output signal is a standard stepped wave, maintaining voltage stability within a preset fixed time interval, and then increasing sequentially by a fixed voltage step; the synchronization pulse signal is strictly synchronized with the synchronization clock signal derived from the measured signal, providing a system timing reference, and its period is always an integer multiple of the DAC's fixed time interval; regarding the delay pulses, when the integer multiple N=1, the trigger period of the delay pulse is consistent with the DAC's fixed time interval, and the delay increment of adjacent pulses is equal to the basic delay step; when N=2 and N=3, the trigger periods of the delay pulses are 2 times and 3 times the DAC's fixed time interval, respectively, and the corresponding delay increments of adjacent pulses are also synchronously 2 times and 3 times the basic delay step.

[0044] The digital control unit controls the DAC to output a stepped wave voltage at a fixed time interval T_step, and at the same time generates a trigger pulse with a period of T_trigger to the pulse generator. By setting T_trigger=N×T_step, the equivalent sampling system can achieve different equivalent delay step amounts ΔT_sys=N×ΔT_base.

[0045] For example, when the minimum delay step is required, N=1 is set, and the equivalent sampling system operates with a base delay step of ΔT_base. When a larger delay step is required, N=2 is set, and the equivalent delay step of the equivalent sampling system is 2×ΔT_base. If an even larger delay step is needed, the value of N can be changed. Unlike traditional methods that directly adjust the delay step by changing the analog voltage (ΔV), this embodiment fixes the analog operating point and instead uses digital timing control (adjusting N) to synthesize the required equivalent step. This method shifts the control core from the analog domain to the digital domain, thereby achieving higher repeatability, stability, and anti-interference capability.

[0046] As one possible implementation, the digital control unit is also used to store and execute a pre-calibrated voltage-delay characteristic lookup table to support uniform step control of the programmable delay line in the nonlinear region.

[0047] When practical applications require operation beyond the linear operating range, the sampling system can employ a pre-calibration scheme. Within the full voltage range, the voltage-delay characteristics of the delay line are measured at small voltage intervals; a voltage-delay characteristic lookup table is established and stored in non-volatile memory; during actual operation, the precise voltage step size is obtained by looking up the table based on the required delay step size; and the voltage increment of the DAC in the nonlinear region of the programmable delay line is adjusted according to the lookup table results, ensuring that the step delay of the programmable delay line in the nonlinear region is the same as that in the linear region.

[0048] The word control unit stores and executes the voltage-delay characteristic lookup table obtained from pre-calibration, which extends the working range of the programmable delay line from the linear region to the full voltage range. It can meet a wider range of delay requirements without replacing the high-precision delay line, reducing the hardware cost and upgrade difficulty of the system.

[0049] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0050] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A sampling delay control method based on an adjustable trigger period, including: S1: Determine the linear operating range of the programmable delay line; S2: Within the linear operating range, a fixed voltage step size is set for the digital-to-analog converter (DAC) to generate a uniform base delay step size for the programmable delay line; S3: The DAC is controlled to increase its output voltage at fixed time intervals, and a pulse generator is controlled to generate a trigger pulse, the period of which is an integer multiple of the fixed time interval; S4: A sampling pulse is output through the programmable delay line, the delay increment between adjacent sampling pulses being an integer multiple of the base delay step size.

2. The sampling delay control method based on an adjustable trigger period according to claim 1, characterized in that, In step S3, the period of the trigger pulse is configured by the digital control unit to be an integer multiple of the fixed time interval, and the digital control unit is any one of a programmable logic device, a microprocessor, or a digital signal processor.

3. The sampling delay control method based on an adjustable trigger period according to claim 1, characterized in that, It also includes an extension step for the nonlinear operating region: measuring the actual delay of the programmable delay line at different voltage points and establishing a voltage-delay characteristic lookup table; adjusting the voltage step sequence of the digital-to-analog converter in the nonlinear region according to the lookup table, so that the step delay of the programmable delay line in the nonlinear region remains uniform.

4. The sampling delay control method based on an adjustable trigger period according to claim 1, characterized in that, The trigger pulse is strictly synchronized with the synchronization clock signal, which is derived from the signal being measured.

5. The sampling delay control method based on an adjustable trigger period according to claim 1, characterized in that, The voltage output by the digital-to-analog converter remains stable within each fixed time interval, forming a stepped wave signal.

6. An equivalent sampling system for implementing the sampling delay control method based on an adjustable trigger period as described in any one of claims 1 to 5, characterized in that, include: The system includes a digital control unit, a digital-to-analog converter module, a pulse generator, and a programmable delay line; the digital control unit is used to coordinate the system timing. The digital-to-analog converter module is used to generate a fixed voltage step sequence; the pulse generator is used to generate a periodically adjustable trigger pulse; and the programmable delay line is used to output a sampled pulse with a precise step delay.

7. A sampling system according to claim 6, characterized in that, The digital control unit is connected to the digital-to-analog converter module and the pulse generator through a digital interface to achieve timing synchronization control.

8. A sampling system according to claim 6, characterized in that, The system also includes a sampler and an analog-to-digital converter. The sampler samples the input signal under the drive of the sampling pulse, and the analog-to-digital converter digitizes the sampled signal under the control of the synchronous acquisition signal.

9. A sampling system according to claim 8, characterized in that, The digital control unit is also used to generate a synchronous acquisition signal for the analog-to-digital converter. The synchronous acquisition signal is driven by a synchronous pulse signal fed back by the pulse generator to ensure strict synchronization between sampling and delay.

10. A sampling system according to claim 6, characterized in that, The digital control unit is also used to store and execute the pre-calibrated voltage-delay characteristic lookup table to support uniform step control of the programmable delay line in the nonlinear region.

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