Adaptive anti-interference synchronization method for spread spectrum communication system based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a self-adaptive anti-interference synchronization method for a spread spectrum communication system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: inputting a zero intermediate frequency signal containing a signal, interference and noise into the FPGA; converting the zero intermediate frequency signal from a time domain signal to a frequency domain signal; identifying an interference frequency point by comparing a real-time calculated dynamic interference threshold value with an actually received frequency domain signal; removing the influence of the interference signal and then converting back to the time domain; frequency slots are divided, and the time domain signals are subjected to synchronous frequency conversion to the corresponding frequency slots; performing matched filtering on the signal in each frequency slot; and repeatedly calling the summator by using the signal updating gap in the sliding correlation process of the local synchronization code and the filtered signal of each frequency slot to complete the synchronization process. According to the method, the interference signals can be quickly and accurately identified and eliminated, the anti-interference capability of the spread spectrum communication system in a complex interference environment is remarkably improved, the bit error rate is reduced, and the communication quality is improved.

Description

Technical Field

[0001] This invention relates to the field of spread spectrum communication technology, and in particular to a frequency domain adaptive interference zeroing and parallel synchronization combination implementation technology for spread spectrum communication systems based on field programmable gate arrays (FPGAs). Background Technology

[0002] With the rapid development of communication technology, spread spectrum communication has been widely used in many fields such as military communication, satellite communication, and mobile communication. However, the actual communication environment is complex and variable, with various interference signals that seriously affect the performance of spread spectrum communication systems. Traditional interference suppression methods often suffer from poor adaptability and slow processing speed, making it difficult to meet the requirements of high-speed and reliable communication. Meanwhile, the synchronization process, as a key link in spread spectrum communication, plays a crucial role in the operation of the entire system due to its accuracy and efficiency. Common synchronization techniques require complex processing algorithms to address the Doppler frequency offset caused by high-speed, high-dynamic-range communication environments; otherwise, synchronization accuracy is easily affected, and the computational complexity of the implementation process is high. When the synchronization code is long, it requires a large amount of DSP or LUT resources, which restricts the further practical application of spread spectrum communication systems. Therefore, a simple and efficient technical solution is urgently needed to solve these problems. Summary of the Invention

[0003] The purpose of this invention is to provide an adaptive anti-interference synchronization method for spread spectrum communication systems based on FPGA, so as to improve the performance of spread spectrum communication systems in complex interference environments, monitor the received signals in real time, realize fast and accurate interference detection, and ensure the reliability of communication; at the same time, by utilizing time slot multiplexing and parallel synchronization technology, the utilization rate of DSP or LUT resources in FPGA is reduced, ensuring the high efficiency of communication implementation and expanding the scope of engineering applications.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] An adaptive anti-interference synchronization method for an FPGA-based spread spectrum communication system includes the following steps:

[0006] Step 1: Input the zero-IF signal containing useful signals, interference, and noise into the FPGA;

[0007] Step 2: Convert the zero intermediate frequency signal from a time domain signal to a frequency domain signal;

[0008] Step 3: Identify the interference frequency by comparing the real-time calculated dynamic interference threshold with the actual received frequency domain signal;

[0009] Step 4: Once the interference frequency is determined, remove the influence of the interference signal and convert back to the time domain;

[0010] Step 5: Divide the frequency slots and synchronously convert the time-domain signal to the corresponding frequency slots;

[0011] Step 6: Perform matched filtering on the signals in each frequency slot;

[0012] Step 7: During the sliding correlation process between the local synchronization code and the filtered signals of each frequency slot, the summer is repeatedly called during the signal update interval to complete the synchronization process.

[0013] Preferably, in step one, the zero intermediate frequency signal is obtained by receiving electromagnetic waves containing useful signals, interference, and noise from the antenna and converting them into electrical signals. These signals are then converted into intermediate frequency band communication channels by low-noise amplifier, filter, and frequency conversion. Finally, the digital zero intermediate frequency signal is obtained by AD sampling and input into the FPGA for processing.

[0014] Preferably, in step two, the fast Fourier transform module inside the FPGA is used to perform fast spectrum analysis on the zero intermediate frequency signal, converting the time domain signal into a frequency domain signal.

[0015] Preferably, in step three, the square of the amplitude of the output data from step two is calculated, and the mean of a segment of data is calculated. Finally, five times the mean is used as the dynamic interference threshold to determine the interference frequency.

[0016] Preferably, in step four, the frequency domain data exceeding the interference threshold is zeroed out to eliminate the influence of interference signals;

[0017] After anti-interference processing, the frequency domain data is converted back to the time domain using inverse fast Fourier transform.

[0018] Preferably, in step five, the frequency slot width is divided according to the maximum Doppler frequency and the maximum synchronous frequency difference tolerance value.

[0019] The beneficial effects of this invention are as follows:

[0020] (1) The frequency domain adaptive interference nulling technology applied in this invention can quickly and accurately identify and eliminate interference signals, significantly improve the anti-interference capability of spread spectrum communication systems in complex interference environments, reduce the bit error rate, and improve communication quality.

[0021] (2) Parallel synchronization technology leverages the parallel processing advantages of FPGA to greatly shorten the synchronization time and improve the synchronization accuracy, ensuring that the spread spectrum communication system can quickly and stably establish a communication connection, which is especially suitable for high-speed and burst communication scenarios.

[0022] (3) Time slot multiplexing technology can make full use of FPGA resources, reduce the requirements for hardware selection, and reduce the investment in hardware equipment.

[0023] (4) The overall implementation scheme based on FPGA has high flexibility and reconfigurability, which facilitates customized development according to different application scenarios and user needs, reduces system development and maintenance costs, and has broad market application prospects. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall structure of an adaptive anti-interference synchronization method for a spread spectrum communication system based on FPGA.

[0025] Figure 2 This is a flowchart of the adaptive interference detection algorithm.

[0026] Figure 3 To obtain the pipeline hierarchy diagram for time slot multiplexing. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0028] like Figure 1 As shown in this embodiment, an adaptive anti-interference synchronization method for a spread spectrum communication system based on FPGA includes the following steps:

[0029] Step 1: Input the zero-IF signal containing useful signals, interference, and noise into the FPGA.

[0030] The antenna receives electromagnetic waves containing useful signals, interference, and noise, converts them into electrical signals, and then converts them into intermediate frequency (IF) communication channels through modules such as low-noise amplifier, filter, and frequency conversion. The resulting digital zero-IF signal is then sampled by an analog-to-digital converter (ADC) and input into the FPGA for processing. At this point, the useful signal, interference, noise, and their sum (i.e., the total input signal) are represented as x(n), j(n), n(n), and y(n), respectively.

[0031] Step 2: Convert the zero intermediate frequency signal from a time domain signal to a frequency domain signal.

[0032] The high-speed Fast Fourier Transform (FFT) module inside the FPGA is used to perform fast spectrum analysis on the zero intermediate frequency signal, converting the time-domain signal into a frequency-domain signal. Assume x(n), j(n), and n(n) correspond to X(k), J(k), and N(k), respectively.

[0033] Step 3: Apply an adaptive interference detection algorithm to quickly and accurately identify interference frequencies by comparing the dynamically calculated interference threshold with the actual received frequency domain signal.

[0034] In a spread-spectrum communication system, after the signal is spread-spectrum processed and transmitted, it can be considered that the sampled x(n) conforms to a random variable with a Gaussian distribution. At the same time, the noise n(n) in the channel can also be regarded as a random variable with a Gaussian distribution. Then, when the interference j(n) does not exist, the total signal y(n) = x(n) + n(n) is also a random variable with a Gaussian distribution. After the signal is transformed to the frequency domain through Step 2, its statistical properties remain unchanged. Let y(n) correspond to Y(k), and there is the magnitude square |Y(k)| 2 conforms to an exponential distribution. Correspondingly, let the parameter of its exponential distribution function be μ, and there is a relationship in engineering implementation

[0035]

[0036] where N is the number of summation times. When the interference j(n) exists, the relationship no longer holds, but interference determination can be performed based on this. Since the power at the interference signal frequency point is much larger than that at the useful signal, let m be a real coefficient and the interference threshold be TH, then there is a relational expression that satisfies

[0037]

[0038] when there is interference in y(n). Then, when m = 5, there is |Y(k)| 2 < TH with a probability of 0.993, which is close to 0.997 and approximately satisfies the 3σ principle. Therefore, the magnitude square of the output data of Step 2 can be calculated, and the mean value of a segment of data can be obtained. Finally, 5 times the mean value is used as the dynamic threshold to determine the interference frequency points. The algorithm flow chart is as Figure 2 shown.

[0039] Step 4: Once the interference frequency points are determined, after removing the influence of the interference signal, it is converted back to the time domain.

[0040] The frequency domain data Y(k) that exceeds the interference threshold is set to zero to eliminate the influence of the interference signal as much as possible, improve the signal-to-interference ratio of the signal, and enable the subsequent synchronization module to more accurately identify the original signal from the received mixed signal.

[0041] The frequency domain data after anti-interference processing is processed by the inverse fast Fourier transform (IFFT) and then converted back to the time domain.

[0042] Step 5: Divide the frequency slots and synchronously frequency-convert the signal into the corresponding frequency slots.

[0043] According to the maximum Doppler frequency and the synchronization maximum frequency difference tolerance value, the width of the frequency slots is divided, and the parallel processing characteristics of the FPGA are utilized to synchronously frequency-convert the signal into the corresponding frequency slots. The finer the frequency slot division, the smaller the frequency difference within each slot, and the better the synchronization performance. At the same time, there is no need to sequentially scan the entire Doppler frequency range, reducing the influence of frequency offset and significantly improving the synchronization rate and success rate.

[0044] Step 6: Perform matched filtering on the signals in each frequency slot.

[0045] Matched filtering of data in each frequency slot can reduce inter-symbol interference and improve the signal-to-noise ratio.

[0046] Step 7: Apply summation time slot multiplexing technology. By leveraging the characteristic that the FPGA system clock is faster than the signal rate, during the sliding correlation process between the local synchronization code and the filtered signals of each frequency slot, the summer is repeatedly called during the signal update interval. This reduces resource usage without affecting the calculation results and completes the synchronization process.

[0047] In FPGAs, local synchronization codes are typically used as equivalent FIR filter coefficients to implement sliding correlation. When the synchronization code is long, it consumes a significant amount of valuable DSP resources, leading to resource constraints on the chip. If a non-multiplexed pipelined summation implementation is used, and the synchronization code length is 2... N The required number of devices is 2. N-1 Furthermore, this will utilize more cache registers, increasing the use of on-chip LUT resources. Since the FPGA processor system time is typically several to tens of times the code rate, the same summer can be reused after each signal refresh to reduce LUT resource usage. Assume the FPGA system clock is 2 times the effective data clock. k = M, where k is a positive integer. Then, the total number of summers required after applying the summation time slot multiplexing is...

[0048]

[0049] As M increases, time slot multiplexing saves more summer resources. The pipeline hierarchy diagram for summation time slot multiplexing is shown below. Figure 3 As shown.

[0050] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. An adaptive anti-interference synchronization method for a spread spectrum communication system based on FPGA, characterized in that... Includes the following steps: Step 1: Input the zero-IF signal containing useful signals, interference, and noise into the FPGA; Step 2: Convert the zero intermediate frequency signal from a time domain signal to a frequency domain signal; Step 3: Identify the interference frequency by comparing the real-time calculated dynamic interference threshold with the actual received frequency domain signal; Step 4: Once the interference frequency is determined, remove the influence of the interference signal and convert back to the time domain; Step 5: Divide the frequency slots and synchronously convert the time-domain signal to the corresponding frequency slots; Step 6: Perform matched filtering on the signals in each frequency slot; Step 7: During the sliding correlation between the local synchronization code and the filtered signals of each frequency slot, the summer is repeatedly called during the signal update interval to complete the synchronization process.

2. The adaptive anti-interference synchronization method for a spread spectrum communication system based on FPGA according to claim 1, characterized in that: In step one, the zero-IF signal is obtained by receiving electromagnetic waves containing useful signals, interference, and noise from the antenna and converting them into electrical signals. These signals are then converted into intermediate frequency band communication channels by low-noise amplifiers, filters, and frequency converters. Finally, the digital zero-IF signal is obtained by AD sampling and input into the FPGA for processing.

3. The adaptive anti-interference synchronization method for an FPGA-based spread spectrum communication system according to claim 1, characterized in that... In step two, the fast Fourier transform module inside the FPGA is used to perform fast spectrum analysis on the zero intermediate frequency signal, converting the time domain signal into a frequency domain signal.

4. The adaptive anti-interference synchronization method for an FPGA-based spread spectrum communication system according to claim 1, characterized in that... In step three, the square of the amplitude of the output data from step two is calculated, and the mean of a segment of data is calculated. Finally, five times the mean is used as the dynamic interference threshold to determine the interference frequency.

5. The adaptive anti-interference synchronization method for an FPGA-based spread spectrum communication system according to claim 1, characterized in that... In step four, frequency domain data exceeding the interference threshold are zeroed out to eliminate the influence of interference signals. After anti-interference processing, the frequency domain data is converted back to the time domain using inverse fast Fourier transform.

6. The adaptive anti-interference synchronization method for an FPGA-based spread spectrum communication system according to claim 1, characterized in that... In step five, the frequency slot width is divided according to the maximum Doppler frequency and the maximum synchronous frequency difference tolerance value.

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