Data transmission method and device between devices, storage medium and electronic device

Abstract

The invention discloses a data transmission method and device between devices, a storage medium and an electronic device. The method comprises the following steps: polling whether to-be-sent target data exists locally or not; in response to target data existing locally, a first signal is sent to the slave device based on the serial peripheral interface, and the first signal is used for notifying the slave device that the master device is about to perform data transmission; and in response to receiving a second signal generated by the slave device according to the first signal, transmitting the target data to the slave device based on the serial peripheral interface, the second signal being used for notifying the master device to perform data transmission. According to the invention, the technical problem of low accuracy of data transmission between devices in the prior art is solved.

Description

Technical Field

[0001] This invention relates to the field of vehicle chips, and more specifically, to a method, apparatus, storage medium, and electronic device for data transmission between devices. Background Technology

[0002] The rapid development of the automotive industry has placed higher demands on vehicle intelligence. To achieve intelligence in in-vehicle products, factors such as cost and ease of function implementation need to be considered comprehensively. Multi-chip solutions are generally adopted, as they not only improve vehicle processing performance but also play a crucial role in vehicle redundancy control, leading to their increasingly widespread application in areas such as intelligent driving. However, efficient, reliable, and stable communication between multiple chips has become a major challenge in multi-chip solutions. Currently, chips communicate with each other via Ethernet, but this method is costly and difficult to widely adopt. Other widely used communication methods, on the other hand, suffer from lower data transmission accuracy.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This invention provides a method, apparatus, storage medium, and electronic device for data transmission between devices, to at least solve the technical problem of low accuracy in data transmission between devices in related technologies.

[0005] According to one aspect of the present invention, a method for data transmission between devices is provided, comprising: polling whether target data to be sent exists locally; in response to the existence of target data locally, moving the target data to a transmission sequence and sending a first signal to a slave device based on a serial peripheral interface, wherein the first signal is used to notify the slave device that the master device is ready to transmit data; in response to receiving a second signal generated by the slave device based on the first signal, transmitting the target data to the slave device based on the serial peripheral interface, wherein the second signal is used to notify the master device to transmit data.

[0006] Optionally, moving the target data to the sequence to be sent and sending a first signal to the slave device based on the serial peripheral interface includes: moving the target data to the sequence to be sent and sending a first signal to the first input interface of the slave device based on the first output interface of the master device in the serial peripheral interface, wherein different output interfaces in the serial peripheral interface are used to characterize different data transmission paths between the master device and the slave device.

[0007] Optionally, transmitting the target data to the slave device based on the serial peripheral interface includes: transmitting the target data in the sequence to be transmitted to the first receiving interface of the slave device based on the first transmitting interface of the master device in the serial peripheral interface.

[0008] Optionally, polling the master device for the existence of target data to be sent includes: polling the local circular buffer for the existence of target data to be sent, wherein the circular buffer is used to buffer the received data in a first-in-first-out queue manner.

[0009] Optionally, the method further includes: in response to the master device receiving multiple data frames, determining the current queue state of the circular buffer; in response to the current queue state indicating whether the circular buffer is empty or not empty, filling the circular buffer with multiple data frames, wherein not empty indicates that the circular buffer stores data and has remaining capacity; in response to the current queue state indicating that the circular buffer is full, moving preset data to the sequence to be sent based on the target address of the sequence to be sent, and filling the circular buffer with multiple data frames.

[0010] Optionally, filling multiple data frames into a circular buffer includes: storing multiple data frames in a read-only memory; and using direct memory access hardware to move a preset number of bytes of data from the read-only memory to the circular buffer based on a preset number of moves.

[0011] Optionally, determining the current queue state of the circular buffer includes: detecting a flag bit of the circular buffer; determining the current queue state to indicate that the circular buffer is empty in response to the flag bit being a first value; determining the current queue state to indicate that the circular buffer is full in response to the flag bit being a second value; and determining the current queue state to indicate that the circular buffer is not empty in response to the flag bit not being the first value and the flag bit not being the second value.

[0012] Optionally, determining the current queue state of the circular buffer includes: determining the current queue state to indicate that the circular buffer is empty in response to the head data and tail data being the same; determining the current queue state to indicate that the circular buffer is full in response to the sum of the tail data and the third value being the same as the head data; and determining the current queue state to indicate that the circular buffer is not empty in response to the head data and tail data being different and the sum being different from the head data.

[0013] According to one aspect of the present invention, a data transmission method between devices is provided, comprising: in response to receiving a first signal sent by a master device, generating a second signal based on the first signal, and sending the second signal to the master device based on a serial peripheral interface, wherein the first signal is used to notify a slave device that the master device is about to perform data transmission, and the second signal is used to notify the master device to perform data transmission; in response to receiving target data sent by the master device according to the second signal, and receiving an interrupt signal sent by the master device, sending the target data to a target application layer, wherein the interrupt signal is used to indicate that the master device has completed data transmission.

[0014] Optionally, sending the target data to the target application layer includes: assembling the target data into multiple data packets; classifying the multiple data packets based on the preset identification information of the target application layer to obtain classification results, wherein the classification results are used to represent the correspondence between the multiple data packets and the target application layer; and sending the multiple data packets to the target application layer corresponding to the multiple data packets based on the classification results.

[0015] Optionally, sending the second signal to the master device includes: sending the second signal to the second input interface of the master device based on the second output interface of the slave device in the serial peripheral interface.

[0016] According to one aspect of the present invention, a data transmission apparatus between devices is provided, comprising: a polling module for polling whether a master device has target data to be transmitted; a moving module for moving the target data to a transmission sequence in response to the presence of target data on the master device, and sending a first signal to a slave device based on a serial peripheral interface, wherein the first signal is used to notify the slave device that the master device is ready to transmit data; and a transmission module for transmitting the target data to the slave device based on the serial peripheral interface in response to receiving a second signal generated by the slave device according to the first signal, wherein the second signal is used to notify the master device to transmit data.

[0017] According to one aspect of the present invention, a data transmission apparatus between devices is provided, comprising: a generation module, configured to generate a second signal based on the first signal in response to receiving a first signal sent by a master device, and to send the second signal to the master device via a serial peripheral interface, wherein the first signal is used to notify the slave device that data transmission is about to occur, and the second signal is used to notify the master device to perform data transmission; and a sending module, configured to send the target data to a target application layer in response to receiving target data sent by the master device according to the second signal and receiving an interrupt signal sent by the master device, wherein the interrupt signal is used to indicate that the master device has completed data transmission.

[0018] According to one aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the execution of any of the above embodiments of the inter-device data transmission method in the processor of the device where it is located.

[0019] According to one aspect of the present invention, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs; and, when the one or more programs are executed by the one or more processors, causing the one or more processors to perform any of the above embodiments of the inter-device data transmission method.

[0020] In this embodiment of the invention, the master device is polled to determine if target data to be sent exists. In response to the presence of target data, the target data is moved to the transmission sequence, and a first signal is sent to the slave device via a serial peripheral interface. This first signal notifies the slave device that the master device is ready to transmit data. Upon receiving a second signal generated by the slave device based on the first signal, the target data is transmitted to the slave device via the serial peripheral interface. This second signal notifies the master device to transmit data, thereby improving the accuracy of data transmission between devices. It is noteworthy that by sending a first signal to the slave device via the serial peripheral interface when target data to be sent exists on the master device, the slave device can be notified that the master device is ready to transmit data, allowing it to prepare for receiving data in advance. The slave device can then send a second signal back to the master device after receiving the first signal to notify it that data transmission is possible. This pre-communication between the master and slave devices before data transmission avoids omissions during transmission, thus improving the accuracy of data transmission and solving the technical problem of low accuracy in data transmission between devices in related technologies. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0022] Figure 1 This is a flowchart of a data transmission method between devices according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of a master-slave device hardware structure according to an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of a data transmission process according to an embodiment of this application;

[0025] Figure 4 This is a schematic diagram of a data receiving process according to an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of a data transmission waveform according to an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of a circular buffer according to an embodiment of this application;

[0028] Figure 7 This is a timeline of periodic message transmission according to an embodiment of this application;

[0029] Figure 8This is a schematic diagram of direct memory access data transmission according to an embodiment of this application;

[0030] Figure 9 This is a schematic diagram of direct memory access data reception according to an embodiment of this application;

[0031] Figure 10 This is a flowchart of a data transmission method between devices according to an embodiment of the present invention;

[0032] Figure 11 This is a schematic diagram of a data transmission device between devices according to Embodiment 3 of this application;

[0033] Figure 12 This is a schematic diagram of a data transmission device between devices according to Embodiment 4 of this application. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Example 1

[0037] According to an embodiment of the present invention, a method for data transmission between devices is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0038] Figure 1This is a flowchart of a data transmission method between devices according to an embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0039] Step S102: Poll the local machine to see if there is target data to be sent.

[0040] The aforementioned local location can be the local location of the master device, which can be the microcontroller unit (MCU) in the vehicle. The aforementioned target data can be the data to be transmitted in the vehicle, such as vehicle driving data or control data sent to the vehicle by the owner.

[0041] In one alternative embodiment, the presence of target data to be sent on the master device can be determined by periodic polling. If the data exists, the data transmission process can be executed.

[0042] In another alternative embodiment, the target data described above can be stored in the buffer area of ​​the main device, and the presence of target data to be sent on the main device can be determined by polling the buffer area of ​​the main device.

[0043] In step S104, in response to the presence of target data locally, a first signal is sent to the slave device via the serial peripheral interface.

[0044] The first signal is used to notify the slave device that the master device is ready to transmit data.

[0045] The slave device in the above embodiments of this application can be a system-on-a-chip (SOC) in a vehicle. In this embodiment, the first signal mentioned above can be an indication signal for data transfer initiation from the master device (IND).

[0046] In one alternative, the external master device can send a first signal to the slave device to inform the slave device that the master device is ready to send data, thus ensuring that the slave device is ready to receive data and avoiding data loss during data transmission, thereby improving the accuracy of data transmission.

[0047] It should be noted that this application uses Serial Peripheral Interface (SPI) communication for cost reduction. To ensure data accuracy and efficiency, the SPI protocol stack needs to be redesigned. In SPI communication, the chip connects the master device's output and the slave device's input, the slave device's output and the master device's input, a chip select signal, and a clock signal. The on-chip system is a non-real-time system, so its response speed to instructions is uncertain. The microcontroller, on the other hand, is a real-time system, and its response speed is guaranteed.

[0048] Step S106: In response to receiving the second signal generated by the slave device based on the first signal, the target data is transmitted to the slave device via the serial peripheral interface.

[0049] The second signal is used to notify the master device to transmit data.

[0050] In one optional embodiment, the second signal can be a Readysignal from the slave device's buffer (RDY). This application can send the second signal to the master device to inform it that the slave device is ready to receive data. At this point, the master device can begin data transmission, preventing data loss and improving the accuracy of data transmission.

[0051] The following is combined Figure 2 The embodiments of this application will be described in detail below. Figure 2This is a schematic diagram of a master-slave device hardware structure according to an embodiment of this application. The master end is a microcontroller, i.e., the aforementioned master device, which includes a chip select not signal (CSN), a clock signal (CLK), a master output / slave input (MOSI), a master input / slave output (MISO), input / output pin 0 (GPIO0), and input / output pin 1 (GPIO1). The slave end is a system-on-a-chip, i.e., the aforementioned slave device, which includes a chip select signal, a clock signal, a master output / slave input, a master input / slave output, a slave device buffer ready signal (RDY), and an indication signal for data transfer initiation from the master device (IND).

[0052] In normal SPI communication, the connection between the two chips includes the master device's output, the slave device's input, the slave device's output, the master device's input, a chip select signal, and a clock signal. The SoC (System-on-a-Chip) is a non-real-time system with an uncertain response speed, while the MCU (Microcontroller Unit) is a real-time system with a guaranteed response speed. Traditional SPI protocols struggle to guarantee completely lossless data reception under heavy loads. Therefore, two GPIO ports, GPIO0 and GPIO1 (mentioned above), can be added to the SPI protocol between the SoC and MCU to receive the RDY and IND signals respectively. Figure 2 As shown, the RDY signal is the SOC informing the MCU that its SPI reception is ready. At this time, the MCU sending SPI will not cause the SOC to lose frames. The IND signal is the MCU informing the SOC that its SPI is ready to send. This can greatly improve the efficiency of information transmission between chips, reduce transmission errors, and save costs.

[0053] The aforementioned GPIO0 and GPIO1 are designated to enhance the performance and reliability of the SPI communication protocol. GPIO0 generates the RDY signal, which notifies the data receiver (slave device) that it is ready to receive data. When the SOC buffer is ready to receive new data, it sets the RDY signal high, notifying the data sender (master device) that SPI data transmission can begin. This mechanism ensures that the slave device's receive buffer is idle at the start of data transmission, thus avoiding frame loss during data transmission and guaranteeing the accuracy and efficiency of data transmission. GPIO1 generates the IND signal, which notifies the data receiver (slave device) that the data sender (master device) is ready to send data. When the master device has data ready to send via SPI, it first sends the IND signal. Upon receiving the IND signal, if the slave device's receive buffer is ready, it will respond with the RDY signal. This mechanism ensures that the slave device's receiving capability has been confirmed before the master device sends data, enhancing communication synchronization and data integrity.

[0054] Through the above mechanism, the RDY and IND signals can work together, making SPI communication more efficient and stable between master and slave devices, adapting to different load conditions, reducing communication latency, avoiding data loss, and significantly improving communication performance and reliability.

[0055] It's important to note that the SOC chip is equipped with a standard SPI controller for communication with the MCU (microcontroller). Unlike traditional SPI configurations, this design employs a single-channel SPI architecture, with the MCU acting as the master and the SOC as the slave. In this configuration, the SPI interface requires six pins for connection, including the four pins required by the standard SPI interface: CSN (chip select), CLK (clock), MOSI (master output, slave input), and MISO (master input, slave output). Furthermore, to enhance communication reliability and efficiency, two additional GPIO (general purpose input / output) pins are configured, named RDY (Ready, indicating the slave is ready to receive data) and IND (Indicator, indicating the master is about to send data). These two additional GPIO pins provide real-time notification of the communication status between the two devices, thus avoiding frame loss issues that may occur under high load conditions and improving the accuracy and efficiency of data transmission.

[0056] In addition to using standard SPI communication, the design also employs a Quad Serial Peripheral Interface (QSPI) for asynchronous communication. QSPI offers a higher data transfer rate than traditional SPI because it allows data to be transmitted simultaneously on both the rising and falling edges of the clock. This means that at the same clock frequency, QSPI's transfer rate is theoretically four times that of SPI. Through Direct Memory Access (DMA) mechanism, QSPI enables high-speed data transfer without the direct involvement of the Central Processing Unit (CPU), significantly reducing the CPU's workload and improving the overall system processing efficiency.

[0057] During data transmission, when the MCU is ready to send data to the SOC, it notifies the SOC via the IND signal. Once the SOC's receive buffer is ready, the SOC pulls the RDY signal high to notify the MCU that SPI data transmission can begin. At this point, the MCU will use a DMA mechanism to move the data from memory to the QSPI's TX FIFO (transmit buffer), and this process is continuous until data transmission is complete. Similarly, when receiving data, when the SOC wants to send data to the MCU, it will first notify the MCU that it is ready to send data via the RDY signal. After detecting the RDY signal, the MCU will use a DMA mechanism to move the data from the QSPI's RX FIFO (receive buffer) to memory until data reception is complete.

[0058] Data transfer via DMA (Direct Memory Access) ensures efficient data transmission while avoiding CPU resource waste, allowing the CPU to focus on other higher-priority tasks. During QSPI transmission and reception, the DMA mechanism handles data transfer between memory and the QSPI FIFO without CPU intervention, thus achieving efficient and low-latency data transfer.

[0059] The method described in this application is divided into two forms: data transmission and data reception. Figure 3 This is a schematic diagram of a data transmission process according to an embodiment of this application, such as... Figure 3As shown, in the data transmission process, chassis data, camera calibration, time synchronization, handshake response, question and answer data, diagnostics, and version information can be placed at the entry point of the ring buffer in the corresponding task and sent to the ring buffer. First, it enters the critical protection zone to check the transmission length and data, and to determine how many frames need to be transmitted. Once filled, it can exit the critical protection zone and then poll the ring buffer at 1ms intervals. "Filled" means that the data to be transmitted has been completely written into the ring buffer until the ring buffer reaches its preset capacity limit or the upper limit of the amount of data to be transmitted. This state is determined based on the head and tail pointers of the ring buffer. After data is written, the head pointer moves forward. If the distance between the head and tail pointers reaches the total capacity of the buffer minus at least one data unit (this is usually reserved space to prevent read / write conflicts), the buffer is considered "filled." At this point, the system can start the data transmission process, such as setting an interrupt, starting DMA transfer, or directly sending data via SPI.

[0060] When no data is about to be sent and the buffer is not empty, data can be retrieved from the circular buffer and placed into the transmission sequence. Simultaneously, data sender 1 (master) sends a master data transmission initiation notification signal (IND signal) to data receiver 2 (slave). Upon receiving the signal, data receiver 2 generates a slave buffer ready notification signal (RDY signal) to data sender 1. Then, data sender 1 transmits data via the serial external interface (SPI) and interrupts upon completion. The aforementioned situation where no data is about to be sent and the buffer is not empty refers to a waiting state during data transmission. At this time, the master device has no ongoing transmission task, meaning no data is being transmitted via SPI, but the circular buffer still contains data from previous tasks that have not yet been processed. This state typically occurs after the previous data transmission is completed, and the system is waiting for the next data transmission trigger. When the system detects this state, it reads data from the buffer, prepares to initiate a new SPI data transmission, and simultaneously notifies the slave device (SOC in this application) to prepare to receive data via the IND signal. This mechanism ensures the continuity and efficiency of data transmission, avoiding excessive waiting time and resource waste.

[0061] The aforementioned serial external interface is a synchronous serial data link standard. It allows full-duplex data transmission between a master device and one or more slave devices, meaning the master device simultaneously receives and sends data during communication. SPI communication is based on four signal lines: master clock (SCLK or CLK), master output / slave input (MOSI), slave output / master input (MISO), and slave select (CS or NSS). The CS line is used to select a specific slave device, while the SCLK line provides the clock signal to coordinate the data transmission rhythm. In this application, SPI is used as a low-cost communication solution between a System-on-Chip (SoC) and a Microcontroller Unit (MCU), optimizing data transmission timing and reliability by adding two GPIOs (RDY and IND).

[0062] The aforementioned circular buffer is an efficient data structure typically used in scenarios requiring cyclic reading and writing of data. In this application, the circular buffer is placed between the application layer and the transport layer, its main function being to serve as temporary storage space for different messages while they are waiting to be sent or received. The circular buffer is positioned between the application layer and the transport layer because it needs to act as a bridge between the data generated by the application layer and the data actually sent by the transport layer. On one hand, data generated by the application layer (such as chassis data, camera calibration information, time synchronization information, etc.) is placed in the circular buffer, waiting for the transport layer to send it via SPI; on the other hand, received data is also temporarily stored in the circular buffer until it is processed by the application layer. The design of the circular buffer avoids the waiting time before data is sent and also prevents overflow problems when receiving data, ensuring data continuity and integrity. Utilizing the First-In-First-Out (FIFO) principle, the circular buffer can effectively manage the data queue, reduce CPU intervention, and improve transmission efficiency.

[0063] The aforementioned critical section typically refers to a code segment in a multi-tasking or multi-threaded environment that accesses and manipulates shared resources. It must ensure that only one task or thread can access the resource at any given time to prevent data conflicts and inconsistencies. Critical sections are typically set up within read / write operations on circular buffers because these buffers are shared resources among multiple tasks. Without protection, multiple tasks might simultaneously read from or write to the buffer, leading to data corruption or loss. For example, while one task is reading data from the circular buffer, another task might simultaneously write data; without the protection of a critical section, this could result in incomplete or erroneous data. By setting critical sections, correctness and consistency in processing data within the circular buffer are ensured. When sending and receiving data, a task or thread must acquire the lock of the critical section before accessing the circular buffer. Only the lock owner can perform read / write operations, and the lock is released after the operation is complete, thus guaranteeing data integrity and system stability.

[0064] Figure 4 This is a schematic diagram of a data receiving process according to an embodiment of this application, such as... Figure 4 As shown, data sender 2 (slave) generates a device buffer ready notification signal (RDY signal) to data receiver 1. Data receiver 1 (master) sends information via the Serial External Interface (SPI) during the RDY interrupt. After the SPI transmission is completed, a transmission completion interrupt is generated. In the interrupt, it first enters critical protection, and then verifies the data link layer (header) and data transmission layer (header). If these headers are correct, the data is then packetized, and then classified according to the application layer identification information (messageID). The data is then distributed to the application layer modules and functions, including handshake, data sensing, question and answer, data reading, over-the-air (OTA) transmission, and diagnostics. Finally, it exits critical protection.

[0065] The specific implementation flow for the aforementioned critical protection and verification process can be as follows: When an SPI transmission completion interrupt occurs, data receiver 1 will jump to a pre-set interrupt service routine. Before executing any actual interrupt service code, the interrupt service routine will first enter a critical protection state, that is, disable further interrupts (usually by setting an interrupt mask register) to ensure that no other interrupts will interrupt the current processing flow during the handling of the SPI interrupt, thereby ensuring the integrity and consistency of data processing.

[0066] Upon entering critical protection, the interrupt service routine begins to verify the data link layer header in the received data frame. The data link layer header typically contains information such as the frame synchronization flag (Sync), frame sequence number (Rolling Counter, RC), and Cyclic Redundancy Check (CRC) to ensure the integrity and correctness of the data frame. The software checks whether these fields conform to the expected patterns or values. If they do not, it may indicate an error occurred during data transmission. In this case, the software will mark the data frame as unusable or erroneous and may take appropriate error handling measures.

[0067] If the data link layer header verification passes, the interrupt service routine will continue to verify the data transmission layer header, which typically contains information about the data content, such as data type, length, and destination. By verifying the transport layer header, the software can determine whether the data frame belongs to the correct target application and whether it contains a complete payload. This step is also to ensure data integrity and processing efficiency.

[0068] If the headers at both the data link layer and data transmission layer pass verification, it indicates that the received data frame is complete and correct. Next, the interrupt service routine assembles the payload (Data) from the data frame into an application layer data packet. Based on the application layer identification information (message ID), the packet is classified and distributed to the various application modules on the SOC.

[0069] After data processing is complete, the interrupt service routine exits the critical protection state, that is, it re-enables interrupts so that the data receiver can respond to subsequent interrupt events. This ensures the exclusivity of the interrupt service routine when handling the current SPI interrupt, while not unduly restricting other operations of the data receiver, thus maintaining the responsiveness and real-time performance of the system.

[0070] Through the above steps, the master device is polled to see if there is target data to be sent. In response to the presence of target data, the target data is moved to the transmission sequence, and a first signal is sent to the slave device via the serial peripheral interface. This first signal notifies the slave device that the master device is ready to transmit data. Upon receiving a second signal generated by the slave device based on the first signal, the target data is transmitted to the slave device via the serial peripheral interface. This second signal notifies the master device to transmit data, thus improving the accuracy of data transmission between devices. It is noteworthy that by sending a first signal to the slave device via the serial peripheral interface when the master device has target data to be sent, the slave device can be notified that the master device is ready to transmit data, allowing the slave device to prepare to receive data in advance. The slave device can then send a second signal back to the master device after receiving the first signal to notify the master device that data transmission is possible. This pre-communication between the master and slave devices before data transmission avoids omissions during transmission, thereby improving the accuracy of data transmission and solving the technical problem of low accuracy in data transmission between devices in related technologies.

[0071] Optionally, moving the target data to the sequence to be sent and sending a first signal to the slave device based on the serial peripheral interface includes: moving the target data to the sequence to be sent and sending a first signal to the first input interface of the slave device based on the first output interface of the master device in the serial peripheral interface, wherein different output interfaces in the serial peripheral interface are used to characterize different data transmission paths between the master device and the slave device.

[0072] The first output interface mentioned above can be a General-Purpose Input / Output (GPIO) pin. The first input interface can be a GPIO pin. The first output interface refers to the GPIO pin, used to send RDY or IND signals to inform the receiver (slave device) whether it is ready to receive or send data.

[0073] GPIO pins are general-purpose input / output pins on microcontrollers or microprocessors, used for communication between external devices and the microcontroller. GPIO pins can be used as digital input pins to receive external signals or as digital output pins to send signals to the outside. Through GPIO pins, connections to various peripherals can be achieved, such as sensors, actuators, and displays. The number and functions of GPIO pins may vary between different microcontrollers or microprocessors.

[0074] Optionally, transmitting the target data to the slave device based on the serial peripheral interface includes: transmitting the target data in the sequence to be transmitted to the first receiving interface of the slave device based on the first transmitting interface of the master device in the serial peripheral interface.

[0075] The first transmitting interface described above refers to the Master Output / Slave Input (MOSI) pin in SPI, which is the interface for transmitting target data in SPI communication. MOSI is a dedicated signal line in the SPI protocol used by the master device to send data to the slave device; it carries the main part of the data stream.

[0076] The aforementioned sequence of data to be transmitted can be associated with a first transmitting interface, through which the target data in the sequence can be transmitted to the first receiving interface of the slave device. The sequence of data to be transmitted is set in a circular buffer (FIFO) of the master device (MCU). By pre-organizing the sequence of data to be transmitted in the circular buffer, it can be ensured that data is quickly ready when it needs to be transmitted, thereby reducing the waiting time before data transmission and improving the efficiency of SPI communication.

[0077] It should be noted that the data sending and receiving processes described above are not mutually exclusive and can occur simultaneously. For example, when data sender 1 initiates a transmission, data sender 2 is also preparing to send; in this case, data exchange can occur concurrently, and the reverse is also true. Since both the sending and receiving processes enter the SPI transmission completion interrupt, it is only necessary to check whether the synchronization flag (SYNC) is valid within the interrupt to determine whether the data is valid. Therefore, this application can support full-duplex operation.

[0078] In communication systems, full-duplex communication allows data to be transmitted simultaneously in both directions, meaning that sending and receiving can occur concurrently without interference. However, traditional SPI (Serial Peripheral Interface) communication is half-duplex, meaning that only one transmission or reception can occur at a time, not both simultaneously. This application achieves full-duplex communication by introducing additional control signals and optimizing the interrupt handling mechanism.

[0079] Two additional GPIO (General Purpose Input / Output) pins, RDY and IND, are introduced to control the timing of SPI communication. The RDY signal is generated by the slave device to notify the master device that it is ready to receive data. The IND signal is generated by the master device to notify the slave device that it is ready to send data. This mechanism ensures that data transmission in both directions occurs only when the other device is ready to receive, thus avoiding the data collisions and frame drops common in half-duplex SPI.

[0080] To determine data validity—that is, whether data transmission is occurring at the correct timing and in the correct state—this application utilizes the SYNC synchronization flag. The SYNC flag is a special flag included in the data frame to indicate the start and end of data transmission, as well as its validity. When data transmission is completed via SPI, it enters the SPI transmit completion interrupt. In this interrupt handler, the system checks the SYNC flag. If the SYNC flag is valid, it means that data transmission was completed within a correct communication cycle, and the data is valid. If the SYNC flag is invalid, it may mean that an error occurred during data transmission, such as incorrect timing or data collisions, in which case the data will be considered invalid. By checking the SYNC flag in the interrupt handler, the accuracy and integrity of the data can be ensured, even in full-duplex communication mode. This mechanism allows the master and slave devices to send and receive data simultaneously without affecting each other, reducing communication latency, improving communication efficiency, and reducing the risk of frame loss. Therefore, this application successfully implemented full-duplex communication in SPI communication by optimizing interrupt handling and introducing control signals, which is the key to its full-duplex support.

[0081] Figure 5 This is a schematic diagram of a data transmission waveform according to an embodiment of this application, such as... Figure 5 As shown, during the process of the master device generating the chip select signal and the slave device generating the enable clock signal, the master device data output, the slave device data input, the master device data input, and the slave device data output can all be performed simultaneously.

[0082] Optionally, polling the local area to check if there is target data to be sent includes: polling the local circular buffer to check if there is target data to be sent, wherein the circular buffer is used to buffer the received data in a first-in-first-out queue manner.

[0083] The circular buffer mentioned above is a "first-in, first-out" (FIFO) data structure and algorithm. It is a way of implementing a queue, where the first to enter are processed first, and the last to enter are processed later. A circular queue is a special FIFO data structure in which the formation is a ring shape.

[0084] Figure 6 This is a schematic diagram of a circular buffer according to an embodiment of this application, as shown below. Figure 6As shown, in a circular queue, the head and tail are considered adjacent elements. To maintain the queue's integrity, special handling is needed for insertion and deletion operations. Since there is no actual circular structure in memory, a circular queue is implemented using the linear space of arrays. Logically, the first and last arrays are connected to form a circular space. The key to a circular queue is determining whether it is full or empty. A queue is full when the tail catches up with the head, and empty when the head catches up with the tail. There are two ways to determine whether it is full or empty:

[0085] Method 1: Add a flag (tag). When the head catches up with the tail, the queue is empty and tag = 0. When the tail catches up with the head, the queue is full and tag = 1.

[0086] Method 2: Restrict the tail from catching up with the head. At least one element space can be left between the tail point and the head point. When the queue is empty, the head equals the tail. When the queue is full, the tail + 1 equals the head.

[0087] Both of the above-mentioned technical solutions can be used in the circular buffer area of ​​this application. This application will use the second method as an example for illustration. After the data frame is filled into the buffer of the circular queue, the address can be pointed to the driver layer, and then the driver layer sends the data through the SPI bus.

[0088] Optionally, the method further includes: in response to the master device receiving multiple data frames, determining the current queue state of the circular buffer; in response to the current queue state indicating whether the circular buffer is empty or not empty, filling the circular buffer with multiple data frames, wherein not empty indicates that the circular buffer stores data and has remaining capacity; in response to the current queue state indicating that the circular buffer is full, moving preset data to the sequence to be sent based on the target address of the sequence to be sent, and filling the circular buffer with multiple data frames.

[0089] In one optional embodiment, if the circular buffer is empty or not empty, it means that it can still hold data. It should be noted that the non-empty state does not include a full state. In this case, multiple data frames can be filled into the circular buffer. If the circular buffer is full, the preset data in the circular buffer can be moved to the waiting sequence, the memory space of the circular buffer can be released, and multiple data frames can be filled into the circular buffer in a first-in-first-out manner.

[0090] The target address mentioned above can be the address to which the sequence to be sent in the driver layer is pointed.

[0091] The aforementioned preset data can be placeholder data or padding data. Its main function is to temporarily replace the actual data that should be sent when the circular buffer is full, ensuring continuous data transmission and preventing the loss of important transmission opportunities. This keeps the SPI communication link active. The purpose of this is to prevent the master device from pausing SPI communication due to a full buffer, thus avoiding idle communication links and ensuring that data transmission can resume immediately after space is cleared from the buffer, reducing latency.

[0092] The master device periodically checks the status of the circular buffer to determine if it is full. If the circular buffer is full, to maintain the communication link's activity, the master device selects preset data from a predefined data pool. This data may contain specific padding patterns or placeholders, such as all zeros, all one-digit numbers, or a specific sequence, and moves this preset data into the pending sequence. The pending sequence can be understood as a temporary area ready to send data; it is based on the data in the circular buffer but is not necessarily a direct part of the circular buffer. When data in the circular buffer is consumed or removed, i.e., the circular buffer changes from a full state to a partially full state, the master device can then begin filling the circular buffer with actual data frames. This means that once there is free space in the circular buffer, the master device immediately replaces the previously sent preset data with actual data to restore normal communication.

[0093] By sending pre-set data, the SPI communication link can be kept active even when the circular buffer is full, preventing interruption due to buffer fullness. This helps maintain the continuity and stability of data transmission under high load. If data needs to be retransmitted for some reason (such as data verification failure), the use of pre-set data also provides a mechanism to maintain the continuity of the communication link while waiting for data retransmission, thereby avoiding additional communication delays.

[0094] Optionally, determining the current queue state of the circular buffer includes: detecting a flag bit of the circular buffer; determining the current queue state to indicate that the circular buffer is empty in response to the flag bit being a first value; determining the current queue state to indicate that the circular buffer is full in response to the flag bit being a second value; and determining the current queue state to indicate that the circular buffer is not empty in response to the flag bit not being the first value and the flag bit not being the second value.

[0095] The first value mentioned above can be 0, and the second value mentioned above can be 1, but it is not limited to these. Users can set it according to the actual situation.

[0096] By detecting the flag bits of the circular buffer, the current queue status of the circular buffer can be detected in a timely manner, and multiple data frames can be moved according to the current queue status.

[0097] Optionally, determining the current queue state of the circular buffer includes: determining the current queue state to indicate that the circular buffer is empty in response to the head data and tail data being the same; determining the current queue state to indicate that the circular buffer is full in response to the sum of the tail data and the third value being the same as the head data; and determining the current queue state to indicate that the circular buffer is not empty in response to the head data and tail data being different and the sum being different from the head data.

[0098] The third value mentioned above can be 1, but is not limited to this; users can set it according to their actual situation.

[0099] The aforementioned header data can be the data that first enters the circular buffer from the data contained in the circular buffer, and the aforementioned tail data can be the data that last enters the circular buffer from the data contained in the circular buffer.

[0100] Optionally, filling multiple data frames into a circular buffer includes: storing multiple data frames in a read-only memory; and using direct memory access hardware to move a preset number of bytes of data from the read-only memory to the circular buffer based on a preset number of moves.

[0101] The aforementioned Direct Memory Access (DMA) hardware can improve data transfer efficiency and reduce processor load.

[0102] The preset bytes mentioned above can be 8 bits, but are not limited to this; you can set them according to the actual situation.

[0103] In this design, different messages are sent at different times. This application needs to design a control over the time when different messages enter the FIFO to prevent data in the FIFO from filling the entire space at the same time. Therefore, frequency division and offset can be used to design the FIFO with periodic messages of 10ms, 20ms and 50ms. Figure 7 This is a timeline for periodic message transmission according to an embodiment of this application, such as... Figure 7 As shown, the first row of arrows can be used to represent periodic messages of 10ms, the second row of arrows can be used to represent periodic messages of 20ms, and the third row of arrows can be used to represent periodic messages of 50ms.

[0104] In designing periodic message transmission with different cycles, this application employs frequency division and time offset methods to prevent multiple periodic messages from contending for FIFO resources at the same time, thus avoiding data overflow or collisions. This is primarily to optimize FIFO utilization efficiency, ensure data continuity and integrity, and avoid data packet loss under high load conditions. Frequency division refers to converting a faster clock signal into a slower one, thereby adjusting the data transmission frequency. In this application, 10ms, 20ms, and 50ms periodic messages represent different data transmission frequencies. By adjusting the frequency division coefficient, it can be ensured that each periodic message is transmitted at different times, thus avoiding the possibility of multiple messages being written to the FIFO simultaneously. For example, if the system clock is 1ms, then a 10ms message is transmitted every 10 system clock cycles, while a 20ms message is transmitted every 20 system clock cycles, and so on.

[0105] Time offset refers to setting an initial transmission time for periodic messages with different periods to stagger their transmission times. For example, assuming periodic messages of 10ms, 20ms, and 50ms start transmission at time points 0ms, 5ms, and 15ms respectively, then on the subsequent timeline, they can be transmitted continuously according to their respective periods, but not at the same time point, effectively avoiding FIFO congestion. The first row of arrows (10ms periodic message) indicates that a message is transmitted once every 10ms. This means that the message enters the FIFO with a period of 10ms, waiting to be transmitted via the SPI bus. The second row of arrows (20ms periodic message) indicates that a message is transmitted every 20ms. This is less frequent than the 10ms periodic message, so it is staggered on the timeline and will not enter the FIFO at the same time point. The third row of arrows (50ms periodic message) indicates that a message is transmitted every 50ms. This is the lowest frequency of the three periodic messages. The sending time of the third row of arrows is significantly different from the first two types of messages, which ensures the reasonable use of FIFO and avoids data congestion.

[0106] By employing such frequency division and time offset strategies, the efficiency and stability of SPI communication can be ensured even under high load conditions. This avoids data overflow caused by multiple periodic messages being written to the FIFO at the same time point, while also ensuring that longer periodic messages can be sent accurately at predetermined time intervals, thereby improving the data transmission quality and reliability of the entire system.

[0107] This application effectively solves the problem of multiple periodic messages simultaneously competing for FIFO resources by implementing frequency division and time offset strategies between different periodic messages, ensuring data continuity and integrity, improving FIFO utilization efficiency and the reliability of the entire communication system. The data link layer single frame in this application can be 256 bytes, with DMA transferring 8 bits each time, requiring a total of 256 transfers, but it is not limited to this.

[0108] Figure 8 This is a schematic diagram of data transmission for direct memory access according to an embodiment of this application, such as... Figure 8 As shown, the data transmission process involves four steps: random access memory, software / hardware direct memory access, four-wire serial peripheral interface, and serial external interface transmission. When the SPI transmit function is called, a software direct memory access (DMA) trigger is first generated to move 8 bits of data from the random access memory (RAM) to the QSPI FIFO. Then, at each time the QSPI TXFIFO is loaded, a hardware DMA is generated, and the hardware DMA moves 8 bits of data from RAM to the FIFO. This process is repeated until 256 times.

[0109] Furthermore, Figure 8This embodiment demonstrates the specific mechanism by which DMA improves SPI data transmission efficiency. In traditional SPI data transmission, the CPU moves data byte by byte into the SPI transmit register, which is inefficient, especially when transmitting large amounts of data. When the application calls the SPI transmit function, software DMA is triggered. The role of software DMA is to initialize the DMA controller and configure DMA transfer parameters, such as the source address (data address in RAM), the destination address (QSPI's TX FIFO address), and the data length (256 bytes in this embodiment). Software DMA moves the first 8 bits of data from RAM to the QSPI's TX FIFO, thus avoiding direct CPU involvement in data movement, reducing the CPU's burden, and improving data transmission efficiency. When there is free space in the TX FIFO, hardware DMA automatically moves 8 bits of data from RAM to the TX FIFO. Hardware DMA is a hardware-level data transfer mechanism that can automatically move data from RAM to the TX FIFO without CPU intervention. Hardware DMA is typically triggered by certain events, such as changes in the available space of the TX FIFO in this embodiment, thereby achieving automatic data movement. This process occurs each time the TX FIFO needs to be filled with data, continuing until all 256 data transfers are complete. To further improve SPI transmission efficiency, after the data in the TX FIFO is moved into the SPI exchange register and sent, the hardware DMA continues to move data from RAM to the TX FIFO, ensuring that the TX FIFO is always full. This minimizes data transmission latency and improves the utilization of the SPI channel. The above data transfer and TX FIFO full-state maintenance process continues until the entire SPI frame (256 bytes) of data has been transmitted. During transmission, the hardware DMA and software DMA work together to achieve efficient data transmission.

[0110] Through the aforementioned optimization mechanism, the embodiments of this application can significantly improve the data transmission efficiency of SPI, enabling the establishment of a more efficient and stable communication link between the SOC and the MCU. Simultaneously, due to the direct data transfer between SPITX and QSPI FIFO, intensive CPU operations can be avoided, further enhancing the system's real-time performance and response speed.

[0111] Figure 9 This is a schematic diagram of data reception for direct memory access according to an embodiment of this application, such as... Figure 9As shown, it includes four steps: serial external interface reception, four-wire serial external interface, hardware direct memory access, and random access memory. During the data reception process, after the SPI transmit function is called, the master sends data and receives data at the same time. The data received from the QSPI RX register is first filled into the RX FIFO. At this time, the hardware DMA is triggered. The hardware DMA will move 8 bits of data each time until 256 data moves are completed, and then the process ends.

[0112] When the SPI transmit function is called, the master device begins sending data via the QSPI bus. Simultaneously, it prepares to receive data from the slave device via the QSPI RX register. The QSPI RX register is the entry point for received data; data is first read into this register. Received data is transferred from the QSPI RX register to the receive FIFO (RX FIFO), a first-in, first-out (FIFO) data structure used for temporary storage. The RX FIFO reduces CPU intervention because data can be directly transferred from the SPI RX register to the FIFO without immediate CPU processing. When data enters the RX FIFO, hardware DMA (Direct Memory Access) is triggered. The DMA controller handles the data transfer from the RX FIFO to RAM (Random Access Memory) without direct CPU involvement. This allows received data to be automatically stored in RAM even when the CPU is busy with other tasks, improving data processing efficiency and system responsiveness. Hardware DMA transfers 8 bits of data at a time until the entire SPI frame (256 bytes) has been transferred. After being transferred to RAM via DMA, the data is stored in a specific buffer, awaiting further processing. RAM provides a fast storage space from which the application layer can read data for further processing, such as error detection, data parsing, and distribution to the appropriate application modules. The high-speed data transfer capability of QSPI and the efficient data handling capability of DMA can significantly improve data reception efficiency and overall system performance. Simultaneously, by controlling the states of the TX FIFO and RX FIFO, data loss and overflow can be effectively avoided, ensuring data accuracy and communication stability.

[0113] Furthermore, to prevent data overflow when the RX FIFO is full, this application halts data transfer from the TX FIFO to the SPI data exchange register until the DMA transfers the data from the RX FIFO to RAM before resuming communication. This effectively prevents data loss and ensures communication reliability. During the data reception process, hardware DMA automatically transfers data to RAM upon completion of SPI communication, reducing the CPU load and ensuring rapid data reception and storage, providing an efficient and stable foundation for subsequent data processing.

[0114] The design goal of the Quad SPI (QSPI) serial peripheral interface is to keep the TX FIFO as full as possible to reduce transmission latency and to keep the RX FIFO as empty as possible to prevent RX FIFO overflow. When the SPI transmit function is called, data is written to the TX FIFO, which generates a hardware DMA request. This process continues until the TX FIFO is full, at which point hardware DMA requests are paused. After the data in the TX FIFO is moved into the SPI's exchange register for transmission, hardware DMA requests will resume when the TX FIFO becomes idle. The goal is to keep the TX FIFO constantly full, minimizing transmission delays caused by DMA transfers that could lead to waiting and reduced efficiency.

[0115] For the RX FIFO, a different strategy is used. Whenever data is written from the SPI exchange register to the RX FIFO, a hardware DMA is generated to move the data to RAM until the RX FIFO is empty. At the same time, an operation can be performed: when the RX FIFO is full, the transfer of data from the TX FIFO to the SPI exchange register is stopped. When the RX FIFO has been freed up by the DMA, communication is resumed. The purpose is to reduce the impact of DMA transfer delay and prevent the RX FIFO from overflowing.

[0116] Currently, the mainstream communication solution between SOC and MCU is Ethernet. Ethernet has a fast transmission rate and a mature protocol stack, but it is relatively expensive and requires a switch chip, which occupies more pin resources. This application can use SPI communication while considering cost reduction. SOC and MCU can communicate through four SPI pins and two GPIO pins, while ensuring data accuracy and efficiency. The SPI protocol stack needs to be redesigned to add two GPIOs. Using the traditional SPI protocol between SOC and MCU, it is difficult to guarantee that data reception will not lose frames under heavy load. Therefore, it is necessary to add two GPIO pins to control the timing of transmission.

[0117] This application can replace Ethernet as a low-cost communication solution between SOC and MCU, reducing the need for switching chips and pin usage associated with Ethernet transmission. Using the traditional SPI protocol between SOC and MCU, the slave end struggles to actively send data, requiring the master to trigger the SPI transmission. Furthermore, the master's periodic data querying of the slave cannot guarantee zero frame loss under heavy loads. Adding the RDY signal allows the slave to promptly notify the master to transmit SPI when it needs to send data, reducing communication latency compared to the periodic master data reading method. It also ensures the slave is capable of handling SPI during transmission, guaranteeing no frame loss. Similarly, adding the IND signal works the same way. When the master needs to send, it actively pulls the IND signal; once the slave is ready, it pulls the RDY pin to notify the master to transmit SPI. This effectively synchronizes the SPI communication capabilities of both the master and slave, preventing frame loss and reducing latency. In short, by adding these two GPIO pins to control the timing of transmission, the timeliness and accuracy of data transmission can be guaranteed.

[0118] The transmission speed of automotive Ethernet is relatively high, generally 100 Mbit / s or 1000 Mbit / s, while the SPI channel used by the MCU has a transmission rate of 10 Mbit / s. Therefore, the transmission utilization rate becomes the key to the transmission of data between the MCU and the SOC by replacing the Ethernet protocol with the SPI protocol. This application uses full-duplex SPI and has made certain design to the protocol stack, which can achieve a theoretical rate of 6 Mbit / s.

[0119] In this application, the SOC and MCU can communicate using a single 4-wire (CLK, CS, MOSI, MISO) SPI, with the MCU acting as the master and the SOC as the slave. The MCU periodically polls to read data from the SOC and simultaneously sends data back to the SOC, making the implementation simple and without additional GPIO resource consumption.

[0120] In this application, the SOC and MCU can also communicate using two 3-wire (CLK, CS, MOSI) SPI interfaces. One interface is used by the SOC (master) to send data to the MCU (slave), and the other is used by the MCU (master) to send data to the SOC (slave). This does not add GPIO; instead, it ensures transmission stability by controlling the frame interval. The implementation is simple and consumes no additional GPIO resources.

[0121] The software architecture for the SPI communication described above is implemented as follows:

[0122] SPI Physical Layer: This is the hardware implementation of the SPI controller at the bottom layer of the chip.

[0123] SPI Driver Layer: This is the driver part of the underlying chip, providing SPI frame transmission and reception and related GPIO interrupt notification mechanisms.

[0124] SPI Data Link Layer: Implements the communication protocol management of SPI, using a fixed-length SPI frame.

[0125] SPI Transport Layer: Responsible for data fragmentation operations for applications, used to transfer variable-length data blocks between application layers.

[0126] SPI Application Layer: Implements the protocol transmission of SPI messages for application-defined data.

[0127] The SPI Service interacts with functional apps through inter-process communication for data distribution.

[0128] The physical layer design includes some configurations for the SPI driver. The recommended SPI transmission rate is 10 Mbps, the SPI data transmission width is in units of 8 bits, and the SPI data transmission direction is the most significant bit (MSB).

[0129] The Data Link Layer needs to have the following functions: a handshake mechanism required for establishing a communication connection; a configurable fixed-length fragmentation mechanism to split SPI-length application data into several fixed-length data packets for transmission; start and end markers for each frame; a buffer mechanism to cache application layer data; necessary verification mechanisms for the data (rolling counter checksum); necessary error diagnosis and error handling mechanisms (error detection, repetition); the data link layer currently has a fixed length of 256 bytes, meaning the minimum packet length on the SPI bus is 256 bytes.

[0130] The Transport Layer (SIL) of the SPI data link layer needs to have the following functions: It transmits variable-length data blocks between the SOC and MCU application layers. Data is fragmented according to the fixed-length design of the data link layer. At the sending end, the message is provided to the transport protocol, which sends it to the client via the data link protocol and notifies the application of success upon completion. At the receiving end, the application provides a buffer, which is filled with correctly received messages by the transport protocol. The transport layer data structure is as follows: The transport layer data transmission mode is divided into single-frame mode and continuous frame mode, distinguished by a mask (the first byte of the transport layer). The Mask (Byte0) structure includes Reserve, End (end frame flag), Consecutive (continuous frame), and Start (first frame flag).

[0131] Application Layer Design: This section describes the application layer functionality of the SOC and the protocol between the application layer and application layer User Data. It mainly includes periodic message formats and diagnostic question-and-answer message formats. Common data structures for the SPI application layer include message header / header (Msg Header) and message content (Msg Content).

[0132] Example 2

[0133] According to an embodiment of the present invention, a method for data transmission between devices is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0134] Figure 10 This is a flowchart of a data transmission method between devices according to an embodiment of the present invention, such as... Figure 10 As shown, the method includes the following steps:

[0135] In step S1002, in response to receiving the first signal sent by the master device, a second signal is generated based on the first signal, and the second signal is sent to the master device based on the serial peripheral interface.

[0136] The first signal is used to notify the slave device that the master device is ready to transmit data, and the second signal is used to notify the master device to transmit data.

[0137] Step S1004: In response to receiving the target data sent by the master device according to the second signal and receiving the interrupt signal sent by the master device, the target data is sent to the target application layer.

[0138] The interrupt signal is used to indicate that the master device has completed data transmission.

[0139] The master device can notify the slave device that data transmission is complete by sending an interrupt signal. At this time, the slave device can send the target data to the target application layer so that the target application layer can use the target data.

[0140] In this embodiment of the invention, in response to receiving a first signal sent by a master device, a second signal is generated based on the first signal, and the second signal is sent to the master device via a serial peripheral interface. The first signal is used to notify the slave device that the master device is ready to transmit data, and the second signal is used to notify the master device to transmit data. In response to receiving target data sent by the master device according to the second signal, and receiving an interrupt signal sent by the master device, the target data is sent to the target application layer. The interrupt signal indicates that the master device has completed data transmission, thereby improving the accuracy of data transmission between devices. It is noteworthy that, when the master device has target data to be sent, a first signal can be sent to the slave device via a serial peripheral interface to notify the slave device that the master device is ready to transmit data, allowing the slave device to prepare to receive data in advance. The slave device can then send a second signal back to the master device after receiving the first signal to notify the master device that data transmission is possible. Pre-communication between the master device and the slave device before data transmission avoids omissions during data transmission, thereby improving the accuracy of data transmission and solving the technical problem of low accuracy in data transmission between devices in related technologies.

[0141] Optionally, sending the target data to the target application layer includes: assembling the target data into multiple data packets; classifying the multiple data packets based on the preset identification information of the target application layer to obtain classification results, wherein the classification results are used to represent the correspondence between the multiple data packets and the target application layer; and sending the multiple data packets to the target application layer corresponding to the multiple data packets based on the classification results.

[0142] In one alternative embodiment, upon receiving an interruption signal, the system enters critical protection mode, where the data link layer checksum header and transport layer header are verified. If these headers are correct, data packets are then assembled. These packets are then categorized based on the application layer message ID and distributed to application layer modules and functions, including handshake, data sensing, Q&A, data reading, and diagnostics. Finally, the critical protection mode exits.

[0143] Optionally, sending the second signal to the master device includes: sending the second signal to the second input interface of the master device based on the second output interface of the slave device in the serial peripheral interface.

[0144] The second output interface mentioned above can be a General-Purpose Input / Output (GPIO) pin. The second input interface mentioned above can be a GPIO pin.

[0145] Example 3

[0146] According to embodiments of the present invention, a data transmission apparatus for implementing the above-described inter-device data transmission method is also provided. Figure 11 This is a schematic diagram of a data transmission device between devices according to Embodiment 3 of this application, as shown below. Figure 11 As shown, the device 1100 includes: a polling module 1102, a sending module 1104, and a transmission module 1106.

[0147] The polling module is used to poll whether there is target data to be sent locally; the sending module is used to send a first signal to the slave device based on the serial peripheral interface in response to the existence of target data locally, wherein the first signal is used to notify the slave device that the master device is ready to transmit data; the transmission module is used to transmit the target data to the slave device based on the serial peripheral interface in response to receiving a second signal generated by the slave device according to the first signal, wherein the second signal is used to notify the master device to transmit data.

[0148] In the above embodiments of this application, the sending module is further configured to move the target data to the sequence to be sent, and send the first signal to the first input interface of the slave device based on the first output interface of the master device in the serial peripheral interface, wherein different output interfaces in the serial peripheral interface are used to characterize different data transmission paths between the master device and the slave device.

[0149] In the above embodiments of this application, the transmission module is further configured to transmit the target data in the sequence to be transmitted to the first receiving interface of the slave device based on the first transmitting interface of the master device in the serial peripheral interface.

[0150] In the above embodiments of this application, the polling module is further used to poll whether there is target data to be sent in the local circular buffer, wherein the circular buffer is used to cache the received data in a first-in-first-out queue manner.

[0151] In the above embodiments of this application, the device further includes: a determining module, a filling module, and a moving module.

[0152] The determination module is used to determine the current queue state of the circular buffer in response to the master device receiving multiple data frames; the filling module is used to fill the circular buffer with multiple data frames in response to the current queue state indicating whether the circular buffer is empty or not, wherein not empty indicates that the circular buffer contains data and has remaining capacity; the moving module is used to move preset data to the waiting sequence based on the target address of the waiting sequence in response to the current queue state indicating that the circular buffer is full, and fill the circular buffer with multiple data frames.

[0153] In the above embodiments of this application, the filling module is also used to store multiple data frames into a read-only memory; and to use direct memory access hardware to move a preset number of bytes of data from the read-only memory into a circular buffer based on a preset number of transfers.

[0154] In the above embodiments of this application, the determining module is further configured to detect the flag bit of the circular buffer; in response to the flag bit being a first value, determine the current queue state to indicate that the circular buffer area is empty; in response to the flag bit being a second value, determine the current queue state to indicate that the circular buffer area is full; in response to the flag bit not being the first value and the flag bit not being the second value, determine the current queue state to indicate that the circular buffer area is not empty.

[0155] In the above embodiments of this application, the determining module is further configured to determine the current queue state to indicate that the circular buffer area is empty in response to the fact that the head data and the tail data in the circular buffer are the same; to determine the current queue state to indicate that the circular buffer area is full in response to the fact that the sum of the tail data and the third value is the same as the head data; and to determine the current queue state to indicate that the circular buffer area is not empty in response to the fact that the head data and the tail data are different and the sum is different from the head data.

[0156] It should be noted that the preferred implementation schemes involved in the above embodiments of this application are the same as the schemes, application scenarios and implementation processes provided in Embodiment 1, but are not limited to the schemes provided in Embodiment 1.

[0157] Example 4

[0158] According to embodiments of the present invention, a data transmission apparatus for implementing the above-described inter-device data transmission method is also provided. Figure 12 This is a schematic diagram of a data transmission device between devices according to Embodiment 4 of this application, as shown below. Figure 12 As shown, the device 1200 includes: a generation module 1202 and a transmission module 1204.

[0159] The generation module is used to respond to receiving a first signal sent by the master device, generate a second signal based on the first signal, and send the second signal to the master device based on the serial peripheral interface. The first signal is used to notify the slave device that the master device is ready to transmit data, and the second signal is used to notify the master device to transmit data. The sending module is used to respond to receiving target data sent by the master device according to the second signal and receiving an interrupt signal sent by the master device, and send the target data to the target application layer. The interrupt signal is used to indicate that the master device has completed data transmission.

[0160] Optionally, the sending module is also used to assemble the target data into multiple data packets; classify the multiple data packets based on the preset identification information of the target application layer to obtain classification results, wherein the classification results are used to represent the correspondence between the multiple data packets and the target application layer; and send the multiple data packets to the target application layer corresponding to the multiple data packets based on the classification results.

[0161] Optionally, the transmitting module is also used to transmit a second signal to the second input interface of the master device based on the second output interface of the slave device in the serial peripheral interface.

[0162] It should be noted that the preferred implementation schemes involved in the above embodiments of this application are the same as the schemes, application scenarios and implementation processes provided in Embodiment 1, but are not limited to the schemes provided in Embodiment 1.

[0163] Example 5

[0164] According to an embodiment of this application, a computer-readable storage medium is also provided, characterized in that the computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the execution of any one of the above embodiments of the inter-device data transmission method in the processor of the device where it is located.

[0165] Example 6

[0166] According to an embodiment of this application, an electronic device is also provided, including: one or more processors; a storage device for storing one or more programs; and a device data transmission method for performing any one of the above embodiments when the one or more programs are executed by the one or more processors.

[0167] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0168] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0170] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0171] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0172] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0173] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for data transmission between devices, characterized in that, Applied to the main equipment, including: Poll the local machine to check if there is target data to be sent; In response to the presence of the target data locally, a first signal is sent to the slave device via a serial peripheral interface, wherein the first signal is used to notify the slave device that the master device is about to transmit data; In response to receiving a second signal generated by the slave device based on the first signal, the target data is transmitted to the slave device via the serial peripheral interface, wherein the second signal is used to notify the master device to perform data transmission.

2. The data transmission method between devices according to claim 1, characterized in that, Sending the first signal to the slave device based on the serial peripheral interface includes: The target data is moved to the sequence to be sent, and the first signal is sent to the first input interface of the slave device based on the first output interface of the master device in the serial peripheral interface, wherein different output interfaces in the serial peripheral interface are used to characterize different data transmission paths between the master device and the slave device.

3. The data transmission method between devices according to claim 1, characterized in that, Transmitting the target data to the slave device via the serial peripheral interface includes: The target data in the sequence to be transmitted is transmitted to the first receiving interface of the slave device based on the first transmitting interface of the master device in the serial peripheral interface.

4. The data transmission method between devices according to claim 3, characterized in that, Polling to check if target data to be sent exists locally, including: The local circular buffer is polled to check if the target data exists, wherein the circular buffer is used to cache the received data using a first-in-first-out queue method.

5. The data transmission method between devices according to claim 4, characterized in that, The method further includes: In response to the master device receiving multiple data frames, the current queue state of the circular buffer is determined; In response to the current queue state indicating whether the circular buffer is empty or not, the plurality of data frames are filled into the circular buffer, wherein the non-empty state indicates that the circular buffer contains data and that the circular buffer has remaining capacity; In response to the current queue state indicating that the circular buffer is full, the target data is moved to the sequence to be sent based on the target address of the sequence to be sent, and the plurality of data frames are filled into the circular buffer.

6. The data transmission method between devices according to claim 5, characterized in that, Filling the plurality of data frames into the circular buffer includes: Store the plurality of data frames into a read-only memory; Based on a preset number of transfers, direct memory access hardware is used to transfer a preset number of bytes of data from the read-only memory to the circular buffer.

7. The data transmission method between devices according to claim 5, characterized in that, Determining the current queue state of the circular buffer includes: Detect the flag bit of the circular buffer; In response to the flag bit being a first value, the current queue state is determined to indicate that the circular buffer area is empty; In response to the flag bit being a second value, the current queue state is determined to indicate that the circular buffer area is full; In response to the flag bit not being the first value and the flag bit not being the second value, the current queue state is determined to indicate that the circular buffer area is non-empty.

8. The data transmission method between devices according to claim 5, characterized in that, Determining the current queue state of the circular buffer includes: In response to the fact that the head data and tail data in the circular buffer are the same, the current queue state is determined to indicate that the circular buffer area is empty; In response to the fact that the sum of the tail data and the third value is the same as the head data, the current queue state is determined to indicate that the circular buffer area is full; In response to the fact that the header data is different from the tail data and the sum value is different from the header data, the current queue state is determined to indicate that the circular buffer area is non-empty.

9. A method for data transmission between devices, characterized in that, Applied to slave devices, including: In response to receiving a first signal sent by the master device, a second signal is generated based on the first signal, and the second signal is sent to the master device via a serial peripheral interface, wherein the first signal is used to notify the slave device that the master device is about to perform data transmission, and the second signal is used to notify the master device to perform data transmission; In response to receiving target data sent by the master device according to the second signal and receiving an interrupt signal sent by the master device, the target data is sent to the target application layer, wherein the interrupt signal is used to indicate that the master device has completed data transmission.

10. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors perform the inter-device data transmission method according to any one of claims 1 to 9.

Images