Chip functionality test packaging structure and chip functionality test method
By stacking chipsets on a test circuit board and bonding multiplexed signal ports, the problems of large chip testing area and low efficiency are solved, and efficient multi-chip testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2026-03-31
AI Technical Summary
Existing technologies require large areas for chip testing, resulting in low testing efficiency and the inability to test multiple chips simultaneously.
A stacked chipset structure is adopted, in which multiple chips are stacked on the test circuit board, and the same multiplexed signal ports are bonded to each other and connected to the on-board ports on the test circuit board. Independent signal ports are connected by gold wires.
It increases the number of chips that can be accommodated on the test circuit board, improves test efficiency, reduces the number of connectors for input/output interfaces, and optimizes signal transmission quality.
Smart Images
Figure CN121763045A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip packaging, and in particular to a chip functional testing packaging structure and a chip functional testing method. Background Technology
[0002] Before a chip is put into use, it needs to undergo FT (functionality testing) to confirm that its functions are normal and usable. Currently, the packaging method for chips requiring functional testing involves first performing COB (Chips on Board) packaging. After packaging, several COB boards are cascaded on a test circuit board and then connected to a driver board for input / output processing speed testing. For details, please refer to [reference needed]. Figure 1 , Figure 1 The image shows a top view of four COB boards cascaded on a circuit board in the prior art. It is easy to see that this testing method requires a large number of COB boards and occupies a huge area on the circuit board, resulting in low testing efficiency when a large number of chips need to be tested.
[0003] Therefore, how to reduce the area occupied by a single chip during testing and increase the number of chips that can be tested on a single driver board in order to improve testing efficiency is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a functional test packaging structure and a functional test method for chips, so as to solve the problems in the prior art where chip testing requires a large area and the number of chips that can be tested is small, resulting in long testing time and low testing efficiency for multi-chip testing.
[0005] To address the aforementioned technical problems, the present invention provides a functional test packaging structure for a chip, including a test circuit board and a stacked chip assembly disposed on the test circuit board.
[0006] The stacked chipset includes multiple stacked chips;
[0007] The same multiplexed signal ports on multiple chips in the same stacked chipset are bonded to each other and connected to the corresponding on-board ports on the test circuit board.
[0008] Optionally, in the functional test package structure of the chip, the mutually bonded multiplexed signal ports pass through the chip located below the corresponding stacked chipset and are connected to the corresponding on-board ports.
[0009] Optionally, in the functional test package structure of the chip, the independent signal ports on the chip are connected to the corresponding on-board ports via gold wires.
[0010] Optionally, in the functional test package structure of the chip, the independent signal port includes at least one of a data output port and an address port.
[0011] Optionally, in the functional test package structure of the chip, a single test circuit board includes multiple stacked chip groups.
[0012] Optionally, the functional test packaging structure of the chip also includes a substrate;
[0013] The substrate is fixed on the test circuit board, and the stacked chipset is disposed on the substrate;
[0014] The ports on the chip are connected to the corresponding ports on the substrate.
[0015] Optionally, in the functional test package structure of the chip, the substrate is connected to the test circuit board via at least one of bonding balls, pads, vias, connectors, and pin headers.
[0016] Optionally, in the functional test package structure of the chip, the multiplexed signal port includes at least one of a ground port, a test control port, and a power port.
[0017] Optionally, in the functional test package structure of the chip, the test circuit board further includes an on-board processor;
[0018] The on-board processor is used to send, receive, and store chip information on the corresponding test circuit board; the chip information includes chip quantity information, chip access address information, and port information.
[0019] A chip functional testing method, the chip functional testing method being used for functional testing of the package structure of a chip as described in any of the above embodiments, comprising:
[0020] Receive chip information from the processor on the board;
[0021] Based on the chip information, determine the number of chips, chip access address information, and port information on the corresponding test circuit board;
[0022] Chip testing is performed based on the chip quantity information, chip access address information, and port information.
[0023] The functional test packaging structure for chips provided by this invention includes a test circuit board and a stacked chip group disposed on the test circuit board. The stacked chip group includes multiple stacked chips. Identical multiplexed signal ports on multiple chips in the same stacked chip group are bonded to each other and connected to corresponding on-board ports on the test circuit board. This invention stacks chips on a test circuit board, greatly increasing the number of chips that can be accommodated on the same test circuit board, which is equivalent to improving the testing efficiency in batch testing of chips. At the same time, because this invention bonds and merges the multiplexed signal ports of the stacked chips, combined with the increased number of chips on the same test circuit board, compared with related technologies, the number of input / output interface connectors required when the driver board drives the same number of chips for testing is greatly reduced, leaving room for optimizing signal transmission quality. This invention also provides a chip functional testing method with the above-mentioned beneficial effects. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the cascaded COB board structure on a circuit board in related technologies;
[0026] Figure 2 A schematic diagram of a specific embodiment of the functional test packaging structure for the chip provided by the present invention;
[0027] Figure 3 A schematic diagram of a specific embodiment of the functional test packaging structure for the chip provided by the present invention;
[0028] Figure 4 A schematic diagram of a specific embodiment of the functional test packaging structure for the chip provided by the present invention;
[0029] Figure 5 A flowchart illustrating a specific implementation of the chip functionality testing method provided by the present invention;
[0030] Figure 6 A flowchart illustrating another specific implementation of the chip functionality testing method provided by the present invention;
[0031] Figure 7 This is a schematic diagram of a specific embodiment of the chip functionality testing device provided by the present invention.
[0032] The diagram includes 10-stacked chipset, 20-test circuit board, 30-substrate, 11-chip, 12-multiplexed signal port, 13-independent signal port, 100-receiving module, 200-information confirmation module, and 300-test module. Detailed Implementation
[0033] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] The core of this invention is to provide a functional test packaging structure for chip 11, and a schematic diagram of one specific embodiment is shown below. Figure 2 As shown, this is referred to as Specific Implementation Method 1, which includes a test circuit board 20 and a stacked chipset 10 disposed on the test circuit board 20.
[0035] The stacked chipset 10 includes a plurality of stacked chips 11;
[0036] The same multiplexed signal ports 12 on multiple chips 11 in the same stacked chipset 10 are bonded to each other and connected to the corresponding on-board ports on the test circuit board 20.
[0037] In this specific embodiment, the same multiplexed signal ports 12 of different chips 11 in the same group can be vertically bonded. The multiplexed signal port 12 refers to a port that can be shared between different chips 11, such as a ground port, a test signal input port (i.e., the test control port), and a power port. The term "same multiplexed signal port 12" refers to ports of the same type. Figure 2 Taking the structure in the middle as an example, Figure 2 The system includes two stacked chip sets 10, each containing two stacked chips 11 (chips A and B as one group, and chips C and D as another group). The power ports of the two chips 11 can be vertically bonded and then connected to the corresponding on-board ports on the test circuit board 20. Similarly, the test control ports of the two chips 11 can be vertically bonded and then connected to the corresponding on-board ports on the test circuit board 20. Of course, more chips 11 can be placed on the same stacked chip set 10; this invention does not limit this. Ports that cannot be shared between different chips 11, such as address ports, are referred to as independent signal ports 13 in this invention.
[0038] In a preferred embodiment, the mutually bonded multiplexed signal ports 12 pass through the chip 11 located below the corresponding stacked chipset 10 and are connected to the corresponding on-board ports.
[0039] In this preferred embodiment, the routing of the bonded multiplexed signal ports 12 is further defined, so that the bonded multiplexed signal ports 12 no longer need to extend outside the chip 11, but instead pass through the chip 11 below the stacked chip group 10 to reach the test circuit board 20. This greatly reduces the complexity of the bonding connections between the chip 11 and the test circuit board 20, reduces the possibility of short circuits caused by the increased bonding wires due to the increased number of chips 11, and improves test stability. The aforementioned "below" chip 11 refers to the chip 11 below two adjacent bonded multiplexed signal ports 12, such as... Figure 2 Chips B and D are mentioned in the text. However, in actual production, there may be situations where there are more than two chips 11 in the same stacked chip group 10. In this case, the lower chip 11 can refer to all the lower chips 11. For example, if a group includes chips E1, E2, and E3 stacked from top to bottom, then for the multiplexed signal port 12 of chip E1, the lower chip 11 should refer to chips E2 and E3, and for the multiplexed signal port 12 of chip E2, the lower chip 11 should refer to chip E3. Furthermore, the wafer-level stacking bonding in this preferred embodiment results in better signal transmission quality. For details, please refer to... Figure 3 , Figure 3 In the diagram, 12A represents the bonding segment of the multiplexed signal port 12 between adjacent chips 11, and 12B represents the electrical connection segment that passes through the lower chip 11 after bonding and contacts the test circuit board 20.
[0040] In addition, the independent signal port 13 on the chip 11 is connected to the corresponding port on the board via gold wire.
[0041] As stated above, each independent signal port 13 on the chip 11 needs to be connected to the corresponding port on the board individually. The connection method using gold wires can improve the degree of freedom in connecting the independent port to the corresponding port on the board.
[0042] The independent signal port 13 includes at least one of a data output port and an address port. The signals (data output signal and address signal, etc.) corresponding to the above ports cannot be shared between different chips 11 and need to be brought out separately to the test circuit board 20.
[0043] In one preferred embodiment, a single test circuit board 20 includes a plurality of stacked chipsets 10.
[0044] In this preferred embodiment, multiple stacked chip groups 10 are further arranged on the test circuit board 20. In this way, the number of chips 11 on a single test circuit board 20 is the number of stacked chip groups 10 multiplied by the number of chips 11 in a single stacked chip group 10 (of course, this refers to the case where the number of chips 11 in each stacked chip group 10 is the same. In actual production, the number of chips 11 in different stacked chip groups 10 can be different, and can be adjusted according to the actual situation). This further increases the packaging density of the chips 11, improves the number of chips 11 that can be tested simultaneously, and increases the efficiency of batch testing of chips 11.
[0045] In one specific embodiment, a substrate 30 is also included;
[0046] The substrate 30 is fixed on the test circuit board 20, and the stacked chip group 10 is disposed on the substrate 30;
[0047] The ports on the chip 11 are connected to the corresponding on-board ports via the substrate 30.
[0048] In some cases, directly connecting chip 11 to the test circuit board 20 increases the difficulty of removing chip 11 from the test circuit board 20 after testing. Therefore, in this specific embodiment, chip 11 is no longer directly connected to the test circuit board 20, but is first connected to the substrate 30, and then connected to the test circuit board 20 through the substrate 30. Please refer to [reference needed]. Figure 4 After the test is completed, the connection between the chip 11 and the substrate 30 can be maintained without damaging the connection between the substrate 30 and the test circuit board 20, thereby greatly reducing the difficulty of transferring the chip 11 after the test is completed.
[0049] In one specific implementation, the substrate 30 is connected to the test circuit board 20 via at least one of bonding balls, pads, through-holes, connectors, and pin headers. The substrate 30 is connected to the test circuit board 20 through these methods. These connection methods not only achieve electrical connection between the substrate 30 and the test circuit board 20, but also provide structural support. That is, they can both complete signal transmission between the test circuit board 20 and the substrate 30 and ensure a fixed connection between them, eliminating the need for other fasteners and reducing the packaging space occupied by the chip 11.
[0050] In a preferred embodiment, the test circuit board 20 also includes an on-board processor;
[0051] The on-board processor is used to send, receive, and store information about the corresponding chip 11 on the test circuit board 20; the chip 11 information includes chip 11 quantity information, chip 11 access address information, and port information.
[0052] In this preferred embodiment, an on-board processor is added to the test circuit board 20. During the test, the relevant information of the chip 11 in the test circuit board 20 can be obtained from the on-board processor, eliminating the need for manual configuration of chip 11 address and other data, and improving the automation level of the test.
[0053] The functional test packaging structure for chip 11 provided by this invention includes a test circuit board 20 and a stacked chip group 10 disposed on the test circuit board 20. The stacked chip group 10 includes multiple stacked chips 11. Identical multiplexed signal ports 12 on multiple chips 11 in the same stacked chip group 10 are bonded to each other and connected to corresponding on-board ports on the test circuit board 20. This invention stacks chips 11 on the test circuit board 20, greatly increasing the number of chips 11 that can be accommodated on the same test circuit board 20, which is equivalent to improving the test efficiency in batch testing of chips 11. At the same time, since this invention bonds and merges the multiplexed signal ports 12 of the stacked chips 11, combined with the increased number of chips 11 on the same test circuit board 20, compared with related technologies, the number of input / output interface connectors required when the driver board drives the same number of chips 11 for testing is greatly reduced, leaving room for optimization of signal transmission quality.
[0054] The present invention also provides a functional testing method for chip 11, and a flowchart of one specific embodiment is shown below. Figure 5 As shown, referred to as Specific Implementation Method Two, the chip 11 functional testing method is used for the functional testing packaging structure of chip 11 as described in any of the above embodiments, including:
[0055] S101: Receive chip 11 information from the processor on the board.
[0056] Please refer to the previous description of the on-board processor, which is used to send, receive, and store information of the chip 11 on the corresponding test circuit board 20.
[0057] S102: Based on the chip 11 information, determine the number of chips 11, chip 11 access address information, and port information on the corresponding test circuit board 20.
[0058] S103: Perform chip 11 testing based on the chip 11 quantity information, chip 11 access address information, and port information.
[0059] Unlike related technologies where one test circuit board 20 corresponds to only one chip 11, and the access address and corresponding data line of this chip 11 need to be manually confirmed and configured by the staff, in this specific embodiment, since multiple chips 11 are set on a single test circuit board 20, it is necessary to cooperate with the on-board processor on the test circuit board 20 to first obtain the relevant information of the corresponding chip 11 from the on-board processor, that is, the chip 11 information, and then automatically configure the corresponding access address and data line through the chip 11 information, which greatly improves the testing efficiency and automation of functional testing.
[0060] The functional testing method for chip 11 provided by this invention includes receiving chip 11 information from the processor on the board; determining the number of chips 11, chip 11 access address information, and port information on the corresponding test circuit board 20 based on the chip 11 information; and performing chip 11 testing based on the number of chips 11, chip 11 access address information, and port information. This invention stacks chips 11 on the test circuit board 20, significantly increasing the number of chips 11 that can be accommodated on the same test circuit board 20, effectively improving the testing efficiency in batch testing of chips 11. Simultaneously, because this invention bonds and merges the multiplexed signal ports 12 of the stacked chips 11, combined with the increased number of chips 11 on the same test circuit board 20, compared to related technologies, the number of input / output interface connectors required when the driver board drives the same number of chips 11 for testing is greatly reduced, creating space for optimizing signal transmission quality.
[0061] The following is a practical operation flow of a functional testing method for memory chips, and the corresponding flowchart is as follows: Figure 6 As shown, it includes:
[0062] Step 1: Connect the package structure to the driver board. The package structure refers to the functional test package structure.
[0063] Step 2: Obtain chip information from the packaging structure.
[0064] Step 3: Based on the chip information, the driver board automatically applies power to the corresponding number of chips.
[0065] Step 4: Input processing speed requirements for the host computer.
[0066] Step 5: Determine if the number of chips on the package structure meets the computing speed requirement in Step 4. If yes, proceed to Step 6; otherwise, return to Step 3. All chips referred to are the chips to be tested.
[0067] Step 6: Automatically configure access addresses and data lines according to the required number of chips.
[0068] Step 7: The FPGA (Field Programmable Gate Array) provides the stimulus timing to write data into the chip.
[0069] Step 8: Observe the chip's output data and record the chip's power consumption.
[0070] Step 9: Determine if the requirements are met. If yes, end the process; otherwise, return to Step 3.
[0071] The chip functionality testing apparatus provided in the embodiments of the present invention will be described below. The chip functionality testing apparatus described below can be referred to in correspondence with the chip functionality testing method described above.
[0072] Figure 7 This is a structural block diagram of the chip functional testing device provided in an embodiment of the present invention, with reference to... Figure 7 Chip functional testing equipment may include:
[0073] The receiving module 100 is used to receive chip information from the processor on the board;
[0074] The information confirmation module 200 is used to determine the number of chips, chip access address information and port information on the corresponding test circuit board based on the chip information.
[0075] The test module 300 is used to perform chip testing based on the chip quantity information, the chip access address information, and the port information.
[0076] The chip functional testing apparatus provided by this invention includes a receiving module 100 for receiving chip information from the on-board processor; an information confirmation module 200 for determining the number of chips, chip access address information, and port information on the corresponding test circuit board based on the chip information; and a testing module 300 for performing chip testing based on the number of chips, the chip access address information, and the port information. This invention stacks chips on a test circuit board, significantly increasing the number of chips that can be accommodated on the same test circuit board, effectively improving testing efficiency in batch chip testing. Furthermore, because this invention bonds and merges the multiplexed signal ports of the stacked chips, combined with the increased number of chips on the same test circuit board, compared to related technologies, the number of input / output interface connectors required when the driver board drives the same number of chips for testing is greatly reduced, creating space for optimizing signal transmission quality.
[0077] The chip functional testing apparatus of this embodiment is used to implement the aforementioned chip functional testing method. Therefore, the specific implementation of the chip functional testing apparatus can be found in the embodiment section of the chip functional testing method above. For example, the receiving module 100, the information confirmation module 200, and the testing module 300 are respectively used to implement steps S101, S102, and S103 in the above-mentioned chip functional testing method. Therefore, the specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.
[0078] The present invention also provides a chip functional testing device, comprising:
[0079] Memory, used to store computer programs;
[0080] A processor is configured to execute the computer program to implement the steps of the chip functional testing method described above. The chip functional testing packaging structure provided by this invention includes a test circuit board and a stacked chip group disposed on the test circuit board; the stacked chip group includes multiple stacked chips; the same multiplexed signal ports on the multiple chips in the same stacked chip group are bonded to each other and connected to corresponding on-board ports on the test circuit board. This invention stacks chips on a test circuit board, greatly increasing the number of chips that can be accommodated on the same test circuit board, which is equivalent to improving the testing efficiency in batch chip testing. Simultaneously, because this invention bonds and merges the multiplexed signal ports of the stacked chips, combined with the increased number of chips on the same test circuit board, compared to related technologies, when the driver board drives the same number of chips for testing, the number of input / output interface connectors required is significantly reduced, creating space for optimizing signal transmission quality.
[0081] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the chip functional testing method described above. The chip functional testing packaging structure provided by this invention includes a test circuit board and a stacked chip group disposed on the test circuit board; the stacked chip group includes multiple stacked chips; the same multiplexed signal ports on the multiple chips in the same stacked chip group are bonded to each other and connected to corresponding on-board ports on the test circuit board. This invention stacks chips on a test circuit board, greatly increasing the number of chips that can be accommodated on the same test circuit board, effectively improving the testing efficiency in batch chip testing. Simultaneously, because this invention bonds and merges the multiplexed signal ports of the stacked chips, combined with the increased number of chips on the same test circuit board, compared to related technologies, the number of input / output interface connectors required when the driver board drives the same number of chips for testing is significantly reduced, creating space for optimizing signal transmission quality.
[0082] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0083] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0084] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0085] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0086] The functional testing packaging structure and chip functional testing method of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
Claims
1. A functional test package structure for a chip, characterized by, The test circuit board and a stacked chip set arranged on the test circuit board; The stacked chip set comprises a plurality of stacked chips; The same multiplexed signal ports on the plurality of chips in the same stacked chip set are bonded to each other and connected to corresponding on-board ports on the test circuit board.
2. The functional test package structure for a chip as claimed in claim 1, wherein, The bonded multiplexed signal ports are connected to the corresponding on-board ports through the chips under the corresponding stacked chip set.
3. The functional test package structure for a chip as claimed in claim 1, wherein, The independent signal ports on the chips are connected to the corresponding on-board ports through gold wires.
4. The functional test package structure for a chip as claimed in claim 3, wherein, The independent signal ports comprise at least one of a data output port and an address port.
5. The functional test package structure for a chip as claimed in claim 1, wherein, A plurality of stacked chip sets are arranged on a single test circuit board.
6. The functional test package structure for a chip as claimed in claim 1, wherein, A substrate is further arranged; The substrate is fixed on the test circuit board, and the stacked chip set is arranged on the substrate; The ports on the chips are connected to the corresponding on-board ports through the substrate.
7. The functional test package structure for a chip as claimed in claim 6, wherein, The substrate is connected to the test circuit board through at least one of a bonding ball, a solder pad, a through hole, a connector and a pin.
8. The functional test package structure for a chip as claimed in claim 1, wherein, The multiplexed signal ports comprise at least one of a ground port, a test control port and a power supply port.
9. The functional test package structure for a chip according to any one of claims 1 to 8, wherein, An on-board processor is further arranged on the test circuit board; The on-board processor is configured to receive and store chip information on the corresponding test circuit board; the chip information comprises chip quantity information, chip access address information and port information.
10. A method of testing the functionality of a chip, characterized by The chip functional test method is used for the chip functional test packaging structure as claimed in claim 9, comprising: Receiving chip information from the on-board processor; According to the chip information, determining chip quantity information, chip access address information and port information on the corresponding test circuit board; According to the chip quantity information, the chip access address information and the port information, performing chip test.