Textured surface preparation method of silicon wafer

Abstract

The invention relates to a textured surface preparation method of a silicon wafer. The method comprises the following steps: providing a silicon wafer; the silicon wafer comprises a first crystal face and a second crystal face which have different crystal orientations; dissociating the deionized water to form hydroxyl radicals, and performing anisotropic etching on the surface of the silicon wafer through the hydroxyl radicals to obtain a textured structure; wherein the etching rates of the hydroxyl free radicals on the first crystal face and the second crystal face are different, and a textured structure can be accurately formed on the surface of the silicon wafer, so that the specific surface area of the silicon wafer is effectively increased, the light absorption capacity is improved, and the photoelectric conversion efficiency is further improved.

Description

Technical Field

[0001] This application relates to the field of solar cell fabrication technology, and in particular to a method for fabricating a textured surface on a silicon wafer. Background Technology

[0002] Heterojunction solar cells, also known as crystalline silicon heterojunction solar cells (HJT), typically require texturing of the silicon wafer during the fabrication process to ensure high light absorption.

[0003] HJTs typically use an amorphous silicon layer (a-Si) to cover a crystalline silicon (c-Si) substrate. Traditional texturing methods can disrupt the uniformity of the amorphous silicon layer, leading to interface defects. This makes it difficult to completely cover the amorphous silicon during deposition, which in turn reduces the photoelectric conversion efficiency of the HJT. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for texturing silicon wafers that can improve the photoelectric conversion efficiency of heterojunction solar cells, addressing the aforementioned technical problems.

[0005] Embodiments of this application provide a method for preparing a textured surface on a silicon wafer, the method comprising:

[0006] A silicon wafer is provided; the silicon wafer includes a first crystal plane and a second crystal plane having different crystal orientations;

[0007] Deionized water is dissociated to form hydroxyl radicals, and the silicon wafer surface is anisotropically etched using the hydroxyl radicals to obtain a textured structure.

[0008] The hydroxyl radicals have different etching rates on the first and second crystal planes.

[0009] In one embodiment, the process of dissociating deionized water to form hydroxyl radicals, and then using these hydroxyl radicals to anisotropically etch the silicon wafer surface to obtain a textured structure, includes:

[0010] The silicon wafer is placed in a transition cavity with a preset vacuum environment;

[0011] Deionized water is heated to generate water vapor, and the water vapor is injected into the transition cavity; the water vapor contains water molecules in various forms.

[0012] The water molecules are dissociated by thermionic electrons generated by a radio frequency power source to obtain hydroxyl radicals;

[0013] The first and second crystal planes are etched by the hydroxyl radicals to obtain a textured structure.

[0014] In one embodiment, the method further includes at least one of the following:

[0015] The pressure of the water vapor ranges from 4×10⁻³ mbar to 6×10⁻³ mbar.

[0016] The texturing power density of the radio frequency power supply ranges from 0.6 W / cm² to 0.8 W / cm².

[0017] The radio frequency power supply generates thermionic electrons using a pulse mode with discharge and non-discharge intervals. The discharge time ranges from 9 to 11 seconds, and the non-discharge time ranges from 4 to 6 seconds.

[0018] The etching time for the hydroxyl radicals to etch the first and second crystal planes ranges from 120s to 140s.

[0019] The etching temperature range for the hydroxyl radicals to etch the first and second crystal planes is 70°C to 80°C.

[0020] In one embodiment, placing the silicon wafer within a transition cavity with a preset vacuum environment includes:

[0021] The silicon wafer is placed inside the transition cavity;

[0022] The transition cavity is evacuated at least once according to a preset vacuum level to create a preset vacuum environment in the transition cavity.

[0023] In one embodiment, the step of evacuating the transition cavity at least once according to a preset vacuum level to create a preset vacuum environment in the transition cavity includes:

[0024] A mechanical pump is used to evacuate the transition chamber for the first time, so that the transition chamber reaches a first preset vacuum level; the value of the first preset vacuum level ranges from 0.9×10-2 mbar to 1.1×10-2 mbar.

[0025] A molecular pump is used to perform a second evacuation of the transition chamber at the first preset vacuum level, so that the transition chamber reaches the second preset vacuum level; the value range of the second preset vacuum level includes 0.9×10-4 mbar to 1.1×10-4 mbar.

[0026] In one embodiment, after placing the silicon wafer within a transition cavity with a preset vacuum environment, the method further includes:

[0027] A sputtering target is provided according to a preset flow rate, and the surface of the silicon wafer is sputtered by the sputtering target to pre-clean the surface of the silicon wafer.

[0028] In one embodiment, the method further includes at least one of the following:

[0029] The preset flow rate of the sputtering target ranges from 50 sccm ± 5 sccm.

[0030] The sputtering power of the sputtering target is 150±10W;

[0031] The sputtering time of the sputtering target is 60±5s.

[0032] In one embodiment, before anisotropically etching the silicon wafer surface using the hydroxyl radicals to obtain the textured structure, the method further includes:

[0033] The silicon wafer is placed in an ozone solution to perform surface cleaning and form an oxide layer on the surface of the silicon wafer.

[0034] The structure obtained by surface cleaning is placed in an alkaline solution of a first preset concentration for isotropic corrosion.

[0035] The structure obtained by isotropic corrosion is placed in an alkaline solution of a second preset concentration for oxide film corrosion.

[0036] The structure obtained by etching the oxide film is placed in a cleaning solution to remove the oxide layer.

[0037] In one embodiment, the method further includes at least one of the following:

[0038] The concentration of the ozone solution ranges from 45 ppm to 55 ppm.

[0039] The first preset concentration ranges from 3% to 3%;

[0040] The corrosion time for the isotropic corrosion ranges from 100s to 150s.

[0041] The second preset concentration ranges from 0.5% to 0.1%.

[0042] The corrosion time for the oxide film corrosion ranges from 220s to 260s.

[0043] The concentration of the cleaning solution ranges from 7% to 1%.

[0044] The peeling time for the oxide layer is in the range of 120s to 140s.

[0045] In one embodiment, the method further includes:

[0046] The surface of the velvet structure is reduced to remove the oxide layer on the surface of the velvet structure.

[0047] In one embodiment, the textured structure includes a first textured structure formed on a first surface of the silicon wafer and a second textured structure formed on a second surface of the silicon wafer; the method further includes:

[0048] A first intrinsic layer, an N-type doped layer, a first conductive layer, and a first electrode are sequentially formed on the first textured surface structure;

[0049] A second intrinsic layer, a P-type doped layer, a second conductive layer, and a second electrode are sequentially formed on the second textured structure.

[0050] The above-mentioned method for preparing a textured silicon wafer involves providing a silicon wafer comprising a first crystal plane and a second crystal plane with different crystal orientations; dissociating deionized water to form hydroxyl radicals; and using these hydroxyl radicals to perform anisotropic etching on the silicon wafer surface to obtain a textured structure. The etching rates of the hydroxyl radicals on the first and second crystal planes are different. By providing a silicon wafer with first and second crystal planes of different crystal orientations, dissociating deionized water to form hydroxyl radicals, and using these hydroxyl radicals to perform anisotropic etching on the silicon wafer surface, the textured structure can be precisely formed on the silicon wafer surface due to the difference in etching rates of the hydroxyl radicals on different crystal planes. This effectively increases the specific surface area of ​​the silicon wafer, enhances its light absorption capacity, and thus improves the photoelectric conversion efficiency. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the fabrication process of heterojunction solar cells in related technologies;

[0053] Figure 2 This is a schematic diagram of the structure of a heterojunction solar cell in one embodiment;

[0054] Figure 3 for Figure 2 Enlarged view of point A in the middle;

[0055] Figure 4 This is a schematic flowchart of a method for preparing the textured surface of a silicon wafer in one embodiment;

[0056] Figure 5 This is a schematic diagram of the process for obtaining the velvet structure in one embodiment;

[0057] Figure 6 This is a schematic diagram of the wet cleaning process in one embodiment;

[0058] Figure 7 This is a schematic diagram of the fabrication process of a heterojunction solar cell in an application example.

[0059] Figure 8 This is a schematic diagram of the composite process for preparing a velvety structure in an application example;

[0060] Figure 9 This is a schematic diagram illustrating the performance test parameters of different processes in an application example.

[0061] Explanation of reference numerals in the attached figures:

[0062] Silicon wafer 110, first intrinsic layer 121, N-type doped layer 131, first conductive layer 141, first electrode 151, first textured structure 161, second intrinsic layer 122, P-type doped layer 132, second conductive layer 142, second electrode 152, second textured structure 162. Detailed Implementation

[0063] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0065] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0066] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0067] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0068] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0069] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the invention.

[0070] As described in the background section, traditional heterojunction solar cells suffer from low photoelectric conversion efficiency. The inventors discovered that this problem arises because traditional heterojunction solar cells have a symmetrical bifacial structure. The central element is N-type crystalline silicon. An intrinsic amorphous silicon thin film and an N-type microcrystalline thin film are sequentially deposited on the front side of the N-type crystalline silicon to form a PN junction. On the back side, an intrinsic amorphous silicon thin film and a P-type microcrystalline thin film are sequentially deposited to form a back surface field. Given the poor conductivity of amorphous silicon, transparent conductive oxides (TCOs) are typically deposited on both sides of the solar cell for conductivity. Finally, screen printing technology is used to form the bifacial electrodes.

[0071] like Figure 1 As shown, the fabrication process of heterojunction solar cells typically involves steps such as initial polishing, gettering, texturing and cleaning (wet texturing), CVD (Chemical Vapor Deposition) coating, PVD (Physical Vapor Deposition) coating, and screen printing. The texturing step requires cleaning the N-type silicon wafer, texturing, and removing surface contaminants, metallic substances, and mechanically damaged layers to obtain a clean silicon wafer. However, due to the unique structure of heterojunction solar cells, the surface of the silicon substrate is directly part of the heterojunction interface. Therefore, a clean silicon surface is necessary to avoid carrier recombination at the junction interface caused by defects and impurities introduced by uncleanliness. The alkaline texturing (pyramidal texture) of traditional monocrystalline silicon solar cells will destroy the uniformity of the amorphous silicon layer, resulting in interface defects. After acid (HF) corrosion, the micropores remaining on the surface make it difficult to completely cover them during amorphous silicon deposition, causing the interface defect density to soar and Voc (Open Circuit Voltage) and FF (Fill Factor) to decrease significantly.

[0072] Based on the above reasons, this application provides a texturing preparation scheme for silicon wafers that can achieve low interface defects and improved reflectivity uniformity. It employs plasma-activated texturing and hydrogen plasma to replace acid in removing the oxide layer, combining wet cleaning and dry etching into a composite process to provide a high-quality substrate for subsequent CVD film deposition. During wet cleaning, the cleaning solution removes the damaged layer on the silicon wafer surface, resulting in a clean wafer surface. During dry etching, plasma dissociates water vapor to generate active free radicals. Through the diffusion of these active free radicals, anisotropic etching is achieved on the silicon wafer surface, forming a nanoscale pyramidal texturing structure. The subsequent removal of the oxide layer helps reduce the reflectivity of the heterojunction solar cell, while simultaneously improving the uniformity of reflectivity and enhancing light-harvesting capabilities.

[0073] In some embodiments, such as Figure 2 As shown, the heterojunction solar cell provided in this embodiment includes a silicon wafer 110, with a first intrinsic layer 121, an N-type doped layer 131, a first conductive layer 141, and a first electrode 151 sequentially stacked on the first surface of the silicon wafer 110, and a second intrinsic layer 122, a P-type doped layer 132, a second conductive layer 142, and a second electrode 152 sequentially stacked on the second surface of the silicon wafer 110. The first surface of the silicon wafer 110 is located on the front side of the silicon wafer 110, and the second surface of the silicon wafer 110 is located on the back side of the silicon wafer 110, with the first and second surfaces of the silicon wafer 110 arranged opposite to each other.

[0074] like Figure 3 As shown, a first textured surface 161 is formed on the first surface using a composite process of wet cleaning and dry etching. Similarly, a second textured surface 162 is simultaneously formed on the second surface using the same composite process. The first textured surface 161 and the second textured surface 162 together form a pyramid textured surface structure. Taking the first textured surface 161 as an example, the first textured surface 161 includes multiple pyramid units. Each pyramid unit has a uniform size and shape, and the pyramid units are closely arranged and interconnected to form the textured surface structure.

[0075] In some embodiments, to improve the photoelectric conversion efficiency of heterojunction solar cells, such as Figure 4 As shown, a method for preparing a textured surface on a silicon wafer is provided, comprising steps 402 to 404. Wherein:

[0076] Step 402, providing a silicon wafer; the silicon wafer includes a first crystal plane and a second crystal plane having different crystal orientations.

[0077] The silicon wafer can be made using a single-crystal silicon wafer. This wafer has a first surface and a second surface disposed opposite to each other. Both the first and second surfaces include exposed first and second crystal planes, which have different crystal orientations. For example, the first crystal plane could be... <100> Crystal orientation, the second crystal plane can be <110> Crystal orientation.

[0078] Optionally, N-type crystalline silicon can be used as the silicon wafer. In practice, the surface of the silicon wafer can be mechanically ground, polished, or pre-etched to expose different crystal orientations on the first and second surfaces of the silicon wafer.

[0079] Step 404: Deionized water is dissociated to form hydroxyl radicals, and the silicon wafer surface is anisotropically etched by the hydroxyl radicals to obtain a textured structure.

[0080] Deionized water is deionized to form hydroxyl radicals. For example, plasma can be generated using a plasma generator, and the plasma can collide with molecules in the deionized water, thereby dissociating hydroxyl radicals, hydrogen radicals, and other active substances from the deionized water. In some optional embodiments, photocatalysis, electrochemistry, or other methods can also be used to excite hydroxyl radicals in the deionized water.

[0081] Because hydroxyl radicals have different etching rates on the first and second crystal planes, the generated hydroxyl radicals can be guided to or brought into contact with the first and second surfaces of the silicon wafer, allowing them to react with the first and second crystal planes. For example, the etching rate of hydroxyl radicals on the first crystal plane is greater than that on the second crystal plane. This causes the first crystal plane, with its faster etching rate, to be consumed more quickly, potentially generating reactive substances, while the second crystal plane, with its slower etching rate, is etched more slowly and becomes relatively prominent. This results in a textured structure composed of tiny protrusions and depressions on the first and second surfaces, increasing their specific surface area.

[0082] The above-mentioned method for preparing a textured silicon wafer involves providing a silicon wafer comprising a first crystal plane and a second crystal plane with different crystal orientations; dissociating deionized water to form hydroxyl radicals; and using these hydroxyl radicals to perform anisotropic etching on the silicon wafer surface to obtain a textured structure. The etching rates of the hydroxyl radicals on the first and second crystal planes are different. By providing a silicon wafer with first and second crystal planes of different crystal orientations, dissociating deionized water to form hydroxyl radicals, and using these hydroxyl radicals to perform anisotropic etching on the silicon wafer surface, the textured structure can be precisely formed on the silicon wafer surface due to the difference in etching rates of the hydroxyl radicals on different crystal planes. This effectively increases the specific surface area of ​​the silicon wafer, enhances its light absorption capacity, and thus improves the photoelectric conversion efficiency.

[0083] In some embodiments, such as Figure 5 As shown, deionized water is dissociated to form hydroxyl radicals, and these hydroxyl radicals are used to anisotropically etch the silicon wafer surface to obtain a textured structure, including:

[0084] Step 502: Place the silicon wafer in a transition cavity with a preset vacuum environment.

[0085] Specifically, the silicon wafer can be placed in the transition cavity of a vacuum processing system, and the transition cavity can be evacuated to a preset vacuum level to obtain a preset vacuum environment. The preset vacuum level in the transition cavity is maintained so that water vapor can exist in multiple forms after injection and so as to facilitate the stable generation of plasma.

[0086] Step 504: Deionized water is heated to generate water vapor, and the water vapor is injected into the transition cavity; the water vapor contains water molecules in various forms.

[0087] Specifically, after a preset vacuum environment is established in the transition chamber, deionized water can be heated to above its boiling point, such as 100°C to 150°C, using a steam generator or heating equipment to generate water vapor. This water vapor is then injected into the transition chamber at a certain flow rate. Because the transition chamber is a preset vacuum environment, the water vapor exists in a mixed state in various forms, such as monomeric water molecules (H2O), dimers (H2O)2, and trimers (H2O)3. The ratio of monomeric water molecules (H2O), dimers (H2O)2, and trimers (H2O)3 can be 68%:25%:7%, providing a reaction source for the generation of hydroxyl radicals in subsequent processes.

[0088] Optionally, the concentration of water molecules in the transition chamber can be controlled by adjusting the pressure of the water vapor, thereby suppressing the concentration of subsequently formed hydroxyl radicals. Specifically, when water vapor is introduced into the transition chamber, the pressure of the water vapor can range from 4 × 10⁻⁶. -3 mbar~6×10 -3 mbar, specifically the pressure of water vapor can be 4 × 10 mbar. - 3 mbar, 4.5×10 -3 mbar, 5×10 -3 mbar, 5.5×10 -3 mbar, 6×10 -3 mbar or any value between these values.

[0089] Step 506: Thermionic electrons generated by the radio frequency power supply dissociate water molecules to obtain hydroxyl radicals.

[0090] Specifically, a radio frequency power supply is installed in the transition cavity, such as around or on top of the transition cavity. After the radio frequency power supply is turned on, an alternating electric field can be formed in the transition cavity. This alternating electric field can accelerate the movement of free electrons in the transition cavity, so that the free electrons can gain energy and form hot electrons. During the movement, the hot electrons can collide with water vapor molecules of various forms in the transition cavity. During the collision, the water vapor molecules can absorb the energy of the hot electrons and dissociate to generate hydroxyl radicals and hydrogen radicals.

[0091] Optionally, the etching rate can be reduced by controlling the texturing power density of the RF power supply, thereby decreasing the height of each pyramid unit in the texturized structure. Specifically, the texturing power density of the RF power supply can range from 0.6 W / cm². 2 ~0.8W / cm 2 Specifically, the texturing power density of the RF power supply can be 0.6 W / cm². 2 0.65W / cm 20.7W / cm 2 0.75W / cm 2 0.8W / cm 2 Or any value between these values.

[0092] Optionally, the uniformity of each pyramid unit in the textured structure can be adjusted by controlling the pulse mode of the RF power supply. For example, the RF power supply can be controlled to generate hot electrons using a pulse mode with discharge and non-discharge intervals to precisely control the generation and concentration distribution of hydroxyl radicals, avoiding excessively fast or slow local etching rates caused by continuous discharge. This results in pyramid units in different regions of the silicon wafer surface being more uniform in size and morphology. In specific implementation, the discharge time ranges from 9 to 11 seconds, specifically 9 seconds, 9.5 seconds, 10 seconds, 10.5 seconds, 11 seconds, or any value between these values; the non-discharge time ranges from 4 to 6 seconds, specifically 4 seconds, 4.5 seconds, 5 seconds, 5.5 seconds, 6 seconds, or any value between these values.

[0093] Step 508: The first and second crystal planes are etched by hydroxyl radicals to obtain a textured structure.

[0094] Specifically, after hydroxyl radicals are generated, they can be accelerated or diffused to the first and second surfaces of the silicon wafer by an alternating electric field formed within the transition cavity. Taking the first surface as an example, the hydroxyl radicals can react with silicon atoms on the first surface. Since the first surface has first and second crystal planes with different crystal orientations, the hydroxyl radicals can etch the first and second crystal planes respectively to form a textured structure. In specific implementation, the first crystal plane is... <100> Crystal plane, the second crystal plane is <110> Crystal planes, hydroxyl radicals in the transition cavity <100> The etching rate of the crystal plane is much greater than that of the crystal surface. <110> Etching of crystal planes. The atomic density of silicon atoms in the first crystal plane can be 6.78 × 10⁻⁶. 14 cm -2 Each silicon atom has two suspensions, and the activation potential of the silicon atom is 0.8 eV. Hydroxyl radicals can rapidly bombard the silicon atoms on the first crystal plane, generating the volatile substance Si(OH)4. The reaction rate of the hydroxyl radicals with the first crystal plane is approximately 400 nm / min. The atomic density of silicon atoms in the second crystal plane can be 7.83 × 10⁻⁶. 14 cm -2The silicon atoms are densely packed, and the activation efficiency of silicon atoms can reach 1.5 eV. The rate at which hydroxyl radicals bombard silicon atoms on the second crystal plane to generate volatile substances Si(OH)4 is relatively low, about 40 nm / min. Thus, the first crystal plane region is consumed and recessed more quickly, while the second crystal plane region is relatively raised due to slower etching, so as to form an uneven structure on the first surface. For example, it can be a pyramid-like, inverted pyramid, groove or other irregular uneven structure, i.e., a textured structure. This textured structure can effectively reduce the light reflectivity of the silicon wafer surface and increase the light absorption path inside the silicon wafer, thereby helping to improve the photoelectric conversion efficiency of the heterojunction solar cell based on this silicon wafer.

[0095] Optionally, the etching depth can be controlled by adjusting the etching time of the hydroxyl radicals etching the first and second crystal planes. Specifically, the etching time of the hydroxyl radicals etching the first and second crystal planes ranges from 120s to 140s. Specifically, the etching time can be 120s, 125s, 130s, 135s, 140s, or any value between these values.

[0096] Optionally, thermal stress on the silicon wafer can be reduced by controlling the etching temperature at which hydroxyl radicals etch the first and second crystal planes. Specifically, the etching temperature range for hydroxyl radicals etching the first and second crystal planes is 70°C to 80°C; more specifically, the etching temperature can be 70°C, 75°C, 80°C, or any value between these values.

[0097] In this embodiment, the silicon wafer is placed in a transition cavity with a preset vacuum environment, and water vapor generated by heated deionized water is injected. The water vapor contains water molecules in various forms. Furthermore, thermionic electrons are generated by the radio frequency power supply to dissociate the water molecules and generate hydroxyl radicals. The hydroxyl radicals can be used to precisely etch the first and second crystal planes of the silicon wafer to obtain a textured structure. The entire process does not introduce corrosive solutions, which can effectively reduce battery defects caused by residual micropores on the surface after solution etching, thereby optimizing the surface microstructure of the silicon wafer and improving the efficiency of the battery cell.

[0098] In some embodiments, placing the silicon wafer within a transition cavity with a preset vacuum environment includes:

[0099] Place the silicon wafer in the transition cavity; evacuate the transition cavity at least once according to the preset vacuum level to create the preset vacuum environment in the transition cavity.

[0100] Specifically, the silicon wafer can be placed on a sample holder within the transition cavity of the vacuum processing system. In practice, this sample holder can be an electrostatic chuck or a mechanical chuck, used to securely hold the silicon wafer and prevent displacement during subsequent vacuuming or processing. Optionally, before placing the silicon wafer into the transition cavity, the interior of the transition cavity can be pre-treated, for example, by purging the transition cavity with an inert gas (such as nitrogen or argon) to remove any residual contaminants or moisture.

[0101] To establish a predetermined vacuum environment within the transition cavity, at least one evacuation process can be performed. Specifically, a multi-stage evacuation method can be employed to create a stable and clean predetermined vacuum environment within the transition cavity. For example, a mechanical pump can be used to perform a first evacuation of the transition cavity, achieving a first predetermined vacuum level; then, a molecular pump can be used to perform a second evacuation, achieving a second predetermined vacuum level. During the first evacuation, since the transition cavity is almost at atmospheric pressure, the mechanical pump can quickly reduce the pressure from atmospheric pressure to a relatively low rough vacuum level, i.e., the first predetermined vacuum level, to rapidly remove a large amount of air and most gaseous contaminants from the transition cavity. During the second evacuation, after the transition cavity reaches the first predetermined vacuum level, a molecular pump can be used to further reduce the pressure to a high vacuum or ultra-high vacuum level, i.e., the second predetermined vacuum level, to further remove residual gas molecules within the cavity, thereby ensuring the quality of subsequent etching.

[0102] Optionally, the range of the first preset vacuum degree includes 0.9 × 10⁻⁶. -2 mbar ~ 1.1 × 10 -2 mbar; specifically, the first preset vacuum level can be 0.9 × 10 mbar. -2 mbar, 1.0×10 -2 mbar, 1.1×10 -2 mbar or any value between these values. The second preset vacuum level can range from 0.9 × 10⁻⁶ mbar. -4 mbar ~ 1.1 × 10 -4 mbar; specifically, the first preset vacuum level can be 0.9 × 10 mbar. -4 mbar, 1.0×10 -4 mbar, 1.1×10 -4 mbar or any value between these values.

[0103] In this embodiment, by performing a vacuuming operation at least once at a preset vacuum level, it is beneficial to establish a preset vacuum environment and ensure the subsequent etching quality.

[0104] In some embodiments, after placing the silicon wafer in a transition cavity with a preset vacuum environment, the method for preparing the textured surface of the silicon wafer further includes:

[0105] The sputtering target is supplied according to the preset flow rate, and the surface of the silicon wafer is sputtered by the sputtering target to pre-clean the surface of the silicon wafer.

[0106] Specifically, after fixing the silicon wafer onto the sample carrier fixture in the transition cavity, the silicon wafer can be further pre-cleaned to reduce the oxygen content on the wafer surface. The sputtering target can be argon gas. In practice, argon gas can be introduced into the sputtering wall, and the argon gas flow rate can be adjusted. The sputtering power and sputtering time can be set, and the sputtering power supply can be started. The generated argon ions can be accelerated and bombarded on the silicon wafer surface under the action of an electric field. Through the physical sputtering effect, adsorbed oxygen atoms, oxide films, and other impurities on the silicon wafer surface are removed, thus achieving the purpose of pre-cleaning.

[0107] Optionally, to control the pre-cleaning time, the preset flow rate of the sputtering target can be adjusted. In practice, the preset flow rate of the sputtering target can range from 50 sccm ± 5 sccm; specifically, the preset flow rate of the sputtering target can be 45 sccm, 48 sccm, 50 sccm, 52 sccm, 55 sccm, or any value between these values.

[0108] Optionally, to control the pre-cleaning process, the sputtering power of the sputtering target can be adjusted. In practice, the sputtering power of the sputtering target is 150±10W; specifically, the sputtering power of the sputtering target can be 140W, 145W, 150W, 155W, 160W, or any value between these values.

[0109] Optionally, to compensate for the passivation requirements of the flat surface, the sputtering time of the sputtering target can be adjusted. In a specific implementation, the sputtering time of the sputtering target is 60±5s; specifically, the sputtering time of the sputtering target can be 55s, 57s, 60s, 63s, 65s, or any value between these values.

[0110] In this embodiment, by providing a sputtering target and using the sputtering target to perform sputtering operations on the silicon wafer surface, the oxygen content on the silicon wafer surface can be effectively reduced, achieving pre-cleaning of the silicon wafer surface and providing a silicon wafer surface with higher cleanliness for subsequent dry etching, which is beneficial to improving the quality of subsequent processes.

[0111] In some embodiments, such as Figure 6 As shown, before obtaining the textured structure by anisotropic etching of the silicon wafer surface using hydroxyl radicals, the texturing process for silicon wafers also includes:

[0112] Step 602: Place the silicon wafer in an ozone solution to clean the surface of the silicon wafer and form an oxide layer on the surface of the silicon wafer.

[0113] Specifically, ozone solution is prepared by passing high-purity oxygen into an ozone generator to produce ozone, and then passing the ozone into deionized water. The silicon wafer is then placed in the ozone solution. During the immersion process, ozone acts as a strong oxidant. On one hand, ozone decomposes into highly oxidizing single oxygen and hydroxyl groups, dissolving microorganisms and some organic matter on the silicon wafer surface, thereby removing metallic impurities and the microcrystalline film layer, effectively cleaning the silicon wafer surface. On the other hand, ozone also reacts with silicon atoms on the silicon wafer surface, oxidizing it. After immersion, the silicon wafer is removed from the ozone solution and can be further rinsed with a large flow of ultrapure water to remove residual ozone solution and reaction products.

[0114] Optionally, to control the degree of oxidation of the silicon wafer surface by the ozone solution, this can be achieved by controlling the concentration of the ozone solution. Specifically, the concentration of the ozone solution can range from 45 ppm to 55 ppm; more specifically, the concentration of the ozone solution can be 45 ppm, 47 ppm, 50 ppm, 53 ppm, 55 ppm, or any value between these values.

[0115] Step 604: The structure obtained by surface cleaning is placed in an alkaline solution of a first preset concentration for isotropic corrosion.

[0116] Specifically, an alkaline solution of a first preset concentration can be prepared, such as NaOH or KOH. Then, the silicon wafer that has been surface-cleaned is placed in the alkaline solution of the first preset concentration, and the alkaline solution is used to perform isotropic etching on the surface of the silicon wafer, that is, the first and second crystal planes on the surface of the silicon wafer are etched away at approximately the same rate, so as to remove a silicon layer of a certain thickness, thereby removing mechanical damage layers, cracks, silicon powder particles, etc. from the surface of the silicon wafer.

[0117] Optionally, to ensure that the alkaline solution can isotropically corrode the first and second crystal planes, the first preset concentration is greater than or equal to 3%; specifically, the first preset concentration can be 3%, 4%, 5%, or any value between or greater than 5%.

[0118] Optionally, to control the amount of corrosion on the silicon wafer surface, the corrosion time for isotropic etching can range from 100s to 150s; specifically, the corrosion time for isotropic etching can be 100s, 110s, 120s, 135s, 150s, or any value between these values.

[0119] Step 606: The structure obtained by isotropic corrosion is placed in an alkaline solution of a second preset concentration for oxide film corrosion.

[0120] Specifically, a second preset concentration of alkaline solution can be prepared, which can be NaOH, H2O2, etc. Then, the silicon wafer that has undergone isotropic etching is placed in the second preset concentration of alkaline solution. The second preset concentration of alkaline solution can be a mixture of NaOH and H2O2. The oxide film formed by H2O2 removes impurities such as organic matter and particulate matter remaining on the surface of the silicon wafer during the etching process in step 604. Then, the oxide film generated is removed by the etching action of NaOH. At the same time as the oxide film is removed, the impurities on the surface of the silicon wafer also fall off, thereby achieving the purpose of removing organic matter, particulate matter, and other impurities from the surface of the silicon wafer.

[0121] Optionally, to effectively remove organic matter, particles, and other impurities from the silicon wafer surface, the second preset concentration can range from 0.5% ± 0.1%; the etching time for oxide film etching can range from 220s to 260s; specifically, the second preset concentration can be 0.4%, 0.45%, 0.5%, 0.55%, 0.6%, or any value between these values, and the etching time for oxide film etching can be 220s, 230s, 240s, 250s, 260s, or any value between these values.

[0122] Step 608: The structure obtained by etching the oxide film is placed in a cleaning solution to remove the oxide layer.

[0123] Specifically, a cleaning solution can be prepared at a certain concentration, such as HF. Then, the silicon wafer that has undergone oxide film etching is placed in the cleaning solution of this concentration, causing the metal adhering to the surface of the silicon wafer to detach along with the oxide layer, thereby removing the metal from the surface of the silicon wafer.

[0124] Optionally, to ensure effective oxide layer removal, the concentration of the cleaning solution can range from 7% ± 1%, and the removal time can range from 120s to 140s. Specifically, the concentration of the cleaning solution can be 6%, 6.5%, 7%, 7.5%, 8%, or any value between these values, and the removal time can be 120s, 125s, 130s, 135s, 140s, or any value between these values.

[0125] In this embodiment, the cleaning method for the silicon wafer in each step is a wet cleaning step. Optionally, before this, the silicon wafer can be initially polished and then gouged to expose the first and second crystal planes on the surface of the silicon wafer.

[0126] In this embodiment, the silicon wafer is first cleaned with an ozone solution to form an oxide layer, which can efficiently remove surface impurities. Then, an isotropic etching process is used with a first preset concentration alkaline solution to remove the damaged layer on the surface and optimize the surface structure. Next, an alkaline solution with a second preset concentration is used to etch the oxide film to remove impurities on the silicon wafer surface. Finally, a cleaning solution is used to peel off the oxide layer, which can thoroughly clean the silicon wafer, improve the surface quality and purity of the silicon wafer, and facilitate subsequent dry etching processes.

[0127] In some embodiments, the method for preparing the textured surface of a silicon wafer further includes:

[0128] The surface of the suede structure is reduced to remove the oxide layer on the surface of the suede structure.

[0129] Specifically, hydrogen plasma can be used to selectively reduce the surface of the textured structure to remove the oxide layer. The textured surface is a SiO2 layer. During the reduction process, the added hydrogen gas is ionized into hydrogen plasma (H-). The hydrogen plasma diffuses to the textured surface, bombards the Si-O bonds in the SiO2 layer and forms Si-OH and Si-H bonds, which dehydrate to generate H2O, causing the oxide layer to expand and fall off.

[0130] Optionally, to ensure the effectiveness of oxide layer removal, the hydrogen concentration can range from 15% ± 2%; the hydrogen flow rate can range from 150 sccm ± 20 sccm; and the process time for oxide layer removal using hydrogen can range from 80 s ± 10 s. Specifically, the hydrogen concentration can be 13%, 14%, 15%, 16%, 17%, or any value between these values; the hydrogen flow rate can be 130 sccm, 140 sccm, 150 sccm, 160 sccm, 170 sccm, or any value between these values; and the process time for oxide layer removal using hydrogen can be 70 s, 75 s, 80 s, 85 s, 90 s, or any value between these values.

[0131] In this embodiment, the reduction treatment of the velvety structure surface can effectively remove the oxide layer on the velvety structure surface, thereby improving its surface quality and increasing the reliability of subsequent film deposition.

[0132] In some embodiments, the textured structure includes a first textured structure formed on a first surface of the silicon wafer and a second textured structure formed on a second surface of the silicon wafer; the method further includes:

[0133] A first intrinsic layer, an N-type doped layer, a first conductive layer, and a first electrode are sequentially formed on the first textured structure; a second intrinsic layer, a P-type doped layer, a second conductive layer, and a second electrode are sequentially formed on the second textured structure.

[0134] The first intrinsic layer is deposited on the side of the first textured structure away from the first surface, and the second intrinsic layer is deposited on the side of the second textured structure away from the second surface. The first and second intrinsic layers can be used to achieve the separation and transport of photogenerated carriers. Specifically, the first and second intrinsic layers can be made of amorphous silicon (a-Si) or doped amorphous silicon materials.

[0135] An N-type doped layer is deposited on the side of the first intrinsic layer away from the first textured surface. The N-type doped layer can form a PN heterojunction with the first intrinsic layer to achieve electron extraction and transport. Specifically, the N-type doped layer can be made of microcrystalline silicon. Further, the N-type doped layer can be obtained by doping the intrinsic microcrystalline semiconductor material with impurities having more than 4 valence electrons (such as phosphorus, arsenic, antimony, etc.). A P-type doped layer is deposited on the side of the second intrinsic layer away from the second textured surface. The P-type doped layer can form a back surface field with the second intrinsic layer to suppress the recombination of photogenerated carriers (mainly holes) on the back surface, while promoting hole transport to the electrode. Specifically, the P-type doped layer can be made of microcrystalline silicon. Further, the P-type doped layer can be obtained by doping the intrinsic microcrystalline semiconductor material with impurities having fewer than 4 valence electrons (such as boron, aluminum, gallium, indium, etc.).

[0136] The first conductive layer is deposited on the side of the N-type doped layer away from the first intrinsic layer, and the second conductive layer is deposited on the side of the P-type doped layer away from the second intrinsic layer. The first and second conductive layers are used to collect and transport photogenerated carriers. Specifically, the first and second conductive layers can be made of TCO (Transparent Coated Carbon). Because TCO has high transmittance and low resistivity, it has extremely high transmittance in the visible light range, allowing most sunlight to penetrate the TCO and reach the internal film layers, where it is effectively absorbed and converted into electrical energy.

[0137] The first electrode is formed on the side of the first conductive layer away from the N-type doped layer, and the second electrode is formed on the side of the second conductive layer away from the P-type doped layer. The first and second electrodes can serve as connection terminals for external circuits to achieve the output of photocurrent. Specifically, the first and second electrodes can be obtained using metallic materials (such as aluminum, silver, copper, etc.) through evaporation, sputtering, or printing processes.

[0138] In one application example, such as Figure 7 The diagram illustrates the process flow for fabricating heterojunction solar cells, including texturing the silicon wafer surface using a composite process of wet cleaning and dry texturing. Specifically, the heterojunction solar cell fabrication method provided in this example includes the following steps:

[0139] S11. Initial polishing. A silicon wafer is provided, and the first and second surfaces of the silicon wafer are initially polished to expose the first and second crystal planes included in the first and second surfaces, respectively.

[0140] S12. Gettering. Gettering is performed on the silicon wafers after initial polishing to remove metallic impurities and defects within the wafer, thereby improving the minority carrier lifetime of the silicon wafers.

[0141] S13. Wet cleaning. A wet cleaning process is used to clean the silicon wafers after gettering to obtain silicon wafers with clean surfaces and no impurities.

[0142] S14. Dry texturing. A dry texturing process is used to texture the silicon wafer after wet cleaning to form a first texturing structure on a first surface and a second texturing structure on a second surface.

[0143] S15. Coating. CVD, PVD and other coating processes are used to sequentially form a first intrinsic layer, an N-type doped layer and a first conductive layer on the first textured structure, and a second intrinsic layer, a P-type doped layer and a second conductive layer on the second textured structure.

[0144] S16. Screen printing. A first electrode is printed on the first conductive layer and a second electrode is printed on the second conductive layer using screen printing technology to obtain a heterojunction solar cell.

[0145] Furthermore, such as Figure 8 The diagram illustrates the process flow of a composite process involving wet cleaning and dry texturing in the fabrication of heterojunction solar cells, specifically including:

[0146] S21, Pre1 (Pre-Clean1, pre-cleaning, i.e., pre-cleaning of wet processes).

[0147] Specifically, the silicon wafer is placed in an ozone solution with a concentration of 50 ppm. Ozone's strong oxidizing properties allow it to decompose into extremely strong single oxygen (O) and hydroxyl (OH) atoms, thereby decomposing contaminants and oxides on the silicon wafer surface. This process dissolves microorganisms and some organic matter, and removes metallic impurities and microcrystalline films from the silicon wafer surface.

[0148] S22, SDC (Silicon Damage Etch).

[0149] Specifically, the pre-cleaned silicon wafer is immersed in an alkaline solution (such as NaOH) with a concentration greater than 3% for 130 seconds. The high concentration of alkaline solution is used to perform isotropic etching on each crystal orientation of the silicon wafer, thereby removing the mechanical damage layer, cracks, and silicon powder particles on the surface of the silicon wafer.

[0150] S23, SC1 (Standard Clean 1).

[0151] Specifically, the SDC-treated silicon wafers are immersed in a 0.5% NaOH solution for 240 seconds. H2O2 is added to the NaOH solution. During the immersion process, the surface of the silicon wafer is oxidized by H2O2 to form an oxide film. While part of the oxide film is corroded by NaOH, the particulate matter attached to the surface of the silicon wafer is detached along with the oxide film, thereby achieving the purpose of removing organic matter, particles and other impurities from the surface of the silicon wafer.

[0152] S24, Final (Final Cleaning).

[0153] Specifically, the silicon wafers after standard cleaning are immersed in a 7% HF solution for 130 seconds. During the immersion process, the oxide layer on the surface of the silicon wafer falls off, and at the same time, the metal attached to the surface of the silicon wafer also falls into the HF solution along with the oxide layer, thereby achieving the purpose of removing the metal attached to the surface of the silicon wafer.

[0154] S25, Drying.

[0155] Specifically, inert gas can be used to dry the surface of the silicon wafer.

[0156] S26. Dry pre-cleaning.

[0157] Specifically, the dried silicon wafer is placed in the transition chamber, and a mechanical pump is used to evacuate the pressure in the transition chamber to 10. - 2 mbar, and then a molecular pump is used to further evacuate the pressure in the transition chamber to 10 mbar. -4 mbar, then Ar+ is sputtered onto the silicon wafer surface at a sputtering power of 150W for 60s to reduce the oxygen content on the silicon wafer surface and prevent oxidation.

[0158] S27, Plasma active fabrication.

[0159] Specifically, deionized water is heated to produce saturated water vapor, and then... -3 A pressure of mbar injects water vapor into the transition chamber. The water vapor exists in a low-pressure (vacuum) environment within the transition chamber as a mixture of 68% monomeric H₂O, 25% dimer (H₂O)₂, and 7% trimer (H₂O)₃, providing a reaction source for the generation of active free radicals. Further, the temperature within the transition chamber is adjusted to 75°C, the radio frequency power supply is activated, and the texturing power density of the radio frequency power supply is controlled to 0.7 W / cm². 2 The radio frequency power supply operates in pulse mode, which starts in 10 seconds and stops in 5 seconds. Texturing takes 130 seconds. The radio frequency power supply can generate hot electrons (plasma) to collide and dissociate water molecules to generate active free radicals, namely hydroxyl radicals. Through hydroxyl radicals, anisotropic etching is achieved on the silicon wafer surface to form a nanoscale pyramid textured surface structure.

[0160] S28, hydrogen plasma deoxidation layer.

[0161] Specifically, H2 with a concentration of 15% is injected into the transition cavity for 80 seconds. Inside the transition cavity, H2 is ionized into hydrogen plasma (H-). The hydrogen plasma diffuses to the surface of the textured structure and bombards the Si-O bonds in the SiO2 layer to form Si-OH and Si-H. Dehydration generates H2O, causing the oxide layer to expand and fall off.

[0162] In the above process, by improving the traditional wet texturing method, a wet process is used to clean the silicon wafer surface. The wet process only cleans the silicon wafer surface, which can optimize the number of wet tanks used, reduce chemical consumption, and reduce wastewater pollution. Then, a dry process is added to texturize the silicon wafer surface, which can optimize the surface microstructure, reduce battery defects caused by residual micropores after acid corrosion, and improve cell efficiency. The combination of wet and dry processes is less expensive than conventional all-dry texturing, can reduce dry processing time to increase overall production capacity, and can also improve the uniformity of the texturized surface and reduce the extreme reflectivity.

[0163] Therefore, the method of this application has the following advantages over conventional flocking methods:

[0164] Firstly, surface cleanliness is optimized: the wet process in this application is only used to remove the damaged layer (contact time <10 minutes), and the subsequent dry process is operated in a vacuum environment, which can avoid cross-contamination in the wet process tank, resulting in higher cleanliness of the silicon wafer surface.

[0165] Secondly, uniformity of the pile surface: the size deviation of each pyramid unit in the pile surface structure formed by the composite process is only ±0.3um, which is 5 times more accurate than the size of the pyramid unit in the pile surface structure obtained by the traditional process (±1.5um).

[0166] Third, reflectivity controllability: It can achieve different reflectivities for different experimental needs in the R&D line, down to as low as 5%, and the reflectivity uniformity is improved, with the range controllable within 0.5%.

[0167] Fourth, control of wafer fragmentation rate: The wet process silicon wafer is in contact with the liquid in the chemical bath for about 30 minutes, and there are working methods such as bubbling and circulation in the bath to ensure the uniformity of the chemical solution, which can easily cause fragmentation; the composite process greatly reduces the contact time with the chemical solution, and the fragmentation rate is reduced from 0.1% to 0.02%, a reduction of 80%.

[0168] Fifth, passivation effect: the surface composite rate of the composite process is <10cm / s, while that of the all-wet process is >100cm / s. The key to improving Voc lies in dry deoxidation to ensure interface quality.

[0169] Sixth, environmental friendliness of the process: reducing the number of wet process tanks can effectively reduce waste liquid discharge.

[0170] Furthermore, to verify the advantages of the textured structure preparation method of this application, battery cells prepared using traditional processes were used as the base group (i.e., base), and battery cells prepared using the preparation process of this application were used as the experimental group (i.e., SY). Multiple rounds of verification (5 rounds) were conducted. In each round of verification, both the base group and the experimental group included multiple battery cells. Through verification, the performance test parameters of the base group and the experimental group in each verification round were measured. The performance test parameters included Eta (photovoltaic conversion efficiency, %), Voc (open-circuit voltage, in V), Isc (short-circuit current, in A), FF (fill factor, %), Rs (series resistance, in mΩ), Rsh (parallel resistance, in Ω), IRev2 (reverse current, in A), maximum Eta value, standard deviation of Eta, and median of Eta. Specific parameters are as follows: Figure 9 As shown in the table, it can be seen that the solar cells prepared using the process of this application have a photoelectric conversion efficiency that is 0.05% to 0.1% higher than those prepared using conventional processes, and both Voc and FF are significantly improved.

[0171] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0172] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0173] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0174] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of texturing a silicon wafer, characterized by, The method comprises: providing a silicon wafer; the silicon wafer comprises a first crystal surface and a second crystal surface with different crystal orientations; dissociating deionized water to form hydroxyl radicals, and performing anisotropic etching on the surface of the silicon wafer by the hydroxyl radicals to obtain a textured structure; wherein the etching rate of the hydroxyl radicals on the first crystal surface and the second crystal surface is different.

2. The method of claim 1, wherein, The method of dissociating deionized water to form hydroxyl radicals, and performing anisotropic etching on the surface of the silicon wafer by the hydroxyl radicals to obtain a textured structure comprises: placing the silicon wafer in a transition chamber in a predetermined vacuum environment; heating the deionized water to generate water vapor, and injecting the water vapor into the transition chamber; the water vapor contains water molecules in multiple forms; dissociating the water molecules by hot electrons generated by a radio frequency power source to obtain hydroxyl radicals; etching the first crystal surface and the second crystal surface by the hydroxyl radicals to obtain a textured structure.

3. The method of claim 2, wherein, The method further comprises at least one of the following: The water vapor pressure is in the range of 4 x 10 -3 mbar to 6 x 10 -3 mbar. The range of the silvering power density of the radio frequency power source includes 0.6 W / cm 2 0.8 W / cm 2 ; The radio frequency power source generates hot electrons in pulse mode with discharging and non-discharging intervals, the discharging time is in the range of 9-11s, and the non-discharging time is in the range of 4-6s; The etching time of the hydroxyl radicals etching the first crystal surface and the second crystal surface is in the range of 120s-140s; The etching temperature of the hydroxyl radicals etching the first crystal surface and the second crystal surface is in the range of 70-80℃.

4. The method of claim 2, wherein, The method further comprises at least one of the following: The method further comprises at least one of the following: After placing the silicon wafer in the transition chamber in the predetermined vacuum environment, the method further comprises:

5. The method of claim 4, wherein, providing a sputtering target at a predetermined flow rate, and sputtering the surface of the silicon wafer by the sputtering target to pre-clean the surface of the silicon wafer. The first vacuumizing of the transition chamber is carried out by a mechanical pump, so that the transition chamber reaches a first preset vacuum degree; the value range of the first preset vacuum degree includes 0.9×10 -2 mbar~1.1×10 -2 mbar. The transition cavity is vacuumized for the second time by a molecular pump, so that the transition cavity reaches a second preset vacuum degree; the second preset vacuum degree is in a range of 0.9*10 -4 mbar~1.1*10 -4 mbar.

6. The method of claim 2, wherein, The method further comprises at least one of the following: The predetermined flow rate of the sputtering target is in the range of 50sccm±5sccm; 7. The method of claim 6, wherein, The sputtering power of the sputtering target is 150±10W; The sputtering time of the sputtering target is 60±5s. Before the method of performing anisotropic etching on the surface of the silicon wafer by the hydroxyl radicals to obtain a textured structure, the method further comprises: placing the silicon wafer in an ozone solution to clean the surface of the silicon wafer and form an oxide layer on the surface of the silicon wafer; 8. The method of claim 1, wherein, placing the structure obtained by surface cleaning in an alkaline solution of a first predetermined concentration for isotropic etching; placing the structure obtained by isotropic etching in an alkaline solution of a second predetermined concentration for oxide film etching; placing the structure obtained by oxide film etching in a cleaning solution for oxide layer stripping. The method further comprises at least one of the following: The concentration of the ozone solution is in the range of 45-55ppm; 9. The method of claim 8, wherein, The first predetermined concentration is greater than or equal to 3%. ​ ​ The isotropic etching time is 100s-150s; The second preset concentration is 0.5%±0.1%; The oxidation film etching time is 220s-260s; The concentration of the cleaning solution is 7%±1%; The oxidation layer stripping time is 120s-140s.

10. The method according to any one of claims 1 to 9, characterized in that, The method further comprises: Reducing the surface of the textured structure to remove the oxidation layer on the surface of the textured structure.

11. The method according to any one of claims 1 to 9, characterized in that, The textured structure comprises a first textured structure formed on a first surface of the silicon wafer and a second textured structure formed on a second surface of the silicon wafer; the method further comprises: A first intrinsic layer, an N-type doped layer, a first conductive layer and a first electrode are sequentially formed on the first textured structure; A second intrinsic layer, a P-type doped layer, a second conductive layer and a second electrode are sequentially formed on the second textured structure.

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