Semiconductor structure, preparation method thereof and integrated circuit

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a preparation method thereof and an integrated circuit, the semiconductor structure comprises a substrate and at least one transistor structure, and the transistor structure comprises a body region which is arranged in the substrate and is of a first conduction type; the drift region is arranged in the substrate and is of the second conduction type, and the drift region and the body region are arranged adjacently; the drain electrode region is arranged in the drift region and is of the second conduction type; and the source electrode region is arranged in the body region, the source electrode region comprises a conductive region of the first conductive type and a plurality of blocks of the second conductive type, the plurality of blocks are embedded in the conductive region at intervals, and the blocks are used for adjusting the source electron concentration of the source electrode region. According to the invention, the IdLin of the transistor structure can be improved, and the conduction speed is further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and an integrated circuit. Background Technology

[0002] Transistor structures are core components of semiconductor devices, playing a crucial role in electronic circuits. They are used for signal amplification, switching control, current amplification, and constructing complex circuits. For example, in BCD (Bipolar-CMOS-DMOS) devices, LDMOS (Lateral Diffused Metal Oxide Semiconductor) is often used as the switching component. LDMOS has a long drift region, high breakdown voltage, and good thermal stability. However, the LDMOS structure is susceptible to the Kirk effect, leading to performance degradation or failure. In related technologies, an electron buffer structure is typically formed perpendicular to the electron emission direction, penetrating the source region. Figure 1 This method reduces the electron concentration in the source region, but it significantly reduces the IDLin (Linear Drain Current) of the LDMOS, affecting the turn-on speed. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this application provides a semiconductor structure, its fabrication method, and an integrated circuit, the specific technical solution of which is as follows:

[0004] On one hand, this application provides a semiconductor structure, including a substrate and at least one transistor structure, the transistor structure comprising:

[0005] The body region is located in the substrate and is of the first conductivity type;

[0006] A drift region is disposed in the substrate and is of a second conductivity type, and the drift region is disposed adjacent to the body region;

[0007] The drain region is located in the drift region and is of the second conductivity type;

[0008] A source region is disposed in the body region. The source region includes a conductive region of the first conductivity type and a plurality of segments of the second conductivity type. The plurality of segments are spaced apart and embedded in the conductive region. The segments are used to adjust the source electron concentration of the source region.

[0009] In a possible implementation, the area ratio of the plurality of segments to the conductive region is greater than or equal to a preset area ratio, which is set to match the upper limit of the source electron concentration of the transistor structure without drain breakdown.

[0010] In a possible implementation, the upper limit of the area ratio is 1.1 to 1.2 times the preset area ratio.

[0011] In a possible implementation, the conductive regions are separated by a plurality of the segments in the thickness direction of the substrate.

[0012] In a possible implementation, the transistor structure further includes:

[0013] A buffer well region is located in the drift region and is of the second conductivity type. The drain region is located in the buffer well region. The doping concentrations of the drift region, the buffer well region, and the drain region increase sequentially.

[0014] In a possible implementation, the first conductivity type is P-type, and the second conductivity type is N-type.

[0015] In a possible implementation, the transistor structure further includes:

[0016] A gate structure is located on one side of the drift region and spans the drift region and the body region.

[0017] In a possible implementation, the transistor structure further includes:

[0018] A field electrode is located on one side of the drift region and adjacent to the gate structure, the field electrode spanning the drain region, the drift region and the gate structure.

[0019] In a possible implementation, the semiconductor structure further includes:

[0020] A deep well region is disposed in the substrate, located on the side of the substrate away from the source region and the drain region, the deep well region is connected to the drift region and the body region respectively, and the deep well region spans at least one transistor structure.

[0021] On the other hand, this application provides a method for fabricating a semiconductor structure, the semiconductor structure including at least one transistor structure, the fabrication method including a method for forming the transistor structure, comprising:

[0022] Provide substrate;

[0023] Adjacent body regions and drift regions are formed in the substrate, wherein the body regions are of a first conductivity type and the drift regions are of a second missile type;

[0024] A drain region is formed in the drift region and a source region is formed in the body region. The drain region is of the second conductivity type. The source region includes a conductive region of the first conductivity type and a plurality of segments of the second conductivity type. The plurality of segments are interleaved in the conductive region. The segments are used to adjust the source electron concentration of the source region.

[0025] In a possible implementation, the fabrication method further includes, prior to forming the source region:

[0026] The transistor structure was simulated based on simulation experiments, and the area ratio of the multiple segments to the conductive region of the source region was modulated until the lower limit of the total area of ​​the multiple segments that could be set without the transistor structure experiencing drain breakdown was determined.

[0027] Based on the lower limit of the total area and the area value of the conductive region corresponding to the lower limit of the total area, a preset area ratio of the plurality of segments to the conductive region is determined; the area ratio of the plurality of segments to the conductive region in the transistor structure is greater than or equal to the preset area ratio.

[0028] On the other hand, this application provides an integrated circuit, which includes the semiconductor structure described above.

[0029] On the other hand, this application provides an electronic device that includes the semiconductor structure described above.

[0030] Based on the above technical solution, this application has the following beneficial effects:

[0031] This application provides a semiconductor structure including at least one transistor structure. The transistor structure includes an adjacent body region and a drift region disposed in a substrate, a drain region disposed in the drift region, and a source region disposed in the body region. The source region contains a conductive region of a first conductivity type and multiple segments of a second conductivity type interleaved within the conductive region. By distributing these segments, the source electron concentration of the transistor structure is adjusted to avoid drain breakdown caused by the Kirk effect and to effectively reduce the total area of ​​the second conductivity type region, thereby increasing the IDLin of the transistor structure and improving the turn-on speed. Furthermore, the multi-segment approach allows for flexible adaptation to the electron concentration adjustment requirements of different transistor structures, which is beneficial for layout design flexibility and device performance optimization. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0033] Figure 1 A top view of a semiconductor structure provided by existing technology;

[0034] Figure 2 A side cross-sectional view of a semiconductor structure provided in an embodiment of this application;

[0035] Figure 3 : Figure 2 Top view of the area defined by the dashed line;

[0036] Figure 4 : A side cross-sectional view of another semiconductor structure provided in the embodiments of this application;

[0037] Figure 5 A schematic flowchart of a method for fabricating a semiconductor structure provided in this application embodiment;

[0038] Reference numerals: 10-Electron buffer structure, 100-Substrate, 200-Transistor structure, 101-Deep well region, 210-Bulk region, 220-Drift region, 230-Drain region, 240-Source region, 241-Conductive region, 242-Blocking region, 250-Buffer well region, 260-Gate structure, 261-Gate material layer, 262-Dielectric layer, 263-Barrier layer, 270-Field plate, 271-Barrier structure, 272-Trench structure, L1-First direction, L2-Second direction. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0040] It should be noted that, in the description of this application, the following definitions shall apply unless a different definition is given elsewhere in the claims or this specification. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​to produce substantially the same properties, functions, results, etc. A range of numerical values ​​indicated by a low value and a high value is defined as including all numerical values ​​within that range and all subranges included within that range.

[0041] It should be noted that in the description of this application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0042] It should be noted that, in the description of this application, the terms "on," "above," "over," and "above" should be interpreted in the broadest sense, meaning that a description containing these terms is interpreted as "a component may be disposed on another component in direct contact, or there may be an intermediate component or layer between the components." Furthermore, for ease of description, this application may also use spatial relative terms such as "below," "under," "below," "on," "above," "lower," and "upper" to describe the relationship between one element or component and another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this application can be interpreted accordingly.

[0043] As used in this application, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or it may extend over a localized area of ​​the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A single layer may comprise multiple layers. For example, a gate layer may comprise a polycrystalline material layer and a dielectric material layer, and may have the same or different materials.

[0044] It should be understood that the terms "consistent" and "perpendicular" used in this application refer to basic consistency or basic perpendicularity that meet the requirements of process tolerance, and do not refer to absolute consistency or absolute perpendicularity in a physical sense.

[0045] It should be understood that the term "plane" as used in this application, such as "first plane", "second plane", etc., refers to the XY plane of the substrate 100, which corresponds to the XY plane of the semiconductor structure. "In-plane direction" refers to the direction parallel to the XY plane, and "thickness direction" or "longitudinal direction" refers to the Z direction relative to the XY plane.

[0046] The following combination Figure 2-4 The semiconductor structure described in this application is explained. It is understood that the semiconductor structure shown in the accompanying drawings is merely a technical solution of one specific embodiment of this application, and the semiconductor structure of this application may include fewer or more structural features, and is not limited to the device structure described in the drawings.

[0047] refer to Figure 2-4 The semiconductor structure includes a substrate 100 and at least one transistor structure 200. One or more transistor structures 200 can be integrated in the semiconductor structure to form a functional component in a semiconductor device. The semiconductor structure can be layout-designed and fabricated based on the actual functional device requirements. In one example, the semiconductor structure is a BCD device.

[0048] The substrate 100 is a semiconductor substrate capable of semiconductor device fabrication processes, such as using an SOI platform, to fabricate semiconductor structures. For example, the constituent material of the semiconductor substrate 100101 can be at least one of the following: silicon, silicon-containing materials (such as gallium arsenide (GaAs) III-V compound semiconductor materials), silicon on insulator (SOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or other types of semiconductor materials capable of forming source and drain regions.

[0049] A transistor (MOS, Metal Oxide Semiconductor) structure refers to a unit structure formed on a substrate 100 that can form a single functional component. This can be, but is not limited to, bipolar junction transistors (BJTs), field-effect transistors (FETs), and insulated-gate bipolar transistors (IGBTs). In one example, the transistor structure 200 is an LDMOS.

[0050] Specifically, the transistor structure 200 includes: a body region 210 disposed in the substrate 100 and of a first conductivity type; a drift region 220 disposed in the substrate 100 and of a second conductivity type, the drift region 220 being adjacent to the body region 210; a drain region 230 disposed in the drift region 220 and of a second conductivity type; and a source region 240 disposed in the body region 210, the source region 240 including a conductive region 241 of the first conductivity type and a plurality of segments 242 of the second conductivity type, the plurality of segments 242 being spaced apart and embedded in the conductive region 241, the segments 242 being used to adjust the source electron concentration of the source region 240.

[0051] In a possible embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

[0052] The drift region 220 is formed in the substrate 100 by doping with a specific type of element. It can be formed at least through ion implantation and etching patterning processes. Exemplarily, the doping element can be, but is not limited to, boron (B), aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). In some embodiments, the drift region 220 is an N-type drift region 220 (N-Drift, NDRF), and the doping element can be phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). Multiple drift regions 220 can be formed in the substrate 100 using a photolithography mask process to serve as structural units in multiple transistor structures 200 for charge transport and voltage regulation.

[0053] The body region 210 is formed in the substrate 100 by doping with a specific type of element. It can be formed at least by ion implantation and etching patterning processes. For example, the doping element can be, but is not limited to, boron (B), aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). In some embodiments, the body region 210 is a P-type body region 210 (P-body), and the doping element can be boron (B), aluminum (Al), gallium (Ga), and indium (In). Multiple body regions 210 can be formed in the substrate 100 by photolithography masking processes to serve as structural units in multiple transistor structures 200, to form a PN junction with the source region 240 and to provide a carrier storage, thereby improving the performance of the transistor structure 200. The body regions 210 are adjacent to the drift regions 220. When multiple transistor structures 200 are arranged adjacently, the multiple body regions 210 and the multiple drift regions 220 are arranged laterally in an alternating manner.

[0054] Drain region 230 is formed in drift region 220 by doping with a specific type of element. In some embodiments, drain region 230 is N+ type, with a higher doping concentration than N-type drift region 220. Source region 240 is formed in body region 210 by doping with multiple types of elements, including doping with elements of a first conductivity type and doping with elements of a second conductivity type. In one example, based on photolithography masking, conductive region 241 can be formed first by ion implantation, then conductive region 241 can be masked, and then multiple blocks 242 can be formed by ion implantation. In one example, the conductive region 241 is an N+ type conductive region 241, and the block 242 is a P+ type region. Multiple blocks 242 are distributed at intervals in the conductive region 241. Under forward bias, the conductive region 241 is used to provide source electrons as charge carriers. The conductivity type of the front section is opposite to that of the conductive region 241, which is used to adjust and appropriately reduce the source electron concentration of the source region 240, so as to avoid the excessive drain electric field caused by the Kirk effect due to the excessive source electron concentration, thereby avoiding drain breakdown.

[0055] In related technologies, refer to Figure 1 An electron buffer structure 10 (buffer P-region) is provided in the source region 240 along the vertical direction of electron conduction to form an overall isolation area in the transmission direction and intercept some source electrons. Although this can effectively avoid drain breakdown, due to the limitations of the fabrication process, the increased overall P-region area is too large and difficult to control, resulting in an excessive decrease in IDLin of the transistor structure 200, thereby reducing the transistor turn-on speed. The above-mentioned technical solution of this application provides a conductive region 241 of the first conductivity type and multiple segments 242 of the second conductivity type embedded in the conductive region 241 at intervals. The source electron concentration of the transistor structure 200 is adjusted by the distributed segments 242 to avoid drain breakdown caused by the Kirk effect and effectively reduce the total area of ​​the second conductivity type region to increase IDLin of the transistor structure 200, thereby improving the turn-on speed, optimizing the device response rate and operating power consumption. Furthermore, the multi-block 242 approach can flexibly adapt to the electron concentration adjustment requirements of different transistor structures 200, which is beneficial to the flexibility of layout design, the optimization of device performance, and the improvement of the robustness of transistor structure 200.

[0056] In some embodiments, reference is made to Figure 3At least some of the multiple segments 242 are arranged at intervals along a first direction L1 to form a column of segments 242, and are spaced apart from the first sidewall of the conductive region 241. The first direction L1 refers to the direction perpendicular to the second direction L2 of electron transport in the XY plane of the semiconductor structure and the transistor structure 200. The first sidewall refers to the sidewall of the conductive region 241 in the transistor structure 200 that faces away from the drain region 230. In this way, by arranging them at intervals along the first direction L1, the segments 242 do not penetrate the conductive region 241 in the first direction L1. While reducing the source electron concentration, multiple continuous transport channels in the electron transport direction are retained in the conductive region 241, which can further improve the channel current. In some embodiments, one or more columns of segments 242 can be provided in the conductive region 241, which can be specifically set based on the total area of ​​the segments 242 and the device structure requirements.

[0057] In some embodiments, the multiple segments 242 are the same size as each other to simplify the fabrication process.

[0058] In some embodiments, reference is made to Figure 2 and Figure 4 In the thickness direction of the substrate 100, multiple segments 242 separate the conductive regions 241. The thickness direction is perpendicular to the XY plane of the semiconductor structure. In the thickness direction, the segments 242 penetrate the conductive regions 241 to form an isolation structure in the conductive regions 241, thereby achieving effective electron concentration regulation in the segment 242 region and improving fabrication efficiency.

[0059] In some embodiments, the area ratio of the plurality of segments 242 to the conductive region 241 is greater than or equal to a preset area ratio. This preset area ratio is set to match the upper limit of the source electron concentration of the transistor structure 200 without drain breakdown. Here, the upper limit of the source electron concentration refers to the critical current density. By setting a preset area ratio that adapts to the transistor structure 200, a lower limit is set for the proportion of the total area of ​​the plurality of segments 242 in the corresponding transistor structure 200. This maximizes the Idlin performance of the transistor structure 200 without causing drain breakdown, thereby accelerating transistor speed.

[0060] In some embodiments, the preset area ratio is determined based on the lower limit of the total area of ​​the multiple segments 242 that can be set when the transistor structure 200 does not experience drain breakdown, obtained from transistor structure 200 simulation. That is, the preset area ratio is the lower limit of the ratio of the total area of ​​the multiple segments 242 to the area of ​​the conductive region 241 when the transistor structure 200 does not experience drain breakdown. It is understood that, in the simulation experiment, apart from the total area of ​​the multiple segments 242, or the area ratio of the total area of ​​the multiple segments 242 to the area of ​​the conductive region 241, other structural parameters or electrical control parameters can be set to constant conditions based on actual needs, so as to facilitate the modulation of the area ratio in the simulation experiment.

[0061] In some embodiments, the upper limit of the area ratio is 1.1 to 1.2 times the preset area ratio. By controlling the upper limit of the ratio of the total area of ​​the segment 242 to the total area of ​​the conductive region 241 to the above range, the total proportion of the segment 242 can be reduced as much as possible to ensure the conduction efficiency of the transistor structure 200.

[0062] Based on some or all of the above embodiments, in some embodiments, reference is made to Figure 4 The transistor structure 200 also includes a buffer well region 250, located within the drift region 220 and of the second conductivity type. A drain region 230 is located within the buffer well region 250. The doping concentrations of the drift region 220, buffer well region 250, and drain region 230 increase sequentially. The buffer well region 250 has the same conductivity type as the drain region 230. By surrounding the drain region 230 with the buffer well region 250, its doping concentration is positioned between that of the drift region 220 and the drain region 230, creating a more uniform electric field in the drift region 220. This effectively mitigates reliability issues caused by high electric fields and further avoids the risk of drain breakdown due to the Kirk effect. With the buffer well region 250, the corresponding preset area ratio also decreases, further reducing the total area of ​​the blocks 242 in the source region 240, thereby significantly improving the Idlin parameter and further enhancing the turn-on speed. In one example, the buffer well region 250 is an N-well.

[0063] Based on some or all of the above embodiments, in some embodiments, reference is made to Figure 2-4 The transistor structure 200 further includes a gate structure 260, located on one side of the drift region 220 and spanning the drift region 220 and the body region 210. The gate structure 260 can be a biased gate or a floating gate. The gate structure 260 may include a dielectric layer 262 located on one side of the drift region 220 and a gate material layer 261 (such as polysilicon) located on the dielectric layer 262, and may also include a barrier layer 263 located on the sidewalls of the gate material layer 261 and the dielectric layer 262. The controllable conduction of the transistor structure 200 is achieved by setting the gate structure 260.

[0064] Based on some or all of the above embodiments, in some embodiments, reference is made to Figure 2-4 The transistor structure 200 further includes a field plate 270 located on one side of the drift region 220 and adjacent to the gate structure 260, the field plate 270 spanning the drain region 230, the drift region 220, and the gate structure 260. The field plate 270 forms an additional electric field control region on the surface of the drift region 220 to improve the breakdown voltage of the transistor structure 200 and reduce the on-resistance. In one example, reference... Figure 2-4By setting a field plate 270 in the LDMOS transistor structure 200, lateral electric field modulation is achieved, the size of the depletion layer is expanded, the electric field concentration problem is reduced, the high voltage resistance performance is improved and the breakdown risk is reduced, while the ldlin parameter is further improved and the speed of LDMOS is accelerated.

[0065] In some embodiments, reference is made to Figure 2-4 The field plate 270 includes a barrier structure 271 and a trench structure 272. The barrier structure 271 is located on the drift region 220 and spans a portion of the gate structure 260, the drift region 220, and a portion of the drain region 230, as shown in the figure. The barrier structure 271 covers a portion of the top wall and one side wall of the gate structure 260 and extends above the drift region 220 to the surface of a portion of the drain region 230. The trench structure 272 is located on the side of the barrier structure 271 facing away from the drift region 220 and is used to form a conductive structure as a conductive path. Applying a forward bias voltage through the conductive path in the trench structure 272 can generate a capacitance effect, causing electrons to accumulate on the channel surface, thereby increasing the capacitance of the transistor structure 200 (e.g., ...). Figure 3 The channel current of the LDMOS transistor is reduced, thus accelerating the transistor speed. Specifically, the barrier structure 271 can be, for example, a metal silicide barrier layer 263 (Silicide Block), or other materials capable of forming a modulated electric field.

[0066] Based on some or all of the above embodiments, in some embodiments, reference is made to Figure 2 and Figure 4 The semiconductor structure further includes a deep well region 101 disposed in the substrate 100, located on the side of the substrate 100 away from the source region 240 and the drain region 230. The deep well region 101 is connected to the drift region 220 and the body region 210, respectively, and spans at least one transistor structure 200. Specifically, the deep well region 101 is located on the side of the drift region 220 and the body region 210 away from the gate structure 260 in the thickness direction, forming a channel with the body region 210. In one example, referencing... Figure 2 and Figure 4 The deep well region 101 is a deep P-well (DPW). The deep well region 101 provides a concentrated electric field region to regulate the electric field distribution in the drift region 220, thereby improving the device breakdown voltage and overall performance.

[0067] In summary, the above technical solution achieves source electron concentration adjustment in the source region 240 by setting spaced-apart blocks 242. Under the constraint of the critical electron concentration for drain breakdown, the number, shape, and area of ​​the blocks 242 can be flexibly set to allow for flexible control of the electron concentration. Under the premise of preventing drain breakdown, the total area of ​​the blocks 242 in the conductive region 241 is minimized to reduce Ron resistance (on-resistance). Compared to... Figure 1 The existing structure can induce a significant increase in source electron concentration, reduce the electric field at the drain position, improve Idlin performance, and thus enhance device response speed, making the transistor circuit more robust. Furthermore, through the segment 242 method, the shape, area, and number of segments 242 can be optimized according to the area / orientation of the transistor array (such as an LDMOS array), adapting to transistor structures 200 with various setup requirements for flexible configuration and embedding, resulting in strong process generalization.

[0068] The following combination Figure 5 This application describes a method for fabricating a semiconductor structure, which includes at least one transistor structure 200. Figure 5 This is a schematic flowchart of a semiconductor structure fabrication method. This specification provides method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many steps and does not represent the only possible execution order. In actual fabrication method execution, the method can be executed in the order shown in the embodiments or drawings or in parallel. The fabrication method includes a method for forming a transistor structure 200, which may include S11-S13:

[0069] S11: Provides substrate 100;

[0070] S12: An adjacent body region 210 and a drift region 220 are formed in the substrate 100, wherein the body region 210 is of the first conductivity type and the drift region 220 is of the second missile type;

[0071] S13: A drain region 230 is formed in the drift region 220 and a source region 240 is formed in the body region 210. The drain region 230 is of the second conductivity type. The source region 240 includes a conductive region 241 of the first conductivity type and multiple segments 242 of the second conductivity type. The multiple segments 242 are interposed in the conductive region 241. The segments 242 are used to adjust the source electron concentration of the source region 240.

[0072] Specifically, the drift region 220 and the body region 210 can be formed in the substrate 100 by at least photolithographic patterning and ion implantation processes. When the first conductivity type is P-type and the second conductivity type is N-type, the drift region 220 is formed by N-doping and the body region 210 is formed by P-doping. For example, the doping element for N-doping can be, but is not limited to, phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and the doping element for P-doping can be, but is not limited to, boron (B), aluminum (Al), gallium (Ga), and indium (In).

[0073] Specifically, the drain region 230 can be formed in the drift region 220 through at least photolithographic patterning and ion implantation processes, and its doping concentration is higher than that of the drift region 220. For example, the drain region 230 is an N+ region. The source region 240 can be formed in the body region 210 through at least two photolithographic patterning processes and two ion implantation processes. Multiple blocks 242 can be implanted and formed at one time. The formation order of the conductive region 241 and the blocks 242 can be set according to actual needs.

[0074] In some embodiments, multiple segments 242 separate conductive regions 241 in the thickness direction of the substrate 100.

[0075] In some embodiments, the area ratio of multiple segments 242 to conductive regions 241 is greater than or equal to a preset area ratio, which is set to match the upper limit of the source electron concentration of the transistor structure 200 without drain breakdown.

[0076] In some embodiments, the fabrication method further includes steps S21-S22 before forming the source region 240:

[0077] S21: Simulate the transistor structure 200 based on simulation experiments, and modulate the area ratio of multiple segments 242 to the conductive region 241 in the source region 240 until the lower limit of the total area of ​​multiple segments 242 that can be set without drain breakdown of the transistor structure 200 is determined.

[0078] S22: Based on the lower limit of the total area and the area value of the conductive region 241 corresponding to the lower limit of the total area, determine the preset area ratio between the multiple blocks 242 and the conductive region 241.

[0079] Specifically, during the simulation experiment, other transistor parameters, except for the area ratio between the total area of ​​the segment 242 and the area of ​​the conductive region 241, can be determined first. The area ratio is then adjusted to reduce the area ratio until drain breakdown occurs. The critical total area of ​​the multiple segments 242 is determined as the lower limit of the total area of ​​the multiple segments 242. The ratio between the lower limit of the total area and the area value of the conductive region 241 set when the lower limit of the total area is obtained is determined as the preset area ratio. The area ratio of the multiple segments 242 and the conductive region 241 in the transistor structure 200 is greater than or equal to the preset area ratio.

[0080] In some embodiments, the upper limit of the area ratio is 1.1 to 1.2 times the preset area ratio.

[0081] In some embodiments, prior to S12, the method may further include: forming a deep well region 101 in the substrate 100, the deep well region 101 being located on the side of the substrate 100 away from the source region 240 and the drain region 230, the deep well region 101 being connected to the drift region 220 and the body region 210 respectively, and the deep well region 101 spanning at least one transistor structure 200.

[0082] Specifically, the deep well region 101 can be formed at a deeper depth in the substrate 100 by controlling the energy of the injected ions. After the deep well region 101 is formed, the drift region 220 and the body region 210 are formed above the deep well region 101.

[0083] In some embodiments, before forming the drain region 230, the method may further include: forming a buffer well region 250 in the drift region 220, the buffer well region 250 being of a second conductivity type, the drain region 230 being disposed in the buffer well region 250, and the doping concentrations of the drift region 220, the buffer well region 250, and the drain region 230 increasing sequentially.

[0084] Specifically, the buffer well region 250 and the drain region 230 have the same conductivity type and can be formed in the drift region 220 by at least photolithographic patterning and ion implantation, and then the drain region 230 is formed by doping in the buffer well region 250.

[0085] In some embodiments, after S13, the method may further include forming a gate structure 260 on one side of the drift region 220, the gate structure 260 spanning the drift region 220 and the body region 210. The gate structure 260 can be fabricated using existing gate fabrication processes, and is not specifically limited herein.

[0086] In some embodiments, after S13, the method may further include: forming a field plate 270 on one side of the drift region 220, the field plate 270 being adjacent to the gate structure 260, and the field plate 270 spanning the drain region 230, the drift region 220 and the gate structure 260.

[0087] Specifically, a field electrode 270 can be formed on the drift region 220 through at least photolithography patterning, deposition, and trenching processes. The field electrode 270 may include a barrier structure 271 located on a portion of the surface of the gate structure 260, a sidewall of the gate structure 260, the surface of the drift region 220 and a portion of the drain region 230, and a trench structure 272 located on the barrier structure 271. The trench structure 272 is used to form a conductive structure as a conductive path.

[0088] Understandably, the above-described semiconductor structure embodiments and semiconductor structure fabrication method embodiments are based on the same application concept, and the semiconductor structure can be fabricated using the above-described semiconductor structure fabrication method.

[0089] On the other hand, this application provides an integrated circuit, which includes an electronic device made from the above-described semiconductor structure or the method for fabricating the semiconductor structure.

[0090] On the other hand, this application provides an electronic device, which includes an electronic device fabricated using the aforementioned semiconductor structure or method for fabricating a semiconductor structure. This electronic device may include any electronic component such as an integrated circuit or electronic device. Because the semiconductor structure has superior performance, the performance of the electronic device is correspondingly improved.

[0091] The electronic devices in the embodiments of this application can be selected from any electronic products or devices such as mobile phones, PDAs, tablets, laptops, game consoles, televisions, video compact discs (VCDs), digital video discs (DVDs), navigators, cameras, camcorders, voice recorders, MP3 players, MP4 players, and PlayStation Portable (PSPs), or any intermediate products including electronic devices made with the above-described semiconductor structures.

[0092] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0093] The foregoing description has fully disclosed the specific embodiments of this application. It should be noted that any modifications made by those skilled in the art to the specific embodiments of this application do not depart from the scope of the claims. Accordingly, the scope of the claims of this application is not limited to the foregoing specific embodiments.

Claims

1. A semiconductor structure, characterized in that, The transistor includes a substrate and at least one transistor structure, the transistor structure comprising: The body region is disposed in the substrate and is of the first conductivity type; A drift region is disposed in the substrate and is of a second conductivity type, and the drift region is disposed adjacent to the body region; The drain region is located in the drift region and is of the second conductivity type; A source region is disposed in the body region. The source region includes a conductive region of the first conductivity type and a plurality of segments of the second conductivity type. The plurality of segments are spaced apart and embedded in the conductive region. The segments are used to adjust the source electron concentration of the source region.

2. The semiconductor structure according to claim 1, characterized in that, The area ratio of the plurality of segments to the conductive region is greater than or equal to a preset area ratio, which is set to match the upper limit of the source electron concentration of the transistor structure without drain breakdown.

3. The semiconductor structure according to claim 2, characterized in that, The upper limit of the area ratio is 1.1 to 1.2 times the preset area ratio.

4. The semiconductor structure according to claim 1, characterized in that, In the thickness direction of the substrate, a plurality of the segments separate the conductive regions.

5. The semiconductor structure according to claim 1, characterized in that, The transistor structure also includes: A buffer well region is located in the drift region and is of the second conductivity type. The drain region is located in the buffer well region. The doping concentrations of the drift region, the buffer well region, and the drain region increase sequentially.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

7. The semiconductor structure according to any one of claims 1-5, characterized in that, The transistor structure also includes: A gate structure is located on one side of the drift region and spans the drift region and the body region.

8. The semiconductor structure according to any one of claims 1-5, characterized in that, The transistor structure also includes: A field plate is located on one side of the drift region and adjacent to the gate structure, the field plate spanning the drain region, the drift region and the gate structure.

9. The semiconductor structure according to any one of claims 1-5, characterized in that, The semiconductor structure also includes: A deep well region is disposed in the substrate, located on the side of the substrate away from the source region and the drain region, the deep well region is connected to the drift region and the body region respectively, and the deep well region spans at least one transistor structure.

10. A method for fabricating a semiconductor structure, said semiconductor structure comprising at least one transistor structure, characterized in that, The fabrication method includes a method for forming the transistor structure, comprising: Provide substrate; Adjacent body regions and drift regions are formed in the substrate, wherein the body regions are of a first conductivity type and the drift regions are of a second missile type; A drain region is formed in the drift region and a source region is formed in the body region. The drain region is of the second conductivity type. The source region includes a conductive region of the first conductivity type and a plurality of segments of the second conductivity type. The plurality of segments are interleaved in the conductive region. The segments are used to adjust the source electron concentration of the source region.

11. The preparation method according to claim 10, characterized in that, Before forming the source region, the preparation method further includes: The transistor structure was simulated based on simulation experiments, and the area ratio of the multiple segments to the conductive region of the source region was modulated until the lower limit of the total area of ​​the multiple segments that could be set without the transistor structure experiencing drain breakdown was determined. Based on the lower limit of the total area and the area value of the conductive region corresponding to the lower limit of the total area, a preset area ratio of the plurality of segments to the conductive region is determined; the area ratio of the plurality of segments to the conductive region in the transistor structure is greater than or equal to the preset area ratio.

12. An integrated circuit, characterized in that, The integrated circuit comprises the semiconductor structure according to any one of claims 1-9.

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