Complementary metal oxide semiconductor (CMOS) compatible azimuth angle sensitive infrared detector and manufacturing method thereof

Abstract

The invention relates to the technical field of infrared detector preparation, in particular to a CMOS compatible azimuth angle sensitive infrared detector and a manufacturing method thereof, and the method comprises the steps: S1, carrying out the etching of the surface of a silicon substrate, and generating a silicon nanowire array; s2, the silicon nanowire array is placed in an HF solution with the concentration being 4.75%-5.25% to be soaked for 4.5 min to 5.5 min, and the soaked silicon nanowire array is obtained; s3, forming a dielectric deposition layer on the soaked silicon nanowire array to obtain a sample to be sputtered; s4, the sample to be sputtered is subjected to pre-sputtering treatment for 0.8-1.2 h in the inert gas atmosphere, and a pre-sputtered sample is obtained; s5, sputtering on the surface of the deposition layer of the pre-sputtering sample to form a TiN plasmon layer; and S6, processing an upper electrode on the TiN plasmon layer, and processing a lower electrode on one side, deviating from the TiN plasmon layer, of the silicon substrate. The method has the advantages that expensive materials are not used, high vacuum packaging is not depended on, and the direction sensitive infrared detector can be prepared in a standard CMOS process.

Description

Technical Field

[0001] This application relates to the technical field of infrared detectors, and in particular to a CMOS-compatible azimuth-sensitive infrared detector and its fabrication method. Background Technology

[0002] Infrared detectors are sensitive devices that convert thermal radiation or reflected radiation in the 0.75–1000 μm wavelength band into electrical signals. With their high-contrast imaging capabilities for temperature, materials, and scenes, infrared detectors have become core components in numerous industries, including: military applications (night vision, reconnaissance, missile early warning and target designation); civilian security (firefighting and search and rescue, security monitoring, border inspection and night navigation); industrial inspection (process monitoring, pipeline leaks, semiconductor defects); medical and life sciences (thermal imaging diagnosis and metabolic monitoring); and environmental and meteorological applications (remote sensing of greenhouse gases and atmospheric composition). The global market size continues to grow.

[0003] Traditional infrared detectors (such as HgCdTe, InSb, QWIP, Type II superlattice, and microbolometers) primarily respond to the total intensity (or power) of the incident light and are not sensitive to the direction of the electric field vector (i.e., polarization state or azimuth angle).

[0004] In numerous infrared remote sensing and imaging applications, infrared detectors must be sensitive to the azimuth angle of the incident photoelectric field amplitude in order to accurately analyze and reconstruct the angular information of the target. Therefore, the structural design and materials engineering of infrared detectors typically need to be optimized for angle sensitivity to meet the requirements of high-precision directional detection and situational awareness applications.

[0005] Furthermore, in scenarios such as night vision, intelligent driving, environmental monitoring, and even space telescopes, there is an increasingly urgent need for low-cost, megapixel-level large-area, CMOS-compatible infrared focal plane arrays (IR FPA).

[0006] CMOS compatibility means that front-end processes can be completed directly on 200 mm or even 300 mm silicon lines and integrated on the same chip as digital / RF circuits—this is key to truly bringing infrared to the consumer and automotive markets. However, existing commercial infrared detectors are incompatible with CMOS due to their complex epitaxial growth techniques.

[0007] The urgent problem to be solved is how to provide a new direction-sensitive infrared detection solution that does not require expensive materials, does not rely on high-vacuum packaging, and can be completed within the standard CMOS process. Summary of the Invention

[0008] In order to provide a novel orientation-sensitive infrared detector that does not require expensive materials, does not rely on high-vacuum packaging, and can be completed within a standard CMOS process, the purpose of this application is to provide a CMOS-compatible azimuth-sensitive infrared detector and its fabrication method.

[0009] Firstly, the method for fabricating the CMOS-compatible azimuth-sensitive infrared detector provided in this application adopts the following technical solution: A method for fabricating a CMOS-compatible azimuth-sensitive infrared detector includes the following steps: S1. Etching a silicon nanowire array onto a silicon substrate surface; S2. Immerse the silicon nanowire array in a 4.75-5.25% HF solution for 4.5-5.5 min to obtain the immersed silicon nanowire array. S3. After immersion, a dielectric layer is deposited on the silicon nanowire array to obtain the sample to be sputtered. S4. The sample to be sputtered is pre-sputtered in an inert gas atmosphere for 0.8-1.2 h to obtain a pre-sputtered sample. S5. Sputtering a TiN plasmonic layer onto the surface of the pre-sputtered sample's deposited layer; S6. Fabricate an upper electrode on the TiN plasmonic layer and fabricate a lower electrode on the side of the silicon substrate away from the TiN plasmonic layer.

[0010] Optionally, in step S2, the silicon nanowire array is immersed in a 5% HF solution for 5 min.

[0011] Optionally, the inert gas atmosphere in step S4 is Ar.

[0012] Optionally, in step S5, the sputtering power is set to 700-800 W in the TiN plasmonic layer formed by sputtering on the surface of the pre-sputtered sample deposition layer.

[0013] Optionally, the sputtering power in step S5 is 740-760 W.

[0014] Optionally, in step S5, the thickness of the TiN plasmon layer formed by sputtering on the surface of the pre-sputtered sample deposition layer is 15-45 nm.

[0015] Optionally, in step S5, the thickness of the TiN plasmon layer formed by sputtering on the surface of the pre-sputtered sample deposition layer is 20-35 nm.

[0016] Optionally, in step S5, the chamber pressure in the TiN plasmonic layer formed by sputtering on the surface of the pre-sputtered sample is 0.48-0.52 Pa, the sputtering atmosphere is 90-94 sccm Ar 10-6 sccm N2, and the sputtering rate is 0.1-3 nm / min.

[0017] Optionally, step S1, which involves etching a silicon nanowire array onto a silicon substrate surface, includes: Photolithography is used to form a nanowire array etching window to obtain a photolithographic silicon substrate; The photolithographic silicon substrate was immersed in a mixed solution of AgNO3, HF, and deionized water for 20 s to 4 min to obtain the immersed silicon substrate. The volume ratio of AgNO3, HF, and deionized water was AgNO3:HF:deionized water = 1-2:2.5-5:9. The immersed silicon substrate was transferred to a mixed solution of HF, H2O2 and deionized water for etching for 4-15 min, wherein the volume ratio of HF, H2O2 and deionized water was HF:H2O2:deionized water = 5:0.5-5:20.

[0018] Secondly, the CMOS-compatible azimuth-sensitive infrared detector provided in this application adopts the following technical solution: A CMOS-compatible azimuth-sensitive infrared detector was fabricated using a CMOS-compatible azimuth-sensitive infrared detector fabrication method.

[0019] In summary, this application includes at least one of the following beneficial technical effects: 1. Terahertz radiation is achieved in a metallic (TiN) system through HF solution immersion followed by pre-sputtering treatment and power adjustment during sputtering, thus exhibiting azimuth sensitivity. This allows the detector to emit terahertz waves upon infrared illumination, and the radiation characteristics of these waves change significantly with the device's azimuth angle, enabling accurate analysis and reconstruction of the target's angular information.

[0020] 2. While achieving azimuth-sensitive infrared detection, it meets the requirements of not relying on high-vacuum packaging, being able to mass-produce under standard CMOS processes, supporting large-area pixel integration, and low-cost production. It is suitable for multiple application scenarios such as defense, automobiles, and consumer electronics, thus overcoming the limitations of metasurface solutions in terms of cost, size, and compatibility. Attached Figure Description

[0021] Figure 1This is a schematic diagram of the infrared detector device according to Embodiment 1 of this application, wherein TiN corresponds to the TiN plasmon layer; Al2O3 corresponds to the dielectric layer; Si NWs corresponds to the silicon nanowire array; Si substrate corresponds to the silicon substrate; and Electrode corresponds to the lower electrode. Figure 2 These are the azimuth-THz peak spectra of the infrared detectors of Embodiments 1-3 and Comparative Examples 1-3 of this application; Figure 3 These are the THz-TDS delay scan images of Comparative Examples 4 and 5 of this application; Figure 4 These are the IV characteristic curves of Comparative Examples 4 and 6 of this application. Detailed Implementation

[0022] The following is in conjunction with the appendix Figure 1 -Appendix Figure 4 The present application will be further described in detail with reference to the embodiments.

[0023] Example 1: Embodiment 1 of this application discloses a method for fabricating a CMOS-compatible azimuth-sensitive infrared detector, referring to... Figure 1 This includes the following steps: S1. A silicon nanowire array is formed by etching on the surface of a silicon substrate.

[0024] Etching silicon nanowire arrays onto a silicon substrate surface includes: S1.1, Silicon substrate treatment The silicon substrate specifications are determined as follows: the silicon substrate thickness is controlled between 100-3000 μm, it can be N-type or P-type doped, and it can be single-sided or double-sided polished, with a resistivity of 1-10 Ω·cm. In this embodiment, the silicon substrate thickness is set to 500 μm, P-type doped, double-sided polished, and with a resistivity of 1-10 Ω·cm.

[0025] Chemical cleaning of silicon substrate: The silicon substrate was ultrasonically cleaned in acetone (30 min), ethanol (30 min), and isopropanol (30 min) in sequence to remove surface organic matter and particles.

[0026] S1.2, photolithography Spin-coating tackifier (HMDS) onto the front side of the silicon substrate; The double-sided polished silicon substrate employs a back-sealing process, for example, a back-sealing process may involve applying a resist film to the back or spin-coating 1.4 µm AZ5214E ​​photoresist. Photoresist is coated on the front side, and after exposure and development, a nanowire array etching window is formed.

[0027] S1.3, Silver-catalyzed metal-assisted chemical etching (MACE) S1.3.1 Deoxidation: The silicon substrate can be immersed in a 5% HF solution for 1 min to remove the oxide layer on the sample surface.

[0028] S1.3.2, Silver Nanoparticle Deposition: A silicon substrate is immersed in a mixed solution of AgNO3, HF, and deionized water for 20 s to 4 min to form a silver catalyst layer on the front side of the silicon substrate. The volume ratio of AgNO3, HF, and deionized water is AgNO3:HF:deionized water = 1-2:2.5-5:9. In this embodiment, the silver catalyst layer is formed by immersion in a solution with a volume ratio of AgNO3:HF:H2O = 1:2.5:9 for 20 s.

[0029] S1.3.3 Vertical Etching: The silicon substrate is transferred to a mixed solution of HF, H2O2, and deionized water and etched for 4-15 minutes, wherein the volume ratio of HF, H2O2, and deionized water is HF:H2O2:deionized water = 5:0.5-5:20. In this embodiment, etching is performed in a solution of HF:H2O2:H2O = 5:2:20 for 4 minutes to form a high aspect ratio silicon nanowire array.

[0030] S2. Post-processing of silicon nanowire arrays includes the following steps: S2.1 Rinse with deionized water and then sonicate with acetone for 4-6 minutes to remove the photoresist; S2.2, and then soak in nitric acid solution (63-67% HNO3) to remove residual silver particles; S2.3 Finally, immerse in 4.75-5.25% HF solution for 4.5-5.5 min to remove the oxide layer and simultaneously improve the interface properties.

[0031] In this embodiment, the photoresist was removed by rinsing with deionized water followed by sonication with acetone for 5 minutes; then, it was immersed in nitric acid solution (65% HNO3) to remove residual silver particles; and finally, it was immersed in 5% HF solution for 5 minutes.

[0032] S3, Medium Layer Deposition The thickness of the dielectric layer can be set to 1-3 nm.

[0033] The dielectric layer can be selected from Al2O3 or TiO2. The dielectric layer acts as a passivation layer, between the plasmonic material layer and the silicon nanowire array, so that the plasmonic material layer-dielectric layer-silicon nanowire array form a MIS structure (metal-insulator-semiconductor) to reduce dark current and passivation interface defects.

[0034] Taking the growth of Al2O3 by atomic layer deposition (ALD) as an example, the precursors were set as TMA (trimethylaluminum) and H2O, with alternating pulses and a temperature of 250℃; the number of alternating pulse cycles was 10 cycles, and a 1 nm dense passivation layer was obtained by measurement.

[0035] S4, Pre-sputtering Pre-sputtering was performed in an inert gas atmosphere for 0.8–1.2 hours. In this embodiment, pre-sputtering was performed for 1 hour in a pure Ar atmosphere.

[0036] S5. Sputtering TiN to form a TiN plasmonic layer, including: TiN films were sputtered at a power of 700-800 W under a chamber pressure of 0.48-0.52 Pa and a sputtering atmosphere of 90-94 sccm Ar 10⁻⁶ sccm N₂, with a sputtering rate of 0.1-3 nm / min, resulting in a TiN plasmonic layer thickness of 15-35 nm. In this embodiment, a TiN plasmonic layer was sputtered at a power of 750 W under a chamber pressure of 0.5 Pa and a sputtering atmosphere of 90 sccm Ar 10 sccm N₂, with a sputtering rate of 0.1 nm / min, resulting in a TiN plasmonic layer thickness of 30 nm. The target material was a high-purity titanium target (99.999%), and the chamber background vacuum was set to ≤1×10⁻⁶. -3 Pa.

[0037] S6. Upper electrode machining and lower electrode machining S6.1 The upper electrode fabrication includes preparing the upper electrode on the TiN plasmonic layer by evaporation, sputtering, or coating to achieve signal output at one end. In this embodiment, a 50 nm aluminum layer is vacuum-deposited using a mask, and the upper electrode is formed by a lift-off process.

[0038] S6.2 The lower electrode fabrication involves evaporating, sputtering, or coating a 50-3000 nm conductive material on the back of the silicon substrate as a negative metal electrode. A suitable metal material is selected based on the silicon substrate material to form an ohmic contact. The negative electrode is then connected via wires or silver paste to allow signal output at one end.

[0039] In this embodiment, a negative electrode is formed by evaporating aluminum (100 nm) on the back side of a silicon substrate.

[0040] Example 2: Embodiment 2 of this application discloses a method for fabricating a CMOS-compatible azimuth-sensitive infrared detector. The difference between this embodiment and Embodiment 1 is that the thickness of the plasmon layer prepared in step S5 is 10 nm.

[0041] Example 3: Embodiment 3 of this application discloses a method for fabricating a CMOS-compatible azimuth-sensitive infrared detector. The difference between this embodiment and Embodiment 1 is that the thickness of the plasmon layer prepared in step S5 is 20 nm.

[0042] Comparative Example 1 Comparative Example 1 of this application discloses a method for fabricating an infrared detector, which differs from Example 1 in that the thickness of the plasmon layer prepared in step S5 is 50 nm.

[0043] Comparative Example 2 Comparative Example 2 of this application discloses a method for fabricating an infrared detector, which differs from Example 1 in that the thickness of the plasmon layer prepared in step S5 is 70 nm.

[0044] Comparative Example 3 Comparative Example 3 of this application discloses a method for fabricating an infrared detector, which differs from Example 1 in that the thickness of the plasmon layer prepared in step S5 is 100 nm.

[0045] Comparative Example 4 Comparative Example 4 of this application discloses a method for manufacturing an infrared detector, which differs from Example 1 in that it does not include step S4, that is, it does not include pre-sputtering treatment in an inert gas atmosphere.

[0046] Comparative Example 5 Comparative Example 5 of this application discloses a method for manufacturing an infrared detector, which differs from Example 1 in that the post-processing step S2 does not include: immersing in a 5% HF solution for 5 minutes.

[0047] Comparative Example 6 Comparative Example 6 of this application discloses a method for manufacturing an infrared detector, which differs from Example 1 in that step S4 is not included, that is, the pre-sputtering treatment in an inert gas atmosphere is not included; and the post-processing of step S2 does not include immersion in 5% HF solution for 5 minutes.

[0048] experiment 1. Take the infrared detectors prepared in Examples 1-3 and Comparative Examples 1-5 and perform pump-probe delay scan tests in terahertz time-domain spectroscopy (THz-TDS) to obtain THz-TDS delay scan maps.

[0049] The test results of Comparative Example 4 and Comparative Example 5 are as follows: Figure 3 (a) Figure 3(b) Analysis shows that no obvious peak appears in the entire delay range (the size of the peak reflects the intensity of the terahertz field at that moment), that is, the infrared detectors prepared in Comparative Example 4 and Comparative Example 5 did not realize terahertz radiation.

[0050] Examples 1-3 showed strong peaks, while Comparative Examples 1-3 showed slight peaks. The time-domain waveforms corresponding to the THz-TDS delay scan maps of Examples 1-3 and Comparative Examples 1-3 were converted into "Azimuth Angle - THz Peak" spectra, as shown below. Figure 2 As shown.

[0051] according to Figure 2 As can be seen, the infrared detectors corresponding to Examples 1-3 possess azimuth-sensitive characteristics. When illuminated by infrared light, the detector emits terahertz waves, and the radiation characteristics of these terahertz waves change significantly with the azimuth angle of the device. This enables azimuth-sensitive detection, thereby achieving accurate analysis and reconstruction of the angle information of the target. Furthermore, the detection array with azimuth resolution capability not only significantly improves spatial resolution and target positioning accuracy but also effectively suppresses stray radiation and noise in complex backgrounds, thereby improving the overall signal-to-noise ratio and imaging quality, meeting the needs of high-precision directional detection and situational awareness applications.

[0052] The azimuth sensitivity of Comparative Examples 1-3 is significantly weaker than that of Examples 1-3.

[0053] In summary, by combining HF solution immersion post-treatment with pre-sputtering treatment and power adjustment during sputtering, terahertz (THz) radiation was achieved in a metal (TiN) system, challenging the conventional understanding that metals cannot serve as active THz emission sources.

[0054] To further investigate the effects of HF solution immersion and pre-sputtering treatment on the performance of the infrared detector, oxygen content and IV (current-voltage) characteristic curves were tested.

[0055] 2. Oxygen content test To investigate the effect of the pre-sputtering process in step S4, the composition of the TiN plasmonic layers prepared by Comparative Example 5 (pre-sputtered) and Comparative Example 6 (without pre-sputtering) was determined, as shown in Table 1 below. According to Table 1, the pre-sputtering process can effectively reduce the oxygen atom content of the TiN plasmonic layer.

[0056] Table 1. Composition determination of TiN plasmon layers. 3. IV (Current-Voltage) Characteristic Curve Test To investigate the effect of the "HF solution immersion treatment" in the post-processing step S2, infrared detectors prepared from Comparative Example 4 (treated with HF solution immersion treatment) and Comparative Example 6 (not treated with HF solution immersion treatment) were used to test the IV (current-voltage) characteristic curves. The test results are as follows: Figure 4 As shown, one of them, Figure 4 (a) corresponds to a ratio of 6. Figure 4 (b) corresponds to a ratio of 6.

[0057] Analysis shows that immersion in HF solution can improve the rectification characteristics of the Schottky junction, thereby enhancing the separation electric field and ultimately strengthening the TES signal. Specifically: First, HF (hydrofluoric acid) cleaning is a common surface treatment process designed to remove natural oxides (such as SiO2) and organic contaminants from the surface of semiconductor substrates (such as silicon). This study found that immersion in an HF solution after obtaining silicon nanowire arrays can effectively improve the rectification characteristics of Schottky junction devices. The mechanism is speculated to include: Reducing interface defect states: Oxides and contaminants on the substrate surface introduce high-density interface states (such as dangling bonds or charge traps). These defect states pin the Fermi level, weakening the formation of the built-in electric field. HF cleaning can effectively etch away the oxide layer, exposing a clean semiconductor surface, reducing the interface state density, and thus promoting a more ideal Schottky barrier construction.

[0058] Optimized band alignment: A clean interface allows the differences in the work functions of materials to be fully realized, resulting in more significant band bending and a stronger built-in electric field. For example, in Si-based heterojunctions, the surface work function after HF treatment is closer to the intrinsic value, enhancing charge transfer efficiency when in contact with metals, and improving the Schottky barrier height and rectification ratio.

[0059] Enhanced interface contact quality: HF cleaning can also improve the physical contact of heterojunctions, reduce interface voids or non-ideal layers, ensure that the built-in electric field is uniformly distributed at the interface, and avoid local electric field weakening.

[0060] This process significantly improves the rectification characteristics (i.e., unidirectional conductivity and built-in electric field strength) of the Schottky junction, laying the physical foundation for TES signal enhancement.

[0061] Secondly, a stronger separation electric field (i.e., a built-in electric field) directly amplifies the TES signal. This process involves multiple stages of carrier dynamics, each based on the heterojunction TES mechanism: Accelerated carrier separation efficiency: After the electric field is enhanced, the Coulomb force experienced by photogenerated electrons and holes at the interface is greater, and the separation speed is faster (completed on the sub-picosecond scale). This reduces the carrier recombination probability and increases the peak amplitude of the transient current.

[0062] Increasing transient current density: According to the drift-diffusion model, the transient current J(t) is proportional to the electric field strength E (J ∝ σE, where σ is the conductivity). Increased electric field directly increases the current density, resulting in a corresponding increase in the THz radiation electric field E_THz(t) ∝ dJ / dt.

[0063] Improved signal-to-noise ratio: A strong electric field can also suppress random noise caused by thermally excited carriers or defects, making the THz signal purer and more stable. For example, in a Schottky junction, improved rectification characteristics mean lower reverse bias leakage current, thereby reducing background interference and enhancing the signal-to-noise ratio of TES measurements.

[0064] 4. The carrier concentration / cm³ of the infrared detectors prepared in Example 1 and Comparative Example 6 were measured respectively. 3 Mobility, resistivity / ohm*cm.

[0065] Table 2 Compared with Comparative Example 6, Example 1 can effectively increase carrier concentration and improve mobility and resistivity.

[0066] The embodiments described in this specific implementation are preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, all equivalent changes made to the structure, shape, and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method for fabricating a CMOS-compatible azimuth-sensitive infrared detector, characterized in that, Includes the following steps: S1. Etching a silicon nanowire array onto a silicon substrate surface; S2. Immerse the silicon nanowire array in a 4.75-5.25% HF solution for 4.5-5.5 min to obtain the immersed silicon nanowire array. S3. After immersion, a dielectric layer is deposited on the silicon nanowire array to obtain the sample to be sputtered. S4. The sample to be sputtered is pre-sputtered in an inert gas atmosphere for 0.8-1.2 h to obtain a pre-sputtered sample. S5. Sputtering a TiN plasmonic layer onto the surface of the pre-sputtered sample's deposited layer; S6. Fabricate an upper electrode on the TiN plasmonic layer and fabricate a lower electrode on the side of the silicon substrate away from the TiN plasmonic layer.

2. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 1, characterized in that, In step S2, the silicon nanowire array is immersed in a 5% HF solution for 5 min.

3. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 1, characterized in that, In step S4, the inert gas atmosphere is Ar.

4. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 1, characterized in that, In step S5, the sputtering power is set to 700-800 W in the TiN plasmonic layer formed by sputtering on the surface of the pre-sputtered sample deposition layer.

5. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 4, characterized in that, In step S5, the sputtering power is 740-760 W.

6. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 4, characterized in that, In step S5, a TiN plasmonic layer is formed by sputtering on the surface of the pre-sputtered sample deposition layer. The thickness of the TiN plasmonic layer is 15-45 nm.

7. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 4, characterized in that, In step S5, a TiN plasmonic layer is formed on the surface of the pre-sputtered sample by sputtering, and the thickness of the TiN plasmonic layer is 20-35 nm.

8. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 4, characterized in that, In step S5, the chamber pressure in the TiN plasmonic layer formed by sputtering on the surface of the pre-sputtered sample is 0.48-0.52 Pa, the sputtering atmosphere is 90-94 sccm Ar 10-6 sccm N2, and the sputtering rate is 0.1-3 nm / min.

9. The method for fabricating a CMOS-compatible azimuth-sensitive infrared detector according to claim 1, characterized in that, Step S1, which involves etching a silicon nanowire array onto a silicon substrate surface, includes: Photolithography is used to form a nanowire array etching window to obtain a photolithographic silicon substrate; The photolithographic silicon substrate was immersed in a mixed solution of AgNO3, HF, and deionized water for 20 s to 4 min to obtain the immersed silicon substrate. The volume ratio of AgNO3, HF, and deionized water was AgNO3:HF:deionized water = 1-2:2.5-5:

9. The immersed silicon substrate was transferred to a mixed solution of HF, H2O2 and deionized water for etching for 4-15 min, wherein the volume ratio of HF, H2O2 and deionized water was HF:H2O2:deionized water = 5:0.5-5:

20.

10. A CMOS-compatible azimuth-sensitive infrared detector, characterized in that, It was prepared using the fabrication method of the CMOS-compatible azimuth-sensitive infrared detector as described in any one of claims 1-9.

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