Nuclear power DCS system timing method and system, electronic equipment and medium

Abstract

The invention provides a nuclear power DCS system time calibration method and system, an electronic device and a medium, in the method, when a time calibration task is responded, whether a reference clock is forcibly calibrated or not is judged through local time and first calendar time of a dynamic clock, and the reference clock is forcibly calibrated without forcibly calibrating; the crystal oscillator error is quantized based on the second calendar time and the local time of the reference clock so as to capture the actual condition of the crystal oscillator deviation, then the dynamic clock timing rate is corrected by combining the first calendar time, the local time and the quantization parameter, and the obtained crystal oscillator deviation compensation parameter can dynamically adjust the dynamic clock timing rate instead of direct hopping timing. Time deviation caused by crystal oscillator errors is eliminated, the time reference of lower-level equipment can be effectively unified, and the problem of time errors caused by the crystal oscillator errors among the modules in the nuclear power DCS system is effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of nuclear power systems, in particular to a nuclear power DCS system time correction method and system, electronic equipment and medium. BACKGROUND

[0002] For the multi-level time correction mechanism applied in the current nuclear power DCS (Distributed Control System) system, the time correction mechanism takes the DCS time correction source as the core node, and differentiates the time correction of the lower control layer according to the precision of different servers or controllers, so as to adapt to the time synchronization demand under the DCS distributed architecture. However, in the current multi-level time correction scene, in the process of the controller as the time source correcting the time of each module (such as IO module, server, communication interface module, etc.) in the control station, the time deviation between each module in the control station caused by the precision of the crystal oscillator device may cause the time correction boundary to appear event time rollback and / or event time advance. For details, please refer to Figure 1 A case of event time rollback and time advance is disclosed, as shown in the figure, the target time correction node is set as T0, the time output under the influence of the crystal oscillator error is T1 before T0 is reached, at this time if an event E1 occurs, the time mark of E1 will be before T1, which is the case of event time advance. Further, after reaching the target time correction node T0, if another event E2 occurs in the time period of T0-T1, the time mark of E2 will be before T1. In this case, although event E2 occurs after event E1, it occurs before E1 in the time mark layer, which is the case of event time rollback.

[0003] Based on this, the time error problem caused by the crystal oscillator error between each module in the control station in the nuclear power DCS system has become a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0004] Based on the above problems, in order to solve the time error problem caused by the crystal oscillator error between each module in the control station in the nuclear power DCS system, the present application provides a nuclear power DCS system time correction method, system, electronic equipment and medium.

[0005] The present application provides the following technical solutions: In a first aspect, the embodiments of the present application provide a nuclear power DCS system time correction method, applied to a DCS controller, the DCS controller comprising a clock control module, the clock control module comprising a dynamic clock and at least one reference clock; the dynamic clock being a clock source for a subordinate device in the DCS system; the calendar time recorded by the dynamic clock and the reference clock respectively being determined based on the accumulated time of the crystal oscillator clock frequency of the clock control module; the method comprising: in response to a time correction task processing request, obtaining a local time of the DCS controller and a first calendar time currently output by the dynamic clock; determining whether to perform forced correction processing on the reference clock according to the local time and the first calendar time; in a case where it is determined that forced time correction processing is not required on the reference clock, performing crystal oscillator error quantification according to a second calendar time currently output by the reference clock and the local time to obtain a crystal oscillator error quantification parameter; performing timing rate correction according to the first calendar time, the local time, and the crystal oscillator error quantification parameter to obtain a crystal oscillator deviation compensation parameter for the dynamic clock; the crystal oscillator deviation compensation parameter is used to adjust the timing rate of the dynamic clock.

[0006] In a possible implementation, the determining whether to perform forced correction processing on the reference clock according to the local time and the first calendar time comprises: determining a first calendar time difference between the local time and the first calendar time; in a case where the first calendar time is not greater than a first error threshold, determining that forced correction processing is not required on the reference clock; in a case where the first calendar time is greater than the first error threshold, determining that forced correction processing is required on the reference clock.

[0007] In a possible implementation, the performing crystal oscillator error quantification according to the second calendar time currently output by the reference clock and the local time to obtain a crystal oscillator error quantification parameter comprises: determining a second calendar time difference between the local time and the second calendar time; performing crystal oscillator error quantification according to a preset time correction interception period and the second calendar time difference to obtain the crystal oscillator error quantification parameter; the preset time correction interception period is determined based on the first error threshold and a pre-calibrated crystal oscillator frequency deviation.

[0008] In a possible implementation, the timing rate correction according to the first calendar time, the local time, and the crystal oscillator error quantization parameter to obtain a crystal oscillator deviation compensation parameter for the dynamic clock comprises: performing parameter calculation according to the first calendar time difference, a preset adjustment step of the dynamic clock, and the crystal oscillator error quantization parameter to obtain a timing rate adjustment parameter; determining a time calibration amplitude and a time calibration tendency for a timing rate of the dynamic clock according to the timing rate adjustment parameter; determining the time calibration amplitude and the time calibration tendency as the crystal oscillator deviation compensation parameter.

[0009] In a possible implementation, the time calibration tendency comprises: a lead calibration and a lag calibration. The determining of the time calibration amplitude and the time calibration tendency for the timing rate of the dynamic clock according to the timing rate adjustment parameter comprises: obtaining a numerical direction of the timing rate adjustment parameter; in a case where the numerical direction of the timing rate adjustment parameter is negative, determining the time calibration tendency as the lag calibration, and determining a negative numerical value of the timing rate adjustment parameter as the time calibration amplitude; in a case where the numerical direction of the timing rate adjustment parameter is positive, determining the time calibration tendency as the lead calibration, and determining a positive numerical value of the timing rate adjustment parameter as the time calibration amplitude.

[0010] In a possible implementation, the performing of the parameter calculation according to the first calendar time difference, the preset adjustment step of the dynamic clock, and the crystal oscillator error quantization parameter to obtain the timing rate adjustment parameter comprises: obtaining a numerical direction of the first calendar time difference; in a case where the numerical direction of the first calendar time difference is positive, determining a sum value between the crystal oscillator error quantization parameter and the preset adjustment step as the timing rate adjustment parameter; in a case where the numerical direction of the first calendar time difference is negative, determining a difference value between the crystal oscillator error quantization parameter and the preset adjustment step as the timing rate adjustment parameter.

[0011] In a second aspect, the embodiments of the present application provide a nuclear power DCS system time correction system, applied to a DCS controller, the DCS controller comprising a clock control module, a dynamic clock and at least one reference clock; the dynamic clock is a clock source for a subordinate device in the DCS system; the calendar time recorded by the dynamic clock and the reference clock is determined based on the accumulated time of the crystal oscillator clock frequency of the clock control module; the system comprises: a time acquisition module configured to acquire a local time of the DCS controller and a first calendar time currently output by the dynamic clock in response to a time correction task processing request; a determination module configured to determine whether to perform forced correction processing on the reference clock according to the local time and the first calendar time; an error quantification module configured to, in a case where it is determined that the forced time correction processing is not needed to be performed on the reference clock, perform crystal oscillator error quantification according to a second calendar time currently output by the reference clock and the local time to obtain a crystal oscillator error quantification parameter; a clock correction module configured to perform timing rate correction according to the first calendar time, the local time and the crystal oscillator error quantification parameter to obtain a crystal oscillator deviation compensation parameter for the dynamic clock; the crystal oscillator deviation compensation parameter is used to adjust the timing rate of the dynamic clock.

[0012] In a possible implementation, the determination module is specifically configured to: determine a first calendar time difference between the local time and the first calendar time; in a case where the first calendar time is not greater than a first error threshold, determine that the forced correction processing is not needed to be performed on the reference clock; in a case where the first calendar time is greater than the first error threshold, determine that the forced correction processing is needed to be performed on the reference clock.

[0013] In a third aspect, the embodiments of the present application provide an electronic device, the device comprising: a processor, a memory and a system bus; the processor and the memory are connected through the system bus; the memory is configured to store one or more programs, the one or more programs comprising instructions, the instructions causing the processor to execute any possible nuclear power DCS system time correction method in the first aspect when executed by the processor.

[0014] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, having a computer program stored thereon, the program being executed by a processor to implement any possible nuclear power DCS system time correction method in the first aspect.

[0015] Compared with the prior art, the application has the following beneficial effects: the embodiment of the application provides a nuclear power DCS system time correction method, system, electronic equipment and medium, in the method, the dynamic clock of the DCS controller is used as a subordinate clock source, and the reference clock is based on the same crystal frequency accumulation time of the clock control module, thereby reducing the error interference caused by the independent crystal of different modules from the basic level. When responding to the time correction task, whether to force the reference clock is judged by the local time and the first calendar time of the dynamic clock, thereby ensuring the reliability of the reference. In the case where the time correction is not forced, the crystal error is quantified based on the second calendar time of the reference clock and the local time, so as to capture the actual situation of the crystal deviation, and then the first calendar time, the local time and the quantization parameter are combined to correct the dynamic clock timing rate, so that the crystal deviation compensation parameter can dynamically adjust the dynamic clock timing rate, instead of directly jumping to correct the time, thereby effectively avoiding the time stamp jumping problem. This makes the time output by the dynamic clock always continuous and stable, eliminates the time deviation caused by the crystal error, effectively unifies the time reference of the subordinate equipment, greatly improves the resolution accuracy of the system time sequence event, and effectively solves the problem of time error caused by the crystal error between modules in the nuclear power DCS system. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A case diagram of event time stamp rollback and time time stamp advance is provided for the embodiment of the application. Figure 2 A structure diagram of a DCS controller is provided for the embodiment of the application. Figure 3 A flowchart of a nuclear power DCS system time correction method is provided for the embodiment of the application. Figure 4 A flowchart of determining a crystal deviation compensation parameter is provided for the embodiment of the application. Figure 5 A fluctuation diagram of a first calendar time difference is provided for the embodiment of the application. Figure 6 A structure diagram of a nuclear power DCS system time correction system is provided for the embodiment of the application. Figure 7 A structure diagram of an electronic equipment is provided for the embodiment of the application. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to specific embodiments and drawings. It should be specifically pointed out that the embodiments described in the embodiments of the present application are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0019] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the usual meanings understood by those of ordinary skill in the art to which the present application belongs. The terms "first", "second" and similar terms used in the embodiments of the present application do not represent any order, number or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] As described above, in the current multi-level time synchronization scenario, in the process of the controller as a time source to synchronize the time of each module (such as an IO module, a server, a communication interface module, etc.) in the control station, the time deviation between each module in the control station caused by the precision of the crystal oscillator device may cause the event time stamp to be rolled back and / or the event time stamp to be advanced when the time synchronization boundary event occurs. For details, please refer to Figure 1 A case of event time stamp rollback and time stamp advance is disclosed, as shown in the figure, the target time synchronization node is set as T0, the time output under the influence of the crystal oscillator error is T1 before T0 is reached, at this time if an event E1 occurs, the time stamp of E1 will be before T1, which is the case of event time stamp advance. Further, after the target time synchronization node T0 is reached, if another event E2 occurs in the time period of T0-T1, the time stamp of E2 will be before T1. In this case, although event E2 occurs after event E1, it occurs before E1 in the time stamp layer, and the event time stamp rollback occurs.

[0021] Based on this, the time error problem caused by the crystal oscillator error between each module in the control station in the nuclear power DCS system becomes a technical problem that those skilled in the art need to solve.

[0022] In view of the above problems, the embodiment of the present application provides a nuclear power DCS system time correction method and system, electronic equipment and medium. In the method, the dynamic clock of the DCS controller is used as a subordinate clock source, and the reference clock is based on the same crystal frequency accumulation time of the clock control module, thereby reducing the error interference caused by the independent crystal of different modules from the basic level. When responding to the time correction task, whether to force the reference clock is judged by the local time and the first calendar time of the dynamic clock, thereby ensuring the reliability of the reference. In the case of not needing to force the time correction, the crystal error is quantified based on the second calendar time of the reference clock and the local time, so as to capture the actual situation of the crystal deviation, and then the first calendar time, the local time and the quantization parameter are combined to correct the dynamic clock timing rate. The obtained crystal deviation compensation parameter can dynamically adjust the dynamic clock timing rate, rather than directly jump to the time correction, thereby effectively avoiding the time stamp jump problem. This makes the time output by the dynamic clock always continuous and stable, eliminates the time deviation caused by the crystal error, effectively unifies the time reference of the subordinate equipment, greatly improves the resolution accuracy of the system time sequence event, and effectively solves the time error problem caused by the crystal error between modules in the nuclear power DCS system.

[0023] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0024] Reference is made to Figure 2The figure is a structural schematic diagram of a DCS controller provided by the embodiment of the application. As shown in the figure, a hardware architecture of the DCS controller is adopted, which cooperates with a CPU and a clock control module (in a specific scenario, an FPGA board card can be used as the clock control module). The clock control module undertakes the basic functions of core clock generation and adjustment. The clock control module integrates a dynamic clock and at least one reference clock. Both of them are based on the crystal clock frequency of the clock control module, and form a complete calendar time through time accumulation, including year, month, day, hour, minute, second, millisecond and other dimensions, to provide bottom support for accurate clock recording. The dynamic clock is a dedicated clock source of the DCS system facing the subordinate equipment, which directly determines the time reference received by the subordinate equipment, and the reference clock is a reference basis for time calibration, which provides data support for the adjustment of the dynamic clock. The two clocks have unified basic configuration capabilities, and can reset the starting time through a software interface to realize time calibration. At the same time, the dynamic clock also has the additional dynamic adjustment characteristic, which can flexibly adjust the timing speed according to the subsequent parameter configuration, to meet the requirements of time stability and time calibration accuracy.

[0025] In particular, in a possible implementation, a plurality of reference clocks can be added in the DCS controller, and a reference event corresponding to the plurality of reference clocks is calculated through a weighted average algorithm, to further improve the step precision. The plurality of newly added reference clocks have the same logic as the single reference clock in the original setting logic, and all rely on the crystal clock frequency of the clock control module to accumulate and generate calendar time, only have the time calibration function without the dynamic adjustment capability, and the time deviation is purely determined by the hardware crystal precision, and the dynamic clock and the subordinate equipment share the same hardware crystal basis, to ensure the consistency of error sources. Through the weighted average calculation, the random errors of the reference clocks can be effectively offset, to provide a second calendar time with higher stability.

[0026] Referring to Figure 3 The figure is a flow schematic diagram of a time calibration method of a nuclear power DCS system provided by the embodiment of the application, which specifically includes the following steps: S101: In response to a time calibration task processing request, a local time of the DCS controller and a first calendar time currently output by the dynamic clock are acquired.

[0027] The triggering mode of the time correction task processing request in this step is based on real-time time monitoring of the DCS controller and state determination of the external clock source. Specifically, there are two time correction task triggering modes corresponding to the presence and absence of the external clock source. First, when the external clock source exists, the CPU continuously receives the time signals of the external stable clock sources such as NTP and NM197, and compares them with the local time of the DCS controller in real time. If the single deviation is less than the configurable error range, it is determined to be normal fluctuation, and no time correction is triggered. However, if the deviation exceeds the error range for several times in succession, it means that the deviation between the external clock source and the local time has accumulated to the extent of affecting the time reference of the subordinate equipment, and the CPU will immediately generate a time correction task processing request. Second, when there is no external clock source, the local and dynamic clock deviation triggers. The CPU obtains the output time of the dynamic clock in real time through the internal high-speed bus, compares it with the local time maintained by itself, and when the deviation exceeds the preset error threshold, the time correction task is triggered to force calibration to avoid the dynamic clock output time deviating from the reference continuously.

[0028] In response to the time correction task processing request, the DCS controller will accurately obtain the local time and the first calendar time currently output by the dynamic clock according to the predetermined process, to establish a data basis for subsequent deviation calculation and adjustment parameter configuration. Among them, the acquisition of the local time needs to be combined with the clock source state. When the external clock source is stable, the local time is the accurate time maintained by the CPU after synchronization with the external clock source, which has the reliability consistent with the external reference. When there is no external time correction source or the external source fails, the local time is the reference time constructed by the controller itself based on the hardware time sequence, which is continuously maintained by the CPU to ensure its stability. The first calendar time is the real-time output time of the dynamic clock, which is generated by the dynamic clock on the clock control module based on the crystal clock frequency. After the dynamic adjustment in the early stage, it directly provides time reference for subordinate IO modules and other equipment. During the acquisition process, the CPU establishes low-delay communication with the clock control module (such as FPGA board) through the high-speed bus, quickly reads the current calendar time data of the dynamic clock in the clock control module, and ensures the real-time of the first calendar time.

[0029] S102: Determine whether to perform forced calibration processing on the reference clock according to the local time and the first calendar time.

[0030] In the time correction logic of the DCS controller, whether to perform the forced correction processing on the reference clock according to the local time and the first calendar time is a prerequisite for ensuring the reliability of the time reference. The essence of this step is to determine through the time difference to avoid the subsequent time adjustment logic from being invalid due to the accumulation of deviation, and to ensure that the reference clock can always provide a reliable reference. When it is determined that the forced correction processing on the reference clock is not needed, the reference clock is only used as a reference for quantifying the error of the crystal oscillator in the hardware device, and the subsequent time correction process is only performed on the dynamic clock and does not involve the reference clock, so as to ensure the accurate quantification of the error of the crystal oscillator. On the contrary, when it is determined that the forced correction processing on the reference clock is needed, it indicates that there is a serious time error in the controller, and the time correction processing only for the dynamic clock cannot ensure the rapid recovery of the correct time. Therefore, in this case, both the dynamic clock and the reference clock need to perform the forced time correction processing, and the reference clock is no longer used as the basis for quantifying the error of the crystal oscillator, and both types of clocks perform the forced time correction processing at the same time to reset the time and prevent the accumulation of errors.

[0031] Specifically, the step of determining whether to perform the forced correction processing on the reference clock in step S102 is implemented through the following three steps: Step one, determining the first calendar time difference between the local time and the first calendar time.

[0032] In the time correction logic of the DCS controller, whether to perform the forced correction processing on the reference clock according to the local time and the first calendar time is a prerequisite for ensuring the reliability of the time reference. The essence of this step is to determine through the time difference to avoid the subsequent time adjustment logic from being invalid due to the accumulation of deviation, and to ensure that the reference clock can always provide a reliable reference. When it is determined that the forced correction processing on the reference clock is not needed, the reference clock is only used as a reference for quantifying the error of the crystal oscillator in the hardware device, and the subsequent time correction process is only performed on the dynamic clock and does not involve the reference clock, so as to ensure the accurate quantification of the error of the crystal oscillator. On the contrary, when it is determined that the forced correction processing on the reference clock is needed, it indicates that there is a serious time error in the controller, and the time correction processing only for the dynamic clock cannot ensure the rapid recovery of the correct time. Therefore, in this case, both the dynamic clock and the reference clock need to perform the forced time correction processing, and the reference clock is no longer used as the basis for quantifying the error of the crystal oscillator, and both types of clocks perform the forced time correction processing at the same time to reset the time and prevent the accumulation of errors.

[0033] Step two, determining that the forced correction processing on the reference clock is not needed in the case that the first calendar time is not greater than the first error threshold.

[0034] The first error threshold is a criterion for determining whether to perform forced calibration. The first error threshold can be flexibly configured in combination with the frequency deviation parameter of the crystal oscillator device, the tolerance of the subordinate device to time stability, the accuracy requirement of the on-site event timing analysis, and other actual scenarios. When the calculated first calendar time difference is not greater than the threshold, it is determined that forced calibration of the reference clock is not needed. At this time, the deviation of the dynamic clock from the local time is within the acceptable range of the system, and the time state of the reference clock also remains in a reasonable interval, and can still provide a reliable reference for subsequent dynamic adjustment. Subsequently, only the dynamic adjustment parameters need to be calculated by the CPU, and the timing rate of the dynamic clock is fine-tuned by the clock control module, so that small deviations can be gradually offset, the continuity of time output is maintained, and the timing stability of the DCS system is improved.

[0035] Step three, in the case where the first calendar time is greater than the first error threshold, it is determined that forced calibration processing of the reference clock is needed.

[0036] When the first calendar time difference exceeds the first error threshold, it is determined that forced calibration processing of the reference clock is needed. At this time, the deviation has exceeded the compensation capability of the dynamic adjustment mechanism, and if not timely intervened, the time reference value of the reference clock will be greatly reduced, and the crystal oscillator deviation quantified based thereon will have a significant error, causing the adjustment direction and amplitude of the dynamic clock to deviate from the actual demand, and ultimately causing problems such as time stamp jumping of the subordinate device and timing event judgment confusion. Specifically, the processing flow of forced calibration is executed by the CPU, and a time correction instruction is sent to the clock control module through a software interface to synchronously reset the starting time of the reference clock and the dynamic clock, so that they are quickly synchronized with the local time maintained by the CPU. This synchronous reset method can quickly restore the reference consistency of the entire clock system without causing time asynchrony problems that may be caused by single clock calibration, and can effectively compensate for the defects of related technologies in handling large time deviations.

[0037] S103: In the case where it is determined that forced time correction processing of the reference clock is not needed, the crystal oscillator error is quantified according to the second calendar time currently output by the reference clock and the local time, to obtain a crystal oscillator error quantification parameter.

[0038] In the scenario where it is determined that no forced time correction processing needs to be performed on the reference clock, the crystal oscillator error needs to be quantified according to the second calendar time currently output by the reference clock and the local time of the DCS controller, so as to accurately characterize the crystal oscillator error existing between the current hardware devices when transmitting time data, which will serve as the basis for subsequent adjustment of the timing rate of the dynamic clock, so as to compensate the crystal oscillator error between the hardware devices into the current timing data and achieve accurate time correction. Specifically, the reason why the second calendar time output by the reference clock can quantify the crystal oscillator error of the hardware device lies in the core of the design characteristics and the purity of the time generation logic. The reference clock and the dynamic clock are homologous, and are both formed based on the same crystal oscillator clock frequency accumulated by the clock control module in the DCS controller to form a calendar time, and share the same hardware crystal oscillator basis, which ensures that the error source of the reference clock is completely consistent with the crystal oscillator error of the dynamic clock and the subordinate device. At the same time, the reference clock only has time correction function without dynamic adjustment capability, and will not be affected by the adjustment parameters, step correction and other human interventions, and the time deviation is only caused by the precision defects of the crystal oscillator itself (such as frequency drift and ppm deviation), which isolates other interference factors and can truly reflect the original error state of the hardware crystal oscillator. When the second calendar time is compared with the local time maintained by the CPU, the second calendar time difference between the two is the cumulative error of the crystal oscillator in the preset time correction interception period, and the preset time correction interception period is accurately calculated in combination with the ppm parameter of the crystal oscillator and the system allowed error threshold, which can match the error accumulation rate. The cumulative error can be converted into a quantization parameter through a specific formula, which directly corresponds to the actual frequency deviation of the crystal oscillator, so as to accurately quantify the hardware crystal oscillator error.

[0039] Specifically, the process of quantifying the crystal oscillator error according to the second calendar time and the local time in step S103 is realized through the following two steps: Step one, determining the second calendar time difference between the local time and the second calendar time.

[0040] Determining the second calendar time difference between the local time and the second calendar time is the premise of quantifying the crystal oscillator error, which functions to capture the cumulative time deviation caused by the hardware crystal oscillator deviation. The difference between the local time and the second calendar time is the total amount of time deviation caused by the crystal oscillator deviation in the preset time correction interception period, and the positive and negative of the difference directly reflects the leading or lag phenomenon of the reference clock relative to the local time, thereby providing intuitive and reliable original data for subsequent error quantification and ensuring that the quantification result matches the actual situation of the hardware.

[0041] Step two, quantifying the crystal oscillator error according to the preset time correction interception period and the second calendar time difference to obtain the crystal oscillator error quantification parameter; the preset time correction interception period is determined based on the first error threshold and the pre-calibrated crystal oscillator frequency deviation.

[0042] Further, the crystal oscillator error quantification according to the preset time correction interception period and the second calendar time difference is a link of converting the time offset into an operable adjustment parameter. The preset time correction interception period is calculated in combination with the first error threshold and the pre-labeled crystal oscillator frequency deviation. The first error threshold is the maximum time deviation allowed by the system, which is directly related to the tolerance of the subordinate equipment to the time stability; the crystal oscillator frequency deviation determines the accumulation rate of the error, and the greater the ppm value, the faster the error accumulates per unit time. The logic of designing the preset time correction interception period is to complete the quantification and adjustment before the time error accumulates to the first error threshold, so as to avoid triggering the forced time correction and ensure the continuity of the time output.

[0043] Specifically, the quantification process of the crystal oscillator error quantification parameter is realized through a specific formula, that is, the crystal oscillator error quantification parameter (Pb) = -Tb (1000000000 / (Tc 60 1000), wherein Tb represents the second calendar time difference, and Tc represents the preset time correction interception period. The essence of the formula is to allocate the total time deviation in the preset time correction interception period to each crystal oscillator period, and to convert the time difference into a second-level adjustment parameter through unit conversion.

[0044] S104: correcting the timing rate according to the first calendar time, the local time and the crystal oscillator error quantification parameter to obtain a crystal oscillator deviation compensation parameter for the dynamic clock; the crystal oscillator deviation compensation parameter is used to adjust the timing rate of the dynamic clock.

[0045] Finally, on the basis of obtaining the crystal oscillator error quantification parameter, the current time deviation can be determined in combination with the first calendar time and the local time output by the dynamic clock, and the timing rate of the dynamic clock is further corrected through the hardware crystal oscillator error represented by the crystal oscillator error quantification parameter, which can double-optimize the timing parameters of the dynamic clock from two aspects of the actual time error and the hardware crystal oscillator error, so as to improve the time correction accuracy and the time stability.

[0046] The crystal oscillator error quantization parameter has quantized the inherent error characteristics of the hardware crystal oscillator based on the real deviation of the reference clock, and the comparison result of the first calendar time and the local time can directly reflect the actual event deviation of the dynamic clock at present. The combination of the two and the local time makes the generated crystal oscillator deviation compensation parameter adapt to the inherent error law of the hardware crystal oscillator, so as to adapt to the real-time running state of the dynamic clock and avoid overcompensation or undercompensation. The compensation parameter is not a direct time correction of the dynamic clock, but a smooth correction through adjusting the timing rate, so as to avoid the time jump problem caused by direct time correction in the prior art and ensure the continuity of time output. At the same time, it can continuously and dynamically adapt to the cumulative change of the crystal oscillator deviation. Whether the external time correction source is stable, missing or invalid, the dynamic clock can always keep consistent with the system reference time, thereby unifying the time reference of each device and improving the resolution accuracy of the system time sequence event, and providing key time support for the reliable operation of the DCS system.

[0047] Next, the process of determining the crystal oscillator deviation compensation parameter in step S104 will be introduced in combination with specific flow embodiments and drawings. Referring to Figure 4 , which is a flow diagram for determining the crystal oscillator deviation compensation parameter provided by the embodiments of the present application, and specifically includes the following steps: S1041: performing parameter calculation according to the first calendar time difference, the preset adjustment step of the dynamic clock and the crystal oscillator error quantization parameter to obtain a timing rate adjustment parameter.

[0048] In this step, the first calendar time difference as the real-time deviation of the dynamic clock and the local time can effectively reflect the time deviation direction and size of the dynamic clock at present. When the first calendar time difference is greater than 0, it means that the dynamic clock is ahead of the local time, otherwise, it means that the dynamic clock is lagging behind. The crystal oscillator error quantization parameter is data calculated based on the time deviation of the reference clock and the preset time correction interception, which is used to quantify the error law of the hardware crystal oscillator and provide a basis for the timing rate adjustment parameter. The preset adjustment step of the dynamic clock plays a role in smooth adjustment. The design purpose of the preset adjustment step is to avoid time jump caused by too large single adjustment amplitude. The calculation logic of the three needs to be adjusted according to the value direction of the first calendar time difference, which specifically includes the following three steps: Step one, obtaining the value direction of the first calendar time difference.

[0049] The positive and negative of the value direction directly reflects the running state of the dynamic clock: when the value direction is positive, it means that the timing speed of the dynamic clock is faster than the local time, and there is a leading deviation, which needs to be slowed down to approach the reference; on the contrary, when the value direction is negative, it means that the timing speed of the dynamic clock is slower than the local time, and there is a lagging deviation, which needs to be accelerated to catch up.

[0050] Step two, in the case of the first calendar time difference being positive, the sum value between the crystal oscillator error quantization parameter and the preset adjustment step is determined as the timing rate adjustment parameter.

[0051] Step three, in the case of the first calendar time difference being negative, the difference value between the crystal oscillator error quantization parameter and the preset adjustment step is determined as the timing rate adjustment parameter.

[0052] After determining the numerical direction of the first calendar time difference, the system generates a timing rate adjustment parameter based on the preset adjustment logic. When the numerical direction is positive, it means that the dynamic clock is running fast, and it needs to be corrected by reducing its timing rate. The specific method is to perform a sum operation between the crystal oscillator error quantization parameter and the preset adjustment step to determine the timing rate adjustment parameter. The crystal oscillator error quantization parameter is the basis for adjustment obtained by analyzing the running data of the reference clock, which reflects the average error level of the crystal oscillator in a period of time. The preset adjustment step is the adjustment amplitude set according to the system's requirement for time resolution, used to control the precision of each adjustment and prevent time jump. The essence of the sum is to add a positive adjustment amount to the basic error to suppress the fast trend of the dynamic clock, i.e. Pa=Pb+Pp; in the formula, Pa represents the timing rate adjustment parameter, Pb represents the crystal oscillator error quantization parameter, and Pp represents the preset adjustment step of the dynamic clock. Conversely, when the numerical direction is negative, the dynamic clock is running slowly, and it needs to be corrected by increasing its timing rate. The system will perform a difference operation between the crystal oscillator error quantization parameter and the preset adjustment step, i.e. Pa=Pb-Pp, to reduce the basic error amount and speed up the running speed of the dynamic clock, so that the time difference between the two gradually decreases. In this way, precise control can be implemented for different deviation states, ensuring the pertinence of the adjustment and taking into account the continuity of the time output, effectively solving the deviation correction problem of the dynamic clock ahead of time, and making the adjustment parameter more suitable for the actual running state of the hardware. It needs to be noted that in the process of generating the timing rate adjustment parameter, the parameter adjustment range of the dynamic clock needs to be synchronized, i.e. the adjustable timing range, to ensure the calculation accuracy of the timing rate adjustment parameter.

[0053] The role of the timing rate adjustment logic in this step is to achieve adaptive correction of the clock system through dynamic calculation. Whether the clock runs fast or slow, the direction of the first calendar time difference is used to determine the timing rate adjustment parameters. These parameters are then combined with the crystal oscillator error quantization parameters and a preset adjustment step to generate precise timing rate adjustment parameters. The hardware logic of the clock control module then fine-tunes the timing rate of the dynamic clock. This mechanism allows the controller to automatically eliminate time errors caused by crystal oscillator accuracy deviations without external intervention, ensuring a continuous and stable time base for the next-level devices and avoiding the timestamp jump problems that may occur in traditional solutions. Simultaneously, the configurability of the preset adjustment step allows the DCS system to adapt to the time resolution requirements of different scenarios. This simplifies system time synchronization design and effectively improves the accuracy of time sequence event resolution and overall availability in complex industrial environments such as nuclear power DCS systems.

[0054] S1042: Determine the time calibration amplitude and time calibration tendency for the dynamic clock timing rate based on the timing rate adjustment parameters.

[0055] In this step, the time calibration amplitude of the dynamic clock timing rate refers to the amount of adjustment to the clock's running speed, while the time calibration tendency is the direction of adjustment, including lead calibration and lag calibration. As mentioned earlier, the function of the timing rate adjustment parameter is to transform abstract time errors into executable calibration instructions. The value of this parameter is essentially an indicator of the clock's running state. When the value is negative, it indicates that the current dynamic clock's timing rate is slower than the reference time, meaning its accumulated time value lags behind expectations; if the value is positive, it means the dynamic clock's timing rate is faster, and the time value leads the reference. Therefore, when determining the time calibration amplitude and time calibration tendency based on the timing rate adjustment parameter, the direction of the timing rate adjustment parameter's value also needs to be considered. This process is mainly achieved through the following three steps: Step 1: Obtain the numerical direction of the timing rate adjustment parameter; Step 2: When the numerical direction of the timing rate adjustment parameter is negative, the time calibration tendency is determined as the hysteresis calibration, and the negative value of the timing rate adjustment parameter is determined as the time calibration amplitude. Step 3: When the numerical direction of the timing rate adjustment parameter is positive, the time calibration tendency is determined as the advance calibration, and the positive value of the timing rate adjustment parameter is determined as the time calibration amplitude.

[0056] In this embodiment, the direction of the timing rate adjustment parameter is crucial for determining the dynamic clock's operating state. A negative value indicates a lag in the dynamic clock, and the time calibration tendency is determined to be lag calibration. The corresponding processing logic involves reducing the clock's timing rate to minimize the deviation between the first calendar time and the reference time. Specifically, the system sets the negative value of the timing rate adjustment parameter as the time calibration amplitude, i.e., the time calibration amplitude M = -Pa (timing rate adjustment parameter). In this formula, the negative value of the timing rate adjustment parameter represents the amount of lag that needs to be compensated. For example, when the timing rate adjustment parameter is -10000 nanoseconds / cycle, the calibration amplitude is 10000 nanoseconds / cycle, meaning that the dynamic clock needs to record 10000 nanoseconds less in each crystal oscillator cycle to slow its accumulation and gradually catch up with the reference time. Conversely, when the parameter direction is positive, the dynamic clock is in a leading state, and the calibration tendency becomes leading calibration. The system directly uses the positive value as the calibration amplitude. For example, a parameter of +8000 nanoseconds / cycle means that 8000 nanoseconds need to be recorded per crystal oscillator cycle, correcting the leading error by accelerating the accumulation speed. This design, which binds the parameter sign to the calibration tendency and corresponds the absolute value of the timing rate adjustment parameter to the calibration amplitude term, can suppress excessively fast tendencies and compensate for excessively slow lags, ensuring that the dynamic clock always fluctuates within the acceptable error range of the reference time (see [link to product description] for details). Figure 5 The diagram illustrates the fluctuation of the first calendar time difference, where Ta represents the first calendar time difference between the first calendar time and the local time, and the controller standard time corresponds to the local time of the DCS controller.

[0057] S1043: The time calibration amplitude and the time calibration tendency are determined as the crystal oscillator deviation compensation parameters.

[0058] This application provides a time synchronization method, system, electronic device, and medium for a nuclear power DCS system. In this method, the dynamic clock of the DCS controller serves as a dedicated clock source for lower-level devices. Both the dynamic clock and the reference clock are based on the accumulated time of the crystal oscillator frequency of the same clock control module, reducing error interference caused by independent crystal oscillators in different modules at the fundamental level. When responding to a time synchronization task, the system determines whether to force synchronization of the reference clock by comparing the local time with the first calendar time of the dynamic clock, ensuring the reliability of the reference. When forced time synchronization is not required, the crystal oscillator error is quantized based on the second calendar time of the reference clock and the local time to capture the actual crystal oscillator deviation. This is then combined with the first calendar time, local time, and quantization parameters to correct the dynamic clock timing rate. The resulting crystal oscillator deviation compensation parameters dynamically adjust the dynamic clock timing rate instead of directly jumping to synchronize the time, effectively avoiding timestamp jumps. This ensures that the time output by the dynamic clock remains continuous and stable, eliminating time deviations caused by crystal oscillator errors and effectively unifying the time reference of lower-level devices. This significantly improves the resolution accuracy of system timing events and effectively solves the time error problem caused by crystal oscillator errors between modules within a nuclear power DCS system.

[0059] The following describes a nuclear power DCS system time synchronization system provided in the embodiments of this application. The nuclear power DCS system time synchronization system described below and the nuclear power DCS system time synchronization method described above can be referred to in correspondence.

[0060] See Figure 6 The figure is a schematic diagram of the structure of a nuclear power DCS system time synchronization system provided in an embodiment of this application, which specifically includes the following modules: The time acquisition module 100 is used to acquire the local time of the DCS controller and the first calendar time currently output by the dynamic clock in response to the time synchronization task processing request. The determining module 200 is configured to determine, based on the local time and the first calendar time, whether to perform a forced calibration process on the reference clock; The error quantization module 300 is used to perform crystal oscillator error quantization based on the second calendar time currently output by the reference clock and the local time when it is determined that there is no need to perform forced time synchronization processing on the reference clock, so as to obtain crystal oscillator error quantization parameters. The clock correction module 400 is used to correct the timing rate based on the first calendar time, the local time, and the crystal oscillator error quantization parameter to obtain the crystal oscillator deviation compensation parameter for the dynamic clock; the crystal oscillator deviation compensation parameter is used to adjust the timing rate of the dynamic clock.

[0061] In one possible implementation, the determining module 200 is specifically used for: Determine the first calendar time difference between the local time and the first calendar time; If the first calendar time is not greater than the first error threshold, it is determined that no forced calibration process needs to be performed on the reference clock; If the first calendar time is greater than the first error threshold, it is determined that a forced calibration process needs to be performed on the reference clock.

[0062] See Figure 7 The figure is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including: Memory 11 is used to store computer programs; The processor 12 is used to implement the steps of the time synchronization method for a nuclear power DCS system as described in any of the above method embodiments when executing the computer program.

[0063] In this embodiment, the device can be an in-vehicle computer, a PC (Personal Computer), or a terminal device such as a smartphone, tablet computer, handheld computer, or portable computer.

[0064] The device may include a memory 11, a processor 12, and a bus 13.

[0065] The memory 11 includes at least one type of readable storage medium, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the device, such as the hard disk of the device. In other embodiments, the memory 11 can also be an external storage device of the device, such as a plug-in hard disk, SmartMediaCard (SMC), SecureDigital (SD) card, FlashCard, etc., all equipped on the device. Furthermore, the memory 11 can include both internal and external storage units of the device. The memory 11 can be used not only to store application software and various types of data installed on the device, such as program code executing fault scenario screening methods, but also to temporarily store data that has been output or will be output. In some embodiments, the processor 12 can be a central processing unit (CPU).

[0066] In some embodiments, processor 12 may be a central processing unit (CPU), controller, microcontroller, microprocessor or other data processing chip, used to run program code stored in memory 11 or process data, such as program code for executing a fault scenario screening method.

[0067] This bus 13 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0068] Furthermore, the device may also include a network interface 14, which may optionally include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), typically used to establish communication connections between the device and other electronic devices.

[0069] Optionally, the device may further include a user interface 15, which may include a display, an input unit such as a keyboard, and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the device and to display a visual user interface.

[0070] Figure 7 Only devices with components 11-15 are shown; those skilled in the art will understand that... Figure 7 The structure shown does not constitute a limitation on the device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0071] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a computer-readable storage medium storing computer instructions for causing the computer to execute the nuclear power DCS system time synchronization method as described in any of the above embodiments.

[0072] The computer-readable media in this application embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0073] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the nuclear power DCS system time synchronization method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0074] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the system, method, electronic device, and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The system, method, electronic device, and medium embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0075] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A time synchronization method for a nuclear power plant DCS system, characterized in that, Applied in a DCS controller, the DCS controller includes a clock control module, the clock control module includes a dynamic clock and at least one reference clock; The dynamic clock is the clock source for lower-level devices in the DCS system. The calendar times recorded by the dynamic clock and the reference clock are both determined based on the accumulated time of the crystal oscillator clock frequency of the clock control module; the method includes: In response to the time synchronization task processing request, the local time of the DCS controller and the first calendar time currently output by the dynamic clock are obtained; Based on the local time and the first calendar time, determine whether to perform a forced calibration process on the reference clock; If it is determined that no forced time synchronization processing is required for the reference clock, the crystal oscillator error is quantized according to the second calendar time currently output by the reference clock and the local time to obtain the crystal oscillator error quantization parameters. The timing rate is corrected based on the first calendar time, the local time, and the crystal oscillator error quantization parameter to obtain the crystal oscillator deviation compensation parameter for the dynamic clock; the crystal oscillator deviation compensation parameter is used to adjust the timing rate of the dynamic clock.

2. The method according to claim 1, characterized in that, The step of determining whether to perform a forced calibration process on the reference clock based on the local time and the first calendar time includes: Determine the first calendar time difference between the local time and the first calendar time; If the first calendar time is not greater than the first error threshold, it is determined that no forced calibration process needs to be performed on the reference clock; If the first calendar time is greater than the first error threshold, it is determined that a forced calibration process needs to be performed on the reference clock.

3. The method according to claim 2, characterized in that, The step of performing crystal oscillator error quantization based on the second calendar time currently output by the reference clock and the local time to obtain crystal oscillator error quantization parameters includes: Determine the second calendar time difference between the local time and the second calendar time; The crystal oscillator error is quantized based on the preset time synchronization interception period and the second calendar time difference to obtain the crystal oscillator error quantization parameter; the preset time synchronization interception period is determined based on the first error threshold and the pre-calibrated crystal oscillator frequency deviation.

4. The method according to claim 2, characterized in that, The step of correcting the timing rate based on the first calendar time, the local time, and the crystal oscillator error quantization parameters to obtain crystal oscillator deviation compensation parameters for the dynamic clock includes: The timing rate adjustment parameters are obtained by calculating parameters based on the first calendar time difference, the preset adjustment step of the dynamic clock, and the crystal oscillator error quantization parameters. Based on the timing rate adjustment parameters, determine the time calibration amplitude and time calibration tendency for the dynamic clock timing rate; The time calibration amplitude and the time calibration tendency are determined as the crystal oscillator deviation compensation parameters.

5. The method according to claim 4, characterized in that, The time calibration tendencies include: leading calibration and lagging calibration; The step of determining the time calibration amplitude and time calibration tendency for the dynamic clock timing rate based on the timing rate adjustment parameters includes: Obtain the numerical direction of the timing rate adjustment parameter; When the numerical direction of the timing rate adjustment parameter is negative, the time calibration tendency is determined as the hysteresis calibration, and the negative value of the timing rate adjustment parameter is determined as the time calibration amplitude. When the numerical direction of the timing rate adjustment parameter is positive, the time calibration tendency is determined as the advance calibration, and the positive value of the timing rate adjustment parameter is determined as the time calibration amplitude.

6. The method according to claim 4, characterized in that, The step of calculating the timing rate adjustment parameters based on the first calendar time difference, the preset adjustment step of the dynamic clock, and the crystal oscillator error quantization parameters includes: Obtain the direction of the first calendar time difference; When the numerical direction of the first calendar time difference is positive, the summation between the crystal oscillator error quantization parameter and the preset adjustment step is determined as the timing rate adjustment parameter; When the numerical direction of the first calendar time difference is negative, the difference between the crystal oscillator error quantization parameter and the preset adjustment step is determined as the timing rate adjustment parameter.

7. A time synchronization system for a nuclear power plant DCS system, characterized in that, This is applied in a DCS controller, which includes a clock control module, a dynamic clock, and at least one reference clock; the dynamic clock is the clock source for lower-level devices in the DCS system. The calendar times recorded by the dynamic clock and the reference clock are both determined based on the accumulated time of the crystal oscillator clock frequency of the clock control module; the system includes: The time acquisition module is used to respond to the time synchronization task processing request, acquire the local time of the DCS controller, and the first calendar time currently output by the dynamic clock; The determining module is configured to determine, based on the local time and the first calendar time, whether to perform a forced calibration process on the reference clock; The error quantization module is used to perform crystal oscillator error quantization based on the second calendar time currently output by the reference clock and the local time when it is determined that there is no need to perform forced time synchronization processing on the reference clock, so as to obtain crystal oscillator error quantization parameters. The clock correction module is used to correct the timing rate based on the first calendar time, the local time, and the crystal oscillator error quantization parameter to obtain the crystal oscillator deviation compensation parameter for the dynamic clock; the crystal oscillator deviation compensation parameter is used to adjust the timing rate of the dynamic clock.

8. The system according to claim 7, characterized in that, The determining module is specifically used for: Determine the first calendar time difference between the local time and the first calendar time; If the first calendar time is not greater than the first error threshold, it is determined that no forced calibration process needs to be performed on the reference clock; If the first calendar time is greater than the first error threshold, it is determined that a forced calibration process needs to be performed on the reference clock.

9. An electronic device, characterized in that, The device includes: a processor, a memory, and a system bus; The processor and the memory are connected via the system bus; The memory is used to store one or more programs, the one or more programs including instructions that, when executed by the processor, cause the processor to perform the nuclear power DCS system time synchronization method according to any one of claims 1-6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the nuclear power DCS system time synchronization method as described in any one of claims 1-6.

Images