Content addressable memory and semiconductor device

Abstract

The invention relates to a content addressable memory and a semiconductor device. A content addressable memory includes a cell array capable of storing a plurality of data entries, a plurality of valid cells provided for each of the data entries, a full invalidation detection circuit, a search unit, and a control unit, the storage unit is configured to store valid bits indicating that the data entries are valid or invalid, the full-invalidation detection circuit is configured to detect that all of the plurality of valid bits indicate invalidation, and the search unit is configured to determine whether the plurality of data entries are matched or not matched with the search data; the control unit is configured to stop the search unit when the full invalidation detection circuit detects that all significant bits indicate invalidation.

Description

Cross Reference to Related Applications

[0001] The disclosure of Japanese Patent Application No. 2024-174875 filed on October 4, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. BACKGROUND

[0002] The present application relates to a content addressable memory and a semiconductor device, for example, a semiconductor device having a content addressable memory, which has a function of determining a match between a plurality of data entries and search data.

[0003] A storage device called a search memory or a content addressable memory (CAM) searches for a word matching a search word (search data) among stored data words (also called data entries), and outputs the address thereof when a matching data word is found.

[0004] A CAM includes a BCAM (binary CAM) and a TCAM (ternary CAM). Each memory cell of a BCAM stores information "0" or "1". On the other hand, in the case of a TCAM, each memory cell can store "don't care" information in addition to "0" and "1". "Don't care" indicates that either "0" or "1" is acceptable.

[0005] A TCAM has been widely used for address search and access control in routers in networks such as the Internet.

[0006] A technique is disclosed below.

[0007] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2018-206451

[0008] Patent Literature 1 describes that a content addressable memory has a valid cell that stores, for each data entry, a valid bit indicating whether the data entry is valid or invalid. SUMMARY

[0009] The valid bit (valid cell) described in Patent Literature 1 indicates whether a data entry is valid or invalid, and can reduce power consumption of match line precharge and the like by excluding data entries whose valid bits are invalid from the target of a search operation. On the other hand, since a search line provided with search data crosses a plurality of data entries, a search operation cannot stop as long as there is one data entry whose valid bit indicates valid.

[0010] Embodiments to be described below are made in consideration of the above-described circumstances, and other problems and novel features will be apparent from the description of the present specification and drawings.

[0011] A content addressable memory according to an embodiment includes a cell array, a valid cell, an invalid detection cell, a first search cell, and a control cell, the cell array is capable of storing a plurality of data entries, the valid cell is provided for each of the data entries and is configured to store information indicating that the data entry is valid or invalid, the invalid detection cell is configured to detect that the information all indicates invalid, the first search cell is configured to determine a match or a mismatch between the plurality of data entries and search data inputted from outside, and the control cell is configured to deactivate the first search cell when the invalid detection cell detects that the information all indicates invalid.

[0012] According to the above-described embodiment, it is possible to reduce power consumption of the content addressable memory. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a schematic diagram of a conventional content addressable memory;

[0014] Figure 2 is a schematic configuration diagram of a content addressable memory according to a first embodiment;

[0015] Figure 3 is a circuit diagram of a main part of the content addressable memory in Figure 2

[0016] Figure 4 is a circuit diagram of a timing generation circuit;

[0017] Figure 5 is a schematic diagram of a valid cell;

[0018] Figure 6 is a circuit diagram of a BL / SL driver;

[0019] Figure 7 is a circuit diagram of a match line output circuit;

[0020] Figure 8 is a circuit diagram of an All-invalid detection circuit;

[0021] Figure 9 is a flowchart showing an operation of the content addressable memory according to the first embodiment;

[0022] Figure 10 is a schematic diagram of a semiconductor device provided with a plurality of content addressable memories;

[0023] Figure 11 is a circuit diagram of a timing generation circuit according to a second embodiment;

[0024] Figure 12 ​is a flowchart showing operation of the content addressable memory according to the second embodiment;

[0025] Figure 13 is a schematic diagram of a semiconductor device according to the third embodiment; and

[0026] Figure 14 is a schematic diagram showing an application example of the present embodiment. DETAILED DESCRIPTION

[0027] In the following embodiments, the present application will be described in a plurality of sections or embodiments, if necessary, for the convenience of explanation, but these sections or embodiments are not independent of each other unless otherwise specified, and one section or embodiment has a modified, detailed, supplementary description, etc. relationship with a part or all of another section or embodiment. In addition, in the following embodiments, when referring to the number of elements and the like (including the number, numerical value, amount, range, and the like), the number is not limited to a specific number unless otherwise specified or fundamentally limited to a specific number. The number can be equal to or greater than or less than the specific number.

[0028] In addition, in the following embodiments, it is self-evident that components (including element steps and the like) are not necessarily essential unless otherwise specified or fundamentally considered to be obviously essential. Similarly, in the following embodiments, when referring to the shape, positional relationship, and the like of components and the like, it is assumed to include components substantially approximate or similar to the shape and the like unless otherwise specified or fundamentally considered. The same applies to the above numerical values and ranges.

[0029] In addition, the circuit elements of each functional block constituting the embodiments are not particularly limited, but are formed on a semiconductor substrate such as a single-crystal silicon substrate by a well-known integrated circuit technology for a complementary MOS transistor (CMOS) or the like. In the embodiments, a metal oxide semiconductor field effect transistor (MOSFET, simply referred to as MOS transistor) is used as an example of a metal insulator semiconductor field effect transistor (MISFET), but this does not exclude the use of a non-oxide film as a gate insulating film. In addition, in the embodiments, a p-channel MOSFET and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively.

[0030] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, fundamentally the same components are denoted by the same reference numerals, and repetitive description thereof will be omitted.

[0031] (First Embodiment)

[0032] Figure 1A schematic diagram of a semiconductor device according to the present embodiment is shown. In the present embodiment, a content addressable memory will be described in which a search operation is performed on a cell array including a plurality of TCAM cells in a row direction, the cells being arranged in a matrix and configured to store data entries (hereinafter, in some cases, simply referred to as entries) consisting of bit strings consisting of a plurality of bits.

[0033] [Problems to be Solved by the Present Embodiment]

[0034] As described above, although measures for reducing power consumption of match line precharge and the like have conventionally been taken, as Figure 1 As shown on the left side, the search line spans a plurality of entries, and therefore the search operation cannot stop as long as there is one entry whose valid bit indicates valid. Figure 1 is a schematic diagram of a conventional content addressable memory 100, in which reference numeral 101 denotes a cell array, reference numeral 102 denotes a peripheral circuit such as a control unit and the like, and reference numeral SL denotes a search line. The cell array 101 includes TCAM cells in which data to be data entries are stored and the above-described valid cells. The peripheral circuit 102 controls writing to and reading from the cell array 101, and performs match determination between input search data and data entries stored in the TCAM cells and the like.

[0035] Conventionally, as Figure 1 As shown on the left side, the content addressable memory 100 is configured to have one cell array 101 (for example, a capacity of 1 Mbit). This is because, when the cell array 101 is divided into, for example, four portions each having 256 bits, and area saving is prioritized, the area of the peripheral circuit 102 increases greatly.

[0036] However, in recent years, there has been a demand for content addressable memories that operate at a higher frequency than before, and this demand is sometimes satisfied using a configuration of a content addressable memory having a plurality of divisions (for example, a configuration of a content addressable memory having four divisions) Figure 1 on the right side. Figure 1 on the right side is a schematic diagram of a configuration of a content addressable memory including a plurality of divisions. Figure 1 Reference numerals 100a, 100b, 100c, and 100d on the right side respectively denote divided content addressable memories, and the four content addressable memories 100a, 100b, 100c, and 100d combined together have the same capacity as the content addressable memory shown on the left side.

[0037] In Figure 1In the case where data of even only one entry is written in the configuration of one cell array 101 shown on the left side, the validity and invalidity of the valid bits of the cell array 101 exist mixedly, and thus it is not possible to stop the search operation. However, by dividing the cell array into a plurality of cell arrays 101 as shown on the right side, it is possible to have a content addressable memory in which all the data entries stored in one cell array 101 are invalid. For example, if valid data entries are sequentially written from a certain content addressable memory, the content addressable memories to which data has not been written are all invalid. In Figure 1 In the case where the valid bits of the content addressable memories 100a, 100b, and 100c are all invalid, the content addressable memories 100a, 100b, and 100c do not store valid data. Thus, the content addressable memories 100a, 100b, and 100c consume unnecessary power during the search operation.

[0038] [Outline of the Present Embodiment]

[0039] A content addressable memory according to the present embodiment will be described with reference to Figure 2 A content addressable memory 1 includes an input / output circuit 11, a cell array 12, a full invalidity detection circuit 13, a match line output circuit 14, a control unit 15, and a word line driver 16.

[0040] The input / output circuit 11 inputs data to be stored in the cell array 12, and outputs read data. The input / output circuit 11 also receives search data for determining whether or not the data stored in the cell array 12 (data entry) matches.

[0041] The cell array 12 includes a TCAM cell that stores data to be a data entry, and a valid cell that stores a valid bit, which is information indicating whether each data entry is valid or invalid. In other words, the cell array 12 can store a plurality of data entries, and further includes a valid cell that is provided for each data entry and stores information indicating that the data entry is valid or invalid.

[0042] The full invalidity detection circuit 13 detects whether or not the valid bits stored in all the valid cells indicate invalidity. In other words, the full invalidity detection circuit 13 functions as an invalidity detection unit that detects that all the valid bits indicate invalidity. The match line output circuit 14 bundles and outputs the match lines outputted from the cell array 12 per data entry. The control unit 15 includes a timing generation circuit and the like, which will be described later, and controls the operation of the content addressable memory 1. The word line driver 16 drives a word line for accessing the TCAM cell of the cell array 12.

[0043] In Figure 2The search unit 10 is configured of the input / output circuit 11, the cell array 12, the match line output circuit 14, and the word line driver 16 shown in the content addressable memory 1. In other words, the search unit 10 functions as a first search unit that determines a match or a mismatch between a plurality of data entries and search data.

[0044] [Circuit example of this embodiment]

[0045] Next, a circuit example of the content addressable memory 1 will be described with reference to Figures 3 to 8 The circuit shown below is an example, and it goes without saying that other circuit configurations can be used as long as they can achieve the same functions. Furthermore, the logic levels indicating the assertion and negation of each signal can also be changed as appropriate. Figure 3 A circuit example of the main part of the content addressable memory 1 is shown.

[0046] Figure 3 The BL / SL driver 11a shown corresponds to Figure 2 The input / output circuit 11 shown. The BL / SL driver 11a shows only the part of the functions of the input / output circuit 11 that is related to the search line SL into which search data is input. Similarly, Figure 3 The timing generation circuit 15a shown corresponds to Figure 2 The control unit 15 shown. The timing generation circuit 15a is a circuit that generates control signals mainly related to search operations among the functions of the control unit 15. Similarly, Figure 3 The WL / ML driver 16a shown corresponds to Figure 2 The word line driver 16 shown. In addition to the circuit that drives the word line, the WL / ML driver 16a also includes a circuit that drives the match line that indicates whether an entry matches the search data.

[0047] The cell array 12 includes a plurality of TCAM cells MC arranged in a matrix. Furthermore, there is provided one valid cell VC for each row (each entry). Furthermore, there are provided a word line WL and a match line ML along the row direction, and a pair of search lines SL, SLB along the column direction. That is, there is provided one word line WL and one match line ML for each entry, and there are provided search lines that span a plurality of entries.

[0048] Figure 3The reference numeral 17 in FIG. 1 indicates a precharge circuit. The precharge circuit 17 includes a two-input NAND circuit and a pMOS transistor. An output signal of the valid cell VC and a control signal PCE are input to the two-input NAND circuit. The source of the pMOS transistor is connected to the match line ML, the drain thereof is connected to Vdd, and the gate thereof is connected to the output of the two-input NAND circuit. The precharge circuit 17 is provided for each entry (match line ML). As described later, the control signal PCE is generated by the timing generation circuit 15a and is asserted during the search operation. The precharge circuit 17 precharges the match line ML according to the value of the valid cell VC during the search operation.

[0049] Figure 4 is an example of a circuit diagram of the timing generation circuit 15a. The timing generation circuit 15a is a circuit that generates the control signal PCE, the control signal MAE, and the control signal SLE in response to the clock signal CLK. In the circuit of Figure 4 In the circuit of the timing generation circuit 15a, the assertion of the control signals PCE and SLE is stopped when the control signal AIF is input. As described later, the control signal AIF is an output signal of the all invalid detection circuit 13, and the control signals PCE and SLE are signals that are asserted during the search operation. Therefore, when the all invalid detection circuit 13 detects that all valid bits indicate invalid, the timing generation circuit 15a stops the search unit 10.

[0050] The timing generation circuit 15a includes flip-flops 1501 and 1502, AND circuits 1503 and 1504, inverters 1505, 1509, 1518, 1520, 1521, 1522, 1523, and 1524, a pMOS transistor 1506 and 1512, nMOS transistors 1507, 1508, 1513, and 1514, capacitor elements 1510 and 1515, NOR circuits 1511 and 1516, and NAND circuits 1517 and 1519.

[0051] The flip-flop 1501 receives and outputs a control signal CEN based on the clock signal CLK. The control signal CEN is a chip enable signal, and is a control signal that controls the validity and invalidity of the clock signal CLK. The flip-flop 1502 receives and outputs a control signal CMP based on the clock signal CLK. The control signal CMP is a search request signal.

[0052] The AND circuit 1503 receives the clock signal CLK, the inverted signal of the output of the flip-flop 1501, and the output signal of the flip-flop 1502, and outputs the result of the AND logical operation (control signal CK1). The AND circuit 1504 receives the control signal CK1 and the inverted signal of the output of the inverter 1518, and outputs the result of the AND logical operation (control signal TDECCM).

[0053] The inverter 1505 inverts the control signal TDECCM and outputs it to the gate of the pMOS transistor 1506, the gate of the nMOS transistor 1507, and the gate of the nMOS transistor 1508.

[0054] The pMOS transistor 1506 and the nMOS transistors 1507 and 1508 are connected in series between a power supply potential (voltage Vdd level) and a ground potential (voltage Vss level). The control signal is output from the connection node between the pMOS transistor 1506 and the nMOS transistor 1507.

[0055] The inverter 1509 inverts and outputs the control signal output from the connection node between the pMOS transistor 1506 and the nMOS transistor 1507.

[0056] The NOR circuit 1511 inverts the control signal output from the connection node between the pMOS transistor 1506 and the nMOS transistor 1507 and outputs it to the gate of the pMOS transistor 1512, the gate of the nMOS transistor 1513, and the gate of the nMOS transistor 1514. Further, the capacitor element 1510 (whose other electrode is connected to the ground potential (voltage Vss level)) is connected to the input node of the NOR circuit 1511.

[0057] The pMOS transistor 1512 and the nMOS transistors 1513 and 1514 are connected in series between the power supply potential and the ground potential. The control signal is output from the connection node between the pMOS transistor 1512 and the nMOS transistor 1513.

[0058] The NOR circuit 1516 inverts and outputs the control signal output from the connection node between the pMOS transistor 1512 and the nMOS transistor 1513. Further, the capacitor element 1515 (whose other electrode is connected to the ground potential) is connected to the input node of the NOR circuit 1516.

[0059] The NAND circuit 1517 receives the output signal of the NOR circuit 1516 and the output signal of the inverter 1509 and outputs the result of the NAND logical operation. The inverter 1518 inverts and outputs the output signal of the NAND circuit 1517 (control signal BACKCM).

[0060] The NAND circuit 1519 receives the control signal TDECCM, the output signal of the NAND circuit 1517, and the control signal AIF and outputs the result of the NAND logical operation. The inverters 1520 and 1521 output the output of the NAND circuit 1519 as the control signal PCE.

[0061] The inverters 1522 and 1523 output the output signal of the NAND circuit 1519 as a control signal SLE. The inverter 1524 inverts the control signal BACKCM and outputs it as a control signal MAE.

[0062] Figure 5 is an example of a circuit of an effective cell VC. The effective cell VC includes pMOS transistors V1, V3, and V7 and nMOS transistors V2, V4, V5, V6, V8, and V9.

[0063] The pMOS transistor V1 and the nMOS transistor V2 are connected in series between, for example, a power supply potential Vdd and a power supply potential Vss to form an inverter (hereinafter referred to as a first inverter for identification). Further, the pMOS transistor V3 and the nMOS transistor V4 are connected in series between, for example, the power supply potential Vdd and the power supply potential Vss to form an inverter (hereinafter referred to as a second inverter for identification). Further, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter.

[0064] The source and drain of the nMOS transistor V5 are connected between the output of the first inverter and a bit line VBT. Further, the gate of the nMOS transistor V5 is connected to a word line WL. The source and drain of the nMOS transistor V6 are connected between the output of the second inverter and a bit line VBB. Further, the gate of the nMOS transistor V6 is connected to the word line WL. The bit line pair VBT, VBB is a wiring shared by each effective cell VC. The word line WL is a wiring shared by an entry (TCAM cell MC) corresponding to the effective cell VC.

[0065] The pMOS transistor V7 and the nMOS transistor V8 are connected in series between, for example, the power supply potential Vdd and the power supply potential Vss to form an inverter (hereinafter referred to as a third inverter for identification). The output of the second inverter is input to the third inverter. Further, the output of the third inverter is input to the precharge circuit 17 and the all-invalidation detection circuit 13 as an effective bit.

[0066] The source and drain of the nMOS transistor V9 are connected between the power supply potential Vss and the input of the second inverter. The gate of the nMOS transistor V9 is connected to a reset signal RT. The reset signal RT is a signal shared by each effective cell VC.

[0067] When the word line WL is in a selected state, an effective bit can be written to the effective cell VC by supplying write data to the effective cell VC via the bit line pair VBT, VBB.

[0068] Figure 6is an example of a circuit of the BL / SL driver 11a. The BL / SL driver 11a includes a flip-flop 111, an inverter 112, and NOR circuits 113 and 114. Figure 6 The circuit corresponding to one search line pair SL, SLB is shown, and Figure 6 The circuit of is actually provided as a plurality of circuits according to the number of bits of the data entry (and the search data).

[0069] The flip-flop 111 receives the search data supplied to the data terminal D based on the clock signal CLK and outputs it to the NOR circuits 113 and 114. The inverter 112 inverts the control signal SLE and outputs it.

[0070] The NOR circuit 113 receives the output signal of the flip-flop 111 and the output signal of the inverter 112 and outputs the result of the NOR logic operation as the search line SLB. The NOR circuit 114 receives the inverted output of the flip-flop 111 and the output signal of the inverter 112 and outputs the result of the NOR logic operation as the search line SLB.

[0071] The BL / SL driver 11a is a circuit that asserts the search line pair SL, SLB to each TCAM cell MC. When the control signal SLE becomes Hi, the set of search data in the data terminal D is asserted to the search line pair SLB, SLB. Therefore, as described in the timing generation circuit 15a, when the control signal AIF stops the assertion of the control signal SLE, the assertion of the search data stops. In other words, the control unit 15 stops the input of the search data based on the control signal AIF (invalidation control signal).

[0072] Figure 7 is an example of the match line output circuit 14. Figure 7 is a circuit corresponding to one match line ML, and Figure 7 The circuit in is actually provided as a plurality of circuits according to the number of match lines ML (the number of entries).

[0073] The WL / ML driver 16a includes a pMOS transistor 161. The source and drain of the pMOS transistor 161 are connected between the power supply potential (voltage Vdd level) and the match line ML. The control signal PCE is connected to the gate of the pMOS transistor 161. The WL / ML driver 16a is a circuit for driving the match line ML. When the control signal PCE is Lo, the match line ML is precharged, and when the control signal PCE is Hi, the precharge is cut off.

[0074] The match line output circuit 14 includes inverters 142, 143, 144, 145, and 146.

[0075] When the control signal MAE is input, the inverter 142 outputs an inverted signal of the match line ML. The inverter 143 outputs an inverted signal of the output signal of the inverter 142 or the inverter 144 as an All-miss determination input AMI. The All-miss determination input is an input signal for determining whether all data entries are not matched (missed) due to a search operation.

[0076] When the control signal MAE is input, the inverter 144 outputs an inverted signal of the output signal of the inverter 143. When a signal is output from the inverter 142, the inverter 145 outputs an inverted signal of the output signal of the inverter 142 to the match signal output line MLO. Further, when a signal is output from the inverter 144, the inverter 145 outputs an inverted signal of the output signal of the inverter 144 to the match signal output line MLO. The inverter 146 outputs an inverted signal of the control signal MAE as a control signal of the inverters 142 and 144.

[0077] The control signal MAE is asserted at the timing at which the match line ML is determined, and the match line output circuit 14 transfers the data of the match line MLO to the match signal output line MLO and the All-miss determination input AMI.

[0078] In detail, when the control signal MAE is asserted, the inverter 142 turns on and outputs an inverted signal of the match line ML. At the same time, the inverter 144 turns off, and thus does not output a signal. Therefore, when the control signal MAE is asserted, the data of the match line ML is transferred to the match signal output line MLO and the All-miss determination input AMI. When the control signal MAE is negated, the inverter 142 turns off, and thus does not output a signal. At the same time, the inverter 144 turns on and inverts the output signal of the inverter 143, and returns it to the inverter 143, and also outputs it to the inverter 145. Therefore, when the control signal MAE is negated, the signal level of the match signal output line MLO and the All-miss determination input AMI is maintained at its previous value.

[0079] Figure 8 is an example of the All-invalid detection circuit 13. The All-invalid detection circuit 13 is a circuit that outputs a control signal AIF when all valid cells VC indicate invalid. In other words, when all entries are invalid, the control signal AIF is asserted. In Figure 8 In the, the All-invalid detection circuit 13 is shown as being constituted by AND circuits connected in multiple stages, but other circuit configurations can also be used as long as they are capable of achieving the above-described function.

[0080] [Operation of the present embodiment]

[0081] Next, the operation of the present embodiment will be described with reference to Figure 9The flowchart in FIG. 1 describes the operation of the content addressable memory 1 configured as described above. First, the content addressable memory 1 is powered (step S101). Next, the control unit 15 initializes all valid cells VC to invalid (all invalid) (step S102). This is because all data in the TCAM cells MC is invalid data immediately after power-up. In step S102, a reset signal RT is output from the control unit 15 to initialize all valid cells VC to the invalid state.

[0082] Next, the writing of initial data and valid cells VC is performed (step S103). In step S103, the initial data is written to the TCAM cells MC of the cell array 12, and the valid cells VC corresponding to the entries that have been written with the initial data are set to valid.

[0083] Next, when a search key (search data) is input from the input / output circuit 11 (step S104), the all invalid detection circuit 13 determines whether all valid cells VC are invalid (all invalid) (step S105). If the result of the determination in step S105 is all invalid (step S105: YES), the control signals PCE and SLE are asserted, and the processing proceeds to step S108 without performing steps S106 and S107.

[0084] On the other hand, if the result of the determination in step S105 is not all invalid (step S105: NO), the control signals PCE and SLE are asserted, and the processing proceeds to step S106. Then, a search operation is performed using the search key input in step S104 (step S106), and a match or no match is determined (step S107). In other words, the value of the match line ML of each entry is output as a match signal output line MLO. Here, steps S104 to S107 are performed within one processing cycle. In the present embodiment, one processing cycle is one period of the clock signal CLK.

[0085] Next, it is determined whether the next processing cycle is a search operation or a write operation (step S108). When a control signal CMP indicating a search request is input to the control unit 15, it is determined that the next processing cycle is a search operation, and when a control signal WEN indicating a write request is input to the control unit 15, it is determined that the next processing cycle is a write operation.

[0086] When it is determined in step S108 that the next processing cycle is a search operation, the processing returns to step S104. On the other hand, when it is determined in step S108 that the next processing cycle is a write operation, the processing proceeds to step S109. In step S109, data is written, and the valid cells VC corresponding to the data entries that have been written with the data are set to valid. Step S109 is performed within one processing cycle.

[0087] Next, it is determined whether the next processing cycle is a search operation or a write operation (step S110). The determination of the search operation or the write operation is the same as in step S108. When it is determined in step S110 that the next processing cycle is a search operation, the processing returns to step S104. On the other hand, when it is determined in step S110 that the next processing cycle is a write operation, the processing returns to step S109.

[0088] Here, even when valid data is written in the data entry, the content addressable memory 1 can invalidate the data to secure the writable area when the data in the data entry is no longer needed. Therefore, even when the initial data is written in the data entry Figure 9 after the flowchart, the full invalidation can be established in the determination in step S105. Further, the writing of the initial data in step S103 can be omitted. When the writing of the initial data in step S103 is omitted, the full invalidation is established in the determination in step S105 until the valid data is written.

[0089] The content addressable memory 1 that operates in this way is preferably applied to a configuration in which it is divided into a plurality of content addressable memories as shown in Figure 10 . Figure 10 is a schematic diagram of a semiconductor device 20 including a plurality of content addressable memories 1. In the configuration of Figure 10 , the same search data is input to each of the plurality of content addressable memories 1.

[0090] In the configuration of Figure 10 , four content addressable memories 1 are handled as one memory having continuous addresses from the outside. For example, it can be used so that valid data can be sequentially stored from the bottommost content addressable memory 1 as shown in Figure 10 . Therefore, there can be a state in which valid data is stored only in the bottommost content addressable memory 1, and the other content addressable memories 1 are all invalidated. In this case, the search operation of the content addressable memories 1 that are all invalidated can be stopped by the control signal AIF output by the full invalidation detection circuit 13.

[0091] With the above configuration, when the full invalidation is detected by the full invalidation detection circuit 13 that detects that all of the plurality of valid cells VC indicate invalidation, the content addressable memory 1 stops the search unit 10. Therefore, the search operation can be stopped in units of the content addressable memories 1, and thus the power consumption can be reduced.

[0092] Further, since the semiconductor device 20 has a plurality of content addressable memories 1, and the same search data is input to each of the plurality of content addressable memories 1, each content addressable memory 1 can be used as a storage capacity capable of high-speed operation. This makes it possible to improve the speed of the semiconductor device 20 while reducing its power consumption.

[0093] (Second Embodiment)

[0094] Next, a second embodiment will be described. Hereinafter, the description of the portion overlapping with the above-described embodiment will be omitted in principle.

[0095] [Problem to be Solved by the Present Embodiment]

[0096] The control signal AIF described in the first embodiment is a signal for stopping the control signal PCE and the like asserted during the search operation in accordance with the state of the valid cell VC. When causing the rewrite of the valid cell VC, the control signal AIF must reach the control unit 15 within the period between the data update and the next processing cycle. In other words, the control signal AIF must change from the asserted state to the negated state within the period between the data update and the next cycle. However, in the case of a chip (semiconductor device) in which the valid cell VC changes greatly, the next processing cycle can start before the control signal AIF is negated, resulting in a malfunction. Although such a chip with a large change can be regarded as a defective chip by testing or the like, this results in a decrease in yield. The present embodiment deals with such a change in the valid cell VC.

[0097] [Circuit Example of the Present Embodiment]

[0098] In the present embodiment, the timing generation circuit 15a is partially modified. Figure 11 The timing generation circuit 15a according to the present embodiment is shown. With respect to Figure 4 the circuit shown in Figure 11 The flip-flops 1525 and 1526, the NOR circuit 1527, the latch 1528, and the OR circuit 1529 are added to the timing generation circuit 15a shown in

[0099] The flip-flop 1525 receives and outputs a control signal RST based on a clock signal CLK. The control signal RST is a reset signal. The flip-flop 1526 receives and outputs a control signal WEN based on the clock signal CLK. As described in the first embodiment, the control signal WEN is a write request signal (write control signal).

[0100] The NOR circuit 1527 receives the output signals of the flip-flops 1501, 1502, 1525, and 1526, and outputs the result of NOR logic operation. The latch 1528 latches the output signal of the NOR circuit 1527 based on the clock signal CLK. The OR circuit 1529 receives the output signal of the latch 1528 and the control signal AIF, and outputs the result of OR logic operation. The output of the OR circuit 1529 becomes an input signal of the NAND circuit 1519.

[0101] In Figure 11 In the circuit shown, the control signals (CEN, WEN, CMP, RST) input to the control unit 15 are held in flip-flops, and the outputs of these flip-flops are bundled and latched to be logically ORed with the control signal AIF. In this way, the state of the content addressable memory 1 one processing cycle ago can be referred to, and if the state is a write, the search is forced to be performed regardless of the control signal AIF. In other words, the latch 1528 functions as a holding unit that holds the control signal indicating a write request for one processing cycle. Then, when the latch 1528 holds the control signal indicating a write request, the timing generation circuit 15a operates the search unit 10 regardless of the result of the all invalid detection circuit 13.

[0102] [Operation of this embodiment]

[0103] Next, the operation of the content addressable memory 1 configured as described above will be described with reference to the flowchart in Figure 12 Figure 12 The flowchart shown is different from the flowchart shown in Figure 9 in that, when it is determined in step S110 that the next processing cycle is a search operation, the return destination is step S106.

[0104] In other words, since the data and the valid unit VC are updated in step S109, the previous processing cycle was a write, and therefore, when a search operation is to be performed in the next processing cycle, the search operation is performed without the need to determine "all invalid". That is, in the next processing cycle of the processing cycle in which the valid unit VC stores valid, the control unit 15 operates the search unit 10 regardless of the result of the all invalid detection circuit 13.

[0105] ​With the above configuration, when the all-invalidation detection circuit 13 stops the search unit 10, if the next processing cycle of the processing cycle in which the write has occurred in the cell array 12 is a search, the content addressable memory 1 performs the search regardless of the control signal AIF output by the all-invalidation detection circuit 13. Thus, by adding a circuit in which a failure is less likely to occur, even a chip (semiconductor device) in which the valid cell VC greatly changes can be stably operated. As a result, the yield of the semiconductor device 20 can be improved.

[0106] (Third Embodiment)

[0107] Next, a third embodiment will be described. Hereinafter, the description of the portion overlapping with the above-described embodiments will be omitted in principle.

[0108] A configuration of a content addressable memory in which a cell array is divided into a plurality of portions in the bit direction and a search operation of a later cell array is stopped if all entries in a previous cell array do not match has been proposed (for example, see Japanese Unexamined Patent Application Publication No. 2023-114100). In this way, from the result that all entries in the previous cell array do not match, it is possible to determine the non-matching of the entire content addressable memory without performing a search in the next cell array. In the present embodiment, the content addressable memory 1 is applied to such a configuration.

[0109] Figure 13 A schematic configuration of the semiconductor device 20 according to the present embodiment is shown. The semiconductor device 20 includes the content addressable memory 1 and content addressable memories 100a and 100b. In the present embodiment, the content addressable memories 100a and 100b are configured in the same manner as the content addressable memory 1. Figure 13 In the configuration of the content addressable memory 1, the stored data (data entry) is divided into a plurality of memory blocks along the column direction (bit direction) of the cell array. That is, the content addressable memory 1 is a first block, and the content addressable memories 100a and 100b are combined together to form a second block. Further, the content addressable memories 100a and 100b each form a sub-block. Further, the content addressable memory 1 can be referred to as a master block, and the content addressable memories 100a and 100b can be referred to as slave blocks.

[0110] Figure 13 The content addressable memory 1 including only the input / output circuit 11, the cell array 12, the match line output circuit 14, and the control unit 15 is shown in FIG. 10, but it has the same configuration as that shown in FIG. 1, and further includes the all-invalidation detection circuit 13, the word line driver 16, and the like. Figure 2 The content addressable memories 100a and 100b each include the input / output circuit 11, the cell array 12, the match line output circuit 14, and the control unit 15, but they have the same configuration as that shown in FIG. 1, and further include the all-invalidation detection circuit 13, the word line driver 16, and the like.

[0111] The content addressable memories 100a and 100b have the same configuration as the content addressable memory 1. However, the all-miss detection circuit 13 that is a feature of the content addressable memory 1 can not be provided, and the control function of the timing generation circuit 15a using the control signal AIF can also not be provided. In other words, in the content addressable memories 100a and 100b, the cell array 12 functions as a second cell array, and the input / output circuit 11, the match line output circuit 14, and the like function as a second search unit.

[0112] In Figure 13 In the semiconductor device 20 illustrated, one data entry or search data is divided and input to each of the content addressable memories 1, 100a, and 100b accordingly. For example, when the cell arrays 12 of the content addressable memories 1, 100a, and 100b are each 40 bits, 120 bits of data are each divided into 40 bits, and stored as a data entry at the same address of each cell array 12. Then, search data is also each divided into 40 bits, and input to each input / output circuit 11. That is, the 40 bits stored in the content addressable memory 1 correspond to a first portion, and the 80 bits stored in the content addressable memories 100a and 100b correspond to a second portion. Further, in the 80 bits corresponding to the second portion, the 40 bits stored in the content addressable memory 100a and the 40 bits stored in the content addressable memory 100b each correspond to a third portion.

[0113] In Figure 13 In the configuration illustrated, the search operation of the master block is executed in a first processing cycle, and the search operation of the slave blocks is executed in a second processing cycle. When the search operation of the content addressable memory 1 as the master block results in all data entries not matching, it stops the search operation of the content addressable memories 100a and 100b as the slave blocks to be executed in the next processing cycle.

[0114] In this case, the control unit 15 of the content addressable memory 1 detects that all data entries in the cell array 12 do not match, and outputs a control signal for stopping the slave blocks to the control unit 15 of each slave block (content addressable memories 100a and 100b). Specifically, with reference to Figure 7 The all-miss determination input AMI is illustrated, when the all-miss determination input AMI corresponding to all the match lines ML indicates a miss, the control signal for stopping the slave devices described above is output. In other words, when the search unit 10 determines that all entries do not match, the control unit 15 stops the search operation of the second blocks.

[0115] In Figure 13In the illustrated configuration, the second block is composed of two sub-blocks (content addressable memories 100a and 100b), but the number of sub-blocks can be three or more. Further, the second block need not be divided into sub-blocks.

[0116] With the above configuration, by using the content addressable memory 1 as the main block, the power consumption of the main block that is frequently operated can be reduced.

[0117] (Application Examples)

[0118] Finally, application examples of the above embodiments will be described. Figure 10 The illustrated semiconductor device 20 and other devices can be used for address search and access control in a router of a network such as the Internet. Figure 14 An example of an address search system in a router using the semiconductor device 20 is shown.

[0119] Figure 14 The illustrated address search system 60 includes the semiconductor device 20, a PLL 51, a central control device 52, a data input block 53, and an output processing block 54.

[0120] The semiconductor device 20 includes a plurality of content addressable memories 1, as shown in Figure 10 The same search data is input to each of the plurality of content addressable memories 1.

[0121] The PLL 51 is a well-known phase-locked loop circuit, and outputs a clock signal CLK to the semiconductor device 20. The central control device 52 outputs a search request signal to the semiconductor device 20. Further, the central control device 52 outputs search data to the data input block 53. The data input block 53 outputs the search data input from the central control device 52 to the semiconductor device 20. Based on the search result output from the semiconductor device 20, the output processing block 54 outputs a matching (hit) address to the central control device 52.

[0122] Figure 14 The illustrated address search system 60 stores network data such as IP addresses in advance. Then, after starting a search operation, the central control device 52 inputs a search request signal to the semiconductor device 20, while inputting data to be searched from the data input block 53 to the semiconductor device 20. The semiconductor device 20 compares the data stored in the cell array 12 with the data to be searched, and transmits all matching addresses to the output processing block 54. The output processing block 54 outputs the corresponding address having the highest priority to the central control device 52. The priority can be determined by the address, for example, by placing information having a high priority at a lower address of the cell array, or can be determined by providing a priority encoder or the like.

[0123] In the foregoing, the invention made by the present inventors has been specifically described based on the embodiments, but it is needless to say that the present invention is not limited to the above-described embodiments, but can be variously modified without departing from the scope of the gist thereof.

Claims

1. A content-addressable memory, comprising: A cell array can store multiple data entries; A valid unit is provided for each data entry in the data entries and is configured to store information indicating whether the data entry is valid or invalid; The invalidity detection unit is configured to detect that all of the information indicates invalidity; The first search unit is configured to determine whether the plurality of data entries match or do not match with search data input from an external source; as well as The control unit is configured to stop the first search unit when the invalidity detection unit detects that all the information indicates invalidity.

2. The content-addressable memory according to claim 1, The invalid detection unit outputs an invalid control signal indicating that all the information is invalid, and The control unit stops the input of the search data based on the invalid control signal.

3. The content-addressable memory according to claim 1, The control unit operates the first search unit in the next processing cycle after the processing cycle in which valid information is stored in the valid unit, regardless of the result of the invalid detection unit.

4. The content-addressable memory according to claim 3, The control unit includes a holding unit configured to hold a write control signal indicating a write request for one processing cycle. When the holding unit holds the write control signal, the control unit operates the first search unit regardless of the result of the invalid detection unit.

5. A semiconductor device comprising a plurality of content-addressable memories according to claim 1, The same search data is input into each of the plurality of content-addressable memories.

6. A semiconductor device, comprising: The first block includes the content-addressable memory as described in claim 1, and is configured to store a first portion of the bit string constituting the data entry; as well as The second block is configured to store a second portion of the bit string other than the first portion. The search data has the same number of bits as the bit string that constitutes the data entry. The second block includes a second cell array and a second search unit. The second cell array is capable of storing multiple second portions, and the second search unit is configured to determine whether the multiple second portions match or not match with the corresponding portions of the search data. The portion of the bit string that constitutes the search data, corresponding to the first part, is input into the first block, and When the first search unit determines that none of the data entries match, the control unit stops the search operation of the second block.

7. The semiconductor device according to claim 6, The second block is composed of multiple sub-blocks, and the multiple sub-blocks store each of the multiple third parts that constitute the second part.

Images