Frequency jittering circuit and DCDC conversion circuit
By adjusting the amplitude of the initial dithering control signal through a dithering control module and an amplitude processing module, and combining a low-pass filter module and a bias current source, the problem of large dithering variation range in the prior art is solved, and a smaller dithering variation range and circuit integration are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LEN TECH LTD
- Filing Date
- 2026-03-12
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies struggle to achieve a smaller range of frequency variation while maintaining the accuracy of the frequency dithering cycle.
The initial dithering control signal is output by the dithering control module, and its amplitude is adjusted by the amplitude processing module. Combined with the low-pass filter module and the bias current source, the target dithering control signal is output to the clock signal generation module to achieve a smaller dithering variation range.
While ensuring the accuracy of the dithering cycle, the range of dithering variation is reduced, the circuit area is reduced, and it is easy to integrate.
Smart Images
Figure CN121813852B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and in particular to a frequency dithering circuit and a DC-DC conversion circuit. Background Technology
[0002] During switching, the voltage and current changes of the switching transistor in a DC-DC converter are very steep, generating strong electromagnetic interference (EMI) at the switching frequency and its harmonics. Frequency dithering technology modulates the switching frequency, causing it to vary periodically or randomly within a certain range. This disperses energy from a fixed frequency point to a specific frequency range, thus enabling the converter to pass electromagnetic compatibility (EMC) tests.
[0003] In existing technologies, the clock signal generation circuit is typically controlled by a frequency dithering control signal. Since the voltage variation period of the frequency dithering control signal is much longer than the clock signal period of the clock signal generation circuit, the clock signal period of the clock signal generation circuit will change slowly in accordance with the voltage variation period of the frequency dithering control signal. The frequency dithering range of the clock signal is the same as the voltage amplitude variation range of the frequency dithering control signal, and the frequency dithering period is the same as the period of the frequency dithering control signal.
[0004] In existing technologies, it is difficult to achieve a smaller range of frequency variation while ensuring the accuracy of the frequency dithering cycle. Summary of the Invention
[0005] The purpose of this invention is at least to provide a frequency dithering circuit and a DC-DC conversion circuit that can achieve a smaller frequency dithering variation range while ensuring the accuracy of the frequency dithering period.
[0006] In a first aspect, the present invention provides a frequency dithering circuit, comprising: a frequency dithering control module, an amplitude processing module, and a clock signal generation module, wherein: the frequency dithering control module is adapted to generate and output an initial frequency dithering control signal; the amplitude processing module is coupled to the frequency dithering control module, adapted to input the initial frequency dithering control signal, adjust the amplitude of the initial frequency dithering control signal, and output a target frequency dithering control signal after amplitude adjustment; the clock signal generation module is coupled to the amplitude processing module, adapted to generate a corresponding target clock signal based on the target frequency dithering control signal; the frequency dithering range of the target clock signal is related to the amplitude of the target frequency dithering control signal.
[0007] The initial dithering control signal is output via the dithering control module. The amplitude adjustment module adjusts the amplitude of the initial dithering control signal and then outputs the target dithering control signal to the clock signal generation module. In the above dithering circuit, the difference between the maximum and minimum amplitude of the initial dithering control signal can be set relatively large to ensure the accuracy of the dithering period. By adjusting the amplitude of the initial dithering control signal through the amplitude adjustment module, a smaller dithering variation range can be achieved.
[0008] Optionally, the amplitude processing module includes a low-pass filter module; the input terminal of the low-pass filter module is coupled to the output terminal of the frequency dithering control module, and the output terminal of the low-pass filter module is coupled to the input terminal of the clock signal generation module, which is suitable for performing low-pass filtering processing on the initial frequency dithering control signal to obtain the target frequency dithering control signal.
[0009] Optionally, the low-pass filter module includes: a first PMOS transistor, a second PMOS transistor, and a filter capacitor, wherein: the source of the first PMOS transistor receives the initial dithering control signal, the gate of the first PMOS transistor is coupled to the drain of the first PMOS transistor and the gate of the second PMOS transistor, and the drain of the first PMOS transistor is grounded; the source of the second PMOS transistor receives the initial dithering control signal, and the drain of the second PMOS transistor is coupled to the clock signal generation module; the first terminal of the filter capacitor is coupled to the drain of the second PMOS transistor, and the second terminal of the filter capacitor is grounded.
[0010] By using a low-pass filter module composed of a first PMOS transistor, a second PMOS transistor, and a filter capacitor, the circuit area of the frequency dithering circuit can be reduced, making it easier to integrate the circuit.
[0011] Optionally, the low-pass filter module further includes: a bias current source; the first end of the bias current source is coupled to the drain of the first PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor, and the second end of the bias current source is grounded.
[0012] By setting a bias current source, the equivalent resistance of the low-pass filter module can be adjusted, thereby enabling flexible adjustment of the frequency dithering range.
[0013] Optionally, the frequency dithering circuit further includes: an operational amplifier; the first input terminal of the operational amplifier receives the initial frequency dithering control signal, the second input terminal of the operational amplifier is coupled to the output terminal of the operational amplifier, and the output terminal of the operational amplifier is coupled to the source of both the first PMOS transistor and the source of the second PMOS transistor.
[0014] Optionally, the bias current output by the bias current source is adjustable.
[0015] Optionally, the low-pass filter module includes a filter resistor and a filter capacitor, wherein: the first terminal of the filter resistor is input to the initial dithering control signal, the second terminal of the filter resistor is coupled to the first terminal of the filter capacitor and the clock signal generation module; and the second terminal of the filter capacitor is grounded.
[0016] Optionally, the target frequency dithering control signal is input to the clock signal generation module, and the amplitude of the target frequency dithering control signal is used as the reference voltage of the clock signal generation module.
[0017] Optionally, the target frequency dithering control signal is input to the clock signal generation module, which is adapted to control the magnitude of the charging current in the clock signal generation module.
[0018] Secondly, the present invention also provides a DC-DC conversion circuit, including any of the frequency dithering circuits described above. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of an existing frequency dithering circuit;
[0020] Figure 2 This is a schematic diagram of the structure of a frequency dithering circuit in an embodiment of the present invention;
[0021] Figure 3 This is a schematic diagram of another frequency dithering circuit in an embodiment of the present invention. Detailed Implementation
[0022] Reference Figure 1 A schematic diagram of an existing frequency dithering circuit is presented.
[0023] Figure 1 In this circuit, the frequency dithering circuit includes a frequency dithering control module 10 and a clock signal generation module 20. The frequency dithering control module 10 outputs a frequency dithering control signal Vramp, which is used as the reference signal VREF in the clock signal generation module 20 to achieve frequency dithering. In other embodiments, the frequency dithering control signal Vramp can be used to control the output current of the third current source I3 in the clock signal generation module 20 to achieve frequency dithering.
[0024] Currently, to precisely control the jitter cycle, a relatively large difference between VREFH and VREFL (i.e., VREFH-VREFL) is usually chosen. For example, setting VREFH to 1.15V and VREFL to 0.85V corresponds to a jitter variation range of ±15%.
[0025] However, a large difference between VREFH and VREFL can lead to a large range of jitter variations. Therefore, a trade-off needs to be struck between the jitter period and the range of jitter variations.
[0026] In this embodiment of the invention, an initial dithering control signal is output via a dithering control module. The amplitude adjustment module adjusts the amplitude of the initial dithering control signal and then outputs a target dithering control signal to the clock signal generation module. In the above dithering circuit, the difference between the maximum and minimum amplitude of the initial dithering control signal can be set relatively large to ensure the accuracy of the dithering period. By adjusting the amplitude of the initial dithering control signal through the amplitude adjustment module, a smaller dithering variation range can be achieved.
[0027] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0028] Reference Figure 2 This invention provides a frequency dithering circuit, including: a frequency dithering control module 10, a clock signal generation module 20, and an amplitude processing module 30.
[0029] In specific implementation, the frequency dithering control module 10 is adapted to generate and output the initial frequency dithering control signal Vramp;
[0030] The amplitude processing module 30 is coupled to the frequency dithering control module 10. It inputs the initial frequency dithering control signal Vramp, adjusts the amplitude of the initial frequency dithering control signal Vramp, and outputs the target frequency dithering control signal.
[0031] The clock signal generation module 20 is coupled to the amplitude processing module 30 and is adapted to generate a corresponding target clock signal Clock based on the control of the target dithering control signal. The dithering range of the target clock signal Clock is related to the amplitude of the target dithering control signal.
[0032] In practice, the jitter range of the target clock signal (Clock) is positively correlated with the amplitude of the target jitter control signal. That is, the larger the amplitude of the target jitter control signal, the larger the jitter range of the target clock signal (Clock); conversely, the smaller the amplitude of the target jitter control signal, the smaller the jitter range of the target clock signal (Clock).
[0033] Therefore, by adjusting the amplitude processing module 30 so that it outputs target jitter control signals with different amplitudes, the jitter range of the target clock signal Clock can be adjusted.
[0034] In some embodiments, the initial dithering control signal Vramp can be a triangular wave signal. The maximum amplitude of the triangular wave signal is VREFH, and the minimum amplitude of the triangular wave signal is VREFL.
[0035] In other embodiments, the initial dithering control signal Vramp can be a sine wave signal, a cosine wave signal, a square wave, or other types of analog signals.
[0036] In this embodiment of the invention, the amplitude processing module 30 can be used to adjust the amplitude of the initial dithering control signal Vramp. Specifically, the amplitude processing module 30 can be used to reduce the amplitude of the initial dithering control signal Vramp. That is, the amplitude of the target dithering control signal can be smaller than the amplitude of the initial dithering control signal Vramp.
[0037] In practice, the amplitude processing module 30 does not adjust the frequency of the initial dithering control signal Vramp. That is, the frequency of the target dithering control signal can be equal to the frequency of the initial dithering control signal Vramp.
[0038] In a specific implementation, the amplitude processing module 30 may include a low-pass filter module. The input terminal of the low-pass filter module is coupled to the output terminal of the dithering control module 10, and the output terminal of the low-pass filter module is coupled to the input terminal of the clock signal generation module 20. The initial dithering control signal Vramp is low-pass filtered to obtain the target dithering control signal and then output.
[0039] In some embodiments, the initial dithering control signal Vramp is a triangular wave signal, which includes a fundamental frequency and odd-numbered harmonic components. A low-pass filter module filters out at least some of the odd-numbered harmonic components from the triangular wave signal to obtain the target dithering control signal. Because at least some of the odd-numbered harmonic components in the triangular wave signal are filtered out, the amplitude of the obtained target dithering control signal is smaller than the amplitude of the initial dithering control signal Vramp.
[0040] In a specific implementation, the low-pass filter module may include a first PMOS transistor MP1, a second PMOS transistor MP2, and a filter capacitor C0.
[0041] The source of the first PMOS transistor MP1 can be input with the initial dithering control signal Vramp. The gate of the first PMOS transistor MP1 can be coupled to the drain of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2. The drain of the first PMOS transistor MP1 is grounded.
[0042] The source of the second PMOS transistor MP2 can be input with the initial frequency dithering control signal Vramp, and the drain of the second PMOS transistor MP2 is coupled to the clock signal generation module 20.
[0043] The first terminal of the filter capacitor C0 is coupled to the drain of the second PMOS transistor MP2, and the second terminal of the filter capacitor C0 is grounded.
[0044] In this embodiment of the invention, a low-pass filter module is formed by a first PMOS transistor MP1, a second PMOS transistor MP2, and a filter capacitor C0. The first PMOS transistor MP1 and the second PMOS transistor MP2 form an equivalent resistance, resulting in a smaller circuit area and easier subsequent integration.
[0045] In a specific implementation, the low-pass filter module may further include a bias current source I0. The first terminal of the bias current source I0 is coupled to the drain of the first PMOS transistor MP1, the gate of the first PMOS transistor MP1, and the gate of the second PMOS transistor MP2, while the second terminal of the bias current source I0 is grounded. The bias current source I0 can be an adjustable current source, meaning its output current is adjustable.
[0046] By adjusting the bias current output of the bias current source I0, the resistance value of the equivalent resistance of the low-pass filter module can be adjusted, thereby adjusting the amplitude of the target frequency dithering control signal.
[0047] In practical implementation, when the low-pass filter module includes a bias current source I0, its corresponding equivalent resistance value is: ;in, , ; The aspect ratio of the first PMOS transistor MP1 is... The aspect ratio of the second PMOS transistor MP2 is... The output current of the bias current source I0. The transconductance parameter of the first PMOS transistor MP1 is given.
[0048] Therefore, by adjusting the output current of the bias current source I0 This allows for adjustment of the filtering frequency of the low-pass filter module.
[0049] Reference Figure 3 The present invention provides a schematic diagram of another frequency dithering circuit in an embodiment of the present invention.
[0050] In a specific implementation, the frequency dithering circuit may also include an operational amplifier COMP0. The first input terminal of the operational amplifier COMP0 receives the initial frequency dithering control signal Vramp, the second input terminal of the operational amplifier COMP0 is coupled to the output terminal of the operational amplifier COMP0, and the output terminal of the operational amplifier COMP0 is coupled to the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2.
[0051] By setting the operational amplifier COMP0, the operational amplifier COMP0 is used as a buffer to buffer the initial dithering control signal input.
[0052] In a specific implementation, the low-pass filter module may also include a filter resistor and a filter capacitor, wherein: the first terminal of the filter resistor receives the initial dithering control signal, and the second terminal of the filter resistor is coupled to the first segment of the filter capacitor and the clock signal generation module 20. The second terminal of the filter capacitor is grounded.
[0053] In specific implementation, combined with Figures 1-3 .
[0054] The frequency dithering control module 10 includes: a first comparator COMP1, a second comparator COMP2, a first RS flip-flop RS1, an inverter INV, a first current source I1, a second current source I2, a first capacitor C1, a first NMOS transistor MN1, and a third PMOS transistor MP3, wherein:
[0055] The first terminal of the first current source I1 is input to the power supply voltage, and the second terminal of the first current source I1 is coupled to the source of the third PMOS transistor MP3, and outputs the first current Ichg.
[0056] The drain of the third PMOS transistor MP3 is coupled to the drain of the first NMOS transistor MN1, and the gate of the third PMOS transistor MP3 is coupled to the output terminal of the inverter INV.
[0057] The gate of the first NMOS transistor MN1 is coupled to the output terminal of the inverter INV, and the source of the first NMOS transistor MN1 is coupled to the first terminal of the second current source I2.
[0058] The second terminal of the second current source I2 is grounded;
[0059] The first comparator COMP1 receives the initial dithering control signal at its positive input terminal, the first reference signal at its inverting input terminal, and the output terminal of the first comparator COMP1 is coupled to the R terminal of the first RS flip-flop RS1.
[0060] The initial dithering control signal is input to the positive input terminal of the second comparator COMP2, the second reference signal is input to the inverting input terminal of the second comparator COMP2, and the output terminal of the second comparator COMP2 is coupled to the S terminal of the first RS flip-flop RS1.
[0061] The Q terminal of the first RS flip-flop RS1 is coupled to the input terminal of the inverter INV;
[0062] The output of the inverter INV is coupled to the gate of the first NMOS transistor MN1 and the gate of the third PMOS transistor MP3, respectively.
[0063] The first terminal of the first capacitor C1 receives the initial frequency dithering control signal, and the second terminal of the first capacitor C1 is grounded.
[0064] The clock signal generation module 20 may include a third current source I3, a second capacitor C2, a second NMOS transistor MN2, a third comparator COMP3, a delay unit, and a second RS flip-flop RS2.
[0065] Specifically, the first terminal of the third current source I3 is input to the power supply voltage VDD, and the second terminal of the third current source I3 is coupled to the first terminal of the second capacitor C2 and the drain of the second NMOS transistor MN2.
[0066] The second terminal of the second capacitor C2 is grounded;
[0067] The source of the second NMOS transistor MN2 is grounded, and the gate of the second NMOS transistor MN2 is coupled to the output terminal of the clock signal generation module 20.
[0068] The positive input terminal of the third comparator COMP3 is coupled to the second terminal of the third current source I3. The negative input terminal of the third comparator COMP3 can input the target frequency dithering control signal. The output terminal of the third comparator COMP3 is coupled to the S terminal of the second RS flip-flop RS2.
[0069] The R terminal of the second RS flip-flop RS2 is coupled to the output terminal of the delay unit, and the Q terminal of the second RS flip-flop RS2 is coupled to the output terminal of the clock signal generation module 20.
[0070] The input of the delay unit is coupled to the Q terminal of the second RS flip-flop RS2.
[0071] like Figure 1 The clock signal generation module 20 provided in the middle can input the target jitter control signal to the inverting input of the third comparator COMP3, thereby realizing the control of the jitter range of the target clock signal.
[0072] In practice, the output current Iosc of the third current source I3 can also be controlled by the target jitter control signal to adjust the jitter range of the target clock signal.
[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A frequency dithering circuit, characterized in that, include: The module includes a frequency dithering control module, an amplitude processing module, and a clock signal generation module, among which: The frequency dithering control module is adapted to generate and output an initial frequency dithering control signal; The amplitude processing module, coupled to the frequency dithering control module, is adapted to input the initial frequency dithering control signal, adjust the amplitude of the initial frequency dithering control signal, and output the target frequency dithering control signal after amplitude adjustment. The amplitude processing module includes a low-pass filtering module. The input terminal of the low-pass filtering module is coupled to the output terminal of the frequency dithering control module, and the output terminal of the low-pass filtering module is coupled to the input terminal of the clock signal generation module. It is adapted to perform low-pass filtering processing on the initial frequency dithering control signal to obtain the target frequency dithering control signal. The low-pass filter module includes a first PMOS transistor, a second PMOS transistor, and a filter capacitor, wherein: the source of the first PMOS transistor receives the initial dithering control signal, the gate of the first PMOS transistor is coupled to the drain of the first PMOS transistor and the gate of the second PMOS transistor, and the drain of the first PMOS transistor is grounded; the source of the second PMOS transistor receives the initial dithering control signal, and the drain of the second PMOS transistor is coupled to the clock signal generation module; the first terminal of the filter capacitor is coupled to the drain of the second PMOS transistor, and the second terminal of the filter capacitor is grounded; The clock signal generation module is coupled to the amplitude processing module and is adapted to generate a corresponding target clock signal based on the target dithering control signal; the dithering range of the target clock signal is related to the amplitude of the target dithering control signal.
2. The frequency dithering circuit as described in claim 1, characterized in that, The low-pass filter module further includes: a bias current source; the first end of the bias current source is coupled to the drain of the first PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor, and the second end of the bias current source is grounded.
3. The frequency dithering circuit as described in claim 2, characterized in that, It also includes: an operational amplifier; the first input terminal of the operational amplifier receives the initial dithering control signal, the second input terminal of the operational amplifier is coupled to the output terminal of the operational amplifier, and the output terminal of the operational amplifier is coupled to the source of both the first PMOS transistor and the source of the second PMOS transistor.
4. The frequency dithering circuit as described in claim 2, characterized in that, The bias current output by the bias current source is adjustable.
5. The frequency dithering circuit as described in claim 1, characterized in that, The target frequency dithering control signal is input to the clock signal generation module, and the amplitude of the target frequency dithering control signal is used as the reference voltage of the clock signal generation module.
6. The frequency dithering circuit as described in claim 1, characterized in that, The target frequency dithering control signal is input to the clock signal generation module, which is suitable for controlling the magnitude of the charging current in the clock signal generation module.
7. A DC-DC conversion circuit, characterized in that, Includes the frequency dithering circuit as described in any one of claims 1 to 6.