High-voltage comparator, chip and electronic device

Abstract

The application provides a high-voltage comparator, a chip and an electronic device. The high-voltage comparator comprises a first PMOS tube, a second PMOS tube, a first current source, a clamping circuit and a load circuit. The clamping circuit receives a high-voltage power supply and is connected to a positive input end of the high-voltage comparator, a negative input end of the high-voltage comparator, a source of the first PMOS tube and a source of the second PMOS tube, respectively. The drain of the first PMOS tube and the drain of the second PMOS tube are connected to the load circuit to output a comparison result signal. The clamping circuit is configured to work when the voltage difference between the input signals of the positive input end and the negative input end exceeds a preset voltage threshold, so that the gate-source voltage of the first PMOS tube and the gate-source voltage of the second PMOS tube are within a safe range. The application has the advantages of high input impedance, support for high-voltage wide input range, simple structure, small area consumption, fast comparison speed and no need to use a parasitic diode.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to a high-voltage comparator, chip, and electronic device. Background Technology

[0002] In integrated circuits, voltage comparators are a common circuit module. By comparing an input signal with a reference voltage, the magnitude relationship between the input signal and the reference voltage can be determined. When the input signal is greater than the reference voltage, a high-level signal is output; conversely, a low-level signal is output. This characteristic makes voltage comparators widely used in many electronic systems.

[0003] To address the limitation of some existing voltage comparators to applications where the input is driveable, a voltage comparator is provided in the prior art. For example, please refer to... Figure 1 , Figure 1 This is a schematic diagram of the topology of one type of comparator in the prior art. For example... Figure 1 As shown, the inputs IN+ and IN- are directly connected to the gates of the comparator's input transistors MP01 and MP02, achieving high input impedance. This solves the problem that voltage division by sampling resistors for high-impedance inputs would severely reduce comparison accuracy and render the device unusable. Furthermore, if the input transistors MP01 and MP02 are low-voltage devices, the comparator is a basic low-voltage comparator; if they are high-voltage devices, it forms a basic high-voltage comparator. However, in most BCD (Bipolar-CMOS-DMOS, a power integrated circuit manufacturing technology that integrates bipolar transistors, complementary metal-oxide-semiconductor, and double-diffused metal-oxide-semiconductor technologies on the same chip) processes, even if the input transistors MP01 and MP02 are high-voltage devices, only their drains can withstand high voltage; their gate-source voltage VGS cannot. If the input voltage difference between the input signals IN+ and IN- is too large, the lack of proper protection at the gate and source terminals can lead to circuit damage. Therefore, this circuit also limits its application scenarios.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a high voltage comparator, chip, and electronic device. The high voltage comparator provided by this invention not only has the advantages of high input impedance and support for a wide high voltage input range, but also has the advantages of simple structure, small area consumption, fast comparison speed, and no need to use parasitic diodes.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a high-voltage comparator comprising a first PMOS transistor, a second PMOS transistor, a first current source, a clamping circuit, and a load circuit. The first terminal of the clamping circuit and the gate of the first PMOS transistor are connected to the positive input terminal of the high-voltage comparator. The second terminal of the clamping circuit and the gate of the second PMOS transistor are connected to the negative input terminal of the high-voltage comparator. The third terminal of the clamping circuit and the current inflow terminal of the first current source receive high-voltage power. The fourth terminal of the clamping circuit and the source of the first PMOS transistor are connected to a first node. The fifth terminal of the clamping circuit and the first terminal of the second PMOS transistor are connected to a second node. The sixth terminal of the clamping circuit is connected to the current outflow terminal of the first current source. The drains of the first PMOS transistor and the second PMOS transistor are connected to the load circuit to output a comparison result signal. The clamping circuit is configured to operate when the voltage difference between the input signals at the positive and negative input terminals exceeds a preset voltage threshold, so that the gate-source voltages of the first and second PMOS transistors are within a safe range.

[0007] Optionally, the clamping circuit includes a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor. The drains of the third and fourth NMOS transistors receive the high-voltage power supply. The gate of the third NMOS transistor is connected to the gate of the first PMOS transistor. The source of the third NMOS transistor and the first end of the first resistor are connected to the first node. The gate of the fourth NMOS transistor is connected to the gate of the second PMOS transistor. The source of the fourth NMOS transistor and the second end of the second resistor are connected to the second node. The second ends of the first and second resistors are connected to the current outflow terminal of the first current source.

[0008] Optionally, the first PMOS transistor, the second PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all high-voltage MOS transistors.

[0009] Optionally, the resistance value of the first resistor and the resistance value of the second resistor are the same.

[0010] Optionally, the parameters of the first PMOS transistor are the same as those of the second PMOS transistor, and / or the parameters of the third NMOS transistor are the same as those of the fourth NMOS transistor.

[0011] Optionally, the load circuit includes a current mirror load circuit or a current source load circuit.

[0012] Optionally, the current mirror load circuit includes a fifth MOSFET to a tenth MOSFET. The source of the fifth MOSFET and the source of the sixth MOSFET receive a low-voltage power supply. The gate of the fifth MOSFET, the gate and drain of the sixth MOSFET, and the drain of the tenth MOSFET are connected. The drain of the fifth MOSFET and the drain of the seventh MOSFET are connected to the output terminal of the high-voltage comparator. The gate of the seventh MOSFET, the gate and drain of the eighth MOSFET are connected to the drain of the first PMOS transistor. The gate and drain of the ninth MOSFET and the gate of the tenth MOSFET are connected to the drain of the second PMOS transistor. The source of the seventh MOSFET and the source of the tenth MOSFET are connected to reference ground.

[0013] Optionally, the preset voltage threshold is less than or equal to the rated gate-source voltage of the first PMOS transistor and the second PMOS transistor.

[0014] To achieve the above objectives, the present invention also provides a chip on which the high voltage comparator described in any of the preceding claims is integrated.

[0015] To achieve the above objectives, the present invention also provides an electronic device comprising the high voltage comparator described in any of the preceding claims or the aforementioned chip.

[0016] Compared with existing technologies, the high-voltage comparator, chip, and electronic device provided by this invention have the following advantages: The high-voltage comparator provided by this invention, by adopting a design that connects the gates of the first PMOS transistor and the second PMOS transistor to the positive and negative input terminals of the high-voltage comparator respectively, enables the first and second input signals to be directly received through the gates of the first and second PMOS transistors respectively. This gives the high-voltage comparator the advantage of high input impedance, effectively improving the applicability of this invention. Furthermore, by using a clamping circuit (e.g., employing a high-voltage MOS transistor design) to receive high-voltage power supply at its third terminal, the high-voltage comparator can operate normally even when the voltages of the first and second input signals are lower than the high-voltage power supply voltage, thereby enhancing the overall performance of this invention. The high-voltage comparator provided by this invention is suitable for high-voltage applications. Furthermore, when the voltage difference between the input signals at the positive and negative input terminals exceeds a preset voltage threshold, the clamping circuit operates, ensuring that the gate-source voltages of the first and second PMOS transistors are within a safe range. This not only effectively protects the first and second PMOS transistors, improving the applicability and reliability of the high-voltage comparator, but also increases its slew rate, achieving a faster comparison speed. Moreover, the clamping circuit avoids the use of parasitic diodes, completely eliminating the risk of latch-up or interference with surrounding circuits caused by diode conduction. Furthermore, the input stage circuit formed by the first PMOS transistor, the second PMOS transistor, the first current source, and the clamping circuit can be adapted to all load circuits, thereby improving the flexibility of the output. In summary, the high-voltage comparator provided by this invention not only has the advantage of high input impedance but also features simple structure, small area consumption, fast comparison speed, and the elimination of the need for parasitic diodes.

[0017] Furthermore, since the chip and electronic device provided by this invention belong to the same inventive concept as the high voltage comparator provided by this invention, the chip and electronic device provided by this invention have at least all the advantages of the high voltage comparator provided by this invention. For details on the beneficial effects of the chip and electronic device provided by this invention, please refer to the relevant description of the beneficial effects of the high voltage comparator provided by this invention above, which will not be repeated here. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the topology of a comparator in the prior art.

[0019] Figure 2 This is a block diagram of the high-voltage comparator provided by the present invention.

[0020] Figure 3 This is a schematic diagram of the topology of a high-voltage comparator provided in one embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the circuit structure of a high-voltage comparator provided in one embodiment of the present invention.

[0022] Figure 5 A schematic diagram of the circuit structure of a high-voltage comparator provided for another embodiment of the present invention.

[0023] The reference numerals in the attached figures are explained as follows:

[0024] First PMOS transistor - M1, Second PMOS transistor - M2, Clamping circuit - 100, Third NMOS transistor - M3, Fourth NMOS transistor - M4, First current source - I1, Second current source - I2, First resistor - R1, Second resistor - R2; Load circuit - 200, Current mirror load circuit - 210, Fifth MOS transistor - M5, Sixth MOS transistor - M6, Seventh MOS transistor - M7, Eighth MOS transistor - M8, Ninth MOS transistor - M9, Tenth MOS transistor - M10; Inverter - X1, Eleventh MOS transistor - M11, Twelfth MOS transistor - M12, Thirteenth MOS transistor - M13; High voltage power supply - VDD_HV, Low voltage power supply - VDD_LV, Reference ground - GND; First input signal - IN+, Second input signal - IN-; First node - N1, Second node - N2. Detailed Implementation

[0025] The following detailed description, in conjunction with the accompanying drawings, provides a further detailed account of a high-voltage comparator, chip, and electronic device proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read them, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same objectives as this invention, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items, so once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0027] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0028] The core idea of ​​this invention is to provide a high voltage comparator, chip, and electronic device. The high voltage comparator provided by this invention not only has the advantages of high input impedance and support for a wide high voltage input range, but also has the advantages of simple structure, small area consumption, fast comparison speed, and no need to use parasitic diodes.

[0029] To achieve the above-mentioned goals, one embodiment of the present invention provides a high-voltage comparator. For example, please refer to... Figure 2 , Figure 2 This is a block diagram of the high-voltage comparator provided by the present invention. Figure 2 It can be seen that the high-voltage comparator includes a first PMOS transistor M1, a second PMOS transistor M2, a first current source I1, a clamping circuit 100, and a load circuit 200. The first terminal of the clamping circuit 100 and the gate of the first PMOS transistor M1 are connected to the non-inverting input terminal of the high-voltage comparator. Figure 2 (Not shown in the diagram, using the first input signal IN+ for illustration), the second terminal of the clamping circuit 100 and the gate of the second PMOS transistor M2 are connected to the negative input terminal of the high-voltage comparator. Figure 2 (Not shown in the diagram, using the second input signal IN- for illustration) The third terminal of the clamping circuit 100 and the current inflow terminal of the first current source I1 receive a high-voltage power supply VDD_HV. The fourth terminal of the clamping circuit 100 is connected to the source of the first PMOS transistor M1 at the first node N1. The fifth terminal of the clamping circuit 100 is connected to the source of the second PMOS transistor M2 at the second node N2. The sixth terminal of the clamping circuit 100 is connected to the current outflow terminal of the first current source I1. The drains of the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the load circuit 200 to output a comparison result signal. Further, the clamping circuit 100 is configured to operate when the voltage difference between the input signals at the positive input terminal and the negative input terminal exceeds a preset voltage threshold, so that the gate-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are within a safe range.

[0030] Therefore, the high-voltage comparator provided by this invention, by adopting a design in which the gates of the first PMOS transistor M1 and the second PMOS transistor M2 are respectively connected to the positive input terminal and the negative input terminal of the high-voltage comparator, enables the first input signal IN+ and the second input signal IN- of the high-voltage comparator to be directly received through the gates of the first PMOS transistor M1 and the second PMOS transistor M2, respectively. This gives the high-voltage comparator the advantage of high input impedance, effectively improving the applicability of this invention. Furthermore, by using the clamping circuit 100 (for example, by adopting a high-voltage MOS transistor design) to receive the high-voltage power supply VDD_HV at its third terminal, the high-voltage comparator can operate normally even when the voltages of the first input signal IN+ and the second input signal IN- are lower than the voltage of the high-voltage power supply VDD_HV, thereby enabling the high-voltage comparator provided by this invention to operate normally. The comparator is suitable for high-voltage applications. Furthermore, when the voltage difference between the input signals at the positive and negative input terminals exceeds a preset voltage threshold, the clamping circuit 100 operates, ensuring that the gate-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are within a safe range. This not only effectively protects the first PMOS transistor M1 and the second PMOS transistor M2, improving the applicability and reliability of the high-voltage comparator, but also increases its slew rate, achieving a faster comparison speed. Furthermore, the clamping circuit 100 avoids the use of parasitic diodes, completely eliminating the risk of latch-up or interference with surrounding circuits caused by diode conduction. Even further, the input stage circuit formed by the first PMOS transistor M1, the second PMOS transistor M2, the first current source I1, and the clamping circuit 100 can be adapted to all load circuits 200, thereby improving the flexibility of the output. In summary, the high-voltage comparator provided by this invention not only has the advantage of high input impedance but also features simple structure, small area consumption, fast comparison speed, and the elimination of the need for parasitic diodes.

[0031] It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the specific values ​​of the high-voltage power supply VDD_HV and the preset voltage threshold. These values ​​should be set reasonably according to actual needs when implementing the present invention. For example, in some exemplary embodiments, the preset voltage threshold is less than or equal to the rated values ​​of the gate-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 (preferably, the rated values ​​of the gate-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are the same). Preferably, the selection of the first PMOS transistor M1, the second PMOS transistor M2, and the third NMOS transistor M3 and the fourth NMOS transistor M4 (described below) should be coordinated with the high-voltage power supply VDD_HV. Further, the rated drain-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are preferably the upper limit of the range of the high-voltage power supply VDD_HV. For example, if in a specific example the voltage range of the high-voltage power supply VDD_HV is 12V~40V, then the first PMOS transistor M1 and the second PMOS transistor M2 are preferably devices with a gate-source voltage rating of not less than 40V. In this case, the preset voltage threshold is actually around 2V, and is definitely less than 5V. As another example, if the upper limit of the high-voltage power supply VDD_HV voltage range is 120V, then the first PMOS transistor M1 and the second PMOS transistor M2 are preferably devices with a gate-source voltage rating of not less than 120V. It should be understood that this is merely an illustrative example and not a limitation. In the specific implementation of this invention, the preset voltage threshold can also be higher than 40V, and the specific value is determined by the parameters of the devices implementing the clamping circuit 100.

[0032] It should be further noted that when the voltage difference between the input signals at the positive input terminal and the negative input terminal does not exceed a preset voltage threshold, the clamping circuit 100 may or may not operate. However, as a preferred embodiment, the clamping circuit 100 is not operated to further reduce energy consumption and improve efficiency. Additionally, the statement in this document that the gate-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are within a safe range means that the gate-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are lower than their rated voltages to protect this input pair. For example, in an application scenario where the rated gate-source voltage is 5V, the preset voltage threshold of the clamping circuit 100 is preferably set to a maximum of 5V, so that the gate-source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 do not exceed 5V during operation, thereby protecting the input pair.

[0033] It should also be noted that those skilled in the art should understand that, since the output terminal of the high-voltage comparator provided by this invention is related to the structure of the load circuit 200, and this invention does not impose excessive limitations on the specific structure of the load circuit 200, the location of the output terminal of the high-voltage comparator provided by this invention is very flexible. For example, the output terminal of the high-voltage comparator can be the drain of the first PMOS transistor M1, the drain of the second PMOS transistor M2, or other nodes in the load circuit 200. When implementing this invention, the location can be set according to the specific structure of the load circuit 200. Therefore, Figure 2 The output terminal of the high voltage comparator is not shown in the diagram.

[0034] For example, please see Figure 3 , Figure 3 This is a schematic diagram of the topology of a high-voltage comparator provided in one embodiment of the present invention. Figure 3 The green area in the diagram illustrates the devices included in the clamping circuit 100 described below, to facilitate a more intuitive understanding of the invention. From Figure 3 As can be seen, in some exemplary embodiments, the clamping circuit 100 includes a third NMOS transistor M3, a fourth NMOS transistor M4, a first resistor R1, and a second resistor R2. The drains of the third NMOS transistor M3 and the fourth NMOS transistor M4 receive the high-voltage power supply VDD_HV. The gate of the third NMOS transistor M3 is connected to the gate of the first PMOS transistor M1. The source of the third NMOS transistor M3 and the first end of the first resistor R1 are connected to the first node N1. The gate of the fourth NMOS transistor M4 is connected to the gate of the second PMOS transistor M2. The source of the fourth NMOS transistor M4 and the first end of the second resistor R2 are connected to the second node N2. The second ends of the first resistor R1 and the second ends of the second resistor R2 are connected to the current outflow terminal of the first current source I1.

[0035] Therefore, the clamping circuit 100 employs a design using a third NMOS transistor M3, a fourth NMOS transistor M4, a first resistor R1, and a second resistor R2. This design not only makes the high-voltage comparator provided by this invention suitable for high-voltage scenarios, but also, through the protection unit 110, eliminates the need for substrate diodes for the third NMOS transistor M3 and the fourth NMOS transistor M4, effectively avoiding the risk of latch-up effects or interference with surrounding circuits caused by parasitic transistor turn-on, thus improving reliability and safety. Furthermore, it effectively avoids the drawback of splitting the tail current source of the high-voltage comparator in two, effectively reducing the offset voltage of the high-voltage comparator, thereby improving its comparison accuracy, stability, and reliability. Moreover, this invention requires small components, offering advantages such as small circuit area consumption and low cost.

[0036] It should be noted that those skilled in the art should understand that the implementation of the clamping circuit 100 described herein using the third NMOS transistor M3, the fourth NMOS transistor M4, the first resistor R1, and the second resistor R2 is merely an illustrative description of a preferred embodiment and not a limitation of the present invention. The present invention does not impose excessive limitations on the specific implementation of the clamping circuit 100.

[0037] Preferably, in some exemplary embodiments, the third NMOS transistor M3 is configured to clamp the gate-source voltage of the first PMOS transistor M1, and the fourth NMOS transistor M4 is configured to clamp the gate-source voltage of the second PMOS transistor M2.

[0038] It should be noted that those skilled in the art should understand that, as a preferred embodiment, the first PMOS transistor M1, the second PMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are all high-voltage MOS transistors. This arrangement can ensure the reliability and safety of the high-voltage comparator.

[0039] It should be noted that the specific implementations of the first PMOS transistor M1, the second PMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 in this invention are merely illustrative and not limiting. For example, the first PMOS transistor M1, the second PMOS transistor M2, the third NMOS transistor, and the fourth NMOS transistor M4 can be either NMOS transistors or PMOS transistors. The connection method of the source and gate can be adaptively adjusted in the circuit topology according to the type of MOS transistor used. For instance, in other embodiments, the first NMOS transistor can replace the first PMOS transistor M1, the second NMOS transistor can replace the second PMOS transistor M2, the third PMOS transistor can replace the third NMOS transistor M3, and the fourth PMOS transistor can replace the fourth NMOS transistor. The connection method of the source and gate of each MOS transistor can be adaptively modified according to the current flow direction, which will not be elaborated further here.

[0040] For example, in some exemplary embodiments, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 are the same. This effectively ensures the symmetry of the high-voltage comparator, thereby further improving the reliability and applicability of the high-voltage comparator provided by the present invention.

[0041] Exemplary examples include, in some exemplary embodiments, the parameters of the first PMOS transistor M1 are the same as those of the second PMOS transistor M2; in other exemplary embodiments, the parameters of the third NMOS transistor M3 are the same as those of the fourth NMOS transistor M4; and in still other embodiments, the parameters of the first PMOS transistor M1 are the same as those of the second PMOS transistor M2, the parameters of the third NMOS transistor M3 are the same as those of the fourth NMOS transistor M4, and the resistance values ​​of the first resistor R1 and the second resistor R2 are the same.

[0042] It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the specific implementation of the load circuit 200. Exemplarily, in some exemplary embodiments, the load circuit 200 is implemented, including but not limited to, using a current mirror load circuit or a current source load circuit.

[0043] For example, please see Figure 4 , Figure 4 This is a schematic diagram of the circuit structure of a high-voltage comparator provided in one embodiment of the present invention. Figure 4 The green area in the diagram illustrates the components included in the clamping circuit 100 to facilitate a more intuitive understanding of the invention. From Figure 4 As can be seen, the current mirror load circuit 210 includes a fifth MOS transistor M5 to a tenth MOS transistor M10. The source of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 receive a low-voltage power supply VDD_LV. The gate of the fifth MOS transistor M5, the gate and drain of the sixth MOS transistor M6, and the drain of the tenth MOS transistor M10 are connected. The drain of the fifth MOS transistor M5 and the drain of the seventh MOS transistor M7 are connected to the output terminal of the high-voltage comparator. The gate of the seventh MOS transistor M7, the gate and drain of the eighth MOS transistor M8 are connected to the drain of the first PMOS transistor M1. The gate and drain of the ninth MOS transistor M9 and the gate of the tenth MOS transistor M10 are connected to the drain of the second PMOS transistor M2. The source of the seventh MOS transistor M7 to the source of the tenth MOS transistor M10 are connected to reference ground GND.

[0044] Therefore, the high-voltage comparator provided by the present invention, through the design of the fifth MOS transistor M5 to the tenth MOS transistor M10 of the current mirror load circuit 210, can copy the current of the first PMOS transistor M1 and the second PMOS transistor M2 to the low voltage domain (VDD_LV) and compare them through the seventh MOS transistor M7 to the tenth MOS transistor M10, and finally obtain the comparison result signal of the high-voltage comparator. At the same time, it can also enable the high-voltage comparator to have excellent dynamic performance, stable operating point and good matching.

[0045] For example, please see Figure 5 , Figure 5 A schematic diagram of the circuit structure of a high-voltage comparator provided for another embodiment of the present invention. Wherein, Figure 5 The green area in the diagram illustrates the components included in the clamping circuit 100 to facilitate a more intuitive understanding of the invention. (Comparison) Figure 4 and Figure 5 It can be seen that the difference between the two implementation methods of the high-voltage comparator lies in the different implementation methods of the load circuit 200. From Figure 5 As can be seen, the load circuit 200 of the high-voltage comparator provided in this embodiment includes a second current source I2, an inverter X1, and eleventh to thirteenth MOS transistors M11 to M13. The current inflow terminal of the second current source I2 receives the low-voltage power supply VDD_LV. The current outflow terminal of the first current source I1, the input terminal of the inverter X1, and the drain of the eleventh MOS transistor M11 are connected. The gate of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12 are connected to the drain of the second PMOS transistor M2. The gate of the twelfth MOS transistor M12, the gate of the thirteenth MOS transistor M13, and the drain are connected to the drain of the first PMOS transistor M1. The source of the eleventh MOS transistor M11, the source of the twelfth MOS transistor M12, and the source of the thirteenth MOS transistor M13 are connected to the reference ground GND. The output terminal of the inverter X1 is connected to the output terminal of the high-voltage comparator.

[0046] To better understand this invention, Figure 4 The working principle of the high-voltage comparator provided by this invention is explained below using an example:

[0047] First, when the voltages of the first input signal IN+ and the second input signal IN- are both VIN, the source voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are both higher than the voltages of the first input signal IN+ and the second input signal IN-, approximately VIN+VGSP. At this time, the gate-source voltages of the third NMOS transistor M3 and the fourth NMOS transistor M4 are negative, and neither of them is conducting. In this case, the operating principle of the high-voltage comparator provided by this invention is exactly the same as that of existing comparators excluding the clamping circuit 100, and will not be described again here. Only when the input voltages IN+ and IN- differ significantly will the clamping circuit 100 (i.e., the third NMOS transistor M3 or the fourth NMOS transistor M4) operate and play its role in protecting the first PMOS transistor M1 and the second PMOS transistor M2 input pair.

[0048] Next, let's take the case where the voltage of the first input signal IN+ is much higher than the voltage of the second input signal IN- as an example. Assume the voltage of the first input signal IN+ is VINP, and the voltage of the second input signal IN- is VINN. In this case, the first PMOS transistor M1 in the differential pair is turned off, and the second PMOS transistor M2 is turned on. Therefore, the source voltage of the second PMOS transistor M2 is VINN + VGSP2. If there is no third NMOS transistor M3 to protect the first PMOS transistor M1, then the source voltage of the first PMOS transistor M1 is VINN + VGSP2 + I1 * R2. Therefore, the gate-source voltage of the first PMOS transistor M1 is VINP - VINN - VGSP2 - I1 * R2. If this voltage difference is greater than 5V, it may damage the first PMOS transistor M1. However, with the third NMOS transistor M3, since the gate-source voltages of the first PMOS transistor M1 and the third NMOS transistor M3 are the same, the gate-source voltage of the first PMOS transistor M1 will not become particularly large, but will be clamped by the third NMOS transistor M3. At this time, the third NMOS transistor M3 is turned on, and the source voltage of the first PMOS transistor M1 is clamped to VINP - VGSN1 by the third NMOS transistor M3, thus limiting the gate-source voltage of the third NMOS transistor M3. The first resistor R1 and the second resistor R2 act as current limiters because, in this state, the source voltage of the first PMOS transistor M1 will be significantly higher than the source voltage of the second PMOS transistor M2, and current will flow from the first node N1 to the second node N2 (e.g., ...). Figure 4 As shown, the current flows from the left end of the first resistor R1 to the right end of the second resistor R2. This current is determined by the first resistor R1 and the second resistor R2. This current increases the slew rate of the high-voltage comparator, making its switching speed faster. It should also be noted that if the current flowing through the first resistor R1 and the second resistor R2 increases, the power consumption of the high-voltage comparator will also increase. Therefore, when implementing this invention, the design should be tailored to actual needs.

[0049] It should be noted that the present invention does not limit the voltage values ​​of the high-voltage power supply VDD_HV and the low-voltage power supply VDD_LV. For example, the voltage of the high-voltage power supply VDD_HV can be, but is not limited to, 12V, 20V, 40V, etc., and the voltage of the low-voltage power supply VDD_LV can be, but is not limited to, 5V, 3.3V, 1.8V, etc.

[0050] Another embodiment of the present invention provides a chip on which the high voltage comparator described in any of the above embodiments is integrated.

[0051] It should be noted that those skilled in the art should understand that the present invention does not limit the manufacturing process, application field, or function of the chip. For example, the chip may be, but is not limited to, a 7nm chip, a 14nm chip, or a 28nm chip; the chip may be, but is not limited to, automotive chips, consumer electronics chips, and medical chips, etc.

[0052] Another embodiment of the present invention provides an electronic device, in some embodiments of which the electronic device includes a high voltage comparator provided in any embodiment of the present invention; in other embodiments, the electronic device includes a chip provided in the present invention.

[0053] Since the electronic device provided by this invention and the high-voltage comparator or chip provided by this invention belong to the same inventive concept, and the chip provided by this invention and the high-voltage comparator provided by this invention belong to the same inventive concept, the electronic device provided by this invention has at least all the advantages of the high-voltage comparator provided by this invention. For details on the beneficial effects of the electronic device provided by this invention, please refer to the above description of the beneficial effects of the high-voltage comparator provided by this invention, which will not be repeated here.

[0054] More specifically, the electronic device provided in this embodiment, in addition to at least a processor and a memory, may further include display components, communication components, sensor components, power supply components, multimedia components, and input / output interfaces, etc., as needed. The display components, memory, communication components, sensor components, power supply components, multimedia components, and input / output interfaces are all connected to the processor. The memory can be static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, etc. The processor can be a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can all be implemented using general-purpose components; due to space limitations, they will not be described in detail here. For more detailed information, please refer to the relevant technical adaptation understanding known to those skilled in the art.

[0055] It should be noted that the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0056] In summary, compared with the prior art, the high-voltage comparator, chip, and electronic device provided by the present invention have the following advantages:

[0057] (1) Since the first input signal IN+ and the second input signal IN- are directly connected to the gates of the first PMOS transistor M1 and the second PMOS transistor in the input pair, they have infinitely large input impedance and do not restrict the input circuit.

[0058] (2) Due to the addition of clamping circuit 100, that is, the addition of third NMOS transistor M3 and fourth NMOS transistor M4, the input voltages of the first input signal IN+ and the second input signal IN- can work normally when the high voltage power supply VDD_HV is below. Even if the voltage difference between the first input signal IN+ and the second input signal IN- is very high, it can still work normally and will not be damaged.

[0059] (3) With appendix Figure 1 Compared to the high-voltage comparator in the previous version, only two high-voltage devices, the third NMOS transistor M3 and the fourth NMOS transistor M4, and the first resistor R1 and the second resistor R2, are added, resulting in a smaller area consumption.

[0060] (4) There is no need to split the tail current source into two parts, and the first resistor R1 and the second resistor R2 are added to the source of the first PMOS transistor M1 and the second PMOS transistor M2, which reduces the offset voltage of the high voltage comparator.

[0061] (5) When the voltage difference between the first input signal IN+ and the second input signal IN- is large, the third NMOS transistor M3 or the fourth NMOS transistor M4 will be turned on, and the slew rate of the high voltage comparator will also increase accordingly, so as to achieve a faster comparison speed.

[0062] (6) No substrate diode is used, so there is no diode conduction. This completely eliminates the risk of the parasitic transistor turning on due to diode conduction, which could lead to latch-up or affect the surrounding circuit.

[0063] The above description is merely a description of preferred embodiments of the high-voltage comparator, chip, and electronic equipment provided by the present invention, and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A high-voltage comparator, characterized in that, The high-voltage comparator includes a first PMOS transistor, a second PMOS transistor, a first current source, a clamping circuit, and a load circuit. The first terminal of the clamping circuit and the gate of the first PMOS transistor are connected to the positive input terminal of the high-voltage comparator. The second terminal of the clamping circuit and the gate of the second PMOS transistor are connected to the negative input terminal of the high-voltage comparator. The third terminal of the clamping circuit and the current inflow terminal of the first current source receive high-voltage power supply. The fourth terminal of the clamping circuit and the source of the first PMOS transistor are connected to a first node. The fifth terminal of the clamping circuit and the source of the second PMOS transistor are connected to a second node. The sixth terminal of the clamping circuit is connected to the current outflow terminal of the first current source. The drains of the first PMOS transistor and the drains of the second PMOS transistor are connected to the load circuit to output a comparison result signal. The clamping circuit is configured to operate when the voltage difference between the input signals at the positive input terminal and the negative input terminal exceeds a preset voltage threshold, so that the gate-source voltage of the first PMOS transistor and the gate-source voltage of the second PMOS transistor are within a safe range.

2. The high-voltage comparator according to claim 1, characterized in that, The clamping circuit includes a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor. The drains of the third and fourth NMOS transistors receive the high-voltage power supply. The gate of the third NMOS transistor is connected to the gate of the first PMOS transistor. The source of the third NMOS transistor and the first end of the first resistor are connected to the first node. The gate of the fourth NMOS transistor is connected to the gate of the second PMOS transistor. The source of the fourth NMOS transistor and the first end of the second resistor are connected to the second node. The second ends of the first and second resistors are connected to the current outflow terminal of the first current source.

3. The high-voltage comparator according to claim 2, characterized in that, The first PMOS transistor, the second PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all high-voltage MOS transistors.

4. The high-voltage comparator according to claim 2, characterized in that, The resistance value of the first resistor is the same as the resistance value of the second resistor.

5. The high-voltage comparator according to claim 2, characterized in that, The parameters of the first PMOS transistor are the same as those of the second PMOS transistor, and / or the parameters of the third NMOS transistor are the same as those of the fourth NMOS transistor.

6. The high-voltage comparator according to claim 1, characterized in that, The load circuit includes a current mirror load circuit or a current source load circuit.

7. The high-voltage comparator according to claim 6, characterized in that, The current mirror load circuit includes a fifth MOSFET to a tenth MOSFET. The source of the fifth MOSFET and the source of the sixth MOSFET receive a low-voltage power supply. The gate of the fifth MOSFET, the gate and drain of the sixth MOSFET, and the drain of the tenth MOSFET are connected. The drain of the fifth MOSFET and the drain of the seventh MOSFET are connected to the output terminal of the high-voltage comparator. The gate of the seventh MOSFET, the gate and drain of the eighth MOSFET are connected to the drain of the first PMOS transistor. The gate and drain of the ninth MOSFET and the gate of the tenth MOSFET are connected to the drain of the second PMOS transistor. The source of the seventh MOSFET and the source of the tenth MOSFET are connected to a reference ground.

8. The high-voltage comparator according to claim 1, characterized in that, The preset voltage threshold is less than or equal to the rated gate-source voltage of the first PMOS transistor and the second PMOS transistor.

9. A chip, characterized in that, It integrates a high-voltage comparator as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes a high-voltage comparator as described in any one of claims 1 to 8, or a chip as described in claim 9.

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