Semiconductor device and data storage system including same

Abstract

A semiconductor device and a data storage system including the same are provided. A semiconductor device includes: a stack structure including a gate electrode, where the stack structure includes a first region, a second region, and a third region therebetween; an insulating layer on the stacked structure; a channel structure extending into the stack structure in the first region; first contact plugs extending into the insulating layer, in which the first contact plugs are electrically connected to pad regions of some of the upper gate electrodes, respectively, in the third region; second contact plugs extending into at least one of the gate electrode and the insulating layer, where some of the second contact plugs extend to different lengths in the second region; a side surface insulating structure extending around a side surface of each of the second contact plugs; and an upper side surface insulating layer extending around a side surface of each of the first contact plugs.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0134940, filed on October 4, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Example embodiments of the present disclosure can relate to a semiconductor device and a data storage system including the same. BACKGROUND

[0004] There has been a need for a semiconductor device capable of storing high-capacity data in a data storage system requiring data storage. Accordingly, methods for increasing the data storage capacity of a semiconductor device have been researched. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been suggested. SUMMARY

[0005] Example embodiments of the present disclosure can provide a semiconductor device formed through a simplified manufacturing process.

[0006] Example embodiments of the present disclosure can provide a data storage system including a semiconductor device formed through a simplified manufacturing process.

[0007] According to example embodiments of the present disclosure, a semiconductor device includes: a conductive layer; a stack structure on the conductive layer, wherein the stack structure includes a first region, a second region, and a third region between the first region and the second region in a first direction parallel to an upper surface of the conductive layer, wherein the stack structure further includes lower gate electrodes, memory gate electrodes, and upper gate electrodes stacked and spaced apart from each other in a second direction perpendicular to the upper surface of the conductive layer, and wherein some of the upper gate electrodes extend to different lengths from each other in the first direction in the third region, and some of the upper gate electrodes respectively include pad regions; an insulating layer on the stack structure; a channel structure extending into the stack structure in the second direction in the first region; first contact plugs extending into the insulating layer in the second direction, wherein the first contact plugs are respectively electrically connected to the pad regions of some of the upper gate electrodes in the third region; second contact plugs extending into the upper gate electrodes, into at least one of the memory gate electrodes and the lower gate electrodes, and into the insulating layer in the second direction, wherein some of the second contact plugs extend to different lengths from each other in the second direction, and are respectively electrically connected to the lower gate electrodes and / or the memory gate electrodes in the second region; side surface insulating structures extending around side surfaces of each of the second contact plugs in the second region; and an upper side surface insulating layer extending around side surfaces of each of the first contact plugs in the third region.

[0008] According to example embodiments of the present disclosure, a semiconductor device includes: a conductive layer; a stack structure on the conductive layer, wherein the stack structure includes a first region, a second region, and a third region between the first region and the second region in a first direction parallel to an upper surface of the conductive layer, wherein the stack structure further includes memory gate electrodes and upper gate electrodes stacked and spaced apart from each other in a second direction perpendicular to the upper surface of the conductive layer, and wherein some of the upper gate electrodes extend to different lengths from each other in the first direction in the third region, and some of the upper gate electrodes respectively include pad regions; an insulating layer on the stack structure; isolation regions extending to the upper gate electrodes in the first direction in the first region and the third region; a channel structure extending to the stack structure in the second direction in the first region; first contact structures extending to the insulating layer in the second direction, wherein the first contact structures are respectively electrically connected to the pad regions of some of the upper gate electrodes in the third region; second contact structures extending to at least one of the upper gate electrodes, the insulating layer, and the memory gate electrodes, wherein the second contact structures are respectively electrically connected to the memory gate electrodes in the second region, and wherein respective upper surfaces of the second contact structures are coplanar with respective upper surfaces of the first contact structures; first pillars on the first contact structures; and second pillars on the second contact structures, wherein respective upper surfaces of the first pillars are coplanar with respective upper surfaces of the second pillars, and wherein respective lower surfaces of the first pillars are coplanar with respective lower surfaces of the second pillars.

[0009] According to example embodiments of the present disclosure, a data storage system includes a semiconductor storage device including a first semiconductor structure including a circuit device, a second semiconductor structure on the first semiconductor structure, and an input / output pad electrically connected to the circuit device, and a controller electrically connected to the semiconductor storage device through the input / output pad, wherein the controller is configured to control the semiconductor storage device, wherein the second semiconductor structure includes: a conductive layer; a stack structure on the conductive layer, wherein the stack structure includes a first region, a second region, and a third region between the first region and the second region in a first direction parallel to an upper surface of the conductive layer, wherein the stack structure further includes lower gate electrodes, memory gate electrodes, and upper gate electrodes stacked in a second direction perpendicular to the upper surface of the conductive layer and spaced apart from each other, and wherein some of the upper gate electrodes extend to different lengths from each other in the first direction in the third region, and includes a pad region; an insulating layer on the stack structure; a channel structure extending into the stack structure in the second direction in the first region; first contact plugs extending into the insulating layer in the second direction, wherein the first contact plugs are electrically connected to the pad regions of the upper gate electrodes, respectively, in the third region; second contact plugs extending into the upper gate electrodes, extending into at least one of the memory gate electrodes and the lower gate electrodes, and extending into the insulating layer in the second direction, wherein some of the second contact plugs extend to different lengths from each other in the second direction and are electrically connected to the lower gate electrodes and / or the memory gate electrodes, respectively, in the second region; a side surface insulating structure extending around a side surface of each of the second contact plugs in the second region; and an upper side surface insulating layer extending around a side surface of each of the first contact plugs in the third region. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] FIG. 1 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0012] FIG. 2A and FIG. 2B is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0013] FIG. 3A , FIG. 3B and FIG. 3C are enlarged views showing a partial region in FIG. 2A ;

[0014] FIG. 4 to FIG. 7 is an enlarged cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0015] FIG. 8 to FIG. 10 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0016] FIG. 11A 、 FIG. 11B 、 FIG. 11C 、 FIG. 11D 、 FIG. 11E 、 FIG. 11F 、 FIG. 11G 、 FIG. 11H 、 FIG. 11I 、 FIG. 11J and FIG. 11K is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0017] FIG. 12 is a view showing a data storage system including a semiconductor device according to an example embodiment of the present disclosure; and

[0018] FIG. 13 is a perspective view showing a data storage system including a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0020] FIG. 1 is a plan view showing a semiconductor device according to an example embodiment. FIG. 2A and FIG. 2B are cross-sectional views showing a semiconductor device according to an example embodiment. FIG. 2A is a cross-sectional view showing a region of the semiconductor device in FIG. 1 taken along line I-I', and FIG. 2B is a cross-sectional view showing a region of the semiconductor device in FIG. 1 taken along line II-II'. FIG. 3A is an enlarged view showing a region "A" in FIG. 2A , FIG. 3B is an enlarged view showing a region "B" in FIG. 2A , FIG. 3C is an enlarged view showing a region "C" in FIG. 2A .

[0021] With reference to FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C , the semiconductor device 100 can include a memory region R1 and an extension region R2 at a side of the memory region R1 in a first horizontal direction (e.g., X direction).

[0022] The memory region R1 can be configured as a memory cell region in which a memory cell string CSTR is disposed, and a channel structure CH can be disposed in the memory region R1. The extension region R2 can be a region for electrically connecting the channel structure CH to a peripheral circuit structure, and for this purpose, a plurality of word line contact plugs MC2 electrically connected to gate electrodes of different levels can be disposed in the extension region R2, but example embodiments thereof are not limited thereto.

[0023] The upper contact region R3 can be disposed between the memory region R1 and the extension region R2 (in the first horizontal direction). The upper contact region R3 can be a region in which upper contact plugs MC1 electrically connected to upper gate electrodes 130U are disposed. For example, the upper contact plugs MC1 electrically connected to erase gate electrodes (e.g., erase gate electrodes 130U5, 130U6, and 130U7) and string selection gate electrodes (e.g., string selection gate electrodes 130U1, 130U2, 130U3, and 130U4) can be disposed in the upper contact region R3.

[0024] More specifically, the upper contact region R3 can be defined to include a first upper contact region R3a adjacent to the memory region R1 in which the upper contact plugs MC1 electrically connected to the erase gate electrodes 130U5, 130U6, and 130U7 and the string selection gate electrodes 130U1, 130U2, 130U3, and 130U4 are disposed, and a second upper contact region R3b in which the upper contact plugs MC1 are not disposed between the first upper contact region R3a and the extension region R2 (in the first horizontal direction) and the upper gate electrodes 130U form a staircase shape.

[0025] In the first upper contact region R3a, the upper gate electrodes 130U electrically connected to the upper contact plugs MC1, respectively, can form a step difference structure having a staircase shape in which the number of steps decreases toward the extension region R2 in the first horizontal direction (e.g., the X direction), and regions of the exposed upper gate electrodes 130U can form pad regions GP and can be in contact with the upper contact plugs MC1 in the pad regions GP, respectively. The second upper contact region R3b can be connected to the extension region R2 and can form a staircase shape symmetrically (in the first horizontal direction) to the first upper contact region R3a and can form a step difference structure having a staircase shape in which the number of steps increases toward the extension region R2 in the X direction. Accordingly, the upper contact region R3 can also be defined as a region etched such that the upper gate electrodes 130U can form a staircase shape.

[0026] The semiconductor device 100 can have a structure in which the memory region R1, the upper contact region R3, and the extension region R2 are disposed in order in the first horizontal direction (e.g., the X direction).

[0027] The semiconductor device 100 can include a conductive layer 101, a stack structure GS (GS1-GSk, where k is a positive integer) in which gate electrodes 130 and interlayer insulating layers 120 are alternately stacked on an upper surface of the conductive layer 101 in a memory region R1, an upper contact region R3, and an extension region R2, a channel structure CH disposed in the memory region R1 to extend into (e.g., penetrate) the stack structure GS1-GSk, an isolation region MS extending into (e.g., penetrating) the stack structure GS1-GSk and extending in a first horizontal direction (e.g., X direction), and an insulating region SS extending into (e.g., penetrating) at least a portion of the gate electrode 130. An interconnection structure and a passivation layer can also be included under the conductive layer 101.

[0028] In the extension region R2, a support structure SH and a word line contact plug MC2 can be disposed, and in the upper contact region R3, a dummy channel structure DH and an upper contact plug MC1 can be disposed.

[0029] In FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C , the contact plugs MC1 and MC2 (the upper contact plug MC1 and the word line contact plug MC2) are shown as extending to different lengths for the (electrical) connection between each gate electrode 130 and the contact plugs MC1 and MC2, but example embodiments thereof are not limited thereto.

[0030] The memory region R1 and the extension region R2 can include a cell region insulating layer 190 as an upper portion of the stack structure GS. For example, the cell region insulating layer 190 can be on the stack structure GS. A first upper insulating layer 192 can be on the cell region insulating layer 190, and a second upper insulating layer 194 can be on the first upper insulating layer 192. The first upper insulating layer 192 can be between the cell region insulating layer 190 and the second upper insulating layer 194. The contact plugs MC1 and MC2 can extend into (e.g., penetrate) the cell region insulating layer 190 and / or the first upper insulating layer 192, although embodiments are not limited thereto. The memory region R1, the extension region R2, and the upper contact region R3 can include a first stud 180a, a second stud 180b, and a third stud 180c for electrical connection with the channel structure CH and the contact plugs MC1 and MC2. For example, the memory region R1, the extension region R2, and the upper contact region R3 can include the third stud 180c, the first stud 180a, and the second stud 180b, respectively, although embodiments are not limited thereto. The first stud 180a, the second stud 180b, and the third stud 180c can extend into (e.g., penetrate) the second upper insulating layer 194, although embodiments are not limited thereto. In some embodiments, the first stud 180a, the second stud 180b, and the third stud 180c can be in contact with the contact plugs MC1 and MC2. The memory region R1, the extension region R2, and the upper contact region R3 can include a cell interconnect line 185 on the second upper insulating layer 194. The cell interconnect line 185 can be (electrically) connected to the first stud 180a, the second stud 180b, and the third stud 180c.

[0031] The conductive layer 101 can include a conductive material such as doped silicon, metal, and / or metal nitride as a common source (common source line). For example, the conductive layer 101 can include a silicon layer having N-type conductivity, which can be a common source.

[0032] The gate electrodes 130 can be vertically spaced apart from each other on the upper surface of the conductive layer 101, and can form a stack structure GS (GS1-GS3) together with the interlayer insulating layer 120.

[0033] The gate electrodes 130 can include at least one lower gate electrode 130L forming a gate of a ground select transistor, memory gate electrodes 130M forming gates of a plurality of memory cells, and an upper gate electrode 130U as a string select gate forming a gate of a string select transistor, for the entire stack structure GS. Here, the lower gate electrode 130L and the upper gate electrode 130U can be referred to as "lower" and "upper" with respect to a direction during a manufacturing process. The number of the memory gate electrodes 130M forming the gates of the memory cells can be determined according to a capacity of the semiconductor device 100. According to an example embodiment, the number of each of the upper gate electrode 130U and the lower gate electrode 130L can be 1 to 2 or more, and can have the same or different structure from that of the memory gate electrodes 130M. In an example embodiment, the number of the upper gate electrode 130U can be shown as seven. Erase gate electrodes 130U5, 130U6, and 130U7 can be disposed on the string select gate electrodes 130U1, 130U2, 130U3, and 130U4, and can be included in the upper gate electrode 130U. Thus, the seven upper gate electrodes 130U can be understood to have three erase gate electrodes 130U7, 130U6, and 130U5 and four string select gate electrodes 130U4, 130U3, 130U2, and 130U1 disposed in a downward order. Further, a portion of the gate electrodes 130 (e.g., the memory gate electrodes 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) can be a dummy gate electrode 130, but example embodiments thereof are not limited thereto.

[0034] The gate electrode 130 can extend from the extension region R2 to the memory region R1 on one side. For example, the gate electrode 130 can extend in a first horizontal direction (e.g., an X direction) between the extension region R2 and one side of the memory region R1. The upper gate electrode 130U can be an upper gate electrode (which can be in an upper portion) among the gate electrodes 130. The upper gate electrode 130U in the upper portion (of the gate electrode 130) can be etched in order from the first upper contact region R3a, and can form a staircase shape that exposes a pad region GP of the upper gate electrode 130U. Also, in the second upper contact region R3b, the upper gate electrode 130U can be etched so as to expose the pad region GP of the upper gate electrode 130U. In this case, the staircase direction of the first upper contact region R3a and the second upper contact region R3b can be formed symmetrically to each other (in the horizontal direction (e.g., the X direction)), but example embodiments thereof are not limited thereto. When the upper gate electrode 130U includes seven gate electrodes 130 from the upper portion of the gate electrode 130, a buffer region SP in which an eighth gate electrode 130 is partially exposed can be further formed, but example embodiments thereof are not limited thereto. The staircase shape of the first upper contact region R3a and the staircase shape of the second upper contact region R3b can be formed to face each other with the buffer region SP as a central portion in the first horizontal direction (e.g., the X direction). Through the staircase shape, the upper gate electrode 130U of the first upper contact region R3a and the second upper contact region R3b can be physically and electrically isolated from each other. For example, the upper gate electrode 130U (of a portion) in the first upper contact region R3a and the upper gate electrode 130U (of a portion) in the second upper contact region R3b can be spaced apart from each other by a cell region insulating layer 190 therebetween.

[0035] The stack structure GS can include stack structures GS1-GS3 vertically stacked at a plurality of levels. In FIG. 2A and FIG. 2B The first stack structure GS1, the second stack structure GS2, and the third stack structure GS3 can be included, but example embodiments thereof are not limited thereto. For example, a stack structure GS of four to eight levels of steps can be included. In some embodiments, the stack structure GS can be configured as a stack structure GS of two levels. The levels of each stack structure GS can be classified as a height of a stack structure that can implement a channel hole process for a predetermined depth of a channel structure CH, and can be distinguished from each other by a channel portion (e.g., a first channel portion CH1, a second channel portion CH2, and a third channel portion CH3) of the channel structure CH. A lower stack structure located on an upper surface of the conductive layer 101 can be referred to as a first stack structure GS1, and stack structures GS2-GS3 on the first stack structure GS1 can be sequentially referred to as a second stack structure GS2 and a third stack structure GS3.

[0036] In the stack structures GS1-GS3, the gate electrodes 130 and the interlayer insulating layers 120 can be alternately stacked in a vertical direction (e.g., a Z direction), and a length in the vertical direction of each of the stack structures GS1-GS3 and a number of the gate electrodes 130 of each of the stack structures GS1-GS3 can be (substantially) the same, but example embodiments thereof are not limited thereto.

[0037] Referring to FIG. 1 , FIG. 2A and FIG. 2B , the gate electrodes 130 can be isolated from each other in a second horizontal direction (e.g., a Y direction) by the isolation regions MS extending continuously from the memory region R1 to the extension region R2. The gate electrodes 130 between a pair of (adjacent) isolation regions MS can form a single memory block BLK, but the range of the memory block BLK is not limited thereto. A portion of the gate electrodes 130 (e.g., memory gate electrodes 130M) can form a single layer in the memory block BLK.

[0038] The gate electrodes 130 can be vertically stacked and spaced apart from each other in the memory region R1, the upper contact region R3, and the extension region R2, and can maintain a continuous flat shape without forming a stepped difference structure of a stair shape in the memory region R1 and the extension region R2. The upper gate electrodes 130U can form a stepped difference structure of a stair shape only in the upper contact region R3. The contact region of each of the gate electrodes 130 can be a region in contact with the upper contact plug MC1, as a pad region GP exposed by the stair shape in the upper contact region R3, and can be defined as a region in contact with a word line contact plug MC2 in the extension region R2.

[0039] The gate electrodes 130 can include a conductive material layer 135, and the conductive material layer 135 can include, for example, W, Ru, Mo, Nb, Ni, Co, Ti, Ta, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and / or a combination thereof, but example embodiments thereof are not limited thereto. According to example embodiments, the gate electrodes 130 can further include a diffusion barrier 132, and for example, the diffusion barrier 132 can include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), and / or a combination thereof.

[0040] The interlayer insulating layers 120 can be disposed between the (adjacent) gate electrodes 130 and can form the stack structure GS. Similar to the gate electrodes 130, the interlayer insulating layers 120 can be spaced apart from each other in a direction perpendicular to the upper surface of the conductive layer 101 (in a vertical direction (e.g., Z direction)) and can extend in the first horizontal direction (e.g., X direction). The interlayer insulating layers 120 can include an insulating material such as silicon oxide and / or silicon nitride.

[0041] In example embodiments, the thickness of the interlayer insulating layers 120 can be (generally and / or substantially) the same, but the thickness of a portion thereof can not be the same. For example, the thickness of the uppermost interlayer insulating layer 121 among the interlayer insulating layers 120 can be greater than the thickness of the other interlayer insulating layers 120, but example embodiments are not limited thereto. In the description, the semiconductor device 100 can include the memory region R1, the upper contact region R3, and the extension region R2, but it can be understood that the stack structure GS can include the memory region R1, the upper contact region R3, and the extension region R2.

[0042] The isolation region MS can extend into (e.g., penetrate) at least a portion of the gate electrode 130 and can extend in the first horizontal direction (e.g., X direction). The isolation region MS can continuously pass through the memory region R1, the upper contact region R3, and the extension region R2 and can extend in the first horizontal direction (e.g., X direction). The isolation regions MS can be disposed in parallel to each other. The isolation region MS can penetrate the entire stack gate electrode 130 and can be connected to the conductive layer 101. The isolation region MS can extend as an integrated region in the first horizontal direction (e.g., X direction), but in some example embodiments, the isolation region MS can extend intermittently or can be disposed only in a partial region. The isolation region MS can have a linear shape in the X-Y plane. In some embodiments, the isolation region MS can have a shape in which a side surface has a continuously curved surface and extends in the first horizontal direction (e.g., X direction).

[0043] An isolation insulating layer can be disposed in the isolation region MS. Due to a high aspect ratio, the isolation insulating layer can have a shape in which a width decreases toward the conductive layer 101, but example embodiments are not limited thereto. An upper surface of the isolation insulating layer can be in contact with the first upper insulating layer 192, and a lower surface can be in contact with the upper surface of the conductive layer 101.

[0044] The insulation region SS can extend in a first horizontal direction (e.g., X direction) between the adjacent isolation regions MS. The insulation region SS can selectively penetrate only the upper gate electrodes 130U1-130U7, i.e., the erase gate electrodes 130U5-130U7 and the string selection gate electrodes 130U1-130U4, and can divide the upper gate electrodes 130U among the stack structure GS (or between the adjacent isolation regions MS) into a plurality of sub-sections.

[0045] Referring to FIG. 1 The insulation region SS can extend in a first horizontal direction (e.g., X direction) across the memory region R1 and the upper contact region R3 (e.g., the first upper contact region R3a). The insulation region SS can include a plurality of insulation regions SS parallel to each other between the isolation regions MS and can be spaced apart from each other in a second horizontal direction (e.g., Y direction), and can selectively isolate only the upper gate electrodes 130U.

[0046] The insulation region SS can be disposed to have the same length in a vertical direction (e.g., Z direction) from the upper portion, and a lower surface can be disposed at a level lower than a level of a lower surface of the lowermost upper gate electrode 130U1 among the upper gate electrodes 130U and can be disposed at a level higher than a level of a lower surface of the interlayer insulation layer 120 below (on a lower surface of) the lowermost upper gate electrode 130U1. Accordingly, the upper gate electrodes 130U (of the memory region R1) can be completely penetrated by the insulation region SS, and also can be isolated from the upper gate electrodes 130U of the extension region R3 by the stepped shape, thereby forming a plurality of sub-sections physically / electrically (completely) spaced apart from each other. In this context, the term "level", "vertical level", "height", and the like can refer to a relative position in a vertical direction (e.g., Z direction) with respect to a reference element. The level, the vertical level, the height, and the like can be a distance in the vertical direction from an upper surface of the conductive layer 101. For example, a higher level can mean a distance further in the vertical direction from the upper surface of the conductive layer 101, and a lower level can mean a distance closer in the vertical direction from the upper surface of the conductive layer 101.

[0047] Since the insulation region SS selectively penetrates only the upper gate electrodes 130U and does not extend into (below) the memory gate electrodes 130M, the memory gate electrodes 130M and the lower gate electrodes 130L can not be isolated by the insulation region SS, and the memory gate electrodes 130M and the lower gate electrodes 130L in the memory region R1, the upper contact region R3, and the extension region R2 can be stacked into a single slab shape.

[0048] The insulating regions SS can be disposed across (overlap with) a portion of the channel structures CH in the memory region R1. The insulating regions SS can have a predetermined width and can extend by crossing in a wave shape in the first horizontal direction (e.g., the X direction) between a plurality of channel structures CH arranged in a zigzag manner. Accordingly, when the plurality of channel structures CH are arranged to have the same interval, the insulating regions SS can extend to cut (overlap) the channel structures CH at each apex of the wave shape. The insulating regions SS can be recessed into an upper end portion of the channel structures CH, e.g., portions of the channel structures CH opposite the seven upper gate electrodes 130U, and thus a portion of the channel structures CH can be removed. In this case, when viewed on the X-Y plane, the channel structures CH can be recessed so as to cut (about) 1 / 3 to 1 / 4 of the circumference of the upper surface, for example. The insulating regions SS can be disposed such that the insulating regions SS can not pass through the channel center axes of the channel structures CH, and more than (about) 2 / 3 of the channel structures CH can remain on the upper surface, but example embodiments thereof are not limited thereto. The channel structures CH into which the insulating regions SS are recessed can be actual channel structures that can function as memory cells, rather than dummy channel structures. The insulating regions SS can extend in a wave shape in the memory region R1 and can extend in a linear shape (in a plan view) in the upper contact region R3. In this case, the widths of the wave shape and the linear shape can be kept (substantially) the same, but example embodiments thereof are not limited thereto. Each of the insulating regions SS can include an upper isolation insulating layer. The upper isolation insulating layer can include an insulating material, e.g., silicon oxide, silicon nitride, and / or silicon oxynitride.

[0049] The channel structures CH can form rows and columns on the conductive layer 101 of the memory region R1 and can be spaced apart from each other. In the memory region R1, the channel structures CH can be disposed in a zigzag shape in one direction on the X-Y plane. The channel structures CH can extend into (e.g., penetrate) the gate electrodes 130, can extend in a vertical direction (e.g., in the Z direction) perpendicular to the upper surface of the conductive layer 101, can have a pillar shape, and can have a slanted side surface whose width can decrease toward the conductive layer 101 according to an aspect ratio.

[0050] Each of the channel structures CH can have a form in which k stacked structures GS1-GSk in which the gate electrodes 130 pass through the k channel portions CH1-CHk (k is 1, 2, 3, or a positive integer) are connected to each other (electrically). In an example embodiment, the first channel portion CH1 to the third channel portion CH3 that respectively penetrate three stacked structures GS1-GS3 can be connected to each other (electrically).

[0051] As FIG. 3AAs shown in the enlarged view in FIG. 1A, in each of the first to third channel portions CH1 to CH3, the width of the upper end can be greater than the width of the lower end, and due to the difference in width between the upper end and the lower end, the side surface can be a sloped surface whose width decreases toward the conductive layer 101. The lower end of the upper first to third channel portions CH1 to CH3 and the upper end of the lower first to third channel portions CH1 to CH3 can be (electrically) connected to each other, and can form a curved portion. For example, the upper end of the first channel portion CH1 can be (electrically) connected to the lower end of the second channel portion CH2, and the upper end of the second channel portion CH2 can be (electrically) connected to the lower end of the third channel portion CH3.

[0052] Each of the channel structures CH can include a first portion in the stack structure GS1-GS3 and a second portion that protrudes to a region below the stack structure GS1-GS3 and is in contact with (extends into) the conductive layer 101.

[0053] The channel layer 140 can be disposed entirely in the first and second portions of the channel structure CH, and can be disposed up to the upper end of the first portion. The channel layer 140 can include a protruding portion that protrudes to a region below the stack structure GS1-GS3 and is exposed, and a non-protruding portion that is disposed in the first portion of the channel structure CH. The protruding length (in the vertical direction) of the protruding portion of the channel layer 140 in the second portion and in the channel structure CH can not be the same, but example embodiments thereof are not limited thereto. According to example embodiments, the channel layer 140 can be formed to have a ring shape whose side surface can extend around (e.g., at least partially surround) the buried insulating layer 147, but can also have a columnar shape such as a cylindrical shape or a prismatic shape without the buried insulating layer 147. The protruding portion of the channel layer 140 can extend into the conductive layer 101 and can be in direct contact with the conductive layer 101. The protruding portion can be formed to have a gentle slope with respect to the non-protruding portion, so that the ring shape can be maintained, as shown in FIG. 1A. FIG. 3A The channel layer 140 can include, for example, a semiconductor material such as polysilicon and / or single crystal silicon, and the semiconductor material can be an undoped material or a material including P-type and / or N-type impurities.

[0054] The channel pad 149 can be disposed in the upper portion of the channel layer 140 in the channel structure CH. The channel pad 149 can be disposed to cover (or overlap in the vertical direction) the upper surface of the buried insulating layer 147 and be electrically connected to the channel layer 140. The channel pad 149 can include, for example, doped polysilicon.

[0055] A channel dielectric layer 145 can be disposed between the gate electrode 130 and the channel layer 140. The channel dielectric layer 145 can include, stacked in order from the channel layer 140, a tunneling layer 141, a charge storage layer 142, and a blocking layer 143. The tunneling layer 141 can tunnel charges into the charge storage layer 142, and can include, for example, silicon oxide (e.g., Si02), silicon nitride (e.g., Si3N4), silicon oxynitride (e.g., SiON), and / or combinations thereof. The charge storage layer 142 can be a charge-trap layer or a floating gate conductive layer. The blocking layer 143 can include, for example, silicon oxide (e.g., Si02), silicon nitride (e.g., Si3N4), silicon oxynitride (e.g., SiON), high-k dielectric material, and / or combinations thereof. According to example embodiments, (at least) a portion of the channel dielectric layer 145 can form a channel dielectric layer extending horizontally along the gate electrode 130.

[0056] The channel dielectric layer 145 can be removed from underneath the stacked structure GS1-GS3, such that the protruding portion of the channel layer 140 can be externally exposed in the second portion (of the channel structure CH). Thus, a lower end of the channel dielectric layer 145 can be in contact with the conductive layer 101, and a side surface of the channel dielectric layer 145 can be disposed to extend (at least partially surround) around the non-protruding portion of the channel layer 140 in the first portion (of the channel structure CH).

[0057] The channel layer 140, the channel dielectric layer 145, and the buried insulating layer 147 can be (electrically) connected to each other between the first to third channel portions CH1-CH3. For example, the channel layer 140 can be in contact with the channel dielectric layer 145 and the buried insulating layer 147.

[0058] The dummy channel structures DH can be disposed in the upper contact region R3, and can have a structure (substantially) identical or similar to that of the channel structure CH, and can not perform an actual memory function in the semiconductor device 100. The dummy channel structures DH can be regularly disposed in rows and columns in the upper contact region R3. The dummy channel structures DH can extend around (surround) the upper contact plug MC1, and as such, can be disposed in the upper contact region R3 in a manner that the dummy channel structures DH are not in contact with the upper contact plug MC1. FIG. 1As shown, four dummy trench structures DH can be disposed around the upper contact plug MC1. The dummy trench structures DH can have a diameter (substantially) equal to or greater than the maximum diameter of the trench structures CH and a diameter smaller than the maximum diameter of the upper contact plug MC1. The shape and number of each of the dummy trench structures DH and / or the distance therebetween can vary. The trench structures CH and the dummy trench structures DH can have a circular shape or a nearly circular shape (in a plan view), but example embodiments thereof are not limited thereto. For example, the trench structures CH and the dummy trench structures DH can have an elliptical shape (in a plan view). The dummy trench structures DH can extend into (e.g., penetrate) the stack structure GS similarly to the trench structures CH, and the trench dielectric layer 145 can be disposed in an area interposed into the conductive layer 101 such that the trench layer 140 can not be exposed and can maintain an insulating state with the conductive layer 101. For example, the trench layer 140 in the dummy trench structures DH can be spaced apart from the conductive layer 101 by the trench dielectric layer 145 in the dummy trench structures DH. The dummy trench structures DH can be a support that can prevent deformation (such as warping) of the stack structure GS.

[0059] The support structures SH can be disposed in the extended area R2. The support structures SH can have a different structure from the dummy trench structures DH. The support structures SH can be regularly disposed in rows and columns in the extended area R2. The support structures SH can have a diameter greater than the maximum diameter of the trench structures CH and can have a diameter smaller than the maximum diameter of the word line contact plug MC2. The shape and number of the support structures SH and / or the distance therebetween can vary. The support structures SH can have a circular shape or a nearly circular shape (in a plan view), but example embodiments thereof are not limited thereto. For example, the support structures SH can have an elliptical shape in a plan view. The support structures SH can extend into (e.g., penetrate) the stack structure GS similarly to the trench structures CH and can include a vertical portion extending in a vertical direction (e.g., Z direction) and a horizontal portion protruding from the vertical portion toward each gate electrode 130, but example embodiments thereof are not limited thereto. The support structures SH can also have a structure including a plurality of curved portions corresponding to the curved portions of the first to third trench portions CH1 to CH3 of the trench structures CH. The support structures SH can be configured as a support for preventing deformation (such as warping) of the stack structure GS.

[0060] The semiconductor device 100 can include contact plugs MC1 and MC2 that are respectively (electrically) connected to the gate electrodes 130 in the upper contact region R3 and the extension region R2. The contact plugs MC1 and MC2 can extend into (e.g., penetrate) the first upper insulating layer 192, the uppermost interlayer insulating layer 121, and / or the cell region insulating layer 190, and can extend downward in a vertical direction (e.g., Z direction) and can be (electrically) connected to upper surfaces of the assigned gate electrodes 130. The contact plugs MC1 and MC2 can have a circular or elliptical shape in the X-Y plane, as shown in FIG. 1 , and can be spaced apart from each other in a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction). The contact plugs MC1 and MC2 can be arranged in a lattice shape or a zigzag shape, and the arrangement and shape of the upper contact plugs MC1 and the word line contact plugs MC2 can be different from each other.

[0061] The word line contact plugs MC2 can be alternately arranged in rows in the extension region R2 in a zigzag pattern, and the upper contact plugs MC1 can be arranged in rows in sub-regions divided by the insulating regions SS.

[0062] The upper contact plugs MC1 can be provided in the upper contact region R3 and can be respectively (electrically) connected to a predetermined number of the upper gate electrodes 130U serving as the erase gate electrodes 130U5-130U7 and a predetermined number of the upper gate electrodes 130U serving as the string selection gate electrodes 130U1-130U4 in the upper gate electrodes 130U.

[0063] In FIG. 1 , FIG. 2A and FIG. 2B , it is shown that the number of the erase gate electrodes 130U5-130U7 can be three and the number of the string selection gate electrodes 130U1-130U4 can be four, and thus, seven upper contact plugs MC1 (electrically) connected to the upper gate electrodes 130U1-130U7 can be provided in each sub-section. That is, the upper contact plugs MC1 respectively (electrically) connected to the upper gate electrodes 130U can be provided in the sub-sections of the upper gate electrodes 130U divided by the insulating regions SS.

[0064] In an example embodiment, the upper gate electrodes 130U can have a stepped difference structure of a ladder shape, such that each pad region GP can be exposed in the upper contact region R3. In this case, the length of the pad region GP in the first horizontal direction (e.g., the X direction), i.e., the length of the ladder, can be smaller in the erase gate electrodes 130U5-130U7 than in the string selection gate electrodes 130U1-130U4. For example, the length of the pad region GP of one of the erase gate electrodes 130U5-130U7 can be (about) 1 / 4 to 1 / 2 of the length of the pad region GP of one of the string selection gate electrodes 130U1-130U4, but example embodiments are not limited thereto.

[0065] The upper contact plugs MC1 (electrically) connected to one of the erase gate electrodes 130U5-130U7 can be (electrically) connected to each other through the erase lines in their upper portions, such that the length of the pad region GP corresponding to the erase line can be required, and the string selection gate electrodes 130U1-130U4 can be (electrically) connected to different string lines in each sub-section, such that the length of the pad region GP at least four circuit interconnections can be required to be spaced apart from each other. However, the length of the pad region GP can be implemented in various ways according to the circuit design.

[0066] In each sub-section, one upper contact plug MC1 can be (electrically) connected to one upper gate electrode 130U, but in some embodiments, a plurality of upper contact plugs MC1 can be (electrically) connected to one upper gate electrode 130U. Accordingly, the number of the upper contact plugs MC1 assigned to each sub-section can be the same, and the number of the upper contact plugs MC1 assigned to each sub-section can satisfy an integer multiple of the number of the upper gate electrodes 130U.

[0067] In each sub-section, the upper gate electrodes 130U1-130U4 can be individually connected to each other through the four string selection contact plugs MC1, and can transmit an electrical signal, thereby selecting the channel structure CH of the corresponding sub-section.

[0068] The upper contact plug MC1 can include a conductive layer, and can be implemented in a pillar shape extending in a vertical direction (e.g., the Z direction), such that the pad region GP and the lower surfaces of the first to seventh upper gate electrodes 130U1-130U7 can contact each other. Specifically, the upper contact plug MC1 can extend from the first upper insulating layer 192 in the vertical direction (e.g., the Z direction) to extend into (e.g., penetrate) the uppermost interlayer insulating layer 121 or the cell region insulating layer 190 and contact the pad region GP of the assigned upper gate electrode 130U.

[0069] The upper surface of the upper contact plug MC1 can be located at (substantially) the same level as the upper surface of the first upper insulating layer 192 (coplanar), and the lower surface can be located at (substantially) the same level as or a lower level than the upper surface of the distributed upper gate electrode 130U in the pad region GP of the distributed upper gate electrode 130U. The upper surface of the upper contact plug MC1 can have a circular shape or an elliptical shape when viewed on the X-Y plane, the width W1 of the upper surface can be greater than the width W3 of the lower surface, and a slanted side surface can be provided between the upper surface and the lower surface. Each side surface of the upper contact plug MC1 can have a continuously inclined slanted surface without a curved portion, but example embodiments thereof are not limited thereto.

[0070] An upper side surface insulating layer 175 can be further provided on the upper region of the side surface of the upper contact plug MC1. The upper side surface insulating layer 175 can extend around (e.g., surround) the upper region of the side surface of the upper contact plug MC1, and can have a ring shape. The upper end of the upper side surface insulating layer 175 can be coplanar with the upper surface of the upper contact plug MC1, and the lower end of the upper side surface insulating layer 175 can be located at a higher level than the level of the lower surface of the upper contact plug MC1. In some embodiments, the lower end of the upper side surface insulating layer 175 can be coplanar with the lower surface of the first upper insulating layer 192. In some embodiments, the lower end of the upper side surface insulating layer 175 can be coplanar with the upper surface of the uppermost interlayer insulating layer 121 or the upper surface of the cell region insulating layer 190.

[0071] As described above, the upper side surface insulating layer 175 can be disposed between the first upper insulating layer 192 and a side surface of the upper contact plug MC1, and can be in direct contact with an upper region of the side surface of the upper contact plug MC1. The upper side surface insulating layer 175 can be disposed to have a substantially uniform side surface thickness ta from the upper end to the lower end, and can be disposed in a shape in which the upper side surface insulating layer 175 extends in a ring shape on the X-Y plane around the upper region of the circular upper contact plug MC1 (e.g., around the upper region of the circular upper contact plug MC1). The side surface thickness ta can be less than (e.g., less than) the thickness of the interlayer insulating layer 120. For example, the side surface thickness ta can be 400 Å to 500 Å. For example, the side surface thickness ta can be (about) 450 Å, but example embodiments are not limited thereto. The upper side surface insulating layer 175 can be formed to have a length (substantially) the same as the thickness t1 of the first upper insulating layer 192 in the vertical direction (e.g., the Z direction). Accordingly, the upper region of the side surface of the upper contact plug MC1 can be in contact with the upper side surface insulating layer 175, and the lower region of the side surface of the upper contact plug MC1 can be in contact with the uppermost interlayer insulating layer 121 or the cell region insulating layer 190. As described above, the side surface of the upper contact plug MC1 can be in contact with different insulating layers according to the level.

[0072] The upper side surface insulating layer 175 can include an atomic layer deposition (ALD) insulating material, and for example, can be formed of silicon oxide, undoped polysilicon, and / or silicon nitride having a uniform thickness ta through an ALD process. Accordingly, even when including the same material as the material of the first upper insulating layer 192, the interlayer insulating layer 120, or the cell region insulating layer 190, the insulating material formed through the ALD process can have a significantly lower density.

[0073] The upper contact plug MC1 and the upper side surface insulating layer 175 as described above can be referred to as an upper contact structure CS1.

[0074] The word line contact plug MC2 can include a conductive layer, can fill a central region of the contact hole, and can have a pillar shape extending in the vertical direction (e.g., the Z direction) from an upper surface that is coplanar with the upper surface of the first upper insulating layer 192 to a lower surface that is in contact with the assigned gate electrode 130. The word line contact plug MC2 can include a length-dependent curved portion, and a width W4 of the upper surface of the word line contact plug MC2 can be greater than a width of its lower surface, and a slanted side surface can be disposed between the upper surface and the lower surface. The upper surface of the word line contact plug MC2 can be coplanar with the upper surface of the upper contact plug MC1, and can be coplanar with the upper surface of the first upper insulating layer 192. A contact barrier layer can be further included on the side surface and the lower surface of the conductive layer, but example embodiments are not limited thereto.

[0075] The first side surface insulating layer 160 can be disposed between the stack structure GS in which the word line contact plug MC2 extends (e.g., penetrates) and the word line contact plug MC2. The first side surface insulating layer 160 can be disposed on a side surface of the word line contact plug MC2 and can be disposed such that an upper end can be located at a level lower than a level of an upper surface of the word line contact plug MC2 and a lower end can be located at a level (substantially) equal to or higher than a level of a lower surface of the word line contact plug MC2. The lower end of the first side surface insulating layer 160 can be disposed to expose an upper surface of the assigned gate electrode 130 and can be disposed to insulate the gate electrode 130 in an upper portion of the assigned gate electrode 130.

[0076] The second side surface insulating layer 170 can be disposed between the first side surface insulating layer 160 and the word line contact plug MC2. The second side surface insulating layer 170 can be in direct contact with a side surface of the word line contact plug MC2, can have an upper end at (substantially) the same level as an upper surface of the word line contact plug MC2 and a lower end at (substantially) the same level as the lower end of the first side surface insulating layer 160. Accordingly, the upper end of the second side surface insulating layer 170 can be located at a level higher than the level of the upper end of the first side surface insulating layer 160 and can extend into (e.g., penetrate) the first upper insulating layer 192. Accordingly, the upper surface of the word line contact plug MC2 and the upper end of the second side surface insulating layer 170 can be exposed on the first upper insulating layer 192 and the upper end of the first side surface insulating layer 160 can not be exposed. The first upper insulating layer 192, the upper surface of the word line contact plug MC2, and the upper end of the second side surface insulating layer 170 can be (substantially) coplanar with each other, but example embodiments thereof are not limited thereto.

[0077] The second side surface insulating layer 170 can be disposed to have a (substantially) uniform side surface thickness ta from the upper end to the lower end, and the side surface thickness ta can be (substantially) equal to or greater than the thickness of the first side surface insulating layer 160. In some embodiments, the side surface thickness ta can be less than the thickness of the interlayer insulating layer 120. The second side surface insulating layer 170 can include the same material as the material of the upper side surface insulating layer 175 of the upper contact structure CS1 and can have the same thickness ta, and the level of the upper end can be (substantially) the same.

[0078] The first side surface insulating layer 160 can include an insulating material, such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second side surface insulating layer 170 can include an ALD insulating layer, such as the upper side surface insulating layer 175, and can include silicon oxide, undoped polysilicon, and / or silicon nitride. Even when the first side surface insulating layer 160 and the second side surface insulating layer 170 include the same material, the second side surface insulating layer 170 can have a lower density than the first side surface insulating layer 160 depending on the formation process. As described above, the first side surface insulating layer 160, the second side surface insulating layer 170, and the word line contact plug MC2 can be referred to as a word line contact structure CS2, but example embodiments thereof are not limited thereto. The first side surface insulating layer 160 and the second side surface insulating layer 170 can electrically insulate the gate electrodes 130 adjacent to the word line contact plug MC2 by extending around (e.g., surrounding) the side surfaces of the word line contact plug MC2. The word line contact plug MC2 can be in physical and electrical contact with the contact area of the assigned gate electrode 130 through the exposed lower surface of the word line contact plug MC2. For example, at least a portion of the side surfaces of the word line contact plug MC2 can be spaced apart from the gate electrodes 130 by the first side surface insulating layer 160 and the second side surface insulating layer 170, and the lower surface of the word line contact plug MC2 can be in contact with the gate electrodes 130.

[0079] In the extension region R2, as the word line contact plugs MC2 are assigned (electrically) one by one to the memory gate electrodes 130M and the lower gate electrodes 130L, the word line contact plugs MC2 can be disposed at different lengths so as to be (electrically) connected to different levels of the gate electrodes 130 (e.g., the memory gate electrodes 130M and the lower gate electrodes 130L).

[0080] In FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C , it is shown that each of the first to third stack structures GS1 to GS3 can include 8 steps of gate electrodes 130, and since the 8 gate electrodes 130 at the upper portion of the first to third stack structures GS1 to GS3 are upper gate electrodes 130U, 17 gate electrodes 130 (e.g., the memory gate electrodes 130M and the lower gate electrodes 130L) can be reserved. The word line contact plugs MC2 can be disposed in the extension region R2, the lengths of which are adjusted differently to be in contact with the upper surfaces of the 17 gate electrodes 130 (e.g., the memory gate electrodes 130M and the lower gate electrodes 130L).

[0081] The arrangement of the word line contact plugs MC2 can vary, and in example embodiments, as FIG. 1As illustrated, it is shown that the gate electrodes 130 can be arranged such that the gate electrodes 130 can be lowered by one level in a vertical direction (e.g., Z direction) in the second horizontal direction (e.g., Y direction) in the column and can respectively contact the assigned gate electrodes 130. Thus, as FIG. 2A As illustrated, when the uppermost gate electrode 130 is referred to as a first gate electrode 130U7, the length of the word line contact plug MC2 arranged in the first horizontal direction (e.g., X direction) in the vertical direction (e.g., Z direction) can be elongated so as to respectively contact the 9th, 12th, and 23rd gate electrodes 130. The elongation of the length of the word line contact plug MC2 in the Z direction can be defined as the level of the upper surface can be the same and the level of the lower surface can be lowered.

[0082] As described above, the word line contact plug MC2 can be arranged to have a longer length in a direction away from the memory region R1 in the first horizontal direction (e.g., X direction), and the word line contact plug MC2 can be arranged to have a longer length downward in the second horizontal direction (e.g., Y direction), but example embodiments thereof are not limited thereto. For example, the word line contact plug MC2 can be arranged in a single row, and can be symmetrically arranged such that the length can increase toward the center. The word line contact plug MC2 disposed in the last row can include a dummy word line contact plug MC2, and can function as a support structure SH without performing the function of selecting an actual word line.

[0083] The upper contact plug MC1 and the word line contact plug MC2 can include the same conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), and / or an alloy thereof. For example, the conductive layer can include tungsten (W). The contact barrier layer can include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), and / or a combination thereof.

[0084] The cell region insulating layer 190 can be disposed to overlap or cover the stack structure GS, and in particular, the cell region insulating layer 190 can be disposed to overlap or cover the space in the upper contact region R3. The cell region insulating layer 190 can include, for example, an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride (e.g., can be formed therefrom).

[0085] A first upper insulating layer 192 and a second upper insulating layer 194 can be sequentially stacked on the cell region insulating layer 190 and the uppermost interlayer insulating layer 121.

[0086] The first upper insulating layer 192 can be provided to have a first thickness t1, can be penetrated by the contact plugs MC1 and MC2, can be penetrated by the upper side surface insulating layer 175, and can be penetrated by the second side surface insulating layer 170. The upper contact plug MC1, the word line contact plug MC2, the upper side surface insulating layer 175, and the second side surface insulating layer 170 can extend into the first upper insulating layer 192.

[0087] The second upper insulating layer 194 can be provided on the first upper insulating layer 192, and can be penetrated by the pillars 180a, 180b, and 180c on each of the contact plugs MC1 and MC2. For example, the first pillar 180a, the second pillar 180b, and the third pillar 180c can extend into the second upper insulating layer 194. The first upper insulating layer 192 and the second upper insulating layer 194 can include the same insulating material, but example embodiments thereof are not limited thereto, and the first upper insulating layer 192 and the second upper insulating layer 194 can include, for example, SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN. The first upper insulating layer 192 can be in direct contact with the outer side surfaces of the upper side surface insulating layer 175 and the second side surface insulating layer 170, and can include the same material as that of the upper side surface insulating layer 175 and the second side surface insulating layer 170. However, the first upper insulating layer 192 can be formed in a different manner from the upper side surface insulating layer 175 and the second side surface insulating layer 170, such that these layers can have different degrees of densification. Specifically, the upper side surface insulating layer 175 and the second side surface insulating layer 170 can be formed by an ALD method, and the first upper insulating layer 192 can be formed by a CVD (chemical vapor deposition) method, such that the degree of densification of the upper side surface insulating layer 175 and the second side surface insulating layer 170 can be lower than that of the first upper insulating layer 192.

[0088] The pillars 180a, 180b, and 180c and the cell interconnection line 185 can be provided. The pillars 180a, 180b, and 180c can include the first pillar 180a extending into (e.g., penetrating) the second upper insulating layer 194 in the upper contact region R3 and in contact with the upper surface of the upper contact plug MC1, and the second pillar 180b provided in the extension region R2, extending into (e.g., penetrating) the second upper insulating layer 194 and in contact with the upper surface of the word line contact plug MC2. The pillars 180a, 180b, and 180c can further include the third pillar 180c provided in the memory region R1, extending into (e.g., penetrating) both the first upper insulating layer 192 and the second upper insulating layer 194, connected to the channel pad 149 of the channel structure CH, and electrically connected to the channel layer 140.

[0089] The upper surfaces of the first and second pillars 180a and 180b can be located at the same level, and the lower surfaces of the first and second pillars 180a and 180b can be located at the same level. The upper surfaces of the first and second pillars 180a and 180b can be coplanar with each other. The lower surfaces of the first and second pillars 180a and 180b can be coplanar with each other. The first and second pillars 180a and 180b can be formed to have the same length (in the vertical direction), and can have inclined side surfaces having a width that decreases from the upper surface to the lower surface. The upper surfaces of the first and second pillars 180a and 180b can have the same upper surface width W2, and the upper surface width W2 of the first and second pillars 180a and 180b can be less than (smaller than) the upper surface width W1 of the first contact plug MC1, and can be (substantially) equal to or less than (smaller than) the lower surface width W3 of the first contact plug MC1. The upper surface width W2 of the first and second pillars 180a and 180b can be, for example, about 100 nm, but example embodiments thereof are not limited thereto.

[0090] The first and second pillars 180a and 180b can be electrically connected to the gate electrode 130 by the contact plugs MC1 and MC2, respectively, which are electrically connected to the lower surfaces thereof, respectively. Each of the pillars 180a, 180b, and 180c can have a plug shape, and each of the cell interconnection lines 185 can have a line shape, but example embodiments thereof are not limited thereto. The first and second pillars 180a and 180b can include the same material, and can include a metal. For example, they can include tungsten (W), copper (Cu), aluminum (Al), or the like.

[0091] The cell interconnection lines 185 can include a metal, such as tungsten (W), copper (Cu), aluminum (Al), or the like. An insulating layer can be further provided to cover the cell interconnection lines 185. The insulating layer can include an insulating material, such as SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN (for example, can be formed therefrom).

[0092] FIG. 4 to FIG. 7 is an enlarged cross-sectional view illustrating a semiconductor device according to an example embodiment.

[0093] FIG. 4 The semiconductor device 100a in FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C The semiconductor device 100 in

[0094] A width W1 of an upper surface of the upper contact plug MC1 can be greater than a width W3 of a lower surface, and the upper contact plug MC1 can have a slanted side surface whose width decreases toward the lower surface. An upper region of the side surface of the upper contact plug MC1 can be formed to be curved as the width can decrease rapidly. Accordingly, the side surface can include a curved region having an inflection point, and the curved region can be included in the upper region. The curved region of the upper contact plug MC1 can be disposed relatively close to the upper surface so that the side surface connected to an edge T curved from the upper surface can have the curved region. A slope of the upper contact plug MC1 can become more gradual downward.

[0095] An upper side surface insulating layer 175 extending around (e.g., surrounding) an upper region of a side surface of the upper contact plug MC1 can be provided. A thickness tb of an upper portion (in the first horizontal direction) of the upper side surface insulating layer 175 can be less than a thickness tc of a lower portion (in the first horizontal direction). The upper side surface insulating layer 175 can have a ring shape, and can include an inner side surface in contact with the upper contact plug MC1 and an outer side surface in contact with the first upper insulating layer 192 between an upper end and a lower end of the upper side surface insulating layer 175. A slope of the inner side surface and a slope of the outer side surface of the upper side surface insulating layer 175 can be different from each other. The outer side surface of the upper side surface insulating layer 175 can have a constant slope from the upper end to the lower end of the upper side surface insulating layer 175, and the inner side surface can have an inflection point whose slope changes from the upper end to the lower end of the upper side surface insulating layer 175. The inflection point of the inner side surface can be the same as the inflection point of the side surface of the upper contact plug MC1, and can be inclined from the inner side surface toward the outer side surface so that the thickness tb of the upper portion of the upper side surface insulating layer 175 can decrease. The width of the upper region of the upper contact plug MC1 can increase by the decrease of the thickness tb of the upper portion of the upper side surface insulating layer 175 so that the upper region (of the upper contact plug MC1) can have an expanded width. In FIG. 4 , shapes of the upper contact plug MC1 and the upper side surface insulating layer 175 can be modified. In some embodiments, shapes of the word line contact plug MC2 and an upper portion of the second side surface insulating layer 170 can be formed to include a curved region (substantially) the same as or similar to the curved region as shown in FIG. 4 .

[0096] FIG. 5 The semiconductor device 100b in FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C can be (substantially) the same as or similar to the semiconductor device 100 in . Shapes of the upper contact structure CS1 can be a main difference.

[0097] The width W1 of the upper surface of the upper contact plug MC1 can be greater than the width W3 of the lower surface, and can have a slanted side surface in which the width decreases toward the lower surface, and can include an extension region having an expanded width Wa (in the first horizontal direction) in the upper region. The extension region of the upper contact plug MC1 can include a width Wa that extends from the width W1 of the upper surface of the upper contact plug MC1 to the edge by a predetermined distance. FIG. 3B

[0098] In the extension region of the upper contact plug MC1, the side surface of the upper contact plug MC1 can be in direct contact with the first upper insulating layer 192 by a first length d1. The side surface of the upper contact plug MC1 can include a curved region having a linear slope of the first length d1 and a width that rapidly decreases below the first length d1. The curved region can be continuously disposed with the extension region, and can be disposed in the upper region of the side surface of the upper contact plug MC1.

[0099] The upper side surface insulating layer 175 that extends around (e.g., surrounds) the upper region of the side surface of the upper contact plug MC1 can be disposed on (in) the curved region of the upper contact plug MC1. The upper side surface insulating layer 175 can have a thickness that increases from the upper end to the lower end. The upper side surface insulating layer 175 can have a ring shape, and can include an inner side surface that is in contact with the upper contact plug MC1 between the upper end and the lower end, and an outer side surface that is in contact with the first upper insulating layer 192, and the slope of the inner side surface and the slope of the outer side surface can be different from each other. The outer side surface of the upper side surface insulating layer 175 can have a constant slope downward, and the slope of the outer side surface can be continuous with the slope of the side surface of the extension region. The inner side surface of the upper side surface insulating layer 175 can have an inflection point in which the slope can change from the upper end to the lower end. The inflection point of the inner side surface can be the same as the inflection point of the side surface of the upper contact plug MC1, and the inner side surface and the outer side surface of the upper side surface insulating layer 175 can intersect as a line at the upper end, and the thickness can start from 0 and can gradually increase toward the lower surface. The width of the upper region of the upper contact plug MC1 can increase by the decrease in the thickness of the upper portion of the upper side surface insulating layer 175, and the upper side surface insulating layer 175 can not exist in the uppermost region of the upper contact plug MC1, and the extension region in which the first upper insulating layer 192 and the side surface of the upper contact plug MC1 are in direct contact with each other can be disposed.

[0100] ​Accordingly, the upper end of the upper side surface insulating layer 175 can be disposed at a level lower than a level of the upper surface of the upper contact plug MC1, and the lower end can be disposed at a level higher than a level of the lower surface of the upper contact plug MC1. In some embodiments, the lower end of the upper side surface insulating layer 175 can be coplanar with the lower surface of the first upper insulating layer 192. The length t2 of the upper side surface insulating layer 175 in the Z-direction can be less than (smaller than) the first thickness t1 of the first upper insulating layer 192. In FIG. 5 , the shape of the upper contact plug MC1 and the upper side surface insulating layer 175 can be modified, and the shape of the upper portion of the word line contact plug MC2 and the second side surface insulating layer 170 can also be formed to include an extended region and a curved region as shown in FIG. 5 .

[0101] FIG. 6 The semiconductor device 100c in FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C can be substantially the same or similar to the semiconductor device 100 in . The shape of the word line contact structure CS2 can be the main difference.

[0102] FIG. 6 The word line contact plug MC2 in FIG. 3C may include an upper region having an extended width W6 in the upper region. The extended width W6 of the upper surface of the word line contact plug MC2 can be greater than the width W4 of the upper surface in . The upper region can have a width that decreases downward, and the lower end of the upper region and the upper end of the lower region connected below the upper region can have different widths. Accordingly, a curved portion Sa including the lower end of the upper region can have a width greater than the width W5 of the upper end of the lower region, and the curved portion Sa can be located at a level (substantially) similar to the level of the lower surface of the first upper insulating layer 192. In some embodiments, the curved portion Sa can be higher than the lower surface of the first upper insulating layer 192 by the thickness of the second side surface insulating layer 170.

[0103] The width of the lower region of the word line contact plug MC2 can decrease from the upper end (of the lower region) of the word line contact plug MC2 to the lower surface, and the width can decrease uniformly.

[0104] By having the extended width W6 in the upper region of the word line contact plug MC2, misalignment with the pillar 180b in the upper portion can be reduced (e.g., prevented).

[0105] The second side surface insulating layer 170 can be formed to be bent along the side surface of the word line contact plug MC2 having a curved portion Sa. Even when the second side surface insulating layer 170 is formed to be bent along the curved portion Sa of the word line contact plug MC2, the same thickness can be maintained. Therefore, the second side surface insulating layer 170 can be extended to the side surface of the lower region of the second side surface insulating layer 170 by bending from the upper end of the second side surface insulating layer 170, which is coplanar with the first upper insulating layer 192, along the side surface of the word line contact plug MC2.

[0106] The first side surface insulating layer 160 can be disposed below the bent portion Sa, that is, between the lower region of the word line contact plug MC2 and the stack structure GS. Therefore, the upper end of the first side surface insulating layer 160 can be separated from the bent portion Sa by the second side surface insulating layer 170, and the first side surface insulating layer 160 can extend without surrounding the bent portion Sa and the extension region (the upper part of the word line contact plug MC2).

[0107] FIG. 7 The semiconductor device 100d in the middle can be with FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C The semiconductor devices 100 in the middle are (substantially) the same or similar. The shapes of the blocking insulating layer 177 and the upper surface insulating layer 175 may be the main differences.

[0108] FIG. 7 The semiconductor device 100d may also include a blocking insulating layer 177 between the first upper insulating layer 192 and the second upper insulating layer 194.

[0109] The blocking insulating layer 177 can be configured to protect the first upper insulating layer 192, the second side surface insulating layer 170, and the upper side surface insulating layer 175 from the lower surface etch-back process of the first side surface insulating layer 160 and the second side surface insulating layer 170 and the upper side surface insulating layer 175 on the lower surface of each contact hole. The blocking insulating layer 177 may include, for example, a carbide layer and / or a nitride layer, but its exemplary embodiments are not limited thereto.

[0110] The blocking insulation layer 177 can be configured to expose the upper ends of each of the contact structures MC1 and MC2. The lower surface of the blocking insulation layer 177 can contact the second side surface insulation layer 170 and the upper side surface insulation layer 175.

[0111] The blocking insulating layer 177 can be disposed between the first upper insulating layer 192 and the second upper insulating layer 194, can be a different material from the first upper insulating layer 192 and the second upper insulating layer 194, and can have a thickness (substantially) less than (smaller than) the thickness of each of the first upper insulating layer 192 and the second upper insulating layer 194.

[0112] Hereinafter, a semiconductor device according to an example embodiment will be described with reference to FIG. 8 to FIG. 10 A semiconductor device according to an example embodiment will be described.

[0113] Referring to FIG. 8 , the semiconductor device 100e can be (substantially) the same as or similar to the semiconductor device 100 in FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C . The structure of the upper gate electrode 130U can be the main difference.

[0114] The upper gate electrode 130U can include a pad region GP to be in contact with the upper contact plug MC1 in the first upper contact region R3a, and can include a step difference structure having a stepped shape such that the pad region GP can be exposed.

[0115] When seven upper gate electrodes 130U1-130U7 are assigned, the seven upper gate electrodes 130U1-130U7 can have a stepped shape of a step difference structure, the length of which increases downward. Accordingly, a pseudo step difference structure having a stepped shape can also be formed in the second upper contact region R3b on the opposite side (in the first horizontal direction). The pseudo step difference structure of the second upper contact region R3b on the opposite side can have a stepped shape, the length of which can be shortened upward. The step width of the pseudo step difference structure of the second upper contact region R3b and the step width of the step difference structure of the first upper contact region R3a can be different from each other. For example, the step width of the pseudo step difference structure of the second upper contact region R3b can be narrower than the step width of the step difference structure of the upper contact region R3a, and can be asymmetric with respect to the buffer region SP (in the first horizontal direction).

[0116] FIG. 9 The semiconductor device 100f in FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3Csemiconductor device 100 in FIG. 1A can be configured as a first semiconductor structure S1, and a second semiconductor structure S2 can be configured as a peripheral circuit structure below the first semiconductor structure S1. The first semiconductor structure S1 can be stacked on the second semiconductor structure S2. Specifically, the first semiconductor structure S1 can be disposed in an upper portion with respect to the second semiconductor structure S2 in the Z-direction. In an example embodiment, the second semiconductor structure S2 can be disposed on an upper portion of the first semiconductor structure S1. For example, FIG. 1 、 FIG. 2A 、 FIG. 2B 、 FIG. 3A 、 FIG. 3B and FIG. 3C An upper portion (e.g., an upper surface) of the first semiconductor structure S1 as shown in FIG. 1A can face downward in the Z-direction. FIG. 9

[0117] The first semiconductor structure S1 can further include a bonding structure. Specifically, a first bonding via 195, a first bonding metal layer 198, and a first bonding insulating layer 199 can form a first bonding structure of the first semiconductor structure S1. The first bonding via 195 can be disposed on the cell interconnect line 185, and the first bonding metal layer 198 can be (electrically) connected to the first bonding via 195. The first bonding metal layer 198 can have an upper surface that is exposed to an upper surface of the first semiconductor structure S1. The first bonding metal layer 198 can be bonded to and (electrically) connected to a second bonding metal layer 298 of the second semiconductor structure S2. The first bonding via 195 and the first bonding metal layer 198 can include an electrically conductive material, such as copper (Cu). The first bonding insulating layer 199 can form a dielectric-dielectric bond with a second bonding insulating layer 299 of the second semiconductor structure S2.

[0118] The second semiconductor structure S2 can include a substrate 201, a source / drain region 205 in the substrate 201, and a device isolation layer 210, a circuit device 220 disposed on (in) the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270, a circuit interconnect line 280, a second bonding via 295, and a second bonding metal layer 298.

[0119] The substrate 201 can have a lower surface that extends in the X-direction and the Y-direction. An active region can be defined by the device isolation layer 210 in the substrate 201. A portion of the active region can have the source / drain region 205 including impurities disposed therein. The substrate 201 can include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, and / or a Group II-VI compound semiconductor. The substrate 201 can be provided as a bulk wafer or an epitaxial layer.

[0120] ​The circuit devices 220 can include planar transistors. Each of the circuit devices 220 can include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The source / drain regions 205 can be disposed as source / drain regions in the substrate 201 on both sides (e.g., opposite sides) of the circuit gate electrode 225.

[0121] The peripheral region insulating layer 290 can be disposed on the circuit devices 220 on the upper surface of the substrate 201 (to cover or overlap the circuit devices 220 on the upper surface of the substrate 201). The peripheral region insulating layer 290 can include multiple insulating layers formed by different processes. The peripheral region insulating layer 290 can include (e.g., can be formed of) an insulating material. A portion of the peripheral region insulating layer 290 can function as the second bonding insulating layer 299.

[0122] The circuit contact plug 270 and the circuit interconnect line 280 can form a circuit interconnect structure electrically connected to the circuit devices 220 and the source / drain regions 205. The circuit contact plug 270 can have a cylindrical shape, and the circuit interconnect line 280 can have a line shape. An electrical signal can be applied to the circuit devices 220 through the circuit contact plug 270 and the circuit interconnect line 280. In a region not shown, the circuit contact plug 270 can also be (electrically) connected to the circuit gate electrode 225. The circuit interconnect line 280 can be (electrically) connected to the circuit contact plug 270 and can be disposed in multiple layers. The circuit contact plug 270 and the circuit interconnect line 280 can include an electrically conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc., and each component can also include a diffusion barrier. In an example embodiment, the number of layers of the circuit contact plug 270 and the circuit interconnect line 280 can vary.

[0123] The second bonding via 295, the second bonding metal layer 298, and the second bonding insulating layer 299 included in the second semiconductor structure S2 can be disposed on a portion of the uppermost part of the circuit interconnect line 280. The second bonding via 295 can have a cylindrical shape, and the second bonding metal layer 298 can have a pad shape having a circular shape or a relatively short line shape in a planar view. An upper surface of the second bonding metal layer 298 can be exposed to an upper surface of the second semiconductor structure S2. The second bonding via 295 and the second bonding metal layer 298 can provide an electrical connection path with the first semiconductor structure S1. In an example embodiment, a portion of the second bonding metal layer 298 can be disposed only for bonding without being (electrically) connected to the circuit interconnect line 280. The second bonding via 295 and the second bonding metal layer 298 can include an electrically conductive material, such as copper (Cu).

[0124] The second bonding insulating layer 299 can be defined as having a predetermined thickness from the upper surface of the peripheral region insulating layer 290, but can also be implemented as another insulating layer on the upper surface of the peripheral region insulating layer 290. The second bonding insulating layer 299 can provide for dielectric-dielectric bonding with the first bonding insulating layer 199 of the first semiconductor structure S1. The second bonding insulating layer 299 can also serve as a diffusion barrier for the second bonding metal layer 298, and can include, for example, SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN.

[0125] The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded to each other by bonding between the first bonding metal layer 198 and the second bonding metal layer 298 and by bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299. The bonding between the first bonding metal layer 198 and the second bonding metal layer 298 can be, for example, a metal-metal bond, such as a copper (Cu)-copper (Cu) bond, and the bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299 can be, for example, a dielectric-dielectric bond, such as a SiCN-SiCN bond. The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded to each other by a hybrid bond including a metal-metal bond and a dielectric-dielectric bond.

[0126] The first semiconductor structure S1 and the second semiconductor structure S2 can be packaged in a form in which the first semiconductor structure S1 can be located on top, as shown in FIG. 9 In some embodiments, the first semiconductor structure S1 and the second semiconductor structure S2 can be packaged upside down in a form in which the second semiconductor structure S2 can be located on top.

[0127] Referring to FIG. 10 , the semiconductor device 100g can include a first semiconductor structure S1 and a second semiconductor structure S2 below the first semiconductor structure S1. The first semiconductor structure S1 can include a memory cell region, and the second semiconductor structure S2 can include a peripheral circuit region. In some example embodiments, the second semiconductor structure S2 can be disposed on the first semiconductor structure S1.

[0128] With respect to the first semiconductor structure S1, the descriptions described with reference to FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B and FIG. 3C may be applied. However, the first semiconductor structure S1 can also include the first horizontal conductive layer 102 and the second horizontal conductive layer 104, the horizontal insulating layer 110, and the substrate insulating layer 122.

[0129] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be stacked in order and can be disposed on the upper surface of the conductive layer 101 in the first region R1. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can form a common source structure with the conductive layer 101 and can function as a common source line of the semiconductor device 100g. The first horizontal conductive layer 102 can be directly connected to the channel layer 140 at a lower portion of the channel structure CH. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can include a semiconductor material, such as polysilicon. In this case, at least the first horizontal conductive layer 102 can be doped with an impurity having the same conductivity as that of the conductive layer 101.

[0130] The horizontal insulating layer 110 can be disposed on the conductive layer 101 at the same level as the first horizontal conductive layer 102 in at least a portion of the upper contact region R3 and the extension region R2. The horizontal insulating layer 110 can include first and second horizontal insulating layers alternately stacked on the conductive layer 101. The horizontal insulating layer 110 can be a layer remaining after a portion thereof is replaced with the first horizontal conductive layer 102 in a process of manufacturing the semiconductor device 100g. The horizontal insulating layer 110 can include, for example, silicon oxide, silicon nitride, silicon carbide, and / or silicon oxynitride. The first and second horizontal insulating layers can include different insulating materials.

[0131] The substrate insulating layer 122 can be disposed to overlap (e.g., cover) a curved portion of the second horizontal conductive layer 104 between the memory region R1 and the upper contact region R3. In some example embodiments, when including a penetrating electrode extending from the first semiconductor structure S1 to the second semiconductor structure S2, the substrate insulating layer 122 can penetrate the conductive layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104, and the penetrating electrode can penetrate the substrate insulating layer 122. The substrate insulating layer 122 can include an insulating material, such as silicon oxide, silicon nitride, silicon carbide, and / or silicon oxynitride.

[0132] FIG. 10 The configuration of the second semiconductor structure S2 in FIG. 9 may be the same as the configuration of the second semiconductor structure S2 in

[0133] FIG. 11A , FIG. 11B , FIG. 11C and FIG. 11D are cross-sectional views illustrating a semiconductor device according to an example embodiment.

[0134] FIG. 11A , FIG. 11B ,FIG. 11C and FIG. 11D is a cross-sectional view showing a semiconductor device according to an example embodiment, showing a cross-sectional surface corresponding to FIG. 2A .

[0135] Referring to FIG. 11A , sacrificial insulating layers 118 and interlayer insulating layers 120 can be alternately stacked on a base substrate SUB, and a topmost interlayer insulating layer 121 can be formed. Vertical sacrificial structures 116 extending into (e.g., penetrating) mold encapsulation structures MS (e.g., mold encapsulation structures MSI-MS3) can be formed, and a cell region insulating layer 190 can be formed.

[0136] The base substrate SUB can be configured as a semiconductor substrate, such as a silicon (Si) wafer, and can be removed by a subsequent process. A first mold encapsulation structure MSI of the mold encapsulation structures MSI-MS3 can be formed first, and a high aspect ratio contact (HARC) etch can be performed to penetrate the structure, a portion of the vertical sacrificial structures 116 can be formed, a second mold encapsulation structure MS2 can be formed, a HARC etch can be performed to extend into (e.g., penetrate) the structure, and a portion of the vertical sacrificial structures 116 can be formed. In (substantially) the same manner, a third mold encapsulation structure MS3 and a portion of the vertical sacrificial structures 116 can be formed.

[0137] The sacrificial insulating layers 118 can be replaced with gate electrodes 130 by a subsequent process (or series of subsequent processes) (see FIG. 2A ). The sacrificial insulating layers 118 can include (e.g., be formed from) a material different from that of the interlayer insulating layers 120, and can include (e.g., be formed from) a material that etches with etch selectivity under certain etching conditions relative to the interlayer insulating layers 120. For example, the interlayer insulating layers 120 can include (e.g., be formed from) silicon oxide and / or silicon nitride, and the sacrificial insulating layers 118 can include (e.g., be formed from) a material other than that of the interlayer insulating layers 120, such as silicon, silicon oxide, silicon carbide, and / or silicon nitride. In example embodiments, the thicknesses of the interlayer insulating layers 120 can not be the same, and the thickness of the topmost interlayer insulating layer 121 can be greater than that of the other interlayer insulating layers 120. The thicknesses of the interlayer insulating layers 120 and the sacrificial insulating layers 118, and the number of films included therein, can vary from the example shown.

[0138] The vertical sacrificial structures 116 can be formed in a mold encapsulation structure MS (e.g., mold encapsulation structure MSI) by a subsequent process (or series of subsequent processes) (see FIG. 2AThe vertical sacrificial structures 116 can be formed, for example, to have the same size as the size of the channel structures CH, the dummy channel structures DH, and the support structures SH. The vertical sacrificial structures 116 can include, for example, carbon (C), but example embodiments thereof are not limited thereto.

[0139] When the third mold seal structure MS3 is formed, a stepped etching for a stepped difference structure of a staircase shape corresponding to the first upper contact region R3a and the second upper contact region R3b can be performed in the upper contact region R3. Accordingly, the uppermost interlayer insulating layer 121 corresponding to the seventh gate electrode (for example, 130U1) to the sacrificial insulating layer 118 can be etched in order, and a staircase shape can be formed. FIG. 2A

[0140] When the stepped difference structure of the staircase shape is formed, the cell region insulating layer 190 can be formed on the staircase shape. In some embodiments, an upper surface of the cell region insulating layer 190 can be coplanar with an upper surface of the uppermost interlayer insulating layer 121.

[0141] Referring to FIG. 11B A mask layer can be formed on the uppermost interlayer insulating layer 121, and accordingly, a contact sacrificial layer 129 for forming the word line contact plug MC2 can be formed.

[0142] Specifically, a contact hole for reaching an assigned gate electrode (corresponding sacrificial insulating layer 118) of each word line contact plug MC2 can be formed by etching a plurality of times. Regarding the formation of the contact hole, the number of etching times and the etching order can be differently applied according to the level of the assigned gate electrode 130.

[0143] For example, when the total number of layers of the entire gate electrode 130 is defined as N, and is converted into binary, the contact etching can be performed as many times as the number of binary digits. The contact etching can be performed at different depths according to the number of converted binary digits. For example, in the contact etching corresponding to the first digit, the sacrificial insulating layer 118 and the interlayer insulating layer 120 corresponding to one gate electrode (2 0 ) can be etched, in the contact etching corresponding to the second digit, the sacrificial insulating layer 118 and the interlayer insulating layer 120 corresponding to two gate electrodes (2 1 ) can be etched at the same time. In the contact etching corresponding to the third digit, the sacrificial insulating layer 118 and the interlayer insulating layer 120 corresponding to four gate electrodes (2 2 ) can be etched, and in the contact etching corresponding to the fourth digit, the sacrificial insulating layer 118 and the interlayer insulating layer 120 corresponding to eight gate electrodes (2 3 ​) corresponding to the sacrificial insulating layers 118 and the interlayer insulating layers 120, the contact etching corresponding to the fifth digit can etch the sacrificial insulating layers 118 and the interlayer insulating layers 120 corresponding to 16 gate electrodes (2 4 ) corresponding to the sacrificial insulating layers 118 and the interlayer insulating layers 120. The number of layers of each gate electrode 130 assigned can be converted into a binary number, and the contact etching corresponding to the number of digits having 1 in the converted binary number can be applied, so that the contact holes can be formed at different depths.

[0144] Therefore, by differently applying the contact etching corresponding to the number of digits of the binary number to the contact holes, only etching corresponding to the number of digits in the binary number can be performed, and the contact holes having different depths, which can open each of the gate electrodes 130 having a relatively large number of layers, can be formed.

[0145] As FIG. 11B indicated, a preliminary contact insulating layer 160P and a contact sacrificial layer 129 can be formed in each of the contact holes.

[0146] The preliminary contact insulating layer 160P can be conformally formed to cover the sidewalls and the lower surface (e.g., the bottom surface) of each of the contact holes. For example, the preliminary contact insulating layer 160P can be formed using a chemical vapor deposition (CVD) process.

[0147] The contact sacrificial layer 129 can be formed to fill each of the contact holes on the preliminary contact insulating layer 160P. The contact sacrificial layer 129 can include a different material from the preliminary contact insulating layer 160P, and can include, for example, carbon (C). The upper end of the contact sacrificial layer 129 and the preliminary contact insulating layer 160P can be formed to be coplanar with the uppermost interlayer insulating layer 121.

[0148] Referring FIG. 11C , a portion of the vertical sacrificial structures 116 can be removed, and a channel structure CH and a dummy channel structure DH can be formed.

[0149] A mask layer exposing only regions corresponding to the channel structure CH and regions corresponding to the dummy channel structure DH in the memory region R1 and in the upper contact region R3 can be formed, and a channel hole can be formed by removing the exposed vertical sacrificial structure 116. At least a portion of the channel dielectric layer 145, the channel layer 140, the buried insulating layer 147, and the channel pad 149 can be sequentially deposited in the channel hole, thereby forming the channel structure CH and / or the dummy channel structure DH.

[0150] The channel dielectric layer 145 can be formed to have a uniform thickness using an ALD and / or CVD process. In this process, the channel dielectric layer 145 can be formed completely or partially, and can extend vertically along the channel structure CH to a portion of the conductive layer 101 in this process. The channel layer 140 can be formed on the channel dielectric layer 145 in the channel hole. The buried insulating layer 147 can be formed to fill the channel hole, and can include (can be) an insulating material. The channel pad 149 can include (may be formed of) a conductive material, for example, the channel pad 149 can include polysilicon (may be formed of).

[0151] In addition, a portion of the vertical sacrificial structure 116 can be removed, and a pre-support structure can be formed.

[0152] A mask layer can be formed to expose the upper contact region R3 and a region of the extension region R2 corresponding to the support structure SH, and a dummy hole can be formed by removing the exposed vertical sacrificial structure 116. A process of expanding the dummy hole by removing a portion of the mold encapsulation structure MS around the dummy hole can be performed. The support structure SH can be formed by filling the expanded dummy hole with an insulating material.

[0153] Reference FIG. 11D The sacrificial insulating layer 118 can be removed and the gate electrode 130 can be formed.

[0154] An opening can be formed for opening a region corresponding to the isolation region MS in the FIG. 1 and FIG. 2B The isolation opening can be formed by forming a plurality of vertical holes in a region in which the isolation region MS is formed, expanding the plurality of vertical holes by a cleaning process, and connecting the holes with adjacent vertical holes. When the isolation opening is formed by expanding the plurality of vertical holes, a side surface of the isolation opening can continuously include a convex surface, but example embodiments thereof are not limited thereto.

[0155] The sacrificial insulating layer 118 exposed through the isolation opening can be removed. The sacrificial insulating layer 118 can be selectively removed with respect to the interlayer insulating layer 120, the channel structure CH, the dummy channel structure DH, the support structure SH, and the pre-contact insulating layer 160P, for example, using a wet etching.

[0156] The gate electrode 130 can be formed by depositing a conductive material on a region in which the sacrificial insulating layer 118 has been removed. The conductive material can include, for example, a metal, polysilicon, and / or a metal silicide material. The diffusion barrier layer 132 (see FIG. 3A) can be formed in the gate electrode 130, and the gate electrode 130 can be formed by depositing a layer of conductive material 135. In some example embodiments, a portion of the channel dielectric layer 145 can be formed prior to forming the gate electrode 130. Thus, the stack structure GS including the first stack structure GS1 to the third stack structure GS3 can be formed. After forming the gate electrode 130, the isolation region MS extending in the X direction as shown in FIG. 1B can be formed by depositing an insulating material in the isolation opening. FIG. 1

[0157] In this case, the insulating region SS extending into (e.g., penetrating) the upper gate electrode 130U can be formed. As shown in FIG. 1C, the trench for removing the upper gate electrode 130U and the interlayer insulating layer 120 in a region corresponding to the insulating region SS can be formed. FIG. 1 FIG. 2B

[0158] Between two adjacent isolation regions MS, a trench corresponding to the insulating region SS can be formed to selectively cut the upper portion of the third stack structure GS3 by penetrating the first upper gate electrode 130U1 to the seventh upper gate electrode 130U7 from the upper portion of the uppermost interlayer insulating layer 121 so as to extend in the X direction in the memory region R1 and the upper contact region R3. The trench can be formed in a wavy shape to extend while cutting a portion of the channel structure CH in the memory region R1, and can extend in a linear shape in the upper contact region R3.

[0159] As shown in FIG. 1D, the first upper insulating layer 192 can be formed, and the first opening OP1 and the second opening OP2 can be formed in a mask layer ML on the first upper insulating layer 192. FIG. 11E

[0160] First, the first upper insulating layer 192 can be formed by overlapping (e.g., covering) the upper surface of the uppermost interlayer insulating layer 121 and the cell region insulating layer 190. The first upper insulating layer 192 can be formed by depositing a first thickness t1, and can include an insulating material such as an oxide and / or a nitride (e.g., can be formed therefrom).

[0161] The mask layer ML can be formed on the first upper insulating layer 192, and the mask layer ML can be patterned by a photolithography process such that the first opening OP1 can be formed in a region corresponding to the upper contact plug MC1, and the second opening OP2 can be formed in a region corresponding to the word line contact plug MC2.

[0162] ​​​​The width of the second opening OP2 can be greater than the width of the first opening OP1, and the width of the second opening OP2 can be the same as the width W4 of the upper surface of the word line contact plug MC2 and the thickness ta of the second side surface insulating layer 170 extending around (e.g., around) the word line contact plug MC2. The width of the first opening OP1 can be the same as the sum of the width W1 of the upper surface of the upper contact plug MC1 and the thickness ta of the upper side surface insulating layer 175 extending around (e.g., around) the upper surface of the upper contact plug MC1. For example, the width of the second opening OP2 can be approximately 400 nm, and the width of the first opening OP1 can be approximately 200 nm, but the exemplary embodiments are not limited thereto.

[0163] As in FIG. 11F In the process, the first upper insulating layer 192 can be etched using the first opening OP1 and the second opening OP2, thereby forming the third opening OP3 and the fourth opening OP4, respectively.

[0164] The third opening OP3 can expose the upper surface of the lower unit region insulation layer 190 or the uppermost interlayer insulation layer 121 by removing the first upper insulation layer 192 via the first opening OP1.

[0165] The fourth opening OP4 can be formed by etching the first upper insulating layer 192 via the second opening OP2 and selectively removing the contact sacrificial layer 129 in the lower portion relative to the pre-contact insulating layer 160P. Therefore, the side and lower surfaces (e.g., bottom surfaces) of the pre-contact insulating layer 160P can be exposed to the fourth opening OP4.

[0166] refer to FIG. 11G A pre-side surface insulating layer 170P can be formed along the third opening OP3 and the fourth opening OP4. The pre-side surface insulating layer 170P can be uniformly topped with a thickness of (approximately) 400 Å to (approximately) 500 Å by atomic layer deposition (ALD).

[0167] The pre-side surface insulating layer 170P may include silicon oxide, silicon nitride, etc. (e.g., it may be formed therefrom), but its exemplary embodiments are not limited thereto, and various insulating materials that can be used in atomic layer deposition may be applied. By atomic layer deposition, an insulating layer with a greater thickness can be formed on the pre-contact insulating layer 160P in the fourth opening OP4, and insulating layers can also be formed on the side surface and lower surface (e.g., bottom surface) of the third opening OP3.

[0168] refer to FIG. 11HBy performing the etch-back process, the exposed pre-side surface insulation layer 170P and the exposed pre-contact insulation layer 160P of the fourth opening OP4 can be removed (e.g., the bottom surface), and the uppermost interlayer insulation layer 121 or the cell region insulation layer 190 can be removed through the lower surface (e.g., the bottom surface) of the pre-side surface insulation layer 170P of the third opening OP3.

[0169] Therefore, the pad region GP of the upper gate electrode 130U, which is allocated to the lower surface (e.g., bottom surface) of the third opening OP3, can be exposed, and the contact regions of the memory gate electrode 130M or lower gate electrode 130L, which are allocated to the lower surface (e.g., bottom surface) of the fourth opening OP4, can be exposed. In the etch-back process, the gate electrode 130 can be used as an etch stop layer, and anisotropic etching can be performed in the vertical direction by dry etching, so that the cell region insulating layer 190 below the third opening OP3 can be etched, so that the contact hole OP5 exposing the upper gate electrode 130U can be formed, and the contact hole OP6 can be formed by removing the exposed pre-side surface insulating layer 170P and the exposed pre-contact insulating layer 160P of the fourth opening OP4 (e.g., bottom surface).

[0170] In this case, the blocking layer 177P can be further formed on the upper part of the pre-side surface insulating layer 170P, specifically on the upper surface of the pre-side surface insulating layer 170P on the first upper insulating layer 192 at the same level as the substrate SUB. When the blocking layer 177P is formed as described above, it can prevent the pre-side surface insulating layer 170P in the upper region of the pre-side surface insulating layer 170P (i.e., the upper region of contact holes OP5 and OP6) from being partially lost during the etch-back process.

[0171] The blocking layer 177P can be formed by a polymer blocking process in a dry etching facility. A portion of it may be lost through a re-etching process, and the remaining blocking layer 177P can be removed by an ashing and stripping process.

[0172] When the blocking layer 177P is formed as a nitride film using a process other than the polymer blocking process in a dry etching facility, the layer can be as follows: FIG. 7 It can be retained as described above, and can be configured to block the insulating layer 177, but its example embodiments are not limited thereto.

[0173] refer to FIG. 11IContact plugs MC1 and MC2 can be formed by filling contact holes OP5 and OP6 and depositing conductive material. Contact plugs MC1 and MC2 can be physically connected to the gate electrode 130 distributed below them, respectively. When contact holes OP5 and OP6 are fully filled, the conductive material and pre-side surface insulating layer 170P can be etched by performing a planarization process until the upper surface of the first upper insulating layer 192 is exposed.

[0174] In this case, a planarization process can be performed by chemical mechanical polishing (CMP), so that the upper surface of the first upper insulating layer 192, the upper surfaces of the contact plugs MC1 and MC2, the upper end of the upper side surface insulating layer 175, and the upper end of the second side surface insulating layer 170 can be coplanar with each other.

[0175] refer to FIG. 11J Interconnect structures can be formed on the stacked structure GS.

[0176] A second upper insulating layer 194 can be formed on the first upper insulating layer 192, and pillars 180a, 180b and 180c and unit interconnects 185 can be formed thereon.

[0177] The first post 180a and the second post 180b can be formed by extending (e.g., penetrating) the second upper insulating layer 194 and exposing the post holes of the contact plugs MC1 and MC2, and filling the post holes with a conductive material. The third post 180c can be formed by extending (e.g., penetrating) the first upper insulating layer 192 and the second upper insulating layer 194 and exposing the post holes of the channel structure CH, and filling the post holes with a conductive material. Cell interconnects 185 can be formed on the posts 180a, 180b, and 180c. An insulating layer can be further formed on the cell interconnects 185, and a layer for connecting to... FIG. 9 The bonding structure is bonded to the second semiconductor structure (e.g., the second semiconductor structure S2).

[0178] refer to FIG. 11K It can remove the substrate SUB and expose the channel layer 140.

[0179] By removing a portion of the substrate SUB and the exposed channel dielectric layer 145 (see...) FIG. 3A ), which can expose the channel layer 140.

[0180] Subsequently, refer to FIG. 2A A conductive layer 101 can be formed that is connected to the channel layer 140, and it can be manufactured FIG. 2A The semiconductor device 100 is located within the channel structure CH. In some example embodiments, the conductive layer 101 may extend along the upper end of the channel structure CH. FIG. 11K (as shown) and the upper end of the pseudo-channel structure DH ( FIG. 11K(As shown in the figure) is formed as a conformal layer.

[0181] FIG. 12 This is a view illustrating a data storage system including semiconductor devices according to an example embodiment.

[0182] refer to FIG. 12 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or as an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, and / or a communication device including one or more semiconductor devices 1100.

[0183] Semiconductor device 1100 can be implemented as a non-volatile memory device, for example, reference FIG. 1 to FIG. 10 The NAND flash memory device described in the foregoing example embodiments. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In the example embodiment, the first structure 1100F may be disposed on the side of the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR disposed between the bit line BL and the common source line CSL.

[0184] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In the example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0185] In an example embodiment, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be configured as gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be configured as the gate electrode of a memory cell transistor MCT, and gate upper lines UL1 and UL2 may be configured as gate electrodes of upper transistors UT1 and UT2, respectively.

[0186] In an example embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series (electrically) with each other. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series (electrically) with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0187] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0188] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0189] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0190] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include controller interface 1221 for handling communication with semiconductor device 1100. Through controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be sent. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command. As used below, the terms “external / external configuration,” “external / external device,” “external / external power supply,” “external / external signal,” or “external” are intended to broadly refer to devices, circuits, blocks, modules, power supplies, and / or signals that reside externally (e.g., outside functional or physical boundaries) relative to a given circuit, block, module, system, or device.

[0191] FIG. 13 This is a perspective view illustrating a data storage system including semiconductor devices according to an example embodiment.

[0192] refer to FIG. 13 The data storage system 2000 in the example embodiment may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 (electrically) formed on the motherboard 2001.

[0193] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via, for example, Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), and / or M-Phy for Universal Flash Memory (UFS). In an example embodiment, the data storage system 2000 may operate via power supplied by the external host through the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0194] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0195] DRAM 2004 can be configured as a buffer memory to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can operate as a high-speed buffer memory and can provide space for temporary data storage during the control operation of the semiconductor package 2003. When the data storage system 2000 may include DRAM 2004, the controller 2002 may further include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003.

[0196] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 respectively disposed on the lower surface of the semiconductor chips 2200, connection structures 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and molding layers 2500 on the semiconductor chips 2200 and the connection structures 2400 on the package substrate 2100 (e.g., covering or overlapping the semiconductor chips 2200 and the connection structures 2400 on the package substrate 2100).

[0197] The package substrate 2100 can be configured as a printed circuit board including upper pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... FIG. 12 The input / output pads 1101 are included. Each of the semiconductor chips 2200 may include a stacked structure GS and a channel structure CH. Each of the semiconductor chips 2200 may include a reference. FIG. 1 to FIG. 10 The semiconductor device described in the foregoing example embodiments.

[0198] In an example embodiment, the connection structure 2400 can be configured to electrically connect the input / output pads 2210 to the bonding wires of the upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other via a bonding wire method and can be electrically connected to the upper pad 2130 of the package substrate 2100. In an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other via a connection structure 2400 that includes a through-electrode (TSV) instead of a bonding wire method.

[0199] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a different interposer substrate than the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be electrically connected to each other via interconnects formed on the interposer substrate.

[0200] According to the aforementioned example embodiment, since the upper gate electrode includes a string select electrode, the string select contact plug can be formed simultaneously with the word line select plug on the pad area of ​​each exposed string select gate electrode, while a stepped step difference structure is formed on the string select electrode. Furthermore, the pillars disposed on the upper portion can be formed simultaneously with the string select contact plugs on the word line select plugs. Therefore, it is not necessary to form pillars for the string select contact plugs separately, thus simplifying the process.

[0201] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Conductive layer; A stacked structure on the conductive layer, wherein the stacked structure includes a first region, a second region, and a third region between the first region and the second region in a first direction parallel to the upper surface of the conductive layer, wherein the stacked structure further includes a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked and spaced apart from each other in a second direction perpendicular to the upper surface of the conductive layer, and wherein some of the upper gate electrodes extend to different lengths from each other in the first direction in the third region, and each of the upper gate electrodes includes a pad region; An insulating layer is present on the stacked structure; A channel structure extends in the first region into the stacked structure in the second direction; A first contact plug extends into the insulating layer in the second direction, wherein the first contact plug is electrically connected in the third region to the pad regions of the upper gate electrodes, respectively; The second contact plug extends in the second direction into the upper gate electrode, into at least one of the memory gate electrode and the lower gate electrode, and into the insulating layer, wherein some of the second contact plugs extend to different lengths from each other in the second direction and are electrically connected to the lower gate electrode and / or the memory gate electrode, respectively, in the second region. A side-surface insulating structure extends around the side surface of each of the second contact plugs in the second region; as well as An upper surface insulating layer extends around the side surface of each of the first contact plugs in the third region.

2. The semiconductor device according to claim 1, wherein, The lower end of the upper surface insulating layer is coplanar with the upper surface of the stacked structure.

3. The semiconductor device according to claim 1, wherein, The upper surface of the first contact plug is coplanar with the upper surface of the second contact plug.

4. The semiconductor device according to claim 1, wherein, The first contact plug and the second contact plug are made of the same material.

5. The semiconductor device according to claim 1, wherein, The side surface insulation structure includes: A first side surface insulating layer is disposed between the side surfaces of the stacked structure and each of the second contact plugs; and A second side surface insulating layer is located between the first side surface insulating layer and the side surface of each of the second contact plugs. The lower ends of the first side surface insulating layer and the lower ends of the second side surface insulating layer are coplanar.

6. The semiconductor device according to claim 5, wherein, The upper end of the second side surface insulating layer is farther from the upper surface of the conductive layer in the second direction than the upper end of the first side surface insulating layer.

7. The semiconductor device according to claim 5, wherein, The upper end of the second side surface insulating layer and the upper surface of the second contact plug are coplanar.

8. The semiconductor device according to claim 5, wherein, The second side surface insulating layer and the upper side surface insulating layer comprise the same material.

9. The semiconductor device according to claim 5, wherein, The second side surface insulating layer and the first side surface insulating layer comprise the same material. The density of the second side surface insulating layer is different from the density of the first side surface insulating layer.

10. The semiconductor device according to claim 1, wherein, The insulating layer and the upper surface insulating layer are made of the same material. The density of the upper surface insulating layer is less than the density of the insulating layer.

11. The semiconductor device according to claim 1, wherein, The upper surface insulating layer includes an inner surface and an outer surface between the upper and lower ends of the upper surface insulating layer, and The slopes of the outer surface and the inner surface are different from each other.

12. The semiconductor device according to claim 11, wherein, The upper end of the upper surface insulating layer is closer to the upper surface of the conductive layer in the second direction than the upper surface of the first contact plug, and Wherein, the lower end of the upper surface insulating layer is farther from the upper surface of the conductive layer in the second direction than the lower surface of the first contact plug.

13. The semiconductor device according to claim 1, further comprising: The first post is on the corresponding upper surface of the first contact plug; as well as The second post is located on the corresponding upper surface of the second contact plug. Wherein, the upper surface of the first column is coplanar with the upper surface of the second column, and The lower surface of the first column is coplanar with the lower surface of the second column.

14. A semiconductor device, comprising: Conductive layer; A stacked structure on the conductive layer, wherein the stacked structure includes a first region, a second region, and a third region between the first region and the second region in a first direction parallel to the upper surface of the conductive layer, wherein the stacked structure further includes memory gate electrodes and upper gate electrodes stacked and spaced apart from each other in a second direction perpendicular to the upper surface of the conductive layer, and wherein some of the upper gate electrodes extend to different lengths from each other in the first direction in the third region, and each of the upper gate electrodes includes a pad region; An insulating layer is present on the stacked structure; An isolation region extends in the first direction into the upper gate electrode in the first region and the third region; A channel structure extends in the first region into the stacked structure in the second direction; A first contact structure extends into the insulating layer in the second direction, wherein the first contact structure is electrically connected in the third region to the pad regions of the upper gate electrodes, respectively; A second contact structure extends into at least one of the upper gate electrode, the insulating layer, and the memory gate electrode, wherein the second contact structure is electrically connected to the memory gate electrode in the second region, and wherein the respective upper surface of the second contact structure is coplanar with the respective upper surface of the first contact structure. The first pillar is located on the first contact structure; as well as The second column, on the second contact structure Wherein, the corresponding upper surface of the first column is coplanar with the corresponding upper surface of the second column, and The corresponding lower surface of the first column is coplanar with the corresponding lower surface of the second column.

15. The semiconductor device according to claim 14, wherein, Each of the first contact structures includes: A first contact plug, wherein the upper surface of the first contact plug is coplanar with the upper surface of the insulating layer, the lower surface of the first contact plug contacts one of the pad regions of the upper gate electrode, and a side surface of the first contact plug lies between the upper surface and the lower surface of the first contact plug; and An insulating layer on the upper surface extends around the side surface of the first contact plug.

16. The semiconductor device according to claim 15, wherein, Each of the second contact structures includes: The second contact plug has an upper surface that is coplanar with the upper surface of the first contact plug, a lower surface that contacts one of the memory gate electrodes, and a side surface that lies between the upper surface and the lower surface of the second contact plug. A first side surface insulating layer extends around the side surface of the second contact plug between the second contact plug and the stacked structure; and A second side surface insulating layer is located between the first side surface insulating layer and the second contact plug.

17. The semiconductor device according to claim 16, wherein, The upper surface insulating layer and the second surface insulating layer comprise the same material, and The upper end of the upper surface insulating layer is coplanar with the upper end of the second surface insulating layer.

18. The semiconductor device according to claim 14, wherein, The diameter of at least one of the respective upper surfaces of the first contact structure is smaller than the diameter of at least one of the upper surfaces of the second contact structure.

19. The semiconductor device according to claim 14, wherein, The diameter of at least one of the respective upper surfaces of the first column is equal to the diameter of at least one of the respective upper surfaces of the second column, and The first column and the second column are made of the same material.

20. A data storage system, comprising: A semiconductor memory device includes a first semiconductor structure comprising circuitry, a second semiconductor structure on the first semiconductor structure, and input / output pads electrically connected to the circuitry; and A controller, electrically connected to the semiconductor memory device via the input / output pads, wherein the controller is configured to control the semiconductor memory device. The second semiconductor structure includes: Conductive layer; A stacked structure on the conductive layer, wherein the stacked structure includes a first region, a second region, and a third region between the first region and the second region in a first direction parallel to the upper surface of the conductive layer, wherein the stacked structure further includes a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked and spaced apart from each other in a second direction perpendicular to the upper surface of the conductive layer, and wherein some of the upper gate electrodes extend to different lengths from each other in the first direction in the third region and include a pad region; An insulating layer is present on the stacked structure; A channel structure extends in the first region into the stacked structure in the second direction; A first contact plug extends into the insulating layer in the second direction, wherein the first contact plug is electrically connected to the pad region of the upper gate electrode in the third region; The second contact plug extends in the second direction into the upper gate electrode, into at least one of the memory gate electrode and the lower gate electrode, and into the insulating layer, wherein some of the second contact plugs extend to different lengths from each other in the second direction and are electrically connected to the lower gate electrode and / or the memory gate electrode, respectively, in the second region. A side-surface insulating structure extending around the side surface of each of the second contact plugs in the second region; and An upper surface insulating layer extends around the side surface of each of the first contact plugs in the third region.

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