Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The method comprises the steps of providing a substrate; forming a first bulge structure and a second bulge structure which are arranged at an interval on the substrate; an interlayer dielectric layer is formed to cover the first protrusion structure and the second protrusion structure, and the interlayer dielectric layer at the interval between the first protrusion structure and the second protrusion structure is provided with a recess towards the surface side of the substrate; a mask layer is formed on the interlayer dielectric layer, and the mask layer exposes the interlayer dielectric layer on the first protruding structure and the second protruding structure and shields the interlayer dielectric layer in other areas; and taking the mask layer as a mask, and etching to remove the exposed part of the interlayer dielectric layer so as to reduce the height difference between the top surface of the interlayer dielectric layer on the first convex structure and the bottom surface of the recess, and reduce the height difference between the top surface of the interlayer dielectric layer on the second convex structure and the bottom surface of the recess.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] The semiconductor device such as Insulated Gate Bipolar Transistor (IGBT) has advantages of unipolar device and bipolar device, and its driving circuit is simple, the control circuit has low power consumption and low cost, the on-state voltage drop is low, and the device itself has small loss, so it is widely used in power electronic systems.

[0003] In the related art, in the preparation process of IGBT, a protruding structure such as a gate electrode and a field plate is formed on a substrate. Subsequently, when depositing an interlayer dielectric layer, since the height of the gate electrode and the field plate is higher than the surface of the substrate, the height of the top surface of the interlayer dielectric layer on the gate electrode and the field plate (which can also be referred to as a Poly region) is significantly higher than the height of the top surface of the interlayer dielectric layer on the substrate surface (i.e., a non-Poly region) between the two, so that the interlayer dielectric layer at the non-Poly region position is recessed. Then, the interlayer dielectric layer is etched to form a via hole penetrating through the interlayer dielectric layer. In this etching process, the recess of the interlayer dielectric layer is etched to increase, resulting in a gap in the metal material layer formed by subsequent deposition. After entering the subsequent packaging process, it is usually necessary to coat polyimide (Polyimide, abbreviated as PI) as a protective layer, and the PI needs to be baked after coating. In the curing process, the air trapped in the gap of the metal material layer will be released into the PI during the curing process, and finally the gas will burst out of the PI layer, resulting in a small pit-shaped defect (Pit defect) on the surface of the PI, thereby affecting the appearance and reliability of the device. SUMMARY

[0004] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor to determine the protection scope of the claimed technical solution.

[0005] In view of the existing problems, the first aspect of the embodiment of the present application provides a preparation method of a semiconductor device, which comprises: providing a substrate; forming a first protruding structure and a second protruding structure arranged at intervals on the substrate; forming an interlayer dielectric layer to cover the first protruding structure and the second protruding structure, wherein the interlayer dielectric layer at the space between the first protruding structure and the second protruding structure has a recess towards the substrate surface side; forming a mask layer on the interlayer dielectric layer, the mask layer exposing the interlayer dielectric layer on the first protruding structure and the second protruding structure and shielding the interlayer dielectric layer in other areas, wherein a first photomask is used in a photolithography process during forming the first protruding structure and the second protruding structure, and a second photomask is used in a photolithography process during forming the mask layer, the light-shielding area in the second photomask corresponding to the light-transmitting area in the first photomask, and the light-transmitting area in the second photomask corresponding to the light-shielding area in the first photomask; using the mask layer as a mask, etching to remove the exposed part of the interlayer dielectric layer, so as to reduce the height difference between the top surface of the interlayer dielectric layer on the first protruding structure and the bottom surface of the recess, and reduce the height difference between the top surface of the interlayer dielectric layer on the second protruding structure and the bottom surface of the recess.

[0006] In some embodiments of the present application, the substrate includes a cell region and a terminal region, the first protruding structure includes a gate electrode formed on the substrate in the cell region, and a field oxide layer is further formed on the substrate in the terminal region, the second protruding structure includes a field plate covering the field oxide layer, and the method for forming the first protruding structure and the second protruding structure includes the following steps: forming a gate material layer on the substrate to cover the surface of the substrate and the field oxide layer; forming a first photoresist layer on the gate material layer; using the first photomask to perform photolithography on the first photoresist layer to form a patterned first photoresist layer, so as to cover the area of the gate material layer for forming the gate electrode and the area for forming the field plate, and expose other areas; using the patterned first photoresist layer as a mask to etch the gate material layer to form the gate electrode in the cell region and the field plate in the terminal region, wherein the field plate covers at least part of the field oxide, and the gate structure and the field plate are arranged in parallel to the surface of the substrate, the first protruding structure includes the gate electrode, and the second protruding structure includes the field plate.

[0007] In some embodiments of the present application, the mask layer includes a second photoresist layer, and the second photoresist layer and the first photoresist layer are the same type of photoresist, and forming the mask layer on the interlayer dielectric layer includes: forming a second photoresist layer on the interlayer dielectric layer; A second photo mask is used to perform photo-etching on the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer exposes the interlayer dielectric layer on the gate electrode and the field plate, and shields the interlayer dielectric layer in other areas, wherein the light-shielding area in the second photo mask corresponds to the light-transmitting area in the first photo mask, and the light-transmitting area in the second photo mask corresponds to the light-shielding area in the first photo mask.

[0008] In some embodiments of the present application, the method further comprises: etching part of the interlayer dielectric layer to form at least one first via, at least one second via and at least one third via in the interlayer dielectric layer, the first via penetrating through the interlayer dielectric layer and exposing part of the gate electrode, the second via penetrating through the interlayer dielectric layer and exposing part of the substrate between the gate electrode and the field plate, and the third via exposing part of the field plate; depositing a metal material layer to fill the first via, the second via and the third via to form a first conductive via, a second conductive via and a third conductive via respectively, and the metal material layer also covers the interlayer dielectric layer.

[0009] In some embodiments of the present application, the method further comprises: forming a protective layer to cover the metal material layer.

[0010] In some embodiments of the present application, forming a protective layer to cover the metal material layer comprises: forming a polyimide layer on the metal material layer as the protective layer; performing a curing bake on the polyimide layer.

[0011] In some embodiments of the present application, the target thickness of the part of the interlayer dielectric layer etched away is less than or equal to the thickness of the first protruding structure and / or the second protruding structure.

[0012] In some embodiments of the present application, etching away the exposed part of the interlayer dielectric layer with the mask layer as a mask comprises: performing dry etching on the interlayer dielectric layer for a predetermined time length to remove a target thickness of the interlayer dielectric layer, wherein the target thickness is equal to the thickness of the first protruding structure, and / or the target thickness is equal to the thickness of the second protruding structure.

[0013] In some embodiments of the present application, the top surface height of one of the first protruding structures is higher than the top surface height of the other one; and / or the thickness of the interlayer dielectric layer is greater than or equal to twice the thickness of the first protruding structure; and / or The thickness of the interlayer dielectric layer is greater than or equal to twice the thickness of the second protruding structure.

[0014] The second aspect of the embodiment of the present application provides a semiconductor device prepared by the preparation method of the semiconductor device.

[0015] According to the semiconductor device and the preparation method thereof, after the deposition of the interlayer dielectric layer, the second mask is introduced for the photolithography and etching process, which specifically solves the problem of uneven surface of the interlayer dielectric layer (ILD) caused by the first protruding structure and the second protruding structure. The process uses the second mask which is complementary to the mask pattern when the protruding structure is formed, to selectively etch the over-thick ILD layer on the protruding structure, thereby significantly reducing or even eliminating the height difference between the part of the interlayer dielectric layer above the protruding structure and the recessed area, realizing the local planarization of the ILD layer at the predetermined position, effectively reducing the overall surface undulation, providing a more planar surface for the subsequent process, thereby effectively inhibiting the problem of excessive etching of the ILD recess when forming the via, avoiding the generation of voids in the subsequently formed metal interconnection layer, and further reducing the possibility of air being trapped in the metal interconnection layer, so as to reduce the surface pit defects of the protective layer caused by the release of residual gas in the subsequent curing process of the protective layer. Therefore, the present application not only significantly improves the appearance yield of the device, but also greatly enhances the reliability of the product by eliminating potential process defects, so that the overall manufacturing process is more stable. BRIEF DESCRIPTION OF DRAWINGS

[0016] The following drawings of the present application are hereby incorporated as a part of the present application for the purpose of understanding the present application. The embodiments of the present application and the description thereof shown in the drawings are used to explain the principles of the present application.

[0017] In the drawings: Figures 1A-1E The cross-sectional schematic diagrams of each step of the preparation method of the semiconductor device in the related art are shown respectively; Figures 2A-2C The schematic diagrams of the PI layer of the semiconductor device with pit defects in the related art are shown respectively; Figure 3 The flowchart of the preparation method of the semiconductor device in one specific embodiment of the present application is shown; Figures 4A-4I The cross-sectional schematic diagrams of each step of the preparation method of the semiconductor device in one specific embodiment of the present application are shown. DETAILED DESCRIPTION

[0018] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon

[0019] It should be understood that the present application can be carried out in different forms without departing from the spirit or essential characteristics thereof. To that end, the present embodiments are to be considered in all respects as illustrative and not restrictive, and the scope of the application should be determined not with reference to the above description but with reference to the appended claims, along with their full scope of equivalents.

[0020] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0021] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] In the related art, the preparation process flow of IGBT is as shown in Figures 1A-1E As shown in Figure 1A , a substrate 100 is provided, the substrate 100 has a cell region and a termination region, wherein the termination region surrounds the cell region, a field oxide layer 110 is formed on the substrate 100 in the cell region, and a polysilicon layer 120 is deposited to cover the surface of the substrate 100 and the field oxide layer 110; then, as shown in Figure 1B , the polysilicon layer 120 is etched to form a gate electrode 121 on the substrate 100 in the cell region and form a field plate 122 in the termination region, wherein the field plate 122 covers at least part of the field oxide layer 110, and there is a gap between the field plate 122 and the gate electrode 121. After that, as shown in Figure 1C , an interlayer dielectric layer is deposited to cover the gate electrode 121 and the field plate 122, or also cover the exposed field oxide layer 110 when the field oxide layer 110 is partially exposed. During the deposition of the interlayer dielectric layer, since the height of the gate electrode 121 and the field plate 122 is higher than the surface of the substrate 100, the height of the top surface of the interlayer dielectric layer on the gate electrode 121 and the field plate 122 (which can also be referred to as the Poly region) is significantly higher than the height of the top surface of the interlayer dielectric layer on the surface of the substrate 100 (i.e. the non-Poly region) between them, so that the interlayer dielectric layer at the position of the non-Poly region presents a recess 1231. After that, as shown in Figure 1D , the interlayer dielectric layer is etched to form a first via, a second via and a third via penetrating through the interlayer dielectric layer, wherein the first via penetrates through the interlayer dielectric layer and exposes part of the surface of the gate electrode 121, the second via penetrates through the interlayer dielectric layer and exposes part of the surface of the substrate 100 between the gate electrode 121 and the field plate 122, and the third via exposes part of the surface of the field plate 122. After that, as shown in Figure 1EAs shown, the metal material layer fills the first via, the second via and the third via and covers the interlayer dielectric layer, wherein the metal material layer filling the first via, the second via and the third via forms the first conductive via 141, the second conductive via 142 and the third conductive via 143, and the metal material layer on the interlayer dielectric layer 130 serves as a metal interconnection layer 150. During the etching process, the recess 1231 of the interlayer dielectric layer is etched to increase, for example, as shown in Figure 1D As shown, the depth of the recess on the second conductive via 142 is also large, resulting in a gap in the metal material layer formed by subsequent deposition, as shown in Figure 2A After entering the subsequent packaging process, it is usually necessary to coat polyimide (PI) as a protective layer. After PI coating, baking is required. During the baking process, the air trapped in the gap of the metal material layer will be released into the PI during the baking process, and finally the gas will burst out of the PI layer, resulting in a small pit defect (Pit defect) left on the surface of the PI (as shown in the area enclosed by the rectangular frame in Figure 2B and Figure 2C , thereby affecting the appearance and reliability of the device.

[0024] Therefore, in view of the foregoing technical problems, the present application proposes a semiconductor device and a preparation method thereof, which are described as follows.

[0025] Embodiment One The embodiment of the present application also provides a preparation method of a semiconductor device, referring to Figure 3 The preparation method mainly includes the following steps: In S1, a substrate is provided; In S2, a first protruding structure and a second protruding structure are formed on the substrate in a spaced manner; In S3, an interlayer dielectric layer is formed to cover the first protruding structure and the second protruding structure, wherein the interlayer dielectric layer at the space between the first protruding structure and the second protruding structure has a recess towards the surface side of the substrate; In S4, a mask layer is formed on the interlayer dielectric layer, the mask layer exposes the interlayer dielectric layer on the first protruding structure and the second protruding structure, and shields the interlayer dielectric layer in other areas, wherein a first photomask is used for photolithography during the formation of the first protruding structure and the second protruding structure, a second photomask is used for photolithography during the formation of the mask layer, the light shielding area in the second photomask corresponds to the light transmission area in the first photomask, and the light transmission area in the second photomask corresponds to the light shielding area in the first photomask; In S5, the exposed part of the interlayer dielectric layer is etched away with the mask layer as a mask, so as to reduce the height difference between the top surface of the interlayer dielectric layer on the first protruding structure and the bottom surface of the recess, and reduce the height difference between the top surface of the interlayer dielectric layer on the second protruding structure and the bottom surface of the recess.

[0026] In the above scheme, by introducing a second mask for photolithography and etching process after the deposition of the interlayer dielectric layer, the problem of uneven surface of the interlayer dielectric layer (ILD) caused by the first protruding structure and the second protruding structure is solved. The process uses a second mask which is complementary to the mask pattern used when forming the protruding structure, to selectively etch the over-thick ILD layer on the protruding structure, thereby significantly reducing or even eliminating the height difference between the part of the interlayer dielectric layer above the protruding structure and the recessed area, achieving local planarization of the ILD layer at the predetermined position, effectively reducing the overall surface undulation, providing a more planar surface for subsequent processes, thereby effectively preventing the problem of excessive etching of the ILD recess when forming the via, avoiding the generation of voids in the subsequently formed metal interconnection layer, thereby reducing the possibility of air being trapped in the metal interconnection layer, and reducing the pit defects in the polyimide (PI) protective layer caused by the release of residual gas during the curing process of the polyimide (PI) protective layer. Therefore, the present application not only significantly improves the appearance yield of the device, but also greatly enhances the reliability of the product by eliminating potential process defects, making the overall manufacturing process more robust.

[0027] The above and other Figures 4A-4I The preparation method of the semiconductor device is described in detail.

[0028] First, referring to Figure 4A , a substrate 300 is provided. The substrate 300 can include a semiconductor base which can include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the semiconductor base can also include silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-on-silicon germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI) or germanium-on-insulator (GeOI) and the like. Although several examples of materials that can form the semiconductor base are described herein, any material that can serve as a semiconductor base falls within the scope of protection of the present application. In addition, the substrate 300 can be divided into an active region, and / or a doped well (not shown) can be formed in the substrate 300, and the like.

[0029] Next, referring to Figures 4A-4C , a first protruding structure and a second protruding structure are formed on the substrate 300.

[0030] The substrate 300 generally comprises a cell region and a termination region, wherein the termination region surrounds the periphery of the cell region. The cell region is integrated with gate, emitter and various well region structures as the core functional area of the device; the termination region is provided with field plate, floating field ring and other auxiliary structures for improving the voltage withstanding capability and working stability of the device. In addition, the collector of the IGBT is usually made on the other side surface of the substrate 300.

[0031] In the cell region, a first drift region is provided, in which a plurality of trench gate structures, P-well regions and N-well regions are distributed. The trench gate is composed of a polysilicon gate and a gate oxide layer around the polysilicon gate. It should be noted that, in addition to the trench gate, the gate of the IGBT can also adopt a planar gate structure. The planar gate structure is, for example, a gate structure formed on the surface of the substrate 300, which can include a gate dielectric layer and a gate electrode layer stacked from bottom to top.

[0032] The termination region is provided with a second drift region, in which a floating field ring and other doped regions are arranged, and functional elements such as field oxide and field plate are provided on the surface thereof.

[0033] Since such structures as the planar gate of the cell region, the field plate of the termination region, the temperature sensor of the termination region and the like protrude from the surface of the substrate 300 in topography, they are collectively classified as protruding structures in the present embodiment, wherein the first protruding structure can be the field plate 322 formed in the termination region, the second protruding structure can be the temperature sensor formed in the termination region, or the first protruding structure and the second protruding structure can be two adjacent gate electrodes 321 formed in the cell region. Hereinafter, the case of simultaneously integrating the field plate 322 of the termination region as the second protruding structure and the gate structure of the cell region as the second protruding structure will be mainly described.

[0034] In one specific example, the first protruding structure includes the gate electrode 321 formed on the substrate 300 in the cell region, and the field oxide layer 310 is further formed on the substrate 300 in the termination region, the second protruding structure includes the field plate 322 covering the field oxide layer, and the method for forming the first protruding structure and the second protruding structure comprises the following steps: As Figure 4AAs shown, a field oxide layer 310 has been formed in the terminal region of the substrate 300. This field oxide layer 310 can be a beak-shaped field oxide layer 310, i.e., a locally oxidized field oxide layer 310, or it can be other forms of field oxide layer 310. The field oxide layer 310 at least partially protrudes from the surface of the substrate 300. A gate material layer 320 is formed on the substrate 300, covering the surface of the substrate 300 and the field oxide layer 310. A gate material layer 320 can be conformally deposited on the entire substrate 300 by chemical vapor deposition or other suitable deposition processes. The gate material layer 320 can be a polysilicon layer, such as a doped polysilicon layer, and its coverage includes the surface of the active region of the cell region, the surface of the field oxide layer 310 in the terminal region, and the transition region between the two. This gate material layer 320 will serve as a common material layer for the subsequent formation of the gate electrode 321 and the field plate 322.

[0035] The material type of the gate material layer 320 can be various. For example, the material of the gate material layer 320 may include polysilicon or other suitable materials. Exemplarily, the polysilicon can be formed using a low-pressure chemical vapor deposition (LPCVD) process. The process conditions for forming polysilicon include: the reactant gas is silane (SiH4), the flow rate of silane can be in the range of 100–200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature inside the reaction chamber can be in the range of 700–750 degrees Celsius; the pressure inside the reaction chamber can be in the range of 250–350 millimeters of mercury (mTorr), such as 300 mTorr; the reactant gas may also include a buffer gas, which can be helium (He) or nitrogen, and the flow rate of helium and nitrogen can be in the range of 5–20 liters per minute (slm), such as 8 slm, 10 slm, or 15 slm.

[0036] It is worth mentioning that a gate dielectric layer (not shown) may also be formed below the gate electrode 321 formed in the cell region. For example, the gate dielectric layer may include silicon oxide or other suitable materials, and its thickness is less than that of the field oxide layer 310.

[0037] like Figure 4B As shown, a first photoresist layer 301 is formed on the gate material layer 320. The type of the first photoresist layer 301 can be selected according to the specific process design. It can be a negative photoresist or a positive photoresist.

[0038] Continue as Figure 4BAs shown, the first photoresist layer 301 is patterned by using the first mask 410 (also referred to as the gate mask) to cover the areas of the gate material layer 320 where the gate electrode 321 and the field plate 322 are to be formed, and to expose other areas. Specifically, the first photoresist layer 301 is exposed and developed using the first mask 410 (i.e. the gate mask). After the photoetching, the first photoresist layer 301 is patterned, with its remaining portions covering the areas of the gate material layer 320 where the gate electrode 321 and the field plate 322 are to be formed. Meanwhile, the photoresist layer is completely removed from other areas, thereby exposing the gate material layer 320 in these areas. Thus, two types of structure patterns are defined at one time by using the same mask.

[0039] The desired patterning effect can be achieved by adjusting the pattern design of the first mask 410 according to the type of photoresist. For example, when the first photoresist layer 301 uses a negative photoresist, the negative photoresist has the characteristic that the portion exposed to ultraviolet light will undergo a cross-linking reaction and become insoluble in the developing solution, while the unexposed portion is removed by development. In this case, the light-transmitting area of the first mask 410 corresponds to the positions where the photoresist is to be retained, i.e. the areas where the gate electrode 321 and the field plate 322 are to be formed; and the light-blocking area corresponds to other areas where the photoresist is to be removed. During photoetching, ultraviolet light passes through the light-transmitting area of the first mask 410, causing the photoresist in the corresponding area to be exposed. After development, the photoresist in the unexposed area (i.e. the pattern area of the gate electrode 321 and the field plate 322) is dissolved and removed because it does not undergo cross-linking, thereby exposing the underlying gate material layer 320; while the photoresist in the exposed area is retained to form a protective mask. The subsequent etching process uses the patterned photoresist layer as a mask to etch the exposed gate material layer 320. Figure 4B When the first photoresist layer 301 uses a positive photoresist, the positive photoresist has the characteristic that the portion exposed to ultraviolet light will undergo a photodegradation reaction and become soluble in the developing solution, while the unexposed portion is retained. In this case, as shown, the light-blocking area 411 of the first mask 410 corresponds to the areas of the gate electrode 321 and the field plate 322 where the photoresist is to be retained; and the light-transmitting area 412 corresponds to other areas where the photoresist is to be removed. During photoetching, ultraviolet light passes through the first mask 410, causing the photoresist in other areas except the pattern area of the gate electrode 321 and the field plate 322 to be exposed. During development, these exposed areas are dissolved and removed, thereby exposing the gate material layer 320 in these areas; while the unexposed areas retain the photoresist as a protective layer 360. The subsequent etching process removes the exposed gate material, thereby forming the desired gate electrode 321 and field plate 322 structure.

[0040] Next, as shown in FIG. 3C, a first photoresist layer 301 is formed to cover the entire substrate 300, and a first protrusion structure is formed by etching the first photoresist layer 301 to expose the gate material layer 320 in the cell region. Figure 4C Then, as shown in FIG. 3D, the gate material layer 320 is etched to form a gate electrode 321 in the cell region and a field plate 322 in the termination region, with the field plate 322 covering at least part of the field oxide, and the gate structure and the plate are arranged in a spaced-apart manner in the direction parallel to the surface of the substrate 300. This method efficiently defines two functionally different structures (the gate electrode 321 and the field plate 322) through one key photolithography and etching step, simplifying the process flow. As for the process of etching the gate material layer 320, various dry anisotropic etching processes such as but not limited to plasma etching can be used, and various wet selective etching processes such as but not limited to wet etching can also be used.

[0041] After that, the first photoresist layer 301 can be removed by, for example, a gray ash process.

[0042] Next, as shown in FIG. 3E, an interlayer dielectric layer 330 is formed to cover the first protrusion structure and the second protrusion structure, and the interlayer dielectric layer 330 in the space between the first protrusion structure and the second protrusion structure has a recess 3231 towards the surface side of the substrate 300. Figure 4D The interlayer dielectric layer 330 can be made of, for example, silicon oxide, fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN), etc. It can be deposited by any suitable deposition process such as a chemical vapor deposition process or a high-density plasma (HDP) manufacturing process, etc.

[0043] Specifically, for example, an interlayer dielectric layer 330 covering all the structures is deposited on the substrate 300 by a chemical vapor deposition process. The interlayer dielectric layer 330 is usually composed of silicon dioxide, and its coverage includes but is not limited to the gate electrode 321 (i.e. the first protrusion structure) in the cell region, the field plate 322 (i.e. the second protrusion structure) in the termination region, and the region of the substrate 300 between these protrusion structures. Due to the conformal coverage characteristics of the deposition process, the interlayer dielectric layer 330 replicates and to some extent amplifies the topological morphology of the underlying structure. Therefore, after the deposition is completed, in the space between the first protrusion structure (the gate electrode 321) and the second protrusion structure (the field plate 322), due to the lowest position of the substrate 300 surface at this location, the top surface of the interlayer dielectric layer 330 above this region is correspondingly recessed, thus naturally forming a recess 3231 towards the surface side of the substrate 300.

[0044] Optionally, the top surface of one of the first protrusion structures is higher than the top surface of the other, for example, the top surface of the field plate 322 is higher than the top surface of the gate electrode 321.

[0045]

[0046] ​To ensure the effectiveness of subsequent planarization processes and provide sufficient insulation for the overall structure, the target thickness of the interlayer dielectric layer 330 deposited in this step is designed to be relatively thick. Specifically, the thickness of the interlayer dielectric layer 330 may be, for example, that the minimum thickness of the interlayer dielectric layer 330 (typically located at the top of the protrusion) should be at least greater than the thickness of the first protrusion, such as the gate electrode 321, and / or at least greater than the thickness of the second protrusion, such as the field plate 322. Furthermore, the thickness of the interlayer dielectric layer 330 may be greater than or equal to twice the thickness of the first protrusion; and / or the thickness of the interlayer dielectric layer 330 may be greater than or equal to twice the thickness of the second protrusion. Its average thickness must ensure that after the dielectric layer above the protrusion is planarized in subsequent etching processes, the interlayer dielectric layer 330 located at the bottom of the recess 3231 retains sufficient thickness to maintain reliable electrical isolation. By giving the interlayer dielectric layer 330 a relatively thick initial thickness, sufficient processing allowance can be provided for the subsequent "gate reverse etching" process, so that the height of the interlayer dielectric layer 330 on the protruding structure can be effectively flattened without damaging the dielectric layer in the recessed 3231 region, thus achieving local planarization.

[0047] Subsequently, as Figure 4E As shown, a mask layer is formed on the interlayer dielectric layer 330. The mask layer exposes the interlayer dielectric layer 330 on the first protrusion structure and the second protrusion structure, and blocks the interlayer dielectric layer 330 in other areas. During the formation of the first protrusion structure and the second protrusion structure, a first photomask 410 is used for photolithography. During the formation of the mask layer, a second photomask 420 is used for photolithography. The light-blocking area 421 in the second photomask 420 corresponds to the light-transmitting area 412 in the first photomask 410, and the light-transmitting area 422 in the second photomask 420 corresponds to the light-blocking area 410 in the first photomask 410.

[0048] After forming the interlayer dielectric layer 330 covering all the protrusions, in order to selectively thin the interlayer dielectric layer 330 on the protrusions, a second photomask 420 is introduced for photolithography in this embodiment. The second photomask 420 is the reverse of the first photomask 410, such as a gate reverse mask. That is, the light-shielding area in the second photomask 420 corresponds to the light-transmitting area in the first photomask 410, and the light-transmitting area in the second photomask 420 corresponds to the light-shielding area in the first photomask 410.

[0049] The second photomask 420 is generated by a logical NOT operation based on the layout data of the first photomask 410 (gate mask) used in forming the first and second raised structures (i.e., gate electrode 321 and field plate 322). Specifically, for example, in the first photomask 410, the area used to define the patterns of the gate electrode 321 and field plate 322 is a light-transmitting area. After the logical NOT operation, in the resulting second photomask 420 (GR mask), the patterned area corresponding to the original gate electrode 321 and field plate 322 becomes a light-blocking area, while the light-blocking area in the original first photomask 410 becomes a light-transmitting area. In other words, the light-blocking area in the second photomask 420 corresponds to the light-transmitting area in the first photomask 410, and the light-transmitting area in the second photomask 420 corresponds to the light-blocking area in the first photomask 410.

[0050] In a specific example, firstly, a layer of photoresist is uniformly coated on the interlayer dielectric layer 330 to form a second photoresist layer 302 as a mask layer. Optionally, the mask layer may also include, for example, a hard mask layer or other suitable mask layer, such as forming a hard mask layer between the second photoresist layer 302 and the interlayer dielectric layer 330. Subsequently, an alignment operation of the photolithography machine is performed. The photolithographic alignment marks of the active layer can be selected as the alignment reference for this photolithography. The active layer is a key layer defined early in device manufacturing and has high-precision alignment marks. Using it as a reference can ensure the overlay accuracy between subsequent layers. Through this alignment step, the position of the subsequent exposure pattern is ensured to be precisely matched with the bottom gate, field plate 322, and other protruding structures. Using the aforementioned second photomask 420, the second photoresist layer 302 is photolithographically ... Since the pattern of the second photomask 420 is the reverse of the first photomask 410, the patterned second photoresist layer 302 formed after photolithography has the following graphic characteristics: the patterned second photoresist layer 302 exposes the interlayer dielectric layer 330 located above the gate electrode 321 and the field plate 322 (i.e., the first and second protrusion structures). At the same time, this photoresist layer shields and protects the interlayer dielectric layer 330 in all other areas (i.e., all areas other than the first and second protrusion structures), especially the recessed 3231 region between the protrusion structures and other parts of the cell region and the terminal region.

[0051] Subsequently, as Figure 4F As shown, using a mask layer as a mask, the exposed portion of the interlayer dielectric layer 330 is etched away to reduce the height difference between the top surface of the interlayer dielectric layer 330 on the first protrusion structure and the bottom surface of the recess 3231, and to reduce the height difference between the top surface of the interlayer dielectric layer 330 on the second protrusion structure and the bottom surface of the recess 3231.

[0052] For example, the second photoresist layer 302 is used as an etching mask to perform dry etching on the underlying interlayer dielectric layer 330. The etching process preferably uses anisotropic etching, such as reactive ion etching, to achieve good profile control. The etching gas can be a mixture of fluorine-containing gases (e.g. CF4, CHF3, C4F8, etc.), and by precisely controlling the RF power, gas flow ratio, and chamber pressure, high selectivity etching of the interlayer dielectric layer 330, such as silicon oxide, can be achieved, ensuring that the etching process slows down or stops when the surface of the underlying protruding structures (the gate electrode 321 and the field plate 322) is reached.

[0053] The etching process selectively removes the interlayer dielectric layer 330 in the areas not covered by the mask layer, such as the second photoresist layer 302, i.e. above the gate electrode 321 and the field plate 322. Due to the shielding effect of the mask layer, at least part of the interlayer dielectric layer 330 in the recessed area 3231 between the protruding structures and other non-target areas is protected from etching.

[0054] By removing the redundant interlayer dielectric layer 330 above the protruding structures and significantly reducing their top surface height, after etching, the top surface height of the interlayer dielectric layer 330 on the first protruding structure (the gate electrode 321) is reduced, thereby significantly reducing the height difference between it and the bottom surface of the recess 3231. At the same time, the top surface height of the interlayer dielectric layer 330 on the second protruding structure (the field plate 322) is also reduced synchronously, effectively reducing the height difference between it and the bottom surface of the recess 3231.

[0055] The process endpoint of this step is not to etch through the interlayer dielectric layer 330, but to control the etching endpoint by a pre-set etching time or real-time film thickness monitoring, and stop etching when the interlayer dielectric layer 330 above the protruding structures is thinned to the target thickness. The final surface topography shows that the surface topography of the entire interlayer dielectric layer 330 tends to be flat, and the sharp "peaks" (protruding areas) and "valleys" (recessed 3231 areas) are greatly smoothed.

[0056] In one specific example, the etching amount of the interlayer dielectric layer 330 is precisely controlled. The target thickness of the interlayer dielectric layer 330 removed by etching is set to be less than or equal to the thickness of the first protruding structure (the gate electrode 321), and / or less than or equal to the thickness of the second protruding structure (the field plate 322). In a preferred embodiment, a dry etching process is performed once by setting a predetermined etching time to accurately remove the target thickness of the interlayer dielectric layer 330. The target thickness is equal to the thickness of the first protruding structure, and / or the target thickness is equal to the thickness of the second protruding structure. By correlating the etching depth with the thickness of the protruding structure, a clear, repeatable and efficient process control method is provided, ensuring the consistency and reliability of the planarization effect.

[0057] The planarized surface achieved by local etching ensures that the etching load of the subsequent via etching in each region tends to be consistent, avoiding over-etching in the recessed region 3231, thereby reducing the risk of voids when filling the metal. Moreover, the more planar surface is conducive to the focusing accuracy of the subsequent photolithography process and the uniform deposition of the metal film, improving the window and robustness of the overall process.

[0058] After etching the interlayer dielectric layer, the mask layer can also be removed, for example by a gray ash process to remove the second photoresist layer.

[0059] In one example, the interlayer dielectric layer can also be planarized, for example by chemical mechanical polishing, to make the surface of the interlayer dielectric layer more planar.

[0060] Further, in some specific examples, the method of the present application further comprises the following steps: First, referring to Figure 4G , etching part of the interlayer dielectric layer 330 to form at least one first via 331, at least one second via 332 and at least one third via 333 in the interlayer dielectric layer 330, the first via 331 penetrating through the interlayer dielectric layer 330 and exposing part of the gate electrode 321, the via penetrating through the interlayer dielectric layer 330 and exposing part of the surface of the underlying gate electrode 321 or extending into the gate electrode 321 to facilitate electrical connection with the gate electrode 321, the second via 332 penetrating through the interlayer dielectric layer 330 and exposing part of the substrate 300 between the gate electrode 321 and the field plate 322, the second via 332 also penetrating through the interlayer dielectric layer 330 but located in the region between the gate electrode 321 and the field plate 322, exposing part of the substrate 300 (e.g. exposing at least part of the emitter or at least part of the well region of the cell region), thereby facilitating the at least part of the emitter or at least part of the well region of the cell region to be led out through the conductive material in the second via 332, and the third via 333 exposing part of the field plate 322, for example exposing part of the upper surface of the field plate 322 or also extending into the field plate 322 to facilitate electrical connection with the field plate 322. Due to the aforementioned planarization process, the improvement of the surface topography of the interlayer dielectric layer 330 makes the etching load of this via etching more uniform in each region. This effectively reduces the risk of the recess 3231 expanding in size due to over-etching in the recessed region 3231, while also avoiding photolithography defects caused by topography fluctuations, ensuring that each via is regular in shape and controllable in size.

[0061] Next, referring to Figure 4H , depositing a layer of metal material to fill the first via 331, the second via 332 and the third via 333 to form a first conductive via 341, a second conductive via 342 and a third conductive via 343 respectively, and the layer of metal material also covers the interlayer dielectric layer 330.

[0062] A continuous metal material layer is conformally deposited by physical vapor deposition, chemical vapor deposition or a process thereof. The metal material layer fills the first via 331, the second via 332 and the third via 333, and covers the interlayer dielectric layer 330. The portion formed in the via respectively forms a first conductive via 341 connected to the gate electrode 321, a second conductive via 342 connected to a specific region (e.g. emitter or well region) of the substrate 300, and a third conductive via 343 connected to the field plate 322. The portion of the metal material layer formed on the surface of the interlayer dielectric layer 330 is a metal interconnect layer 350, which electrically connects the conductive vias and extends to the predetermined region, thereby constructing the complete internal circuit of the device.

[0063] The metal material layer can also be formed in one step or in multiple steps, for example, a metal material layer can be first deposited to fill the via, and then another metal material layer can be deposited to cover the interlayer dielectric layer 330 and the formed metal material layer.

[0064] After the formation of the metal material layer, the metal material layer can also be planarized, for example, by chemical mechanical polishing.

[0065] Further, in some specific examples, the method of the present application further comprises the following steps: as shown in Figure 4I The protective layer 360 is formed to cover the metal interconnect layer 350, so as to encapsulate the device and protect the internal structure of the device from the external environment (e.g. moisture, contaminants, mechanical scratches).

[0066] Taking the polyimide layer as an example, the polyimide layer can be first formed on the metal material layer as the protective layer 360. A polyimide precursor solution is coated on the metal interconnect layer 350 by spin coating or the like, to form a uniform polyimide layer, and then the polyimide layer is cured and baked. In this process, the polyimide precursor undergoes imidization reaction to form a final protective film with excellent chemical stability and mechanical strength. Since the interlayer dielectric layer 330 formed by the foregoing steps has a relatively flat surface, the risk of voids in the metal material layer is reduced, and thus the surface of the protective layer 360 is less likely to have pit defects caused by the expansion and release of gas in the voids during the curing and baking of the polyimide.

[0067] At this point, the main steps of the preparation method of the semiconductor device of an embodiment of the present application are completed. It can be understood that the preparation method of the embodiment not only includes the above steps, but also can include other required steps, which are included in the scope of the preparation method of the semiconductor device of the embodiment.

[0068] It should be understood that the type of semiconductor device contemplated by the present application includes, but is not limited to, Insulated Gate Bipolar Transistors. Based on the same inventive concept disclosed in the present specification, it would be obvious to those skilled in the art to apply the method to fabricate other types of power devices such as Laterally Diffused Metal Oxide Semiconductor Transistors (LDMOS) and the like, and such variations fall within the scope of the present application.

[0069] Embodiment Two The present application also provides a semiconductor device prepared by the method of any one of the above Embodiment One.

[0070] The semiconductor device of the present application is prepared by the above method, and therefore has the same advantages as the above method.

[0071] The present application has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of illustration and description, and are not intended to limit the present application to the scope of the described embodiments. Furthermore, those skilled in the art can understand that the present application is not limited to the above embodiments, and that more variations and modifications can be made in accordance with the teachings of the present application, and such variations and modifications fall within the scope of the present application. The scope of protection of the present application is defined by the attached claims and their equivalent scope.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A first protrusion structure and a second protrusion structure are formed on the substrate at intervals; An interlayer dielectric layer is formed to cover the first protrusion structure and the second protrusion structure, wherein the interlayer dielectric layer at the interval between the first protrusion structure and the second protrusion structure has a recess toward the substrate surface side; A mask layer is formed on the interlayer dielectric layer, which exposes the interlayer dielectric layer on the first protrusion structure and the second protrusion structure, and blocks the interlayer dielectric layer in other areas. During the formation of the first protrusion structure and the second protrusion structure, a first photomask is used for photolithography, and during the formation of the mask layer, a second photomask is used for photolithography. The light-blocking area in the second photomask corresponds to the light-transmitting area in the first photomask, and the light-transmitting area in the second photomask corresponds to the light-blocking area in the first photomask. Using the mask layer as a mask, the exposed portion of the interlayer dielectric layer is etched away to reduce the height difference between the top surface of the interlayer dielectric layer on the first protruding structure and the bottom surface of the recess, and to reduce the height difference between the top surface of the interlayer dielectric layer on the second protruding structure and the bottom surface of the recess.

2. The preparation method according to claim 1, characterized in that, The substrate includes a cell region and a terminal region. The first protrusion structure includes a gate electrode formed on the substrate in the cell region. A field oxide layer is also formed on the substrate in the terminal region. The second protrusion structure includes a field plate covering the field oxide layer. The method for forming the first protrusion structure and the second protrusion structure includes the following steps: A gate material layer is formed on the substrate, covering the surface of the substrate and the field oxide layer; A first photoresist layer is formed on the gate material layer; Using the first photomask, the first photoresist layer is photolithographically patterned to form a patterned first photoresist layer, thereby covering the area of ​​the gate material layer used to form the gate electrode and the area used to form the field plate, while exposing other areas; Using the patterned first photoresist layer as a mask, the gate material layer is etched to form the gate electrode located in the cell region and the field plate located in the terminal region, wherein the field plate covers at least a portion of the field oxide, and the gate structure and the field plate are spaced apart in a direction parallel to the surface of the substrate, the first bump structure includes the gate electrode, and the second bump structure includes the field plate.

3. The preparation method according to claim 2, characterized in that, The mask layer includes a second photoresist layer, which is the same type of photoresist as the first photoresist layer. The mask layer is formed on the interlayer dielectric layer, including: A second photoresist layer is formed on the interlayer dielectric layer; Using a second photomask, the second photoresist layer is photolithographically etched to form a patterned second photoresist layer, wherein the patterned second photoresist layer exposes the gate electrode and the interlayer dielectric layer on the field plate, while blocking the interlayer dielectric layer in other areas, wherein the light-blocking area in the second photomask corresponds to the light-transmitting area in the first photomask, and the light-transmitting area in the second photomask corresponds to the light-blocking area in the first photomask.

4. The preparation method according to claim 2, characterized in that, The method further includes: The interlayer dielectric layer is etched to form at least one first via, at least one second via, and at least one third via in the interlayer dielectric layer. The first via penetrates the interlayer dielectric layer and exposes a portion of the gate electrode. The second via penetrates the interlayer dielectric layer and exposes a portion of the substrate between the gate electrode and the field plate. The third via exposes a portion of the field plate. A deposited metal material layer fills the first through-hole, the second through-hole, and the third through-hole to form a first conductive through-hole, a second conductive through-hole, and a third conductive through-hole, respectively, and the metal material layer also covers an interlayer dielectric layer.

5. The preparation method according to claim 4, characterized in that, The method further includes: A protective layer is formed to cover the metal material layer.

6. The preparation method according to claim 5, characterized in that, Forming a protective layer covering the metal material layer includes: A polyimide layer is formed on the metal material layer as the protective layer; The polyimide layer is then cured and baked.

7. The preparation method according to claim 1, characterized in that, The target thickness of the portion of the interlayer dielectric layer removed by etching is less than or equal to the thickness of the first protrusion structure and / or the second protrusion structure.

8. The preparation method according to claim 1, characterized in that, Using the mask layer as a mask, etching away the exposed portion of the interlayer dielectric layer includes: The interlayer dielectric layer is subjected to dry etching for a predetermined duration to remove the interlayer dielectric layer of a target thickness, wherein the target thickness is equal to the thickness of the first protrusion structure, and / or the target thickness is equal to the thickness of the second protrusion structure.

9. The preparation method according to claim 1, characterized in that, The top surface height of one of the first protrusions is higher than the top surface height of the other; and / or The thickness of the interlayer dielectric layer is greater than or equal to twice the thickness of the first protrusion structure; and / or The thickness of the interlayer dielectric layer is greater than or equal to twice the thickness of the second protrusion structure.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the semiconductor device preparation method as described in any one of claims 1 to 9.

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