Semiconductor device with mixed channel

Abstract

A semiconductor device with mixed channels is suitable for operability at high operating voltages (e.g., 2.5 volts to 3.3 volts). The semiconductor device includes: a drain; a source electrode; the channel comprises a first nanosheet and a second nanosheet; a sacrificial layer disposed between the first nanosheet and the second nanosheet; and a gate electrode formed around the channel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor fabrication technology. More particularly, the present disclosure relates to semiconductor device structures. BACKGROUND

[0002] Semiconductor device structures can be used to provide a more diverse range of operating voltages for implementations of fully wrapped gate-all-around field effect transistor (GAAFET) devices and other similar devices. For example, the semiconductor device structures described herein can be used in various implementations of lateral diffused metal oxide semiconductor (LDMO) for use in a variety of different high power applications, such as power amplifiers, radio frequency (RF) amplifiers, and power transistors for wireless and wireless communication systems. As the demand for high power applications increases, research and development efforts continue to advance semiconductor technology to meet the manufacturing capabilities and yields of foundries and to enhance the functionality of various electronic devices and circuits. SUMMARY

[0003] In one aspect, the present disclosure relates to a semiconductor device comprising: a drain; a source; a channel comprising a first nanosheet and a second nanosheet; a sacrificial layer disposed between the first nanosheet and the second nanosheet; and a gate formed around the channel.

[0004] In another aspect, the present disclosure relates to a semiconductor device comprising: a drain; a source; a channel comprising a first nanosheet, a second nanosheet, and a third nanosheet; a first sacrificial layer disposed between the first nanosheet and the second nanosheet; a second sacrificial layer disposed between the second nanosheet and the third nanosheet; and a gate formed around the channel.

[0005] In another aspect, the present disclosure relates to a circuit comprising: a substrate; and a semiconductor device formed on the substrate, the semiconductor device comprising: a drain; a source; a channel comprising a first nanosheet and a second nanosheet; a sacrificial layer disposed between the first nanosheet and the second nanosheet; and a gate formed around the channel. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a cross-section illustrating components of an example semiconductor device according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0007] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It should be appreciated, however, that the present disclosure can be practiced in other instances without some or all of these specific details. Different examples are described herein, and although various features are attributed to different examples, it should be understood that features described with respect to one example can be incorporated with respect to other examples. However, for the same reason, no single feature or group of features of any described example should be taken as essential to every example, as other examples can omit such features.

[0008] When an element in this disclosure is referred to as being "connected" or "coupled" to another element, it is understood that the element can be directly connected or coupled to the other element or intervening elements can be present between the element and the other element. By contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that no intervening elements are present between the element and the other element. However, the presence of intervening elements does not preclude the presence of other elements between the element and the other element.

[0009] When an element in this disclosure is referred to as being "disposed" in some way relative to another element (e.g., disposed on, disposed between, disposed under, disposed adjacent to, or disposed in some other relative way), it is understood that the element can be disposed directly relative to the other element (e.g., directly on the other element) or have intervening elements present between the element and the other element. By contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that no intervening elements are present in the "direct" instance. However, the presence of intervening elements does not preclude other instances in which intervening elements can be present.

[0010] Likewise, when an element in this disclosure is referred to as a "layer", it is understood that the layer can be a single layer or include multiple layers. For example, a conductive layer can include multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer can include multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as coupled or connected to another layer, it is understood that the coupled or connected layers can include intervening elements present between the coupled or connected layers. By contrast, when an element is referred to as being "directly" connected or coupled to another layer, it is understood that no intervening elements are present between the layers. However, the presence of intervening elements does not preclude other connections in which intervening elements can be present.

[0011] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Rather, they are used to indicate relative positions and / or directions between various parts of objects and / or assemblies.

[0012] Furthermore, all numbers expressing quantities, dimensions, and so forth used herein are to be understood as being modified in all instances by the term "about," unless otherwise specifically noted. In this application, the use of the singular includes the plural, and vice versa, unless specifically stated otherwise. Furthermore, the use of the term "and / or" means "and" or "or," unless specifically stated otherwise. Also, the use of the term "including" and "having" and the like, as well as the use of the term "comprises" and "comprising," are used in the sense of "including and / or having" but not limited to, unless specifically stated otherwise. Moreover, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or," unless specifically stated otherwise. Additionally, the use of the term "including" and "including a" and "comprising" and "comprising a" and "having" and "having a" and "one or more of" and / or "and / or other variations thereof are intended to cover embodiments of the application. Also, the use of the term "about" in relation to a geographic location, unless specifically stated otherwise, means that the geographic location is within a certain distance of the stated geographic location. For example, "about" can mean within 1 mile, 5 miles, 10 miles, 25 miles, 50 miles, 100 miles, or any other distance of the stated geographic location.

[0013] Although some features and aspects have been described with respect to examples, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Further, although the various methods and processes described herein can be described with respect to particular structural and / or functional components for ease of description, methods provided by various embodiments are not limited to any particular structural and / or functional architecture but instead can be implemented in any suitable hardware configuration. Similarly, although some functionality is ascribed to one or more system components, unless the context demands otherwise, this functionality can be distributed among the various other system components in accordance with the several embodiments.

[0014] Further, although the processes described herein are described with respect to particular operational flows for ease of description, persons of ordinary skill in the art will appreciate that the processes can be carried out with respect to a variety of other processes, and that the processes described herein are not limited to any particular order or sequence of steps. Additionally, some of the described processes can be performed concurrently, in sub-processes, or in serial, and one skilled in the art will recognize that this description is not intended to limit the processes to one specific order or sequence. As used in this description, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. Unless specifically stated otherwise, the description herein is not intended to limit the processes described to a single preferred implementation. For ease of description, some of the processes described herein are described as being performed by a single system component, such as a processor, a controller, or the like. However, as would be understood by one skilled in the art, such processes can be performed by a single system component or multiple system components acting in concert. Further, as would be understood by one skilled in the art, such processes can be performed by a single system component or multiple system components acting in concert. Additionally, the processes described with respect to one method or process can be incorporated into other described methods or processes; similarly, system components described with respect to a particular structural architecture and / or with respect to one system can be organized in alternative structural architectures and / or incorporated into other described systems. Accordingly, although the description herein has described several examples, persons of ordinary skill in the art will appreciate that many modifications are possible in the examples noted herein, and that the various implementations described herein are not limited to any particular modified example described. Accordingly, although specific reference can be made to the examples contained herein, persons of ordinary skill in the art will realize that the various features covered herein are not limited to the examples described.

[0015] Reference Figure 1According to some aspects of the disclosure, a cross-section showing components of an illustrative semiconductor device 100 is presented. The semiconductor device 100 can be implemented as various types of semiconductor devices, such as various different types and combinations of transistor structures. For example, the semiconductor device 100 can include a non-planar (three-dimensional) GAAFET device, such as a fully-surrounding gate LDMOS device. As shown in Figure 1 The semiconductor device 100 includes a substrate 110, a well 122, a well 124, a dummy gate 132, a gate 134, a dummy gate 136, a dummy gate 138, a source 142, a drain 144, an isolation structure 152, an isolation structure 154, an isolation structure 156, a channel 160, a nanosheet 162, a nanosheet 164, a nanosheet 166, a sacrificial layer 172, a sacrificial layer 174, a sacrificial layer 176, a trench 180, an interconnect 192, an interconnect 194, and an interconnect 196. The semiconductor device 100 generally provides a structure suitable for use with high operating voltages (e.g., 2.5 volts to 3.3 volts).

[0016] The channel 160 can be implemented in various suitable ways. For example, while the channel 160 is shown in Figure 1 as including three nanosheets (nanosheet 162, nanosheet 164, and nanosheet 166), in some implementations, the channel 160 can also include more than three nanosheets or fewer than three nanosheets. The channel 160 can also be implemented using various alternative structures other than nanosheets, such as nanowires and / or other suitable structures. Furthermore, the gate 134 can be formed around the channel 160 in various suitable ways. For example, the gate 134 can completely surround the channel 160, or the gate 134 can partially surround the channel 160 (e.g., there can be a gap between the channel 160 and the gate 134). Furthermore, layers can be present in the semiconductor device 100 between the gate 134 and the channel 160 such that the gate 134 can or can not directly contact the channel 160. Additionally, the sacrificial layer 172, the sacrificial layer 174, and the sacrificial layer 176 can or can not be considered part of the channel 160. For example, in scenarios where the sacrificial layer 172, the sacrificial layer 174, and the sacrificial layer 176 are considered part of the channel 160 along with the nanosheet 162, the nanosheet 164, and the nanosheet 166, the channel 160 can be considered a “hybrid channel” or a “superlattice” structure.

[0017] The substrate 110 can be formed using silicon material (e.g., crystalline silicon) and / or other suitable materials or combinations of materials. The substrate 110 can be implemented using various fabrication techniques, such as using a silicon-on-insulator (SOI) structure, a bulk semiconductor structure, an alloy semiconductor, a compound semiconductor, germanium, and / or various other suitable materials and combinations thereof. The substrate 110 generally provides a base for forming components of the semiconductor device 100 thereon. The semiconductor device 100 can be implemented in various types of circuitry, resulting in various types of integrated circuit (IC) chips.

[0018] The well 122 and the well 124 can be formed at least partially within the substrate 110. The well 122 and the well 124 can also be formed at least partially apart from the substrate 110, such as at least partially within various types of oxide layers and / or other insulative / dielectric layers within the semiconductor device 100. The well 122 can be relatively lightly doped using a first dopant, while the well 124 can be relatively lightly doped using a second dopant that is different from the first dopant. For an NLDMOS implementation of the semiconductor device 100, the first dopant can be an n-type dopant (and the well 122 can accordingly be an n-type well), and the second dopant can be a p-type dopant (and the well 124 can accordingly be a p-type well). In contrast, for a PLDMOS implementation of the semiconductor device 100, the first dopant can be a p-type dopant (and the well 122 can accordingly be a p-type well), and the second dopant can be an n-type dopant (and the well 124 can accordingly be an n-type well). Various suitable n-type dopants can be used to form the well 122 and / or the well 124, such as including arsenic, phosphorus, and / or other similar n-type dopants. Various suitable p-type dopants can also be used to form the well 122 and / or the well 124, including such as boron and / or other similar p-type dopants.

[0019] As mentioned above, gate 134 can be formed around channel 160. Gate 134 can be formed using various suitable metals (e.g., titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, tungsten, tungsten nitride, tungsten silicide, etc.) to, for example, form a high-k metal gate. A voltage applied at gate 134 can control the operation and electrical conductance of semiconductor device 100 by controlling the operation and electrical conductance of channel 160. Various types of spacers can be formed at least partially around gate 134 to electrically isolate gate 134 and prevent charge leakage. For example, the spacers can include materials having a high dielectric constant, such as silicon nitride, silicon oxide, and / or other suitable materials and combinations thereof. Additionally, one or more gate oxide layers can be formed between gate 134 and channel 160 using suitable dielectric materials such as silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable materials and combinations thereof. Gate 134 is generally used as an active gate, while dummy gate 132, dummy gate 136, and dummy gate 138 are non-active gates. Dummy gate 132, dummy gate 136, and dummy gate 138 can be formed around channel 160 in a similar manner as gate 134. In some embodiments, dummy gate 132, dummy gate 136, and dummy gate 138 can also be formed using various suitable metals. In some embodiments, dummy gate 132, dummy gate 136, and dummy gate 138 can also be formed using polysilicon or other similar materials. Gate 134 can include any material effective to form a gate terminal of a transistor.

[0020] Source 142 and drain 144 can each be implemented at least partially as an epitaxial layer within semiconductor device 100. For example, source 142 and drain 144 can be implemented using a relatively highly doped epitaxial layer formed around channel 160. Source 142 and drain 144 can include any material effective to form a source terminal and a drain terminal, respectively, of a transistor. As with gate 134, source 142 and drain 144 can be formed around channel 160 in various suitable manners. The epitaxial layer used to form source 142 and drain 144 can be formed using various suitable materials, such as silicon, gallium arsenide, and / or other suitable epitaxial materials and combinations thereof. For example, the epitaxial layer used to form source 142 and drain 144 can be highly doped using a suitable n-type dopant (e.g., for an NLDMOS implementation of semiconductor device 100) or a suitable p-type dopant (e.g., for a PLDMOS implementation of semiconductor device 100). Well 122 and well 124 can be doped according to a first doping concentration, the epitaxial layer used to form source 142 and drain 144 can be doped according to a second doping concentration, and the second doping concentration can be greater than the first doping concentration. Source 142 and drain 144 can be formed according to, for example, a raised source / drain (RSD) structure having advantageous electrical properties for preventing electrostatic discharge.

[0021] Isolation structures 152, 154, and 156 can be implemented as, for example, shallow trench isolation (STI) structures. Thus, isolation structures 152, 154, and 156 can be formed as a result of etching trenches in semiconductor device 100. For example, after trench 180 is etched, isolation structure 154 can be formed by at least partially depositing a dielectric material within trench 180. The dielectric material used to form isolation structures 152, 154, and 156 can be, for example, silicon oxide, silicon nitride, and / or other suitable materials and / or combinations of materials. Isolation structures 152, 154, and 156 can generally prevent current leakage between different components of semiconductor device 100.

[0022] Additionally, as shown in Figure 1 Trench 180 can be disposed between gate 134 and drain 144 and within channel 160, as shown in Figure 1 Due to this structure, a depletion region can be formed in substrate 110 (e.g., in well 122 and / or well 124). A depletion region is generally an insulating region in which mobile charge carriers have been diffused away and / or forced away by an electric field. Ionized donor and / or acceptor impurities that remain in the depletion region then cause the charge carriers within the depletion region to be depleted, thereby limiting the amount of current that can flow through the depletion region. As shown by the arrows in Figure 1 The current flow path is also close to the surface of the gate (e.g., the metal surface), as shown in

[0023] Nanosheets 162, 164, and 166 can be implemented in various suitable ways. For example, nanosheets 162, 164, and 166 can be made of silicon, or they can be made of silicon-germanium with a first germanium concentration, and other possibilities. Similarly, sacrificial layers 172, 174, and 176 can be implemented in various suitable ways. For example, sacrificial layers 172, 174, and 176 can be made of silicon-germanium with a second germanium concentration greater than the first concentration, and other possibilities. In some instances, the first germanium concentration can be between 10% and 30%, while the second germanium concentration is between 35% and 65%. Sacrificial layers 172, 174, and 176 can be considered "sacrificial layers" because during some alternative semiconductor fabrication processes, the sacrificial layers can be removed ("sacrificed") during the channel release phase of the fabrication process.

[0024] In some instances, nanosheets 162, 164, and 166 may each have a thickness between 4 nanometers and 12 nanometers (e.g., from...). Figure 1 The vertical thickness shown is measured in the direction between nanosheets 162 and 164 from the perspective shown in the image, while sacrificial layers 172, 174, and 176 may each have a thickness between 8 nanometers and 17 nanometers (e.g., from the perspective shown in the image). Figure 1 The vertical thickness shown is measured in the direction between nanosheets 162 and 164 (the perspective shown). That is, the thickness of sacrificial layers 172, 174, and 176 can generally be greater than the thickness of nanosheets 162, 164, and 166. The ratio of the thickness of sacrificial layers 172, 174, and 176 to the thickness of nanosheets 162, 164, and 166 can be between 1.7 and 2.3.

[0025] To provide a suitable structure under high operating voltage conditions (e.g., 2.5 volts to 3.3 volts), the length of gate 134 (e.g., from...) Figure 1The horizontal length of the gate 134 (measured in the direction between the source 142 and the drain 144) typically needs to be increased relative to some alternative structures. For example, if the length of the gate 134 does not exceed about 150 nanometers, the semiconductor device 100 can be limited to an operating voltage in the range of 1.2 volts to 1.5 volts. However, if the length of the gate 134 is increased to between 190 nanometers and 310 nanometers, the semiconductor device 100 can be suitable for an operating voltage in the range of 2.5 volts to 3.3 volts. In some alternative structures, sacrificial layers similar to the sacrificial layers 172, 174, and 176 can be removed during a channel release phase of the fabrication process. For example, during the channel release phase of the fabrication process, a mask can be placed over the nanosheets 162, 164, and 166, but not over the sacrificial layers 172, 174, and 176. However, as the length of the gate 134 is extended, removing the sacrificial layers during the channel release phase can cause the nanosheets to deform (and in some instances, break) due to stress placed on the nanosheets in subsequent processing phases.

[0026] To prevent such deformation of the nanosheets 162, 164, and 166 during the fabrication process that can be due to the extended length of the gate 134, the fabrication process can be altered such that during the channel release phase of the fabrication process, a mask is placed not only over the nanosheets 162, 164, and 166, but also over the sacrificial layers 172, 174, and 176. Thus, the sacrificial layers 172, 174, and 176 are not removed by etching, but will remain as part of the semiconductor device 100, and the presence of the sacrificial layers 172, 174, and 176 can prevent the nanosheets 162, 164, and 166 from deforming during the fabrication process. As node sizes continue to decrease (e.g., 2nm GAAFET nodes and below), such support provided by the presence of the sacrificial layers 172, 174, and 176 can be particularly important. Thus, the semiconductor device 100 provides a structure that can enable the use of high operating voltages in circuits produced using advanced semiconductor process technology.

[0027] Interconnects 192, 194, and 196 can be implemented using various suitable structures for forming electrical connections between components of semiconductor device 100 and / or components of a circuit (e.g., an IC) that includes semiconductor device 100. For example, interconnects 192, 194, and 196 can be implemented as conductive copper vias and other possible types of interconnect structures. In particular, interconnects 192 can be used to form one or more electrical connections between source 142 and one or more additional components of semiconductor device 100 and / or components of a circuit that includes semiconductor device 100. In particular, interconnects 194 can be used to form one or more electrical connections between gate 134 and one or more additional components of semiconductor device 100 and / or components of a circuit that includes semiconductor device 100. In particular, interconnects 196 can be used to form one or more electrical connections between drain 144 and one or more additional components of semiconductor device 100 and / or components of a circuit that includes semiconductor device 100.

Claims

1. A semiconductor device comprising: Drain; Source pole; The channel comprises a first nanosheet and a second nanosheet; A sacrificial layer is disposed between the first nanosheet and the second nanosheet; and A gate is formed around the channel.

2. The semiconductor device according to claim 1, wherein: The first nanosheet and the second nanosheet are made of silicon; and The sacrificial layer is made of silicon and germanium.

3. The semiconductor device according to claim 1, wherein: The first nanosheet and the second nanosheet are composed of silicon-germanium with a first germanium concentration; The sacrificial layer is composed of silicon-germanium with a second germanium concentration; and The second germanium concentration is greater than the first germanium concentration.

4. The semiconductor device according to claim 3, wherein: The first germanium concentration is between 10% and 30%; and The second germanium concentration is between 35% and 65%.

5. The semiconductor device according to claim 1, wherein: The thickness of the sacrificial layer, measured in the direction between the first and second nanosheets, is between 8 nanometers and 17 nanometers; and The thickness of the first nanosheet, measured in the direction between the first and second nanosheets, is between 4 nanometers and 12 nanometers; and The thickness of the second nanosheet, measured in the direction between the first and second nanosheets, is between 4 nanometers and 12 nanometers.

6. The semiconductor device of claim 1, wherein the thickness of the sacrificial layer, measured in the direction between the first nanosheet and the second nanosheet, is greater than both the thickness of the first nanosheet measured in the direction between the first nanosheet and the second nanosheet and the thickness of the second nanosheet measured in the direction between the first nanosheet and the second nanosheet.

7. The semiconductor device of claim 1, wherein the length of the gate, measured in the direction between the source and the drain, is between 190 nanometers and 310 nanometers.

8. The semiconductor device of claim 1, further comprising a trench disposed between the gate and the drain.

9. The semiconductor device of claim 8, further comprising an isolation structure disposed below the trench, between the gate and the drain, and within the substrate of the semiconductor device.

10. A semiconductor device comprising: Drain; Source pole; The channel comprises a first nanosheet, a second nanosheet, and a third nanosheet; A first sacrificial layer is disposed between the first nanosheet and the second nanosheet; A second sacrificial layer is disposed between the second nanosheet and the third nanosheet; and A gate is formed around the channel.

11. The semiconductor device according to claim 10, wherein: The first nanosheet, the second nanosheet, and the third nanosheet are made of silicon; and The sacrificial layer is made of silicon and germanium.

12. The semiconductor device of claim 10, wherein the ratio of the thickness of the first sacrificial layer, measured in the direction between the first nanosheet and the second nanosheet, to the thickness of the first nanosheet, measured in the direction between the first nanosheet and the second nanosheet, is between 1.7 and 2.

3.

13. The semiconductor device of claim 10, wherein the length of the gate, measured in the direction between the source and the drain, is between 190 nanometers and 310 nanometers.

14. The semiconductor device of claim 10, wherein: The first nanosheet, the second nanosheet, and the third nanosheet are composed of silicon-germanium with a first germanium concentration; The first sacrificial layer and the second sacrificial layer are composed of silicon-germanium having a second germanium concentration; and The second germanium concentration is greater than the first germanium concentration.

15. The semiconductor device of claim 10, comprising: A trench disposed between the gate and the drain; and An isolation structure is disposed below the trench, between the gate and the drain, and within the substrate of the semiconductor device.

16. A circuit comprising: Substrate; and A semiconductor device formed on the substrate, the semiconductor device comprising: Drain; Source pole; The channel comprises a first nanosheet and a second nanosheet; A sacrificial layer is disposed between the first nanosheet and the second nanosheet; and A gate is formed around the channel.

17. The circuit according to claim 16, wherein: The first nanosheet and the second nanosheet are made of silicon; and The sacrificial layer is made of silicon and germanium.

18. The circuit of claim 16, wherein the thickness of the first sacrificial layer, measured in the direction between the first nanosheet and the second nanosheet, is greater than the thickness of the first nanosheet, measured in the direction between the first nanosheet and the second nanosheet.

19. The circuit of claim 16, wherein the length of the gate, measured in the direction between the source and the drain, is between 190 nanometers and 310 nanometers.

20. The circuit according to claim 16, wherein: The first nanosheet and the second nanosheet are composed of silicon-germanium with a first germanium concentration; The sacrificial layer is composed of silicon-germanium with a second germanium concentration; and The second germanium concentration is greater than the first germanium concentration.

Images