Semiconductor device

Abstract

A semiconductor device may include: a channel layer; a barrier layer on the channel layer and including a material having a different energy band gap from the channel layer; a gate electrode on the barrier layer; a gate semiconductor layer between the barrier layer and the gate electrode; a protective layer on the barrier layer and covering the gate electrode; and a source electrode and a drain electrode on opposite sides of the gate electrode and electrically connected to the channel layer, in which the protective layer may include a first protective layer on the barrier layer and including a first insulating material including deuterium, and a second protective layer on the first protective layer and including a second insulating material not including deuterium.

Description

Background Technology

[0001] In modern society, semiconductor devices are closely related to daily life. In particular, the importance of power semiconductor devices is increasing in various fields such as transportation (e.g., electric vehicles, railways, trams), renewable energy systems (e.g., solar and wind power), and mobile devices. Power semiconductor devices are semiconductor devices used to handle high voltages or high currents and perform functions such as power conversion and control in large power systems or high-output electronic devices. Power semiconductor devices have the ability and durability to handle high power, so they can handle large currents and withstand high voltages. For example, power semiconductor devices can handle voltages from hundreds to thousands of volts and currents from tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by minimizing power losses. Furthermore, power semiconductor devices can operate stably even in environments such as high temperatures.

[0002] These power semiconductor devices can be categorized based on their materials, and examples include SiC power semiconductor devices and GaN power semiconductor devices. By using SiC or GaN instead of existing silicon (Si) to fabricate power semiconductor devices, the instability of silicon at high temperatures can be overcome. SiC power semiconductor devices can withstand high temperatures, have low power losses, and are suitable for electric vehicles and renewable energy systems. GaN power semiconductor devices may be more expensive, but they can be highly efficient in terms of speed and suitable for high-speed charging of mobile devices. Summary of the Invention

[0003] This disclosure provides a semiconductor device with improved reliability.

[0004] The semiconductor device may include: a channel layer; a barrier layer located on the channel layer and including a material having a different band gap than the channel layer; a gate electrode located on the barrier layer; a gate semiconductor layer located between the barrier layer and the gate electrode; a protective layer located on the barrier layer and covering the gate electrode; and a source electrode and a drain electrode located on opposite sides of the gate electrode and electrically connected to the channel layer, wherein the protective layer may include a first protective layer located on the barrier layer and including a first insulating material containing deuterium, and a second protective layer located on the first protective layer and including a second insulating material not containing deuterium.

[0005] The semiconductor device may include a channel layer comprising GaN, a barrier layer on the channel layer comprising AlGaN and including an implantation region comprising deuterium; a gate electrode on the barrier layer and comprising a metallic material; a gate semiconductor layer between the barrier layer and the gate electrode and comprising GaN doped with p-type impurities; a protective layer on the barrier layer and covering the gate electrode; and source and drain electrodes on opposite sides of the gate electrode and electrically connected to the channel layer, wherein the protective layer may include: a first protective layer on the implantation region and comprising deuterium; and a second protective layer on the first protective layer.

[0006] The semiconductor device may include: a channel layer; a barrier layer located on the channel layer and including a material having a different band gap from the channel layer, and including an implantation region containing deuterium; a gate electrode located on the barrier layer; a gate semiconductor layer located between the barrier layer and the gate electrode; a protective layer located on the implantation region and covering the gate electrode; and a source electrode and a drain electrode located on opposite sides of the gate electrode and electrically connected to the channel layer, wherein the implantation region is located between the gate electrode and the source electrode and between the gate electrode and the drain electrode, and wherein the protective layer may include: a first protective layer located on the barrier layer and including silicon oxide containing deuterium; and a second protective layer located on the first protective layer and including silicon nitride or silicon oxide nitride that does not contain deuterium.

[0007] Based on the aforementioned and other characteristics described herein, the reliability of semiconductor devices can be improved. Attached Figure Description

[0008] Figure 1 and Figure 2 This is a cross-sectional view showing an example of a semiconductor device.

[0009] Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 5 It is a graph showing the deuterium content in the barrier and protective layers of a semiconductor device.

[0010] Figures 6 to 13 This is a cross-sectional view showing an example of a semiconductor device.

[0011] Figures 14 to 21 This is a cross-sectional view illustrating an example of the process sequence for manufacturing semiconductor devices.

[0012] Figures 22 to 25 This is a cross-sectional view illustrating an example of the process sequence for manufacturing semiconductor devices. Detailed Implementation

[0013] This specification is provided with reference to the accompanying drawings. As those skilled in the art will recognize, the scope of this disclosure is not limited to the examples shown, and various implementations are within the scope of this disclosure.

[0014] For clarity of description, parts or components not related to the description have been omitted, and identical or similar components are indicated by the same reference numerals throughout the specification.

[0015] Furthermore, the dimensions and thicknesses of each element are arbitrarily shown in the accompanying drawings for ease of description, and this disclosure is not necessarily limited to those shown in the drawings. The thicknesses of layers, films, panels, areas, regions, etc., are exaggerated in the accompanying drawings for clarity. The thicknesses of some layers and regions are exaggerated in the accompanying drawings for ease of description.

[0016] It should be understood that when an element such as a layer, film, region, area, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in the specification, the terms "on" or "above" mean disposed on or below the object portion, and do not necessarily mean disposed on the upper side of the object portion based on the direction of gravity.

[0017] Furthermore, unless explicitly stated otherwise, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply inclusion of the stated element but not exclusion of any other element.

[0018] Furthermore, throughout the specification, the phrase "in a plan view" or "on a plane" refers to viewing the target portion from the top, and the phrase "in a cross-sectional view" or "on a cross section" refers to viewing the cross section formed by vertically cutting the target portion from the side.

[0019] Now refer to Figure 1 and Figure 2 Examples describing semiconductor devices. Figure 1 This illustrates the situation where the semiconductor device is in the off state, and Figure 2 This illustrates the state in which the semiconductor device is in the on state.

[0020] Reference Figure 1 and Figure 2The semiconductor device may include a channel layer 132, a barrier layer 136 on the channel layer 132, a gate electrode 155 on the barrier layer 136, a gate semiconductor layer 152 between the barrier layer 136 and the gate electrode 155, a protective layer 500 on the barrier layer 136 and covering the gate electrode 155, and a source electrode 173 and a drain electrode 175 on opposite sides of the gate electrode 155 and electrically connected to the channel layer 132.

[0021] The channel layer 132 is a layer that forms a channel between the source electrode 173 and the drain electrode 175, and a two-dimensional electron gas (2DEG) 134 can be located inside the channel layer 132. The 2DEG 134 is a charge transport model used in solid-state physics, referring to a group of electrons that can move freely in two dimensions (e.g., in the xy plane), but are firmly confined within those two dimensions and cannot move in another dimension (e.g., in the z direction). In other words, the 2DEG 134 can exist in a two-dimensional sheet-like form within three-dimensional space. The 2DEG 134 mainly appears in semiconductor heterojunction structures, and... Figures 1 to 2 In the semiconductor device shown, an electron gas 134 can appear at the interface between the channel layer 132 and the barrier layer 136. For example, a two-dimensional electron gas 134 can be generated in the portion of the channel layer 132 adjacent to the barrier layer 136.

[0022] The channel layer 132 may comprise one or more materials selected from group III-V materials, such as nitrides comprising Al, Ga, In, B, or combinations thereof. The channel layer 132 may be formed as a single layer or multiple layers. The channel layer 132 may be Al... x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 132 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The channel layer 132 may be a doped layer or an undoped layer. The thickness of the channel layer 132 may be approximately several hundred nm or less.

[0023] The channel layer 132 may be located on the substrate 110, and the seed layer 121 and the buffer layer 122 may be located between the substrate 110 and the channel layer 132. The substrate 110, the seed layer 121, and the buffer layer 122 are layers used to form the channel layer 132, and in some cases, they can be omitted. For example, when a GaN substrate is used as the channel layer 132, at least one of the substrate 110, the seed layer 121, and the buffer layer 122 can be omitted. Considering the relatively high cost of GaN substrates, the channel layer 132 including GaN can be grown using a Si substrate 110. In this case, it may not be easy to grow the channel layer 132 directly on the substrate 110 because the lattice structure of Si is different from that of GaN. Accordingly, the seed layer 121 and the buffer layer 122 can be grown first on the substrate 110, and then the channel layer 132 can be grown on the buffer layer 122. In addition, at least one of the substrate 110, seed layer 121 and buffer layer 122 can be used in the manufacturing process and then removed from the final structure of the semiconductor device.

[0024] Substrate 110 may include a semiconductor material. For example, substrate 110 may include sapphire, Si, SiC, AlN, GaN, or combinations thereof. Substrate 110 may be a silicon-on-insulator (SOI) substrate. However, the material of substrate 110 is not limited to this, and all commonly used substrates can be used. In some cases, substrate 110 may include an insulating material. For example, several layers including channel layer 132 may be formed on the semiconductor substrate first, and then the semiconductor substrate may be removed and replaced with an insulating substrate.

[0025] Seed layer 121 may be directly located on substrate 110. However, this disclosure is not limited thereto, and another predetermined layer may be further located between substrate 110 and seed layer 121. Seed layer 121 is a layer used as a seed for growing buffer layer 122, and may be formed by a lattice structure of the seed that serves as buffer layer 122. Buffer layer 122 may be directly located on seed layer 121. However, this disclosure is not limited thereto, and another predetermined layer may be further located between seed layer 121 and buffer layer 122. Seed layer 121 may comprise one or more materials selected from group III-V materials, for example, nitrides comprising Al, Ga, In, B, or combinations thereof. Seed layer 121 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the seed layer 121 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

[0026] Buffer layer 122 may be located on seed layer 121. Buffer layer 122 may be located between seed layer 121 and channel layer 132. Buffer layer 122 may be a layer used to reduce the difference in lattice constant and coefficient of thermal expansion between seed layer 121 and channel layer 132, and / or to prevent parasitic current (leakage current) from flowing through channel layer 132. Buffer layer 122 may include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. Buffer layer 122 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, buffer layer 122 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

[0027] The buffer layer 122 of the semiconductor device may include a superlattice layer 124 located on the seed layer 121, and a high-resistivity layer 126 located on the superlattice layer 124. The superlattice layer 124 and the high-resistivity layer 126 may be sequentially located on the substrate 110.

[0028] A superlattice layer 124 may be located on the seed layer 121. The superlattice layer 124 may be directly located on the seed layer 121. However, this disclosure is not limited thereto, and another predetermined layer may be further located between the seed layer 121 and the superlattice layer 124. The superlattice layer 124 is a layer used to mitigate the difference in lattice constant and coefficient of thermal expansion between the substrate 110 and the channel layer 132, thereby mitigating tensile and compressive stresses generated between the substrate 110 and the channel layer 132, and mitigating stress between all layers formed by growth in the final structure of the semiconductor device. The superlattice layer 124 may comprise one or more materials selected from group III-V materials, for example, nitrides comprising Al, Ga, In, B, or combinations thereof. The superlattice layer 124 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the superlattice layer 124 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

[0029] The superlattice layer 124 can be composed of multiple layers containing different materials, stacked alternately. For example, the superlattice layer 124 can have a structure of repeatedly stacked AlGaN layers and AlN layers. For example, AlGaN / AlN / AlGaN / AlGaN / AlN can be stacked sequentially to form a superlattice layer. The number of AlGaN and GaN layers forming the superlattice layer 124 can be varied, and the materials configuring the superlattice layer 124 can be varied in different implementations. For example, the superlattice layer 124 can have a structure of repeatedly stacked AlGaN layers and GaN layers. For example, AlGaN / GaN / AlGaN / GaN / AlGaN / GaN can be stacked sequentially to form a superlattice layer. In some implementations (e.g., when the superlattice layer 124 comprises GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or combinations thereof), the superlattice layer 124 may have n-type semiconductor characteristics, wherein the electron concentration is greater than the hole concentration, but the material and conductivity type of the superlattice layer 124 are not limited thereto.

[0030] A high-resistivity layer 126 may be located on the superlattice layer 124. The high-resistivity layer 126 may be directly located on the superlattice layer 124. However, this disclosure is not limited thereto, and another predetermined layer may be further located between the superlattice layer 124 and the high-resistivity layer 126. The high-resistivity layer 126 may be located between the superlattice layer 124 and the channel layer 132. The high-resistivity layer 126 is a layer used to prevent leakage current from flowing through the channel layer 132, thereby preventing semiconductor device degradation. The high-resistivity layer 126 may be made of a material with low conductivity to electrically insulate the substrate 110 and the channel layer 132. The high-resistivity layer may include one or more materials selected from group III-V materials, for example, nitrides including Al, Ga, In, B, or combinations thereof. The high-resistivity layer 126 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the high-resistivity layer 126 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The high-resistivity layer 126 may be formed as a single layer or multiple layers.

[0031] The semiconductor device may further include a barrier layer 136 located on the channel layer 132. The barrier layer 136 may be located on the channel layer 132. The barrier layer 136 may be located directly on the channel layer 132. However, this disclosure is not limited thereto, and another predetermined layer may be further located between the channel layer 132 and the barrier layer 136. The region of the channel layer 132 overlapping with the barrier layer 136 between the source electrode 173 and the drain electrode 175 may be a drift region DTR. The drift region DTR may be located between the source electrode 173 and the drain electrode 175. The drift region DTR may refer to the region in which charge carriers move when a potential difference occurs between the source electrode 173 and the drain electrode 175.

[0032] The semiconductor device can be turned on / off depending on whether a voltage is applied to the gate electrode 155 and / or the magnitude of the voltage applied to the gate electrode 155, and accordingly, carrier movement in the drift region DTR can be performed or prevented.

[0033] Barrier layer 136 may comprise one or more materials selected from group III-V materials, for example, nitrides comprising Al, Ga, In, B, or combinations thereof. Barrier layer 136 may be Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). The barrier layer 136 may include GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or combinations thereof. The band gap of the barrier layer 136 can be adjusted by the composition ratio of Al and / or In. The barrier layer 136 may be doped with predetermined impurities. In this case, the impurities doped in the barrier layer 136 may be p-type dopants that can provide holes. For example, the impurities doped in the barrier layer 136 may be magnesium (Mg). By increasing or decreasing the impurity doping concentration of the barrier layer 136, the threshold voltage, temperature resistance, etc., of the semiconductor device can be adjusted.

[0034] The barrier layer 136 may comprise a semiconductor material having properties different from those of the channel layer 132. The barrier layer 136 may differ from the channel layer 132 in at least one aspect of polarization characteristics, band gap, and lattice constant. For example, the barrier layer 136 may comprise a material having a band gap different from that of the channel layer 132. In this case, the barrier layer 136 may have a higher band gap and a higher polarization rate than the channel layer 132. A two-dimensional electron gas 134 can be induced in the channel layer 132, which has a relatively low polarization rate, through the barrier layer 136. In this respect, the barrier layer 136 may be referred to as a channel supply layer or a two-dimensional electron gas supply layer. The two-dimensional electron gas 134 may be formed within a portion of the channel layer 132 located below the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 may have a very high electron mobility. In some implementations, at least a portion of the barrier layer 136 comprises deuterium (D). For example, the barrier layer 136 can be formed from AlGaN containing deuterium (D).

[0035] The barrier layer 136 of the semiconductor device may include an implantation region 136a containing deuterium (D). The implantation region 136a may refer to a region within the barrier layer 136 containing deuterium (D).

[0036] The injection region 136a may be located in the upper part of the barrier layer 136. The injection region 136a may constitute at least a portion of the upper surface 136_U of the barrier layer 136. The upper surface of the injection region 136a may contact the first protective layer 510, which will be described later. The injection region 136a may overlap with the channel layer 132 in the third direction (Z direction). The injection region 136a may be spaced apart from the upper surface 132_U of the channel layer 132 in the third direction (Z direction), but is not limited thereto. As another example, the injection region 136a may contact the upper surface 132_U of the channel layer 132. Reference will be made later. Figure 7 This will be described in detail. Furthermore, the implantation region 136a may not overlap (or may not overlap) with the gate electrode 155 and the gate semiconductor layer 152, which will be described later, either in the third direction (Z direction) or along the third direction (Z direction). This is likely due to the patterning of the gate semiconductor material layer 152a located on the barrier layer 136 (see...). Figure 15 ) and gate electrode material layer 155a (see Figure 15 The process characteristics for forming the gate semiconductor layer 152 and the gate electrode 155 are described.

[0037] The injection region 136a may contact the side surfaces of the source electrode 173 and the drain electrode 175. For example, the injection region 136a may contact a portion of the side surface of the source electrode 173 and the side surface of the drain electrode 175.

[0038] The injection region 136a may be located between a portion of the barrier layer 136 that overlaps with the gate electrode 155 along the vertical direction and the source electrode 173, and may also be located between the portion of the barrier layer 136 that overlaps with the gate electrode 155 along the vertical direction and the drain electrode 175.

[0039] The implantation region 136a may include deuterium (D). For example, the implantation region 136a may be formed of AlGaN containing deuterium (D). The implantation region 136a may have a different content (at%) (or concentration) of deuterium (D) on the upper surface 132_U away from the channel layer 132. Furthermore, the content (at%) of deuterium (D) in the implantation region 136a may differ from the content (at%) of deuterium (D) in the first protective layer 510, which will be described later. (Refer to later...) Figures 3 to 5 This will be described.

[0040] In some implementations, defects may exist in the crystal structure of the elements constituting the barrier layer 136. For example, when the barrier layer 136 comprises gallium (Ga) and nitrogen (N), point defects, including vacancies, may exist within the crystal structure of gallium (Ga) and nitrogen (N). Furthermore, by applying a gate semiconductor material layer 152a (see [link to implementation]) to the barrier layer 136... Figure 15 ) and gate electrode material layer 155a (see Figure 15 During the patterning process to form the gate semiconductor layer 152 and the gate electrode 155, dangling bonds DB can appear on the upper surface 136_U of the barrier layer 136 (see...). Figure 16 Dangling bonds (DB) can refer to the state in which some bonds between some atoms and surrounding atoms within the crystal structure of barrier layer 136 are broken due to coordination unsaturation. Through the vacancies and / or dangling bonds (DB) in barrier layer 136, a portion of the two-dimensional electron gas 134, etc., can be trapped, or external impurities can be bonded, thereby degrading device characteristics.

[0041] When high-voltage deuterium (HPD) annealing is performed on at least a portion of the barrier layer 136 of a semiconductor device (e.g., implantation region 136a), deuterium (D) can be implanted into vacancies located in the barrier layer 136 and / or by dangling bonds DB (see...). Figure 16 In the region generated by ), deuterium (D) can bond with surrounding elements. Therefore, vacancies and dangling bonds DB (see) exist in the barrier layer 136. Figure 16 The ratio or number of the barrier layer 136 can be reduced, and therefore, the barrier layer 136 can be effectively passivated. This prevents the two-dimensional electron gas 134 from leaking to portions other than the interface between the barrier layer 136 and the channel layer 132, and improves the reliability of the semiconductor device.

[0042] The barrier layer 136 can be formed in a single layer or multiple layers. When the barrier layer 136 is formed in multiple layers, the materials of each layer constituting the multiple layers can have different band gaps. The multiple layers constituting the barrier layer 136 can be configured such that the band gap is larger the closer they are to the channel layer 132.

[0043] Gate electrode 155 may be located on barrier layer 136. Gate electrode 155 may overlap with a portion or region of barrier layer 136 in the third direction (Z direction). Gate electrode 155 may overlap with a portion of drift region DTR of channel layer 132 in the third direction (Z direction). Gate electrode 155 may be located between source electrode 173 and drain electrode 175. Gate electrode 155 may be spaced apart from source electrode 173 and drain electrode 175. For example, gate electrode 155 may be located closer to source electrode 173 relative to drain electrode 175. That is, the spacing between gate electrode 155 and source electrode 173 may be smaller than the spacing between gate electrode 155 and drain electrode 175, but the spacing is not limited to this. Here, the third direction (Z direction) may represent the thickness direction of channel layer 132.

[0044] The gate electrode 155 may include a conductive material. For example, the gate electrode 155 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxide nitride. For example, the gate electrode 155 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaCN). Tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but not limited to these. The gate electrode 155 can be formed as a single layer or multiple layers.

[0045] In some implementations, a hard mask layer may be further included on the gate electrode 155. The hard mask layer may be a patterned gate semiconductor material layer 152a (see [link to relevant documentation]) during the process of forming the gate electrode 155. Figure 15 ) and gate electrode material layer 155a (see Figure 15The hard mask is used during etching of the gate electrode material layer. However, the hard mask layer can be removed depending on the etching conditions during etching or the cleaning conditions after etching. For example, the hard mask layer may include silicon oxide, silicon nitride, silicon oxide nitride (SO4), or a combination thereof.

[0046] The gate semiconductor layer 152 may be located between the barrier layer 136 and the gate electrode 155. For example, the gate semiconductor layer 152 may be located on the barrier layer 136, and the gate electrode 155 may be located on the gate semiconductor layer 152. The gate electrode 155 may be a Schottky contact or an ohmic contact with the gate semiconductor layer 152. The gate semiconductor layer 152 may overlap with the gate electrode 155 in the third direction (Z direction). In this case, the gate semiconductor layer 152 may completely overlap with the gate electrode 155 in the third direction (Z direction), and the upper surface of the gate semiconductor layer 152 may be completely covered by the gate electrode 155. For example, the gate semiconductor layer 152 may also have a planar shape (shape in the planar view) that is substantially the same as the gate electrode 155. However, this disclosure is not limited thereto, and the gate electrode 155 may be positioned to cover at least a portion of the gate semiconductor layer 152.

[0047] The gate semiconductor layer 152 may be located between the source electrode 173 and the drain electrode 175. The gate semiconductor layer 152 may be spaced apart from the source electrode 173 and the drain electrode 175. The gate semiconductor layer 152 may be positioned closer to the source electrode 173 relative to the drain electrode 175. For example, the spacing between the gate semiconductor layer 152 and the source electrode 173 may be smaller than the spacing between the gate semiconductor layer 152 and the drain electrode 175, but is not limited thereto.

[0048] In some implementations, the gate semiconductor layer 152 may overlap with the gate electrode 155 in the third direction (Z direction). For example, the gate semiconductor layer 152 may completely overlap with the gate electrode 155 in the third direction (Z direction). For example, the side surface of the gate semiconductor layer 152 may be aligned with the side surface of the gate electrode 155. However, this disclosure is not limited to this, and the gate semiconductor layer 152 may partially overlap with the gate electrode 155.

[0049] The gate semiconductor layer 152 may comprise one or more materials selected from group III-V materials, such as nitrides comprising Al, Ga, In, B, or combinations thereof. The gate semiconductor layer 152 may be Al... x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1). For example, gate semiconductor layer 152 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. Gate semiconductor layer 152 may include a material having a different band gap than barrier layer 136. For example, gate semiconductor layer 152 may include GaN, and barrier layer 136 may include AlGaN. Gate semiconductor layer 152 may be doped with predetermined impurities. For example, the impurities doped into gate semiconductor layer 152 may be p-type dopants that can provide holes. For example, gate semiconductor layer 152 may include GaN doped with p-type impurities. That is, gate semiconductor layer 152 may be formed as a p-GaN layer. However, gate semiconductor layer 152 is not limited thereto, and for example, gate semiconductor layer 152 may be a p-AlGaN layer. As another example, gate semiconductor layer 152 may be formed as a multilayer including p-GaN layers and p-AlGaN layers.

[0050] The depletion region DPR can be formed in the channel layer 132 by the gate semiconductor layer 152. The depletion region DPR can be located within the drift region DTR and can have a narrower width than the drift region DTR. When the gate semiconductor layer 152, having a different band gap than the barrier layer 136, is located on the barrier layer 136, the band level of the portion of the barrier layer 136 overlapping with the gate semiconductor layer 152 can be increased. Therefore, the depletion region DPR can be formed in the region of the channel layer 132 that overlaps with or is adjacent to the gate semiconductor layer 152. The depletion region DPR can be a region in the channel path of the channel layer 132 where no two-dimensional electron gas 134 is formed or can have a lower electron concentration than the rest of the region. That is, the depletion region DPR can mean a region where the flow of two-dimensional electron gas 134 is interrupted within the drift region DTR. With the generation of the depletion region DPR, no current flows between the source electrode 173 and the drain electrode 175, and the channel path can be blocked. Therefore, the semiconductor device can have normally-on characteristics.

[0051] For example, a semiconductor device could be a normally-off high electron mobility transistor (HEMT). Figure 1 As shown, under normal conditions where no voltage is applied to the gate electrode 155, the depletion region DPR can exist, and the semiconductor device can be in a turned-off state. Figure 2 As shown, when a voltage higher than the threshold voltage is applied to the gate electrode 155, the depletion region DPR can disappear, and the two-dimensional electron gas 134 can continue without interruption in the drift region DTR. That is, the two-dimensional electron gas 134 can be formed (e.g., continuously) throughout the channel path between the source electrode 173 and the drain electrode 175, and the semiconductor device can be in a conducting state.

[0052] In summary, a semiconductor device may include semiconductor layers with different polarization characteristics, and a semiconductor layer with a relatively large polarization can induce a two-dimensional electron gas 134 in another semiconductor layer forming a heterojunction with it. The two-dimensional electron gas 134 can serve as a channel between the source electrode 173 and the drain electrode 175, and the continuation or interruption of the flow of the two-dimensional electron gas 134 can be controlled by applying a bias voltage to the gate electrode 155. In the gate-off state, the flow of the two-dimensional electron gas 134 is blocked, and thus current can not flow between the source electrode 173 and the drain electrode 175. In the gate-on state, as the flow of the two-dimensional electron gas 134 continues, current can flow between the source electrode 173 and the drain electrode 175.

[0053] The above description refers to a normally-off high electron mobility transistor (HEP) semiconductor device, but this disclosure is not limited thereto. For example, the semiconductor device may be a normally-on high electron mobility transistor. In the case of a normally-on high electron mobility transistor, the gate semiconductor layer 152 may be omitted, and correspondingly, the gate electrode 155 may be directly located on the barrier layer 136. For example, the gate electrode 155 may be in contact with the barrier layer 136. However, this disclosure is not limited thereto, and a gate insulating layer may be further located between the gate electrode 155 and the barrier layer 136. The insulating layer may be formed as a single layer or multiple layers. The gate insulating layer may completely overlap with the gate electrode 155 in the third direction (Z direction), but is not limited thereto.

[0054] In this structure, the two-dimensional electron gas 134 can be used as a channel when no voltage is applied to the gate electrode 155, allowing current to flow between the source electrode 173 and the drain electrode 175. Furthermore, when a negative voltage is applied to the gate electrode 155, a depletion region DPR, in which the flow of the two-dimensional electron gas 134 is interrupted, can be generated at the lower part of the gate electrode 155. Therefore, it should be understood that this disclosure also applies to normally-on devices.

[0055] The seed layer 121, superlattice layer 124, high-resistivity layer 126, channel layer 132, barrier layer 136, and gate semiconductor layer 152, as described above, can be sequentially stacked on the substrate 110. In a semiconductor device, at least one of the seed layer 121, superlattice layer 124, high-resistivity layer 126, channel layer 132, barrier layer 136, and gate semiconductor layer 152 can be omitted. The seed layer 121, superlattice layer 124, high-resistivity layer 126, channel layer 132, barrier layer 136, and gate semiconductor layer 152 can be made of the same base semiconductor material, and the material composition ratio of each layer can be different considering the function of each layer and the performance required by the semiconductor device.

[0056] A protective layer 500 may be located on the barrier layer 136 and the gate electrode 155. The protective layer 500 may cover the upper and side surfaces of the gate electrode 155 and the side surface of the gate semiconductor layer 152. The lower surface of the protective layer 500 may contact the barrier layer 136 and the gate electrode 155. Therefore, the barrier layer 136, the gate semiconductor layer 152, and the gate electrode 155 can be protected by the protective layer 500.

[0057] The protective layer 500 of the semiconductor device may include a first protective layer 510 and a second protective layer 520 located on the first protective layer 510.

[0058] The first protective layer 510 may be located on the barrier layer 136 and the gate electrode 155. For example, the first protective layer 510 may be located directly on the upper surface 136-U of the barrier layer 136. The first protective layer 510 may cover the upper surface and side surface of the gate electrode 155, as well as the side surface of the gate semiconductor layer 152. The lower surface of the first protective layer 510 may contact the upper surface 136-U of the barrier layer 136, the side surface of the gate electrode 155, and the upper surface of the gate electrode 155. For example, the lower surface of the first protective layer 510 may contact the implantation region 136a of the barrier layer 136. Therefore, the barrier layer 136, the gate semiconductor layer 152, and the gate electrode 155 may be protected by the first protective layer 510. However, this disclosure is not limited thereto, and for example, the gate electrode 155 may penetrate the first protective layer 510 to connect to the gate semiconductor layer 152, and the first protective layer 510 may not cover the upper surface of the gate electrode 155. As another example, the lower surface of the first protective layer 510 may be in contact with the gate semiconductor layer 152.

[0059] Furthermore, the first protective layer 510 may be located on the side surface of the source electrode 173 and the side surface of the drain electrode 175. For example, the first protective layer 510 may cover at least a portion of the side surface of the source electrode 173 and the side surface of the drain electrode 175.

[0060] The first protective layer 510 may include deuterium (D). The first protective layer 510 may be formed of a first insulating material containing deuterium (D). For example, the first insulating material may include, but is not limited to, an oxide in which deuterium (D) is implanted, such as silicon oxide (SiO2) or aluminum oxide (Al2O3). As another example, the first protective layer 510 may include a nitride such as silicon nitride (SiN) or an oxide nitride such as silicon nitride oxide (SiON) in which deuterium (D) is implanted.

[0061] This is likely due to the process characteristics of forming a first protective layer 510 on the barrier layer 136 and the gate electrode 155, and performing high-voltage deuterium (HPD) annealing on the first protective layer 510 and the barrier layer 136. Specifically, this is achieved by patterning the gate semiconductor material layer 152a located on the barrier layer 136 (see...). Figure 15 ) and gate electrode material layer 155a (see Figure 15 In the process of patterning the gate semiconductor layer 152 and the gate electrode 155, and in the process of forming the first protective layer 510 on the exposed barrier layer 136, vacancies, dangling bonds DB (see...) Figure 16 Defects such as those present in the first protective layer 510 and the barrier layer 136 may occur. According to some implementations of this disclosure, when high-pressure deuterium (HPD) annealing is performed on the first protective layer 510 and the barrier layer 136 after its formation, deuterium (D) can be injected into vacancies and / or dangling bonds DB in the first protective layer 510 and the barrier layer 136 (see […]). Figure 16 In other words, the first protective layer 510 can be formed of a material containing deuterium (D). Therefore, the reliability of the semiconductor device can be improved.

[0062] Compared to protium (H), deuterium (D) can have a stronger bonding force with silicon (Si). Therefore, when the first protective layer 510 of the semiconductor device comprises silicon oxide (SiO2), the bonding force between deuterium (D) and silicon (Si) is greater than the bonding force between protium (H) and silicon (Si), and thus, deuterium (D) can relatively easily bond with surrounding atoms in the first protective layer 510.

[0063] In some implementations, the deuterium (D) content (at%) of the first protective layer 510 can vary as a function of distance from the upper surface 136_U of the barrier layer 136. For example, the deuterium (D) content (at%) of the first protective layer 510 can increase with distance from the upper surface 136_U of the barrier layer 136, but the content is not limited thereto. Furthermore, the deuterium (D) content (at%) of the first protective layer 510 can differ from the deuterium (D) content (at%) of the barrier layer 136. Reference will be made later. Figures 3 to 5 This will be described.

[0064] In some implementations, the thickness of the first protective layer 510 along the third direction (Z direction) may be less than the thickness of the second protective layer 520 along the third direction (Z direction). For example, the thickness of the first protective layer 510 along the third direction (Z direction) may be 200 nm or less. The thickness of the first protective layer 510 in the third direction (Z direction) may be 100 nm or less. By performing high-pressure deuterium (HPD) annealing on the first protective layer 510 and the barrier layer 136 when the thickness of the first protective layer 510 is within such a range, deuterium (D) can be easily injected into the first protective layer 510 and the barrier layer 136.

[0065] The second protective layer 520 may be located on the first protective layer 510. The second protective layer 520 may be directly located on the first protective layer 510. The second protective layer 520 may cover the first protective layer 510. The second protective layer 520 may be located between the first protective layer 510 and the field dispersion layer 177, which will be described later. The lower surface of the second protective layer 520 may contact the first protective layer 510, and the upper surface of the second protective layer 520 may contact the field dispersion layer 177, which will be described later. Furthermore, the second protective layer 520 may be located on the side surface of the source electrode 173 and the side surface of the drain electrode 175. That is, the second protective layer 520 may cover at least a portion of the side surfaces of the source electrode 173 and the drain electrode 175.

[0066] The second protective layer 520 may include an insulating material different from the first protective layer 510. The second protective layer 520 may be formed of a second insulating material that does not contain deuterium (D) (e.g., substantially does not contain deuterium (D)). For example, the second insulating material may include, but is not limited to, silicon nitride (SiN) or silicon oxide nitride (SiON) that does not contain deuterium (D). As another example, the second insulating material may include oxides that do not contain deuterium (D), such as silicon oxide (SiO2) or aluminum oxide (Al2O3). Here, the absence of deuterium (D) in the second protective layer 520 may be a result of not performing a high-pressure deuterium (HPD) annealing process on the second protective layer 520. That is, the high-pressure deuterium (HPD) annealing process may be performed prior to the process forming the second protective layer 520, and accordingly, deuterium (D) may not be injected into the material constituting the second protective layer 520.

[0067] It should be understood that, without departing from the scope of this disclosure, trace amounts of deuterium may be present in layers that do not contain or are substantially free of deuterium (e.g., as a result of diffusion from adjacent layers containing deuterium, separate from the infusion of deuterium in the HPD annealing process).

[0068] In some implementations, the thickness of the second protective layer 520 along the third direction (Z direction) may be greater than the thickness of the first protective layer 510 along the third direction (Z direction). Accordingly, after performing a high-voltage deuterium (HPD) annealing process on the first protective layer 510 and the barrier layer 136, the second protective layer 520 is formed with sufficient thickness, and thus, the barrier layer 136, the gate semiconductor layer 152, and the gate electrode 155 can be effectively protected.

[0069] exist Figure 1 and Figure 2 The diagram shows that the second protective layer 520 is formed as a single layer, but it is not limited to this; the second protective layer 520 may be formed as two or more layers.

[0070] exist Figure 1 and Figure 2The diagram shows that the protective layer 500 is formed as a double layer, but it is not limited to this. The protective layer 500 can be formed as a triple layer or a single layer.

[0071] The source electrode 173 and the drain electrode 175 can be located on the channel layer 132. The source electrode 173 and the drain electrode 175 can be in direct contact with the channel layer 132 and can be electrically connected to the channel layer 132.

[0072] Source electrode 173 and drain electrode 175 may extend in a second direction (Y direction). Source electrode 173 and drain electrode 175 may be spaced apart from each other, and gate electrode 155 and gate semiconductor layer 152 may be located between source electrode 173 and drain electrode 175. Gate electrode 155 and gate semiconductor layer 152 may be spaced apart from source electrode 173 and drain electrode 175. For example, source electrode 173 may be electrically connected to channel layer 132 on a first side of gate electrode 155, and drain electrode 175 may be electrically connected to channel layer 132 on a second side of gate electrode 155. Source electrode 173 and drain electrode 175 may be located outside the drift region DTR of channel layer 132. The interface between source electrode 173 and channel layer 132 may be a first side edge of drift region DTR. Similarly, the interface between drain electrode 175 and channel layer 132 may be a second side edge of drift region DTR.

[0073] However, the arrangement is not limited to this. The channel layer 132 may not be recessed, and the source electrode 173 and drain electrode 175 may be located on the upper surface 132_U of the channel layer 132 and the upper surface 136_U of the barrier layer 136. The bottom surfaces of the source electrode 173 and drain electrode 175 may contact the upper surface 132_U of the channel layer 132. The portions of the channel layer 132 and the barrier layer 136 that contact the source electrode 173 and drain electrode 175 may be highly doped. Therefore, charge carriers that have passed through the two-dimensional electron gas 134 may pass through the highly doped portion of the channel layer 132, i.e., the upper part of the two-dimensional electron gas 134, and then be transferred to the source electrode 173 and drain electrode 175. The source electrode 173 and drain electrode 175 may not be in direct contact with the two-dimensional electron gas 134 in the horizontal direction. Here, the horizontal direction may refer to the direction parallel to the upper surface 136_U of the channel layer 132 or the barrier layer 136.

[0074] More specifically, the trenches 141 and 143 penetrate the protective layer 500 and the barrier layer 136 and cause the upper surface 132_U of the channel layer 132 to be recessed (see...). Figure 20 The source electrode 173 and drain electrode 175 can be located on opposite sides of the gate electrode 155 and spaced apart from each other. The source electrode 173 and drain electrode 175 can be located in trenches 141 and 143 located on opposite sides of the gate electrode 155, respectively (see...). Figure 20 The source electrode 173 and drain electrode 175 can be formed to fill trenches 141 and 143 (see...). Figure 20 Within the trench, the source electrode 173 and the drain electrode 175 can contact the channel layer 132 and the barrier layer 136. The channel layer 132 can form the bottom surface and sidewalls of the trench, and the barrier layer 136 can form the sidewalls of the trench. Furthermore, the source electrode 173 and the drain electrode 175 can contact the side surface of the barrier layer 136. That is, the source electrode 173 and the drain electrode 175 can cover the side surfaces of the channel layer 132 and the barrier layer 136.

[0075] In some implementations, the source electrode 173 and drain electrode 175 may cover at least a portion of the side surface of the protective layer 500. For example, the source electrode 173 and drain electrode 175 may cover the side surface of the protective layer 500. The upper surfaces of the source electrode 173 and drain electrode 175 may protrude further than the upper surface of the protective layer 500. Furthermore, at least one of the source electrode 173 and drain electrode 175 may cover at least a portion of the upper surface of the protective layer 500. However, this disclosure is not limited thereto; the source electrode 173 and drain electrode 175 may cover at least a portion of the side surface of the protective layer 500, but may not cover the remaining portion of the side surface of the protective layer 500. In this case, the remaining portion of the protective layer 500 may be located on the upper surfaces of the source electrode 173 and drain electrode 175. Reference will be made later. Figure 10 and Figure 11 Please describe this in detail.

[0076] The source electrode 173 and drain electrode 175 may include conductive materials. For example, the source electrode 173 and drain electrode 175 may include metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, or conductive metal oxynitrides. For example, the source electrode 173 and drain electrode 175 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (Ta). The materials used are, but are not limited to, CN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The source electrode 173 and drain electrode 175 can be formed in a single layer or multiple layers. The source electrode 173 and drain electrode 175 can be in ohmic contact with the channel layer 132. The regions in contact with the source electrode 173 and drain electrode 175 in the channel layer 132 can be doped with a relatively high concentration compared to other regions.

[0077] Figure 1 and Figure 2 The semiconductor device shown includes a pair of source electrodes 173 and drain electrodes 175, but the number of source electrodes 173 and drain electrodes 175 is not limited thereto. For example, the source electrodes 173 may include a plurality of source electrodes sequentially stacked on the channel layer 132 in a third direction (Z direction), and the drain electrodes 175 may include a plurality of drain electrodes sequentially stacked on the channel layer 132 in a third direction (Z direction). Reference will be made later. Figure 9 Please describe this configuration in detail.

[0078] The field dispersion layer 177 may be located between the gate electrode 155 and the drain electrode 175. The field dispersion layer 177 may be located between the source electrode 173 and the drain electrode 175. The field dispersion layer 177 may be located on the guard layer 500. For example, the field dispersion layer 177 may be located on the second guard layer 520. That is, the second guard layer 520 may be located between the first guard layer 510 and the field dispersion layer 177. The field dispersion layer 177 may overlap with the channel layer 132 in the third direction (Z direction).

[0079] The field dispersion layer 177 may comprise the same material as the source electrode 173 and may be located on the same layer as the source electrode 173. The field dispersion layer 177 may be formed simultaneously with the source electrode 173 in the same process. For example, the boundary between the field dispersion layer 177 and the source electrode 173 may be unclear, and the field dispersion layer 177 may be integrally formed with the source electrode 173. However, the construction is not limited to this, and the field dispersion layer 177 may be a separate component separate from the source electrode 173. Furthermore, the field dispersion layer 177 may be located in a different layer than the source electrode 173 and may be formed using a different process.

[0080] The field dispersion layer 177 can be used to disperse the electric field concentrated around the gate electrode 155. For example, in the gate-off state, the two-dimensional electron gas 134 can exist at a very high concentration in the portion of the channel layer 132 located between the gate electrode 155 and the source electrode 173, and in the portion of the channel layer 132 located between the gate electrode 155 and the drain electrode 175. In this case, the electric field can be concentrated on the gate electrode 155 or the gate semiconductor layer 152. At the same time, the gate electrode 155 and the gate semiconductor layer 152 are susceptible to the influence of the electric field, so when the electric field is concentrated, the leakage current increases and the breakdown voltage of the semiconductor device decreases. At this time, the electric field concentrated around the gate electrode 155 or the gate semiconductor layer 152 can be dispersed by the field dispersion layer 177, so that the leakage current can be reduced and the breakdown voltage can be increased.

[0081] Figure 1 and Figure 2 The semiconductor device shown includes a field dispersion layer 177, but the number of field dispersion layers 177 is not limited thereto. For example, the field dispersion layer 177 may include multiple field dispersion layers located on a protective layer 500. As another example, multiple protective layers may be located on the protective layer 500, and multiple field dispersion layers located on different protective layers may be included.

[0082] The barrier layer 136 of the semiconductor device may include an implantation region 136a containing deuterium (D), and the first protective layer 510 may contain deuterium (D). Therefore, defects (such as vacancies, dangling bonds DB, etc.) generated during the formation of the barrier layer 136 and the first protective layer 510 can be improved by bonding with deuterium (D). Deuterium (D) can be implanted onto the first protective layer 510 and the barrier layer 136 through a high-voltage deuterium (HPD) annealing process. Therefore, the reliability of the semiconductor device can be improved.

[0083] Further references will be made below. Figure 3 , Figures 4A to 4D and Figure 5 Describes barrier and protective layers of semiconductor devices according to some embodiments of this disclosure.

[0084] Figure 3 , Figures 4A to 4D and Figure 5 This is a graph showing the deuterium content in the barrier layer and the protective layer of the semiconductor device. As described above, the first protective layer 510 of the implantation region 136a and the barrier layer 136 may include deuterium (D), and the second protective layer 520 may not contain deuterium (D).

[0085] First, further reference Figure 3 The first content (at%) of deuterium (D) in the implantation region 136a of the barrier layer 136 of the semiconductor device can increase with distance from the upper surface 132_U of the channel layer 132. For example, the first content (at%) of deuterium (D) at the lower surface of the implantation region 136a can have a minimum value N1min, and the first content (at%) of deuterium (D) at the upper surface of the implantation region 136a can have a maximum value N1max. The rate of increase of the first content (at%) of deuterium (D) per unit distance in the implantation region 136a can increase with distance from the upper surface 132_U of the channel layer 132. Here, the rate of increase of the first content (at%) of deuterium (D) per unit distance in the implantation region 136a can refer to the change in content per distance in the vertical direction (e.g., the thickness direction of the channel layer 132, which is referred to below as the "third direction (Z direction)"). For example, the first content (at%) of deuterium (D) in the injection region 136a may increase exponentially away from the upper surface 132_U of the channel layer 132. However, this disclosure is not limited thereto; the rate of increase of the first content (at%) of deuterium (D) per unit distance in the injection region 136a may be constant, or it may decrease away from the upper surface 132_U of the channel layer 132. As another example, the rate of increase of the first content (at%) of deuterium (D) per unit distance in the injection region 136a may be constant.

[0086] Furthermore, the second content (at%) of deuterium (D) in the first protective layer 510 can increase away from the upper surface 132_U of the channel layer 132. That is, the second content (at%) of deuterium (D) in the first protective layer 510 can increase away from the upper surface 136_U of the barrier layer 136. For example, the second content (at%) of deuterium (D) at the lower surface of the first protective layer 510 can have a minimum value N2min, and the second content (at%) of deuterium (D) at the upper surface 510_U of the first protective layer 510 can have a maximum value N2max. The rate of increase of the second content (at%) of deuterium (D) per unit distance in the first protective layer 510 can increase away from the upper surface 132_U of the channel layer 132. However, this disclosure is not limited thereto, and the rate at which the second content (at%) of deuterium (D) in the first protective layer 510 increases per unit distance may be constant or may decrease as it moves away from the upper surface 132_U of the channel layer 132.

[0087] In some implementations, the second content (at%) of deuterium (D) in the first protective layer 510 may be greater than or equal to the first content (at%) of deuterium (D) in the injection region 136a. For example, as Figure 3 As shown, the minimum value N2min of the second content (at%) of deuterium (D) included in the first protective layer 510 can be substantially the same as the maximum value N1max of the first content (at%) of deuterium (D) included in the injection region 136a. Furthermore, the maximum value N2max of the second content (at%) of deuterium (D) included in the first protective layer 510 can be greater than the maximum value N1max of the first content (at%) of deuterium (D) included in the injection region 136a, and the minimum value N2min of the second content (at%) of deuterium (D) included in the first protective layer 510 can be greater than the minimum value N1min of the first content (at%) of deuterium (D) included in the injection region 136a. However, this disclosure is not limited thereto; at one or more locations in the injection region 136a and the first protective layer 510, the first content (at%) of deuterium (D) in the injection region 136a can be greater than the second content (at%) of deuterium (D) in the first protective layer 510.

[0088] Meanwhile, the second protective layer 520 may not contain deuterium (D). Therefore, the content (at%) of deuterium (D) can vary discontinuously at the interface between the first protective layer 510 and the second protective layer 520.

[0089] In some implementations, the distribution of the first deuterium (D) content (at%) in the injection region 136a and the second deuterium (D) content (at%) in the first protective layer 510 can be attributed to the characteristics of the high-pressure deuterium (HPD) annealing process. Figure 3 In this paper, the distribution of the first content (at%) of deuterium (D) in the injection region 136a and the second content (at%) of deuterium (D) in the first protective layer 510 are described as examples, but are not limited thereto.

[0090] As another example, see Figure 4AThe minimum value N2min of the second content (at%) of deuterium (D) included in the first protective layer 510 can be greater than the maximum value N1max of the first content (at%) of deuterium (D) included in the injection region 136a. For example, discontinuous changes in the second content (at%) of deuterium (D) can occur at the interface between the injection region 136a and the first protective layer 510. In this case, the maximum value N2max of the second content (at%) of deuterium (D) included in the first protective layer 510 can be greater than the maximum value N1max of the first content (at%) of deuterium (D) included in the injection region 136a, and the minimum value N2min of the second content (at%) of deuterium (D) included in the first protective layer 510 can be greater than the minimum value N1min of the first content (at%) of deuterium (D) included in the injection region 136a.

[0091] As yet another example, see reference Figure 4B The first protective layer 510 may include a section in which the second content (at%) of deuterium (D) is constant. For example, the second content (at%) of the first protective layer 510 may include a constant section.

[0092] As another example, the first protective layer 510 may include an inflection point IFC where the rate of change of the second content (at%) per unit distance changes. For example, the first protective layer 510 may include a segment where the change of the second content (at%) per unit distance increases and an inflection point IFC thereafter where the rate of change of the second content (at%) per unit distance decreases. Accordingly, the rate of change of the second content (at%) of deuterium (D) per unit distance of the first protective layer 510 first increases and then decreases with distance from the upper surface 132_U of the channel layer 132.

[0093] However, this disclosure is not limited thereto, and for example, such as Figure 4D As shown, the rate at which the second content (at%) of deuterium (D) in the first protective layer 510 increases per unit distance can decrease as the upper surface 132_U of the channel layer 132 moves away from the channel layer 132.

[0094] As yet another example, see reference Figure 5 The minimum value N2min of the second deuterium (D) content (at%) included in the first protective layer 510 can be less than the maximum value N1max of the first deuterium (D) content (at%) included in the injection region 136a. For example, the first deuterium (D) content (at%) at the upper surface of the injection region 136a can be greater than the second content (at%) at the lower surface of the first protective layer 510. In this case, the deuterium content (at%) can have a peak PK at the interface between the injection region 136a and the first protective layer 510. This may be due to the characteristics of the high-pressure deuterium (HPD) annealing process.

[0095] exist Figure 5 In the example, the maximum value N2max of the second content (at%) of deuterium (D) included in the first protective layer 510 can be greater than the maximum value N1max of the first content (at%) of deuterium (D) included in the injection region 136a, and the minimum value N2min of the second content (at%) of deuterium (D) included in the first protective layer 510 can be greater than the minimum value N1min of the first content (at%) of deuterium (D) included in the injection region 136a.

[0096] However, this disclosure is not limited to the foregoing example, and the distributions of the first content (at%) of deuterium (D) included in the injection region 136a and the second content (at%) of deuterium (D) included in the first protective layer 510 may be varied.

[0097] In the following text, reference will be made to Figures 6 to 13 Examples of semiconductor devices according to some implementations of this disclosure are described. Figures 6 to 13 This is a cross-sectional view showing a semiconductor device.

[0098] Figures 6 to 13 It shows Figures 1 to 5 Examples of various modifications to the semiconductor device are shown. Figures 6 to 13 The example shown has the same Figures 1 to 5 The examples shown are essentially the same parts; therefore, their descriptions will be omitted, and the differences will be primarily described. Furthermore, the same reference numerals will be used for the same parts as in the previous examples. Regarding... Figures 1 to 5 The provided description also applies to Figures 6 to 13 Unless otherwise stated or the context suggests otherwise.

[0099] refer to Figure 6 The barrier layer 136 of the semiconductor device may not contain deuterium (D). That is, the implantation region 136a may not be located in the barrier layer 136. Accordingly, the upper surface 136_U of the barrier layer 136 without deuterium (D) may contact the first protective layer 510. This may be due to the process characteristics of implanting only deuterium (D) into the first protective layer 510 during the high-pressure deuterium (HPD) annealing process performed at the interface of the first protective layer 510.

[0100] refer to Figure 7 The implantation region 136a of the semiconductor device can contact the channel layer 132.

[0101] In some implementations, the thickness of the implantation region 136a along the third direction (Z direction) can be substantially the same as the thickness of the barrier layer 136 along the third direction (Z direction). For example, the lower surface of the implantation region 136a can contact the channel layer 132, and the upper surface of the implantation region 136a can contact the first protective layer 510. The implantation region 136a can be located between the source electrode 173 and the gate electrode 155, and between the drain electrode 175 and the gate electrode 155. Therefore, the barrier layer 136 can include the implantation region 136a containing deuterium (D) and the barrier region 136b not containing deuterium (D). The portion of the implantation region 136a located between the source electrode 173 and the gate electrode 155 and the portion of the implantation region 136a located between the drain electrode 175 and the gate electrode 155 can be separated from each other along a first direction (X direction). Electrodes 155, 173, 175 may be spaced apart from each other along a "lateral" direction (i.e., along a first direction (X direction) and / or a second direction (Y direction)).

[0102] In having Figure 7 Among the various implementation methods of the configuration, it is understandable to refer to [the relevant documentation / reference]. Figures 3 to 5 The description of the first content (at%) of deuterium (D) can be applied to the content (at%) of deuterium (D) included in the injection zone 136a.

[0103] refer to Figure 8 The protective layer 500 of a semiconductor device can be formed as a single layer.

[0104] In some implementations, the protective layer 500 may be located on the barrier layer 136. For example, the protective layer 500 may be located directly on the upper surface of the injection region 136a of the barrier layer 136. The protective layer 500 may include a second insulating material that does not contain deuterium (D). For example, the protective layer 500 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxide nitride (SiON), or combinations thereof that do not contain deuterium (D). Figures 1 to 5 Some implementations differ, which may be due to the patterning of the gate semiconductor material layer 152a located on the barrier layer 136 (see...). Figure 15 ) and gate electrode material layer 155a (see Figure 15 This is due to the process characteristics of performing a high-pressure deuterium (HPD) annealing process on the upper surface 136_U of the exposed barrier layer 136. Therefore, the dangling bonds DB formed in the upper part of the barrier layer 136 (see...) can be effectively removed. Figure 16 (See below for reference) Figures 22 to 25 Please describe this in detail.

[0105] refer to Figure 9The semiconductor device may also include an upper protective layer 180 located on the protective layer 500. In some implementations (e.g., in conjunction with the upper protective layer 180), the protective layer 500 may be formed as a single layer.

[0106] In some implementations, the protective layer 500 may include deuterium (D). The protective layer 500 may be formed of a first insulating material containing deuterium (D). For example, the insulating material may include, but is not limited to, an oxide in which deuterium (D) is implanted, such as silicon oxide (SiO2) or aluminum oxide (Al2O3). As another example, the protective layer 500 may include a nitride such as silicon nitride (SiN) or an oxide nitride such as silicon nitride oxide (SiON) in which deuterium (D) is implanted. Figure 9 The text describes the protective layer 500 as being formed as a single layer, but is not limited to this, and is related to... Figures 1 to 5 As in the example, the protective layer 500 may include a first protective layer 510 located on the barrier layer 136 and containing deuterium (D), and a second protective layer 520 located on the first protective layer 510 and not containing deuterium (D).

[0107] In some implementations, the upper protective layer 180 may cover the upper surface of the protective layer 500 and the upper and side surfaces of the first field dispersion layer 177a. In some implementations, the upper protective layer 180 may be formed of a second insulating material that does not contain deuterium (D). For example, the second insulating material may include, but is not limited to, silicon nitride (SiN) or silicon oxide nitride (SiON) that do not contain deuterium (D). As another example, the second insulating material may include oxides that do not contain deuterium (D), such as silicon oxide (SiO2) or aluminum oxide (Al2O3). Here, the absence of deuterium (D) in the upper protective layer 180 may be due to the absence of a high-pressure deuterium (HPD) annealing process on the upper protective layer 180, or it may mean that an HPD annealing process was not performed on the upper protective layer 180. For example, a high-pressure deuterium (HPD) annealing process may be performed before the formation of the upper protective layer 180, and accordingly, deuterium (D) may not be injected into the material constituting the upper protective layer 180.

[0108] like Figure 9As shown, the source electrode 173 and / or drain electrode 175 of the semiconductor device can be multiple. The source electrode 173 of the semiconductor device may include a first source electrode 173a and a second source electrode 173b sequentially stacked on the channel layer 132 in a third direction (Z direction), and the drain electrode 175 may include a first drain electrode 175a and a second drain electrode 175b sequentially stacked on the channel layer 132 in a third direction (Z direction). The first source electrode 173a and the first drain electrode 175a can penetrate the protective layer 500 and the barrier layer 136 to connect to the channel layer 132. Each of the second source electrode 173b and the second drain electrode 175b can penetrate the upper protective layer 180 to connect to the first source electrode 173a and the first drain electrode 175a. Each of the first source electrode 173a and the first drain electrode 175a may include the same material as the second source electrode 173b and the second drain electrode 175b, but may include different materials in some implementations.

[0109] The field dispersion layer 177 of the semiconductor device can be provided in multiple quantities. For example, it may include a first field dispersion layer 177a on the protective layer 500 and a second field dispersion layer 177b on the upper protective layer 180. The first field dispersion layer 177a may be located between the protective layer 500 and the upper protective layer 180. The first field dispersion layer 177a may include the same material as the first source electrode 173a. The first field dispersion layer 177a may be formed by the same process as the first source electrode 173a and is located on a layer that is at least a portion of the same as the first source electrode 173a. The second field dispersion layer 177b may be located between the upper protective layer 180 and the capping layer 190. The second field dispersion layer 177b may include the same material as the second source electrode 173b. The second field dispersion layer 177b may be formed by the same process as the second source electrode 173b and is located on a layer that is at least a portion of the same as the second source electrode 173b. However, this disclosure is not limited thereto, and the field dispersion layers 177a and 177b may be located in different layers from the source electrodes 173a and 173b, and may be formed in different processes.

[0110] like Figure 9 As shown, the semiconductor device, according to some implementations, may also include a cover layer 190 located on the upper protective layer 180.

[0111] At least a portion of the upper and side surfaces of the second source electrode 173b and the second drain electrode 175b may be covered by the capping layer 190. The second field dispersion layer 177b may be covered by the capping layer 190. The capping layer 190 is configured to protect the semiconductor device from external stresses (e.g., moisture) and may be located in the uppermost layer of the semiconductor device. For example, the capping layer 190 may be located in the outermost layer of the semiconductor device. The source electrode 173 and the drain electrode 175 may be connected to external wiring, and for connection to wiring, the capping layer 190 may include pad openings 191 and 193. A first pad opening 191 overlapping at least a portion of the source electrode 173 may be formed in the capping layer 190. Through the first pad opening 191, the upper surface of the source electrode 173 may be exposed to the outside. Although not shown in the figures, a wire electrically connected to the source electrode 173 through the first pad opening 191 may be further formed. A second pad opening 193 overlapping at least a portion of the drain electrode 175 may be formed in the capping layer 190. The upper surface of the drain electrode 175 can be exposed to the outside through the second pad opening 193. Although not shown in the figures, a wire electrically connected to the drain electrode 175 through the second pad opening 193 can be further formed.

[0112] The capping layer 190 may include an insulating material. For example, the capping layer 190 may include materials such as polyimide (PI), SiO2, SiN, SiON, etc. The capping layer 190 may be formed as a single layer or multiple layers.

[0113] refer to Figure 10 and Figure 11 According to some implementations, the gate electrode 155 of the semiconductor device can penetrate the protective layer 500 to connect to the gate semiconductor layer 152.

[0114] In some implementations, the gate electrode 155 may penetrate the protective layer 500. For example, the gate electrode 155 may penetrate the first protective layer 510 and the second protective layer 520 on the gate semiconductor layer 152. Accordingly, at least a portion of the side surface of the gate electrode 155 may contact the protective layer 500. The gate electrode 155 may overlap with the gate semiconductor layer 152 in the third direction (Z direction). The lower surface of the gate electrode 155 may contact the upper surface of the gate semiconductor layer 152. The gate electrode 155 may be located on at least a portion of the gate semiconductor layer 152. For example, the gate electrode 155 may be located on a portion of the gate semiconductor layer 152, and the first protective layer 510 may be located on the remaining portion of the gate semiconductor layer 152. For example, the upper surface of the gate semiconductor layer 152 may contact the gate electrode 155 and the first protective layer 510. However, this disclosure is not limited thereto, and the gate semiconductor layer 152 may completely overlap with the gate electrode 155.

[0115] In some implementations, the protective layer 500 may cover at least a portion of the barrier layer 136 and the gate semiconductor layer 152. Furthermore, a field dispersion layer 177 may be located on the protective layer 500. For example, the field dispersion layer 177 may be located between the gate electrode 155 and the drain electrode 175. The field dispersion layer 177 may be connected to the gate electrode 155 or connected to the source electrode 173. However, this disclosure is not limited thereto, and the field dispersion layer 177 may not be connected to the gate electrode 155 and the source electrode 173. Furthermore, the field dispersion layer 177 may extend in one direction. For example, the field dispersion layer 177 may extend in a direction parallel to the gate electrode 155, the source electrode 173, and the gate electrode 155.

[0116] In this case, such as Figure 10 As shown, the barrier layer 136 may include an injection region 136a containing deuterium (D). However, this disclosure is not limited thereto, and as... Figure 11 As shown, the barrier layer 136 may not include the injection region 136a containing deuterium (D).

[0117] In such Figure 10 and Figure 11 In the configuration shown, a high-pressure deuterium (HPD) annealing process can be performed on at least a portion of the barrier layer 136 and the first protective layer 510, and accordingly, at least a portion of the first protective layer 510 and / or the barrier layer 136 may include deuterium (D), and the second protective layer 520 may not contain deuterium (D). Its description will be omitted because it is related to... Figures 1 to 5 The examples are basically the same.

[0118] refer to Figure 12 According to some implementations, the protective layer 500_1 of the semiconductor device may include a third protective layer 530 located on the barrier layer 136 and not containing deuterium (D) and a fourth protective layer 540 located on the third protective layer 530 and containing deuterium (D).

[0119] In some implementations, the third protective layer 530 may be located on the barrier layer 136 and the gate electrode 155. For example, the third protective layer 530 may be located directly on the upper surface 136-U of the barrier layer 136. The third protective layer 530 may cover the upper and side surfaces of the gate electrode 155, as well as the side surface of the gate semiconductor layer 152. The lower surface of the third protective layer 530 may contact the upper surface 136-U of the barrier layer 136, the side surface of the gate electrode 155, and the upper surface of the gate electrode 155. For example, the lower surface of the third protective layer 530 may contact the implantation region 136a of the barrier layer 136. Therefore, the barrier layer 136, the gate semiconductor layer 152, and the gate electrode 155 may be protected by the third protective layer 530. However, this disclosure is not limited thereto; the gate electrode 155 may penetrate the third protective layer 530 to connect to the gate semiconductor layer 152, and the third protective layer 530 may not cover the upper surface of the gate electrode 155. Alternatively, or additionally, the lower surface of the third protective layer 530 may contact the gate semiconductor layer 152. Furthermore, the third protective layer 530 may be located on the side surfaces of the source electrode 173 and the drain electrode 175. For example, the third protective layer 530 may cover at least a portion of the side surfaces of the source electrode 173 and the drain electrode 175.

[0120] The third protective layer 530 may be formed of an insulating material that does not contain deuterium (D). For example, the third protective layer 530 may include oxides that do not contain deuterium (D), such as silicon oxide (SiO2) or aluminum oxide (Al2O3). However, this disclosure is not limited thereto, and as another example, the third protective layer 530 may include nitrides that do not contain deuterium (D), such as silicon nitride (SiN), or oxynitrides such as silicon nitride (SiON).

[0121] The fourth protective layer 540 may be located on the third protective layer 530. The fourth protective layer 540 may be located directly on the third protective layer 530. The fourth protective layer 540 may cover the third protective layer 530. The fourth protective layer 540 may be located between the third protective layer 530 and the field dispersion layer 177, which will be described later. The lower surface of the fourth protective layer 540 may contact the third protective layer 530, and the upper surface of the fourth protective layer 540 may contact the field dispersion layer 177. Furthermore, the fourth protective layer 540 may be located on the side surface of the source electrode 173 and the side surface of the drain electrode 175. That is, the fourth protective layer 540 may cover at least a portion of the side surfaces of the source electrode 173 and the drain electrode 175.

[0122] In some implementations, the fourth protective layer 540 may comprise an insulating material different from the third protective layer 530. The fourth protective layer 540 may be formed of an insulating material containing deuterium (D). For example, the fourth protective layer 540 may comprise, but is not limited to, silicon nitride (SiN) or silicon oxide nitride (SiON) containing deuterium (D). As another example, the fourth protective layer 540 may comprise an oxide containing deuterium (D), such as silicon oxide (SiO2) or aluminum oxide (Al2O3). In some implementations, the deuterium (D) content (at%) of the fourth protective layer 540 may vary as a function of the distance from the upper surface 136 of the barrier layer 136, but is not limited to this.

[0123] Figure 13 The example shown has the same Figure 9 The examples shown are essentially the same parts, therefore their descriptions will be omitted, and the differences will be mainly described. Furthermore, the same reference numerals will be used for the same parts as in the previous examples.

[0124] refer to Figure 13 The protective layer 500_2 of the semiconductor device can be formed as a single layer. In some implementations, the protective layer 500_2 can be formed of an insulating material that does not contain deuterium (D). For example, the protective layer 500_2 can include oxides that do not contain deuterium (D), such as silicon oxide (SiO2) or aluminum oxide (Al2O3). However, this disclosure is not limited thereto, and as another example, the protective layer 500_2 can include nitrides such as silicon nitride (SiN) or oxide nitrides such as silicon oxide nitride (SiON), which do not contain deuterium (D).

[0125] In some implementations, the upper protective layer 180_2 may include an insulating material different from that of the protective layer 500_2. The upper protective layer 180_2 may be formed of an insulating material containing deuterium (D). For example, the upper protective layer 180_2 may include silicon nitride (SiN) or silicon oxide nitride (SiON) containing deuterium (D), but is not limited thereto. As another example, the upper protective layer 180_2 may include oxides containing deuterium (D), such as silicon oxide (SiO2) or aluminum oxide (Al2O3). In some implementations, the deuterium (D) content (at%) of the upper protective layer 180_2 may vary as a function of the distance from the upper surface 136 of the barrier layer 136, but is not limited thereto.

[0126] In the following text, reference will be made to Figures 14 to 21 A method for manufacturing a semiconductor device according to this disclosure is described. Figures 14 to 21 This is a cross-sectional view showing the process of manufacturing semiconductor devices. Figures 14 to 21 It shows according to Figure 1The methods described herein are examples of methods for manufacturing semiconductor devices, but it will be understood that the same or similar operations can be applied to manufacture other semiconductor devices described herein.

[0127] First, such as Figure 14 As shown, a seed layer 121, a buffer layer 122, a channel layer 132, a barrier layer 136, and a gate semiconductor material layer 152a can be sequentially formed on the substrate 110.

[0128] Substrate 110 may include semiconductor materials. For example, substrate 110 may include sapphire, Si, SiC, AlN, GaN, or combinations thereof. Substrate 110 may be a silicon-on-insulator (SOI) substrate. However, the material of substrate 110 is not limited to this, and all commonly used substrates may be used.

[0129] The seed layer 121 and the superlattice layer 124 can be formed sequentially using an epitaxial growth method. The seed layer 121 and the superlattice layer 124 can be made of the same base semiconductor material. However, the material composition ratios of the layers can differ, considering the function of each layer and the performance requirements of the semiconductor device. The seed layer 121 and the superlattice layer 124 can include one or more materials selected from group III-V materials, for example, nitrides containing Al, Ga, In, B, or combinations thereof. The seed layer 121 and the superlattice layer 124 can be Al... x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the seed layer 121 and the superlattice layer 124 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

[0130] In some implementations, the superlattice layer 124 can be formed as multiple layers, wherein layers comprising different materials are alternately stacked. For example, the superlattice layer 124 can have a structure that repeatedly stacks layers formed of AlGaN and layers formed of AlN. That is, AlGaN / AlN / AlGaN / AlN / AlGaN / AlN can be sequentially stacked to form the superlattice layer 124.

[0131] The high-resistivity layer 126 may be formed of a conductive material to electrically insulate the substrate 110 and the channel layer 132. The high-resistivity layer may include one or more materials selected from group III-V materials, such as nitrides comprising Al, Ga, In, B, or combinations thereof. The high-resistivity layer 126 may be Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the high-resistivity layer 126 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The high-resistivity layer 126 may be formed as a single layer or multiple layers.

[0132] In some implementations, the channel layer 132 and the barrier layer 136 can be formed sequentially using an epitaxial growth method. For example, the channel layer 132 can be formed on the high-resistivity layer 126, and the barrier layer 136 can be formed on the channel layer 132.

[0133] The channel layer 132 and the barrier layer 136 can be made of the same base semiconductor material. However, the material composition ratios of the layers can differ depending on the function of each layer and the performance requirements of the semiconductor device. The channel layer 132 and the barrier layer 136 can comprise one or more materials selected from group III-V materials, such as nitrides containing Al, Ga, In, B, or combinations thereof. The channel layer 132 and the barrier layer 136 can be Al... x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 132 and the barrier layer 136 may include AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The barrier layer 136 may include a material having a different band gap than the channel layer 132. The barrier layer 136 may have a higher band gap than the channel layer 132.

[0134] As an example, substrate 110 may include Si, seed layer 121 may include AlN, and superlattice layer 124 may include AlGaN and AlN. High-resistivity layer 126 may include GaN, channel layer 132 may include GaN, and barrier layer 136 may include AlGaN. Channel layer 132 and barrier layer 136 may be doped with impurities or may not be doped with impurities.

[0135] like Figure 15 As shown, the gate electrode material layer 155a can be formed on the gate semiconductor material layer 152a. The gate semiconductor material layer 152a can be located between the barrier layer 136 and the gate electrode material layer 155a.

[0136] The gate electrode material layer 155a can be formed using a deposition process. For example, the gate electrode material layer 155a can be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD), but is not limited thereto.

[0137] The gate electrode material layer 155a may include a conductive material. For example, the gate electrode material layer 155a may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxide nitride. For example, the gate electrode material layer 155a may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaCN). The material may be, but is not limited to, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The gate electrode material layer 155a may be formed as a single layer or multiple layers.

[0138] like Figure 16 As shown, the gate electrode 155 and the gate semiconductor material layer 152a can be formed by patterning the gate electrode material layer 155a and the gate semiconductor material layer 152a using photolithography and etching processes.

[0139] For example, a hard mask layer and a photoresist layer can be sequentially formed on the gate electrode material layer 155a. A photoresist pattern can be formed by patterning the photoresist layer using a photolithography process. A hard mask pattern can be formed by etching the hard mask layer using the photoresist pattern as a mask. Subsequently, at least a portion of the gate semiconductor material layer 152a can be removed by etching the gate semiconductor material layer 152a using the hard mask pattern as a mask. Therefore, the remaining portion of the gate electrode material layer 155a can become the gate electrode 155. Furthermore, the remaining portion of the gate semiconductor material layer 152a can become the gate semiconductor layer 152. The gate semiconductor layer 152 can be located between the barrier layer 136 and the gate electrode 155. The gate electrode 155 can have a Schottky contact or an ohmic contact with the gate semiconductor layer 152. At this time, the hard mask layer can be removed depending on the etching conditions during etching of the gate electrode material layer or the cleaning conditions after etching. Alternatively, the hard mask pattern can remain on the gate semiconductor layer 152 instead of being removed.

[0140] By patterning the gate semiconductor material layer 152a and the gate electrode material layer 155a using the same mask, the gate semiconductor layer 152 and the gate electrode 155 can have the same pattern. For example, the gate semiconductor layer 152 and the gate electrode 155 can have the same planar shape in a planar view. In a cross-sectional view, the gate semiconductor layer 152 and the gate electrode 155 can have the same width. The gate semiconductor layer 152 can completely overlap with the gate electrode 155 in the third direction (Z direction), and the upper surface of the gate semiconductor layer 152 can be completely covered by the gate electrode 155, but is not limited thereto. For example, the gate semiconductor layer 152 and the gate electrode 155 can partially overlap each other in the third direction (Z direction).

[0141] At this point, dangling bonds DB can exist on the upper surface 136_U of the barrier layer 136. A dangling bond DB can refer to a state where some bonds between some atoms and surrounding atoms within the crystal structure of the barrier layer 136 are broken due to coordination unsaturation. Through the dangling bonds DB present on the upper surface 136_U of the barrier layer 136, two-dimensional electron gas 134 can be trapped, or external impurities can be bonded, thereby degrading device characteristics. Furthermore, the crystal structure of the barrier layer 136 may contain point defects, including vacancies.

[0142] like Figure 17 As shown, a first protective layer 510 can be formed on the barrier layer 136 and the gate electrode 155. The first protective layer 510 can be formed using a deposition process. In some implementations, the thickness of the first protective layer 510 along the third direction (Z direction) can be 200 nm or less. For example, the thickness of the first protective layer 510 along the third direction (Z direction) can be 100 nm or less. The first protective layer 510 can include, but is not limited to, oxides such as silicon oxide (SiO2) or aluminum oxide (Al2O3). As another example, the first protective layer 510 can include nitrides such as silicon nitride (SiN) or oxide nitrides such as silicon oxide nitride (SiON), wherein deuterium (D) is implanted. Simultaneously, point defects, including vacancies, can exist in the crystal structure of the first protective layer 510.

[0143] like Figure 18 As shown, a high-pressure deuterium (HPD) annealing process can be performed on the first protective layer 510.

[0144] The high-pressure deuterium (HPD) annealing process can be performed at a high temperature of about 150°C to 600°C, a deuterium atmosphere of 10% to 100%, and a gas pressure of 1 atm to 40 atm. Preferably, the high-pressure deuterium (HPD) annealing process can be performed at a high temperature of about 400°C to 550°C. Accordingly, deuterium (D) can be implanted into defects such as vacancies present in the crystal structure of the first protective layer 510, and deuterium (D) can bond with surrounding elements. Therefore, the first protective layer 510 may include deuterium (D). In some implementations, as high-pressure deuterium (HPD) annealing is performed from the upper surface 510_U of the first protective layer 510, the deuterium (D) content (at%) of the first protective layer 510 can increase away from the upper surface 136_U of the barrier layer 136, but is not limited thereto. For example, the deuterium (D) content (at%) of the first protective layer 510 may have a section on the upper surface 136_U of the barrier layer 136 where the content is constant.

[0145] Meanwhile, in some implementations, based on the thickness of the first protective layer 510 (e.g., because the thickness of the first protective layer 510 along the third direction (Z direction) is 200 nm (or 100 nm) or less), deuterium (D) can be implanted into the barrier layer 136. The thickness of the first protective layer 510 along the third direction (Z direction) is 200 nm (or 100 nm) or less, which allows deuterium (D) to be implanted into the barrier layer 136. Therefore, an implantation region 136a containing deuterium (D) can be formed in the barrier layer 136, and the dangling bonds DB located in the upper part of the barrier layer 136 can be removed (see...). Figure 16 ).

[0146] The implantation region 136a may be located on the upper part of the barrier layer 136. The implantation region 136a may constitute or form at least a portion of the upper surface of the barrier layer 136. The implantation region 136a may overlap with the channel layer 132 in the third direction (Z direction). The implantation region 136a may be spaced apart from the upper surface 132_U of the channel layer 132 in the third direction (Z direction), but is not limited thereto. As another example, the implantation region 136a may contact the upper surface 132_U of the channel layer 132. Alternatively, the implantation region 136a may not overlap with the gate electrode 155 and the gate semiconductor layer 152 in the third direction (Z direction), as will be described later.

[0147] The implantation region 136a may include deuterium (D). For example, the implantation region 136a may be formed of AlGaN containing deuterium (D). In some implementations, the deuterium (D) content (at%) of the implantation region 136a may increase away from the upper surface of the channel layer 132 as high-pressure deuterium (HPD) annealing is performed from the upper surface of the first protective layer 510, but the content is not limited thereto.

[0148] like Figure 19As shown, the second protective layer 520 can be formed on the first protective layer 510. Since the second protective layer 520 is formed after the high-pressure deuterium (HPD) annealing process described above, the second protective layer 520 may not contain deuterium (D).

[0149] like Figure 20 As shown, the first trench 141 and the second trench 143 can be formed by patterning the protective layer 500 using photolithography and etching processes. At this time, not only the protective layer 500, but also the barrier layer 136 and the channel layer 132 can be patterned together.

[0150] For example, a photoresist pattern can be formed on the second protective layer 520, and by using it as a mask, the second protective layer 520, the first protective layer 510, the barrier layer 136, and the channel layer 132 can be etched sequentially. At this time, the second protective layer 520, the first protective layer 510, and the barrier layer 136 can be penetrated through the first trench 141 and the second trench 143, and the upper surface of the channel layer 132 can be recessed. The channel layer 132 may not be penetrated by the first trench 141 or the second trench 143. For example, the depth of the recess on the upper surface of the channel layer 132 can be less than the entire thickness of the channel layer 132. The depth of the recess on the upper surface of the channel layer 132 can be much less than the entire thickness of the channel layer 132. Furthermore, the depth of the recess on the upper surface of the channel layer 132 can be greater than the thickness of the barrier layer 136. However, this is not a limitation, and the depth of the recess on the upper surface of the channel layer 132 can be varied in various ways.

[0151] In the first trench 141 and the second trench 143, the side surfaces of the second protective layer 520, the first protective layer 510, and the barrier layer 136 can be exposed outwards, and the upper surface and side surface of the channel layer 132 can be exposed. The channel layer 132 can form the bottom surface and sidewalls of the first trench 141 and the second trench 143, and the barrier layer 136 can form the sidewalls of the first trench 141 and the second trench 143.

[0152] The first trench 141 and the second trench 143 may be spaced apart from each other. The first trench 141 and the second trench 143 may be located on opposite sides of the gate electrode 155. The first trench 141 may be located on a first side of the gate electrode 155 to be spaced apart from the gate electrode 155. The second trench 143 may be located on a second side of the gate electrode 155 to be spaced apart from the gate electrode 155. The distance between the first trench 141 and the gate electrode 155 may be smaller than the distance between the second trench 143 and the gate electrode 155. The first trench 141 and the second trench 143 are shown to have similar shapes, such as width and depth, but are not limited thereto. The shapes of the first trench 141 and the second trench 143 may be varied.

[0153] like Figure 21As shown, conductive material can be deposited in the first trench 141 and the second trench 143, and by patterning it, source electrode 173 and drain electrode 175 can be formed.

[0154] The source electrode 173 and drain electrode 175 may comprise conductive materials. For example, the source electrode 173 and drain electrode 175 may comprise metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, or conductive metal oxides, etc. The source electrode 173 and drain electrode 175 may be formed as a single layer or multiple layers. For example, the source electrode 173 and drain electrode 175 may be formed by stacking multiple conductive layers comprising different materials and then patterning them. In this case, multiple conductive layers may be etched simultaneously or sequentially using a mask pattern. For example, the source electrode 173 and drain electrode 175 may be formed by sequentially stacking Ti, Al, Ti, and TiN and then patterning them. In this case, the thicknesses of the four conductive layers constituting the source electrode 173 and drain electrode 175 may be similar or different. For example, the layer formed of Al may be relatively thicker compared to the other layers.

[0155] The source electrode 173 can be formed to fill the interior of the first trench 141. Furthermore, the source electrode 173 can be formed to cover at least a portion of the upper surface of the channel layer 132. Therefore, at least a portion of the source electrode 173 can overlap with the channel layer 132, the barrier layer 136, and the drift region (DTR) in the third direction (Z direction). Within the first trench 141, the source electrode 173 can contact the channel layer 132 and the barrier layer 136. The source electrode 173 can contact the side surfaces of the channel layer 132 and the barrier layer 136. The source electrode 173 can cover the side surfaces of the channel layer 132 and the barrier layer 136. The source electrode 173 can be electrically connected to the channel layer 132 through the first trench 141. The upper surface of the source electrode 173 can protrude further than the upper surface of the second protective layer 520.

[0156] Drain electrode 175 can be formed to fill the interior of the second trench 143. Furthermore, drain electrode 175 can be formed to cover at least a portion of the upper surface of the channel layer 132. Therefore, at least a portion of drain electrode 175 can overlap with the channel layer 132, the barrier layer 136, and the drift region (DTR) in the third direction (Z direction). Within the second trench 143, drain electrode 175 can contact the channel layer 132 and the barrier layer 136. Drain electrode 175 can contact the side surfaces of the channel layer 132 and the barrier layer 136. Drain electrode 175 can cover the side surfaces of the channel layer 132 and the barrier layer 136. Drain electrode 175 can be electrically connected to the channel layer 132 through the second trench 143. The upper surface of drain electrode 175 can protrude further than the upper surface of the second protective layer 520.

[0157] The source electrode 173 and drain electrode 175 can make ohmic contacts with the channel layer 132. The regions in contact with the source electrode 173 and drain electrode 175 in the channel layer 132 can be doped at a relatively high concentration compared to other regions. For example, the channel layer 132 can be doped using ion implantation, annealing, or other processes. However, doping is not limited to this, and the doping process of the channel layer 132 can be formed using various other processes. The doping process of the channel layer 132 can be performed before the formation of the source electrode 173 and drain electrode 175. In some implementations, the channel layer 132 may not be doped.

[0158] Inside the channel layer 132, a two-dimensional electron gas 134 can be formed in the portion adjacent to the barrier layer 136. The two-dimensional electron gas 134 can be located at the interface between the channel layer 132 and the barrier layer 136. The two-dimensional electron gas 134 can be located in the drift region DTR between the source electrode 173 and the drain electrode 175. The depletion region DPR can be formed in the channel layer 132 by a gate semiconductor layer 152 having a different band gap than the barrier layer 136. Therefore, the semiconductor device can have normally off characteristics. For example, the semiconductor device can be a normally off high electron mobility transistor (HEMT). In the gate-off state, the two-dimensional electron gas 134 can be located in the drift region DTR of the channel layer 132, excluding the depletion region DPR. In the gate-on state, the flow of the two-dimensional electron gas 134 continues in the depletion region DPR, and the two-dimensional electron gas 134 can be entirely located within the drift region DTR.

[0159] In the steps of forming the source electrode 173 and the drain electrode 175, the field dispersion layer 177 may be formed together with the electrodes 173 and 175. The field dispersion layer 177 may be located between the source electrode 173 and the drain electrode 175. The field dispersion layer 177 may overlap with the gate electrode 155. The field dispersion layer 177 may be electrically connected to the source electrode 173. The field dispersion layer 177 may be integrally formed with the source electrode 173. The field dispersion layer 177 may include the same material as the source electrode 173 and may be located on the same layer as the source electrode 173.

[0160] Accordingly, the first protective layer 510 may be located on the barrier layer 136 between the source electrode 173 and the drain electrode 175. The first protective layer 510 may overlap with the drift region DTR of the channel layer 132 along the third direction (Z direction).

[0161] Furthermore, the first protective layer 510 and the second protective layer 520 may be located between the barrier layer 136 and the field dispersion layer 177. At least a portion of the first protective layer 510 and the second protective layer 520 may overlap with the field dispersion layer 177 along a third direction (Z direction). Therefore, a portion of the first protective layer 510 and a portion of the second protective layer 520 overlapping with the field dispersion layer 177 in the third direction (Z direction) may cover the gate semiconductor layer 152 and the gate electrode 155. Thus, the barrier layer 136, the gate semiconductor layer 152, and the gate electrode 155 may be protected by the protective layer 500.

[0162] In the preceding description, it was described that conductive material is deposited on the second protective layer 520 and, by patterning it, source electrode 173 and drain electrode 175 can be formed, but the fabrication of electrodes 173 and 175 is not limited thereto.

[0163] In the following text, reference will be made to Figures 22 to 25 Methods for manufacturing semiconductor devices according to some implementations of this disclosure are described. Figures 22 to 25 It is a cross-sectional view showing the process sequence for manufacturing semiconductor devices. Figures 22 to 25 It shows according to Figure 8 The methods described herein are examples of methods for manufacturing semiconductor devices, but it will be understood that the same or similar operations can be applied to manufacture other semiconductor devices described herein.

[0164] Figures 22 to 25 The process shown has the same characteristics as Figures 14 to 19 The processes shown are essentially the same, therefore their description will be omitted, and the differences will be mainly described. Furthermore, the same reference numerals will be used for the same parts as in the previous examples.

[0165] like Figure 22 As shown, the seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, gate semiconductor layer 152, and gate electrode 155 can be sequentially formed on the substrate 110. The description of the substrate 110, seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, gate semiconductor layer 152, and gate electrode 155 is consistent with... Figures 14 to 21 The descriptions of the seed layer 121, buffer layer 122, channel layer 132, barrier layer 136, gate semiconductor layer 152 and gate electrode 155 in the process are basically the same and will be omitted.

[0166] like Figure 23 As shown, a high-pressure deuterium (HPD) annealing process can be performed on the upper surface 136_U of the barrier layer 136.

[0167] The high-pressure deuterium (HPD) annealing process can be performed at a high temperature of about 150°C to 600°C, a deuterium atmosphere of 10% to 100%, and a pressure of 1 atm to 40 atm. Preferably, the high-pressure deuterium (HPD) annealing process can be performed at a high temperature of about 400°C to 550°C. Therefore, deuterium (D) can be implanted into defects (such as vacancies) present in the crystal structure of the barrier layer 136, and deuterium (D) can bond with surrounding elements. In addition, dangling bonds DB located in the upper part of the barrier layer 136 can be removed, and an implantation region 136a containing deuterium (D) can be formed in the barrier layer 136. In some implementations, as high-pressure deuterium (HPD) annealing is performed from the upper surface 136_U of the barrier layer 136, the deuterium (D) content (at%) of the implantation region 136a can increase away from the upper surface of the channel layer 132, but is not limited thereto.

[0168] In some implementations, since the gate semiconductor layer 152 and the gate electrode 155 are located on the barrier layer 136, deuterium (D) may not be implanted into the portion of the barrier layer 136 that overlaps with the gate semiconductor layer 152 and the gate electrode 155 in the third direction (Z direction). For example, the implantation region 136a may also not overlap with the gate semiconductor layer 152 and the gate electrode 155 in the third direction (Z direction).

[0169] like Figure 24 As shown, the protective layer 500 can be formed on the barrier layer 136 and the gate electrode 155. The protective layer 500 can be formed using a deposition process. Figure 24 The diagram shows that the protective layer 500 is formed as a single layer, but it is not limited to this, and it can be formed as multiple layers.

[0170] refer to Figure 25 First, the protective layer 500 is patterned using photolithography and etching processes to form the first trench 141 and the second trench 143. At this time, not only the protective layer 500, but also the barrier layer 136 and the channel layer 132 can be patterned together. Finally, conductive material can be deposited in the first trench 141 and the second trench 143, and by patterning them, the source electrode 173 and the drain electrode 175 can be formed, thereby forming a semiconductor device.

[0171] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in the context of individual implementations (e.g., the presence / configuration of floating patterns) may also be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from the combination may be removed from the combination, and the combination may point to a sub-combination or a variation of the sub-combination. For example, without departing from the scope of this disclosure, [the following can be done / understand]... Figure 1 and Figures 6 to 13 The features of the examples are combined in various ways.

[0172] Although this disclosure has been described with reference to various examples, it should be understood that this disclosure is not limited to those examples, but rather is intended to cover various modifications and equivalent arrangements that are included within the spirit and scope of this disclosure.

[0173] Cross-reference to related applications

[0174] This application claims priority and interest in Korean Patent Application No. 10-2024-0133994, filed on October 2, 2024, and Korean Patent Application No. 10-2024-0146004, filed on October 23, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Channel layer; A barrier layer on the channel layer, wherein the barrier layer comprises a material having a band gap different from that of the channel layer; The gate electrode is located on the barrier layer. A gate semiconductor layer is located between the barrier layer and the gate electrode; A protective layer is placed on the barrier layer and covers the gate electrode; as well as Source and drain electrodes are located on opposite lateral sides of the gate electrode, wherein the source and drain electrodes are electrically connected to the channel layer. The protective layer includes: A first protective layer, on the barrier layer and comprising a first insulating material containing deuterium, and The second protective layer is located on top of the first protective layer and includes a second insulating material that is substantially free of deuterium.

2. The semiconductor device of claim 1, wherein the deuterium concentration in the first protective layer increases in a vertical direction away from the upper surface of the barrier layer.

3. The semiconductor device of claim 2, wherein the deuterium concentration in the first protective layer has a maximum value at the upper surface of the first protective layer.

4. The semiconductor device according to claim 1, wherein: The first insulating material comprises silicon oxide; and The second insulating material includes silicon oxide, silicon nitride, or silicon nitride.

5. The semiconductor device according to claim 1, wherein the thickness of the first protective layer is less than the thickness of the second protective layer.

6. The semiconductor device of claim 5, wherein the thickness of the first protective layer is 200 nm or less.

7. The semiconductor device of claim 1, wherein the first protective layer covers the side surface and the top surface of the gate electrode.

8. The semiconductor device of claim 7, further comprising a field dispersion layer, said field dispersion layer being integrally formed with the source electrode and located on the second protective layer. The field dispersion layer overlaps with the gate electrode in the vertical direction.

9. The semiconductor device according to claim 1, wherein: The barrier layer includes an injection region containing deuterium; and The injection area is located on the upper part of the barrier layer.

10. The semiconductor device according to claim 9, wherein, The injection region overlaps with the first protective layer in the vertical direction, but does not overlap with the gate electrode in the vertical direction.

11. The semiconductor device according to claim 9, wherein, The deuterium concentration in the injection region increases in the vertical direction away from the upper surface of the channel layer.

12. The semiconductor device according to claim 11, wherein, The deuterium concentration in the first protective layer has its maximum value at the upper surface of the first protective layer.

13. The semiconductor device of claim 9, wherein the deuterium concentration in the first protective layer is greater than or equal to the deuterium concentration in the implantation region.

14. The semiconductor device according to claim 9, wherein: The upper surface of the injection area is in contact with the first protective layer; and The lower surface of the injection area is in contact with the channel layer.

15. The semiconductor device according to claim 9, wherein, The side surface of the injection region is in contact with the source electrode and the drain electrode.

16. A semiconductor device, comprising: Channel layer, including GaN; A barrier layer on the channel layer, wherein the barrier layer comprises AlGaN and includes an implantation region containing deuterium; A gate electrode is located on the barrier layer and comprises a metallic material; A gate semiconductor layer between the barrier layer and the gate electrode, wherein the gate semiconductor layer comprises GaN doped with p-type impurities; A protective layer is placed on the barrier layer and covers the gate electrode; as well as Source and drain electrodes are located on opposite lateral sides of the gate electrode, wherein the source and drain electrodes are electrically connected to the channel layer. The protective layer includes: A first protective layer, on the injection area and comprising deuterium, and The second protective layer is placed on top of the first protective layer.

17. The semiconductor device according to claim 16, wherein: The injection area is in contact with the first protective layer; and The injection region does not overlap with the gate electrode in the vertical direction.

18. The semiconductor device of claim 16, wherein the deuterium concentration in the implantation region is less than or equal to the deuterium concentration in the first protective layer.

19. The semiconductor device according to claim 16, wherein, The deuterium concentration in the injection region increases in the vertical direction away from the upper surface of the channel layer.

20. A semiconductor device, comprising: Channel layer; A barrier layer on the channel layer, wherein the barrier layer comprises a material having a band gap different from that of the channel layer, and wherein the barrier layer comprises an injection region containing deuterium; The gate electrode is located on the barrier layer. A gate semiconductor layer is located between the barrier layer and the gate electrode; A protective layer is applied to the injection region and covers the gate electrode; as well as Source and drain electrodes are located on opposite lateral sides of the gate electrode, wherein the source and drain electrodes are electrically connected to the channel layer. The injection region is located between the portion of the barrier layer that overlaps with the gate electrode in the vertical direction and the source electrode, and between the portion of the barrier layer that overlaps with the gate electrode in the vertical direction and the drain electrode. The protective layer includes: A first protective layer, on the barrier layer and comprising silicon oxide containing deuterium, and A second protective layer is disposed on the first protective layer and comprises silicon oxide, silicon nitride, or silicon nitride, wherein the silicon oxide, silicon nitride, or silicon nitride of the second protective layer is substantially free of deuterium.

21. A semiconductor device, comprising: Channel layer; A barrier layer on the channel layer, wherein the barrier layer comprises a material having a band gap different from that of the channel layer; The gate electrode is located on the barrier layer. A gate semiconductor layer is located between the barrier layer and the gate electrode; A protective layer is placed on the barrier layer and covers the gate electrode; Source and drain electrodes on opposite lateral sides of the gate electrode, wherein the source and drain electrodes are electrically connected to the channel layer; A field dispersion layer is provided on the protective layer and electrically connected to the source electrode. as well as An upper protective layer covers the field dispersion layer and the protective layer. The protective layer comprises a second insulating material that is substantially free of deuterium, and The upper protective layer comprises a first insulating material containing deuterium.

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