Semiconductor device

Abstract

There is provided a semiconductor device including: a first channel pattern and a second channel pattern at least partially overlapping; a first gate pattern between the first channel pattern and the second channel pattern, and at least partially overlapping the first channel pattern and the second channel pattern; a first connection conductive pattern and a second connection conductive pattern spaced apart from each other in the first direction, and the first channel pattern, the second channel pattern, and the first gate pattern are between the first connection conductive pattern and the second connection conductive pattern; and a first source / drain pattern connected to the first channel pattern and the second channel pattern. The first connection conductive pattern and the second connection conductive pattern are electrically connected to the first gate pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0133959, filed on October 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The exemplary embodiments of this disclosure in the text relate to a semiconductor device, and more specifically, to a semiconductor device including a channel pattern. Background Technology

[0004] Semiconductor devices can include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the size reduction of MOSFETs is also accelerating. With the shrinking size of MOSFETs, the operating characteristics of semiconductor devices may deteriorate. Therefore, research is underway on various methods to overcome the limitations caused by the higher integration density of semiconductor devices in order to form semiconductor devices with improved performance. Summary of the Invention

[0005] The exemplary embodiments of this disclosure provide a semiconductor device with improved electrical characteristics and reliability.

[0006] Some exemplary embodiments of the present invention provide a semiconductor device comprising: a first channel pattern and a second channel pattern that at least partially overlap; a first gate pattern that overlaps with and is between the first channel pattern and the second channel pattern; a first connecting conductive pattern and a second connecting conductive pattern spaced apart from each other in a first direction, with the first channel pattern, the second channel pattern, and the first gate pattern between the first connecting conductive pattern and the second connecting conductive pattern; and a first source / drain pattern connected to the first channel pattern and the second channel pattern. The first connecting conductive pattern and the second connecting conductive pattern are electrically connected to the first gate pattern.

[0007] In some exemplary embodiments of the present invention, the semiconductor device includes a first channel pattern and a second channel pattern that at least partially overlap; a first gate pattern that is between and overlaps with the first channel pattern and the second channel pattern; a first connection conductive pattern that is spaced apart from the first channel pattern and the second channel pattern and electrically connected to the first gate pattern; and source / drain patterns connected to the first channel pattern and the second channel pattern. The first channel pattern, the second channel pattern, and the first gate pattern are located between the upper and lower surfaces of the first connection conductive pattern.

[0008] In some example embodiments of the inventive concepts, a semiconductor device includes: a first channel pattern and a second channel pattern at least partially overlapping; a first gate pattern between and at least partially overlapping the first channel pattern and the second channel pattern; a first connection conductive pattern and a second connection conductive pattern spaced apart from each other in a first direction; and the first channel pattern, the second channel pattern, and the first gate pattern between the first connection conductive pattern and the second connection conductive pattern; a first source / drain pattern connected to the first channel pattern and the second channel pattern; a third channel pattern spaced apart from the first channel pattern in the first direction; a fourth channel pattern spaced apart from the second channel pattern in the first direction and overlapping the third channel pattern; and a second gate pattern between and overlapping the third channel pattern and the fourth channel pattern and spaced apart from the first gate pattern in the first direction; a third connection conductive pattern and a fourth connection conductive pattern spaced apart from each other in the first direction and the third channel pattern, the fourth channel pattern, and the second gate pattern between the third connection conductive pattern and the fourth connection conductive pattern; a second source / drain pattern connected to the third channel pattern and the fourth channel pattern; a first spacer at least partially overlapping the first source / drain pattern and the second source / drain pattern; a first mask pattern at least partially overlapping the first channel pattern, the second channel pattern, and the first gate pattern; a second mask pattern at least partially overlapping the third channel pattern, the fourth channel pattern, and the second gate pattern; a second spacer on the first mask pattern and the second mask pattern and the first spacer; and a cover insulating layer on the first mask pattern and the second mask pattern and the first connection conductive pattern through the fourth connection conductive pattern. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the inventive concepts and are incorporated in and constitute a part of this specification. The drawings illustrate some example embodiments of the inventive concepts and, together with the description, serve to explain the principles of the inventive concepts. In the drawings:

[0010] FIG. 1A is a plan view of a semiconductor device according to some example embodiments;

[0011] FIG. 1B is a cross-sectional view taken along line A-A’ of FIG. 1A

[0012] FIG. 1C is a cross-sectional view taken along line B-B’ of FIG. 1A

[0013] FIG. 1D is a cross-sectional view taken along line C-C’ of FIG. 1A ​​​

[0014] FIG. 1E is a cross-sectional view taken along the line D-D’ of FIG. 1A ;

[0015] FIG. 1F is an enlarged view of the area Q1 of FIG. 1A ;

[0016] FIG. 1G is an enlarged view of the area Q2 of FIG. 1B ;

[0017] FIG. 1H is an enlarged view of the area Q3 of FIG. 1C ;

[0018] FIG. 2 , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 5 , FIG. 6A , FIG. 6B , FIG. 6C , FIG. 7A , FIG. 7B , FIG. 7C , FIG. 7D , FIG. 8A , FIG. 8B , FIG. 8C , FIG. 9A , FIG. 9B , FIG. 9C , FIG. 10A , FIG. 10B , FIG. 10C , FIG. 11A , FIG. 11B , FIG. 12A , FIG. 12B , FIG. 12C , FIG. 13A , FIG. 13B , FIG. 13C , FIG. 14A , FIG. 14B , FIG. 14C and FIG. 14D are diagrams for describing a method of manufacturing a semiconductor device according to FIGS. 1A-1H ;

[0019] FIG. 15A , FIG. 15B and FIG. 15C are cross-sectional views of a semiconductor device according to some example embodiments;

[0020] FIG. 16A and FIG. 16B are enlarged cross-sectional views of a semiconductor device according to some example embodiments; and

[0021] FIG. 17is a cross-sectional view of a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0022] FIG. 1A is a plan view of a semiconductor device according to some example embodiments. FIG. 1B is a cross-sectional view taken along FIG. 1A line A-A' of FIG. 1C is a cross-sectional view taken along FIG. 1A line B-B' of FIG. 1D is a cross-sectional view taken along FIG. 1A line C-C' of FIG. 1E is a cross-sectional view taken along FIG. 1A line D-D' of FIG. 1F is FIG. 1A an enlarged view of a region Q1 of FIG. 1G is FIG. 1B an enlarged view of a region Q2 of FIG. 1H is FIG. 1C an enlarged view of a region Q3 of

[0023] Referring to FIG. 1A , FIG. 1B , FIG. 1C , FIG. 1D and FIG. 1E , the semiconductor device can include a substrate 10. A logic unit can be disposed on the substrate 10. In some example embodiments of the disclosure, the logic unit can represent a logic element (e.g., AND, OR, XOR, XNOR, inverter, etc.) that performs a specific function. The logic unit can include a transistor for constituting the logic element.

[0024] The substrate 10 can be a semiconductor substrate, an insulating substrate, or a silicon-on-insulator (SOI) substrate. For example, the semiconductor substrate can include silicon, germanium, silicon germanium, GaP, or GaAs. The substrate 10 can have a shape of a plate that extends in a plane that extends in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can cross each other. For example, the first direction D1 and the second direction D2 can be horizontal directions that are perpendicular to each other.

[0025] According to some example embodiments, the semiconductor device can not include the substrate 10.

[0026] An insulating pattern 11 can be disposed on the substrate 10. The insulating pattern 11 can include insulating patterns 11 arranged in the first direction D1. The insulating pattern 11 can include insulating patterns 11 arranged in the second direction D2. The insulating pattern 11 can include an insulating material. For example, the insulating pattern 11 can include an oxide.

[0027] According to some example embodiments, the semiconductor device can not include the insulating pattern 11, and the substrate 10 can include an active pattern protruding in a third direction D3. The active pattern can be disposed at a position where the insulating pattern 11 is disposed. The third direction D3 can intersect the first direction D1 and the second direction D2. For example, the third direction D3 can be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0028] An intercalation pattern 12 can be disposed on the substrate 10. The intercalation pattern 12 can include the intercalation pattern 12 arranged in the first direction D1. The intercalation pattern 12 can include the intercalation pattern 12 arranged in the second direction D2. The intercalation pattern 12 can include an insulating material.

[0029] A channel pattern 31 can be disposed. The channel pattern 31 can overlap the insulating pattern 11 in the third direction D3. One insulating pattern 11 and a plurality of channel patterns 31 can overlap each other in the third direction D3.

[0030] The channel pattern 31 can include a semiconductor material. For example, the channel pattern 31 can include a two-dimensional semiconductor material (e.g., WSe2, MoS2, black phosphorus (BP)). According to some example embodiments, the channel pattern 31 can be a single atomic layer.

[0031] The number of channel patterns 31 overlapping each other in the third direction D3 can not be limited to that shown. According to some example embodiments, the number of channel patterns 31 overlapping each other in the third direction D3 can be two or less, or four or more.

[0032] A source / drain pattern SD can be disposed. The source / drain pattern SD can be disposed between the channel patterns 31 spaced apart from each other in the second direction D2. The source / drain pattern SD can be connected to the channel patterns 31 overlapping each other in the third direction D3. The channel patterns 31 overlapping each other in the third direction D3 can be disposed between the source / drain patterns SD spaced apart from each other in the second direction D2. The source / drain pattern SD can be disposed between the intercalation patterns 12 adjacent to each other in the first direction D1.

[0033] The source / drain pattern SD can be an epitaxial pattern formed in a selective epitaxial growth (SEG) process. The source / drain pattern SD can include silicon or silicon germanium. However, example embodiments are not limited thereto. The source / drain pattern SD can be doped with an impurity.

[0034] A gate pattern GE1 can be configured. The gate pattern GE1 can overlap with the insulating pattern 11 and the channel pattern 31 on the third direction D3. One insulating pattern 11, multiple gate patterns GE1, and multiple channel patterns 31 can overlap each other on the third direction D3. The channel patterns 31 can be disposed between the gate patterns GE1. The channel patterns 31 and the gate patterns GE1 can be spaced apart from each other.

[0035] The gate pattern GE1 may include a conductive material. For example, the gate pattern GE1 may include TiAlC or TiN. However, the example embodiment is not limited thereto.

[0036] An upper channel pattern 32 can be configured. The upper channel pattern 32 can overlap with the insulating pattern 11, the channel pattern 31, and the gate pattern GE1 on the third direction D3. One insulating pattern 11, multiple channel patterns 31, multiple gate patterns GE1, and multiple upper channel patterns 32 can overlap each other on the third direction D3. The upper channel pattern 32 can be configured at a higher level than the channel pattern 31 and the gate pattern GE1.

[0037] The upper channel pattern 32 may include a semiconductor material. For example, the upper channel pattern 32 may include a two-dimensional semiconductor material (e.g., WSe2, MoS2, or black phosphorus (BP)). However, the example embodiments are not limited thereto. The upper channel pattern 32 and the channel pattern 31 may include the same material, or they may each include different materials. According to some example embodiments, the upper channel pattern 32 may be a single atomic layer.

[0038] The number of upper channel patterns 32 overlapping each other on the third direction D3 is not limited to those shown. According to some example embodiments, the number of upper channel patterns 32 overlapping each other on the third direction D3 may be two or fewer, or four or more.

[0039] The upper source / drain pattern USD can be configured. The upper source / drain pattern USD can be configured between upper channel patterns 32 spaced apart along the second direction D2. The upper source / drain pattern USD can be connected to upper channel patterns 32 that overlap each other in the third direction D3. The upper channel patterns 32 that overlap each other in the third direction D3 can be configured between upper source / drain patterns USD spaced apart along the second direction D2. The upper source / drain pattern USD can be configured at a horizontal height higher than the source / drain pattern SD.

[0040] The upper source / drain pattern USD can be an epitaxial pattern formed in a selective epitaxial growth (SEG) process. The upper source / drain pattern USD can include silicon or silicon-germanium. However, the example embodiments are not limited thereto. The upper source / drain pattern USD can be doped with impurities. The source / drain pattern SD and the upper source / drain pattern USD can each have different conductivity types. For example, the source / drain pattern SD can have an N-type conductivity type, and the upper source / drain pattern USD can have a P-type conductivity type. However, the example embodiments are not limited thereto.

[0041] An upper gate pattern GE2 can be configured. The upper gate pattern GE2 can overlap with the insulating pattern 11, channel pattern 31, gate pattern GE1, and upper channel pattern 32 on the third direction D3. One insulating pattern 11, multiple gate patterns GE1, multiple channel patterns 31, multiple upper channel patterns 32, and multiple upper gate patterns GE2 can overlap each other on the third direction D3. The upper channel pattern 32 can be disposed between the upper gate patterns GE2. The upper channel pattern 32 and the upper gate pattern GE2 can be spaced apart from each other. The upper gate pattern GE2 can be disposed at a higher level than the channel pattern 31 and the gate pattern GE1.

[0042] The upper gate pattern GE2 may include a conductive material. For example, the upper gate pattern GE2 may include TiAlC or TiN. However, the example embodiment is not limited thereto. The gate pattern GE1 and the upper gate pattern GE2 may include the same material, or they may each include different materials.

[0043] A gate insulating layer GI can be provided. The gate insulating layer GI can contact the gate pattern GE1 and the channel pattern 31, or it can contact the upper gate pattern GE2 and the upper channel pattern 32. The channel pattern 31 and the gate pattern GE1 can be spaced apart from each other by the gate insulating layer GI. The upper channel pattern 32 and the upper gate pattern GE2 can be spaced apart from each other by the gate insulating layer GI. The gate insulating layer GI can include an insulating material. For example, the gate insulating layer GI can include an oxide. However, the exemplary embodiments are not limited thereto.

[0044] An inner spacer IS can be provided. The inner spacer IS can be disposed between the source / drain pattern SD and the gate pattern GE1, or between the upper source / drain pattern USD and the upper gate pattern GE2. The inner spacer IS and the gate pattern GE1 or the upper gate pattern GE2 can be spaced apart from each other by a gate insulating layer GI. The upper channel pattern 32 can be disposed between the inner spacers IS spaced apart along the third direction D3. The channel pattern 31 can be disposed between the inner spacers IS spaced apart along the third direction D3. The inner spacer IS may include an insulating material.

[0045] A first interlayer insulating pattern 43 may be provided. The first interlayer insulating pattern 43 may overlap with the insulating pattern 11, the channel pattern 31, the gate pattern GE1, the upper channel pattern 32, and the upper gate pattern GE2 on the third direction D3. The first interlayer insulating pattern 43 may be disposed between the channel pattern 31 and the upper channel pattern 32, and between the gate pattern GE1 and the upper gate pattern GE2. The first interlayer insulating pattern 43 may include insulating material.

[0046] A second interlayer insulation pattern 44 can be provided. The second interlayer insulation pattern 44 can overlap with the source / drain pattern SD and the upper source / drain pattern USD on the third direction D3. The second interlayer insulation pattern 44 can be provided between the source / drain pattern SD and the upper source / drain pattern USD. The second interlayer insulation pattern 44 may include insulating material.

[0047] The first interlayer insulation pattern 43 and the second interlayer insulation pattern 44 can be arranged alternately in the second direction D2.

[0048] A mask pattern MP can be set. The mask pattern MP can overlap with the insulating pattern 11, the channel pattern 31, the gate pattern GE1, the upper channel pattern 32, and the upper gate pattern GE2 on the third direction D3. One mask pattern MP, one insulating pattern 11, multiple gate patterns GE1, multiple channel patterns 31, multiple upper channel patterns 32, and multiple upper gate patterns GE2 can overlap with each other on the third direction D3.

[0049] The mask pattern MP can be positioned at a level higher than the upper channel pattern 32 and the upper gate pattern GE2. The mask pattern MP can be disposed on the gate insulating layer GI. The lower surface of the mask pattern MP can contact the gate insulating layer GI. The mask pattern MP can include an insulating material. For example, the mask pattern MP can include a nitride.

[0050] A connecting conductive pattern 21 can be provided. A mask pattern MP, an insulating pattern 11, a channel pattern 31, an upper channel pattern 32, a gate pattern GE1, an upper gate pattern GE2, and a gate insulating layer GI, which overlap each other on the third direction D3, can be disposed between two connecting conductive patterns 21 spaced apart from each other along the first direction D1. The connecting conductive pattern 21 can be electrically connected to the gate pattern GE1 and the upper gate pattern GE2. The connecting conductive pattern 21 can contact the gate pattern GE1 and the upper gate pattern GE2. The connecting conductive pattern 21 can contact the mask pattern MP and the gate insulating layer GI. The channel pattern 31 and the upper channel pattern 32 can be spaced apart from the connecting conductive pattern 21 by the gate insulating layer GI.

[0051] The lower surface 21_L of the conductive pattern 21 can contact the substrate 10. The lower surface 21_L of the conductive pattern 21 can be substantially coplanar with the lower surface of the insulating pattern 11. The upper surface 21_U of the conductive pattern 21 can be substantially coplanar with the upper surface of the mask pattern MP. The upper surface 21_U of the conductive pattern 21 can contact the overlay insulating layer 40, which will be described later. The mask pattern MP, the insulating pattern 11, the channel pattern 31, the upper channel pattern 32, the gate pattern GE1, the upper gate pattern GE2, and the gate insulating layer GI can be disposed between the lower surface 21_L and the upper surface 21_U of the conductive pattern 21. The upper surface 21_U of the conductive pattern 21 can be the uppermost part of the conductive pattern 21. The lower surface 21_L of the conductive pattern 21 can be the lowermost part of the conductive pattern 21.

[0052] The connecting conductive pattern 21 may include a conductive material different from the gate pattern GE1 and the upper gate pattern GE2. For example, the connecting conductive pattern 21 may include a two-dimensional conductive material. For example, the connecting conductive pattern 21 may include graphene or a transition metal chalcogenide. However, the example embodiments are not limited thereto. According to some example embodiments, the connecting conductive pattern 21 may be a single atomic layer.

[0053] A cover insulating layer 40 may be disposed on the connecting conductive pattern 21 and the mask pattern MP. The cover insulating layer 40 may include an insertion portion 42 and an upper portion 41 connecting the insertion portion 42. The insertion portion 42 of the cover insulating layer 40 may be disposed at a level lower than the upper portion 41 of the cover insulating layer 40. The insertion portion 42 may be disposed between adjacent connecting conductive patterns 21 along a first direction D1. The insertion portion 42 may contact both connecting conductive patterns 21. The upper portion 41 of the cover insulating layer 40 may contact the upper surface of the mask pattern MP. The cover insulating layer 40 may include an insulating material. For example, the cover insulating layer 40 may include a nitride. However, the exemplary embodiment is not limited thereto.

[0054] A first spacer 22 can be provided. The first spacer 22 can be provided on the source / drain pattern SD and the upper source / drain pattern USD. The first spacer 22 can overlap with the upper source / drain pattern USD and the source / drain pattern SD on the third direction D3.

[0055] The first spacer 22 may include a first portion 22a, a second portion 22b on the first portion 22a, and a third portion 22c on the second portion 22b. The first portion 22a of the first spacer 22 may be disposed between source / drain patterns SD that are adjacent to each other along the first direction D1, and between upper source / drain patterns USD that are adjacent to each other along the first direction D1. The first portion 22a of the first spacer 22 may contact the source / drain patterns SD that are adjacent to each other along the first direction D1, and may also contact the upper source / drain patterns USD that are adjacent to each other along the first direction D1. The width of the first portion 22a of the first spacer 22 in the first direction D1 may be the same as the distance between the source / drain patterns SD that are adjacent to each other along the first direction D1, and the distance between the upper source / drain patterns USD that are adjacent to each other along the first direction D1. The first portion 22a of the first spacer 22 may be disposed on the insertion pattern 12.

[0056] The third portions 22c of the first spacer 22 may be spaced apart from each other along the second direction D2. The first spacer 22 may include insulating material.

[0057] A second spacer 23 may be provided. The second spacer 23 may be provided on the first spacer 22 and the mask pattern MP. The second spacer 23 may extend along a first direction D1. A third portion 22c of the first spacer 22 may be provided between adjacent second spacers 23 along a second direction D2. The second spacer 23 may include an insulating material.

[0058] A filler insulating layer 53 may be provided. The filler insulating layer 53 may be provided on the first spacer 22. The filler insulating layer 53 may be provided between the third portions 22c of the first spacer 22. The filler insulating layer 53 may include an insulating material.

[0059] A first separating insulating layer 51 and a second separating insulating layer 52 may be provided. The first separating insulating layer 51 may penetrate the second portion 22b of the first spacer 22 along the third direction D3. The lower part of the first separating insulating layer 51 may be disposed in the first portion 22a of the first spacer 22. The first separating insulating layer 51 may overlap with the first portion 22a of the first spacer 22 along the third direction D3. The second separating insulating layer 52 may penetrate the second portion 22b of the first spacer 22 along the third direction D3. The lower part of the second separating insulating layer 52 may be disposed in the first portion 22a of the first spacer 22. The second separating insulating layer 52 may overlap with the first portion 22a of the first spacer 22 along the third direction D3. The length of the first separating insulating layer 51 along the third direction D3 may be less than the length of the second separating insulating layer 52 along the third direction D3. The first separating insulating layer 51 and the second separating insulating layer 52 may include insulating material.

[0060] Active contacts AC1 and AC2 can be provided. Active contacts AC1 and AC2 may include a first active contact AC1 and a second active contact AC2. The first active contact AC1 can penetrate along the third direction D3 through the filling insulating layer 53 and the second portion 22b of the first spacer 22. The first active contact AC1 can contact the upper source / drain pattern USD. The second active contact AC2 can penetrate along the third direction D3 through the filling insulating layer 53, the second portion 22b of the first spacer 22, the upper source / drain pattern USD, and the second interlayer insulating pattern 44. The second active contact AC2 can contact the source / drain pattern SD and the upper source / drain pattern USD. Active contacts AC1 and AC2 may include conductive material.

[0061] A gate contact GC can be configured. The gate contact GC can penetrate the upper portion 41 of the covering insulating layer 40, the mask pattern MP, and the gate insulating layer GI on the third-direction D3. The gate contact GC can contact the upper gate pattern GE2. The gate contact GC can include a conductive material.

[0062] A lower active contact LAC can be configured. The lower active contact LAC may overlap with the first active contact AC1 on the third direction D3. The lower active contact LAC may contact the source / drain pattern SD. The lower active contact LAC may penetrate the substrate 10 on the third direction D3. The lower active contact LAC may include a conductive material.

[0063] The channel pattern 31 may include a first channel pattern 31_1 and a second channel pattern 31_2 that overlap each other on the third direction D3, and a third channel pattern 31_3 and a fourth channel pattern 31_4 that overlap each other on the third direction D3.

[0064] The third channel pattern 31_3 can be set at the same horizontal level as the first channel pattern 31_1, and can be spaced apart from the first channel pattern 31_1 along the first direction D1. The fourth channel pattern 31_4 can be set at the same horizontal level as the second channel pattern 31_2, and can be spaced apart from the second channel pattern 31_2 along the first direction D1.

[0065] The gate pattern GE1 may include a first gate pattern GE1_1 disposed between the first channel pattern 31_1 and the second channel pattern 31_2, and a second gate pattern GE1_2 disposed between the third channel pattern 31_3 and the fourth channel pattern 31_4. The second gate pattern GE1_2 may be disposed at the same horizontal level as the first gate pattern GE1_1 and may be spaced apart from the first gate pattern GE1_1 in the first direction D1. The first gate pattern GE1_1 may overlap with the first channel pattern 31_1 and the second channel pattern 31_2 in the third direction D3. The second gate pattern GE1_2 may overlap with the third channel pattern 31_3 and the fourth channel pattern 31_4 in the third direction D3.

[0066] The connecting conductive pattern 21 may include a first connecting conductive pattern 21_1 and a second connecting conductive pattern 21_2 spaced apart from each other in the first direction D1, with a first channel pattern 31_1, a second channel pattern 31_2, and a first gate pattern GE1_1 located between the first connecting conductive pattern 21_1 and the second connecting conductive pattern 21_2. The connecting conductive pattern 21 may also include a third connecting conductive pattern 21_3 and a fourth connecting conductive pattern 21_4 spaced apart from each other in the first direction D1, with a third channel pattern 31_3, a fourth channel pattern 31_4, and a second gate pattern GE1_2 located between the third connecting conductive pattern 21_3 and the fourth connecting conductive pattern 21_4.

[0067] The first connecting conductive pattern 21_1 and the second connecting conductive pattern 21_2 are electrically connected to the first gate pattern GE1_1. The first connecting conductive pattern 21_1 and the second connecting conductive pattern 21_2 are in contact with the first gate pattern GE1_1. The third connecting conductive pattern 21_3 and the fourth connecting conductive pattern 21_4 are electrically connected to the second gate pattern GE1_2. The third connecting conductive pattern 21_3 and the fourth connecting conductive pattern 21_4 are in contact with the second gate pattern GE1_2. The first connecting conductive pattern 21_1 and the second connecting conductive pattern 21_2 are spaced apart from the first channel pattern 31_1 and the second channel pattern 31_2. The third connecting conductive pattern 21_3 and the fourth connecting conductive pattern 21_4 are spaced apart from the third channel pattern 31_3 and the fourth channel pattern 31_4. The first channel pattern 31_1, the second channel pattern 31_2, and the first gate pattern GE1_1 may be disposed between the upper surface 21_U and the lower surface 21_L of each of the first connecting conductive pattern 21_1 and the second connecting conductive pattern 21_2.

[0068] The source / drain pattern SD may include a first source / drain pattern SD1 connected to the first channel pattern 31_1 and the second channel pattern 31_2, and a second source / drain pattern SD2 connected to the third channel pattern 31_3 and the fourth channel pattern 31_4.

[0069] The mask pattern MP may include a first mask pattern MP1 that overlaps with the first channel pattern 31_1, the second channel pattern 31_2, and the first gate pattern GE1_1 on the third direction D3, and a second mask pattern MP2 that overlaps with the third channel pattern 31_3, the fourth channel pattern 31_4, and the second gate pattern GE1_2 on the third direction D3.

[0070] Reference FIG. 1F , FIG. 1G and FIG. 1H The conductive pattern 21 may include a lower portion 21a and an upper portion 21b. The lower portion 21a of the conductive pattern 21 may include a first sidewall portion 21a1 and a second sidewall portion 21a2. The second sidewall portion 21a2 may be connected to the first sidewall portion 21a1. The second sidewall portions 21a2 may be spaced apart from each other along a second direction D2.

[0071] The first sidewall 21a1_S1 of the first sidewall portion 21a1 can contact the sidewall GE1_S of the gate pattern GE1, the sidewall GE2_S of the upper gate pattern GE2, and the sidewall GI_S of the gate insulating layer GI. The first sidewall 21a2_S1 of the second sidewall portion 21a2 can contact the first sidewall 23_S1 of the second spacer 23. The second sidewall 23_S2 of the second spacer 23 can contact the first sidewall 22_S1 of the first spacer 22. The second sidewall 22_S2 of the first spacer 22 can contact the filling insulating layer 53. The first sidewall 23_S1 and the second sidewall 23_S2 of the second spacer 23 can be opposite to each other. The first sidewall 22_S1 and the second sidewall 22_S2 of the first spacer 22 can be opposite to each other.

[0072] The insertion portion 42 covering the insulating layer 40 may include a first portion 42a and a second portion 42b. The first portion 42a of the insertion portion 42 may contact the first sidewall portion 21a1 and the second sidewall portion 21a2. The first portion 42a of the insertion portion 42 may be disposed between the second portions 42b of the insertion portion 42. The second portion 42b of the insertion portion 42 may contact the second sidewall portion 21a2. The width of the first portion 42a of the insertion portion 42 along the first direction D1 may be greater than the width of the second portion 42b of the insertion portion 42 along the first direction D1.

[0073] The first portion 42a of the insertion portion 42 may include a first sidewall 42a_S1 that contacts the second sidewall 21a2_S2 of the second sidewall portion 21a2, and a second sidewall 42a_S2 that contacts the second sidewall 21a1_S2 of the first sidewall portion 21a1. The second portion 42b of the insertion portion 42 may include a first sidewall 42b_S1 that contacts the first sidewall 23_S1 of the second spacer 23, and a second sidewall 42b_S2 that contacts the third sidewall 21a2_S3 of the second sidewall portion 21a2. The third sidewall 21a1_S3 of the first sidewall portion 21a1 may contact the first sidewall 23_S1 of the second spacer 23.

[0074] The upper portion 21b of the conductive pattern 21 may include a first sidewall 21b_S1 that contacts the first portion 42a of the insertion portion 42 and a second sidewall 21b_S2 that contacts the sidewall MP_S of the mask pattern MP.

[0075] The second sidewall 21b_S2 of the upper portion 21b of the conductive pattern 21 and the first sidewall 21a1_S1 of the first sidewall portion 21a1 of the conductive pattern 21 can be connected to each other and can intersect each other. The angle between the second sidewall 21b_S2 of the upper portion 21b of the conductive pattern 21 and the upper surface of the substrate 10 can be different from the angle between the first sidewall 21a1_S1 of the first sidewall portion 21a1 of the conductive pattern 21 and the upper surface of the substrate 10.

[0076] The first sidewall 21b_S1 of the upper portion 21b of the conductive pattern 21 and the second sidewall 21a1_S2 of the first sidewall portion 21a1 of the conductive pattern 21 can be connected to each other and can intersect each other. The angle between the first sidewall 21b_S1 of the upper portion 21b of the conductive pattern 21 and the upper surface of the substrate 10 may be different from the angle between the second sidewall 21a1_S2 of the first sidewall portion 21a1 of the conductive pattern 21 and the upper surface of the substrate 10.

[0077] The sidewall 31_S of the channel pattern 31, a portion of the lower surface 31_L of the channel pattern 31, and a portion of the upper surface 31_U of the channel pattern 31 can contact the source / drain pattern SD. The sidewall 32_S of the upper channel pattern 32, a portion of the lower surface 32_L of the upper channel pattern 32, and a portion of the upper surface 32_U of the upper channel pattern 32 can contact the upper source / drain pattern USD.

[0078] Since the semiconductor device according to some example embodiments includes a connecting conductive pattern 21, the portions electrically connecting the gate patterns GE1 and GE2 can have a relatively constant width. Therefore, the consistency of the threshold voltage of the unit transistor can be improved.

[0079] Since the semiconductor device according to some example embodiments includes a connecting conductive pattern 21, the distance between the channel pattern 31 and the insertion portion 42 of the covering insulating layer 40 in the first direction D1 can be relatively small. For example, the distance between the channel pattern 31 and the insertion portion 42 of the covering insulating layer 40 in the first direction D1 can be about 5.5 nm or less. Therefore, the size of the semiconductor device can be reduced and / or minimized.

[0080] FIG. 2 , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 5 , FIG. 6A , FIG. 6B , FIG. 6C , FIG. 7A , FIG. 7B , FIG. 7C , FIG. 7D , FIG. 8A , FIG. 8B , FIG. 8C , FIG. 9A , FIG. 9B , FIG. 9C , FIG. 10A , FIG. 10B , FIG. 10C , FIG. 11A , FIG. 11B , FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 1F , FIG. 14A , FIG. 14B , FIG. 14C , FIG. 14D and FIGS. 1A-1E It is used to describe the manufacturing process. FIG. 15A A diagram of a method for constructing a semiconductor device.

[0081] Reference FIG. 15B A substrate 10 may be provided. An insulating layer 111 may be disposed on the substrate 10. The insulating layer 111 may include an insulating material.

[0082] A preliminary channel layer 131 and a sacrificial layer 161 may be formed on the insulating layer 111. The preliminary channel layer 131 and the sacrificial layer 161 may be stacked alternately along a third direction D3. The preliminary channel layer 131 may include a semiconductor material. For example, the preliminary channel layer 131 may include a two-dimensional semiconductor material. The sacrificial layer 161 may include an insulating material. For example, the sacrificial layer 161 may include an oxide.

[0083] According to some example embodiments, a preliminary channel layer 131 may be deposited on the sacrificial layer 161. According to some example embodiments, the preliminary channel layer 131 may be deposited on a deposition substrate, and the preliminary channel layer 131 may be transferred from the deposition substrate onto the sacrificial layer 161. According to some example embodiments, the preliminary channel layer 131 may be grown on the sacrificial layer 161.

[0084] An interlayer insulation layer 143 may be formed on the sacrificial layer 161. The interlayer insulation layer 143 may include an insulating material.

[0085] An initial upper channel layer 132 and a sacrificial layer 161 may be formed on the interlayer insulating layer 143. The initial upper channel layer 132 and the sacrificial layer 161 may be stacked alternately along the third direction D3. The initial upper channel layer 132 may include a semiconductor material. For example, the initial upper channel layer 132 may include a two-dimensional semiconductor material.

[0086] According to some example embodiments, a preliminary upper trench layer 132 may be deposited on the sacrificial layer 161. According to some example embodiments, the preliminary upper trench layer 132 may be deposited on a deposition substrate, and the preliminary upper trench layer 132 may be transferred from the deposition substrate to the sacrificial layer 161. According to some example embodiments, the preliminary upper trench layer 132 may be grown on the sacrificial layer 161.

[0087] A mask layer ML may be formed on the sacrificial layer 161. The mask layer ML may include an insulating material.

[0088] Reference FIG. 15C and FIG. 15A The mask layer ML, sacrificial layer 161, initial upper channel layer 132, interlayer insulating layer 143, initial channel layer 131, and insulating layer 111 can be patterned. Each of the mask layer ML, sacrificial layer 161, initial upper channel layer 132, interlayer insulating layer 143, initial channel layer 131, and insulating layer 111 can be divided into multiple parts through patterning.

[0089] A liner 162 may be formed. Forming the liner 162 may include forming the liner 162 on the mask layer ML, the sacrificial layer 161, the preliminary upper channel layer 132, the interlayer insulating layer 143, the preliminary channel layer 131, and the insulating layer 111, and dividing the liner 162 into a plurality of liner 162 by removing the upper portion of the liner 162. The liner 162 may include an insulating material.

[0090] Reference FIG. 15B and FIG. 15C A gate sacrificial layer 163 may be formed on the liner 162 and the mask layer ML. A gate mask layer 164 may be formed on the gate sacrificial layer 163. For example, the gate sacrificial layer 163 may include silicon. The gate mask layer 164 may include an insulating material.

[0091] Reference FIGS. 1A-1H The gate sacrificial layer 163 and the gate mask layer 164 can be patterned. The gate sacrificial layer 163 can be patterned to divide the gate sacrificial layer 163 into multiple gate sacrificial patterns 165. The gate mask layer 164 can be patterned to divide the gate mask layer 164 into multiple gate mask patterns 166.

[0092] A preliminary spacer layer 123 may be formed on the mask layer ML, the gate sacrificial pattern 165, and the gate mask pattern 166. The preliminary spacer layer 123 may include an insulating material.

[0093] Reference FIG. 15A , FIG. 15B and FIG. 15C The mask layer ML, sacrificial layer 161, initial upper channel layer 132, interlayer insulating layer 143, initial channel layer 131, and insulating layer 111 can be patterned. Patterning the mask layer ML, sacrificial layer 161, initial upper channel layer 132, interlayer insulating layer 143, initial channel layer 131, and insulating layer 111 can include performing an etching process using the gate mask pattern 166 and the initial spacer layer 123 as an etching mask. In the etching process using the gate mask pattern 166 and the initial spacer layer 123 as an etching mask, the initial spacer layer 123 can be divided into a plurality of second spacers 23.

[0094] The mask layer ML can be patterned to divide it into multiple mask patterns MP. The sacrificial layer 161 can be patterned to divide it into multiple sacrificial patterns 171. The initial upper channel layer 132 can be patterned to divide it into multiple upper channel patterns 32. The interlayer insulating layer 143 can be patterned to divide it into multiple first interlayer insulating patterns 43. The initial channel layer 131 can be patterned to divide it into multiple channel patterns 31. The insulating layer 111 can be patterned to divide it into multiple insulating patterns 11.

[0095] The sacrificial pattern 171 can be selectively etched by the sidewalls of the sacrificial pattern 171. The sacrificial pattern 171 can be selectively etched such that the width of the sacrificial pattern 171 in the second direction D2 can be smaller than the width of the channel pattern 31 in the second direction D2 and the width of the upper channel pattern 32 in the second direction D2.

[0096] The inner spacer IS can be formed. The inner spacer IS can be formed on the sacrificial pattern 171.

[0097] Source / drain patterns (SDs) can be formed. According to some example embodiments, the channel pattern 31 can be used as a seed to form source / drain patterns (SDs) through an epitaxial growth process.

[0098] A second interlayer insulation pattern 44 can be formed. A second interlayer insulation pattern 44 can be formed on the source / drain pattern SD.

[0099] Upper source / drain patterns (USD) can be formed. According to some example embodiments, the upper channel pattern 32 can be used as a seed to form the upper source / drain pattern (USD) through an epitaxial growth process.

[0100] The first spacer 22 can be formed. The first spacer 22 can be formed on the source / drain pattern SD and the upper source / drain pattern USD.

[0101] A filling insulating layer 53 can be formed on the first spacer 22.

[0102] Reference FIG. 16A , FIG. 16B , FIG. 16A and FIG. 16B The gate mask pattern 166 can be removed. The gate sacrificial pattern 165 can be exposed by removing the gate mask pattern 166. A capping layer 172 can be formed on the filling insulating layer 53. The capping layer 172 may include an insulating material.

[0103] Reference FIGS. 1A-1H , FIG. 16A and FIG. 16B The gate sacrificial pattern 165 can be removed. The sacrificial pattern 171 can be removed. The insertion pattern 12 can be formed by etching the liner 162 in the process of removing the sacrificial pattern 171.

[0104] Reference FIG. 17 , FIG. 17 and FIGS. 1A-1H This allows the formation of a preliminary gate insulating layer (pGI). The preliminary gate insulating layer (pGI) may include an insulating material.

[0105] A preliminary gate layer pGE1 and a preliminary upper gate layer pGE2 can be formed. The preliminary gate layer pGE1 and the preliminary upper gate layer pGE2 may include conductive materials.

[0106] The preliminary gate insulating layer pGI, the preliminary gate layer pGE1, and the preliminary upper gate layer pGE2 can fill the empty spaces formed by removing the sacrificial pattern 171.

[0107] Reference FIG. 17 , ​ and ​ The initial upper gate layer pGE2 can be etched. By etching the initial upper gate layer pGE2, the top part of the initial gate insulating layer pGI can be exposed.

[0108] Reference ​ and ​By using a mask pattern MP as an etching mask, the initial gate layer pGE1 and the initial upper gate layer pGE2 can be etched. The initial upper gate layer pGE2 can be etched to divide the initial upper gate layer pGE2 into the upper gate pattern GE2. The initial gate layer pGE1 can be etched to divide the initial gate layer pGE1 into the gate pattern GE1.

[0109] The shape of the mask pattern MP can be changed during the etching process of the initial gate layer pGE1 and the initial upper gate layer pGE2.

[0110] Reference ​ and ​ A preliminary conductive layer 121 can be formed. The preliminary conductive layer 121 can be formed on the gate pattern GE1, the upper gate pattern GE2, the mask pattern MP, and the second spacer 23. The preliminary conductive layer 121 can contact the sidewalls of the gate pattern GE1, the upper gate pattern GE2, the mask pattern MP, and the second spacer 23, as well as the upper surface of the mask pattern MP.

[0111] For example, a preliminary conductive layer 121 can be formed by a deposition process. The preliminary conductive layer 121 may include a conductive material. For example, the preliminary conductive layer 121 may include a two-dimensional conductive material.

[0112] Reference ​ and ​ The conductive connection pattern 21 can be formed. According to some example embodiments, forming the conductive connection pattern 21 may include: performing a first etching process to etch the portion of the initial conductive connection layer 121 that contacts the upper surface of the mask pattern MP and the portion of the initial conductive connection layer 121 that contacts the upper surface of the substrate; and performing a second etching process to etch the portion of the initial conductive connection layer 121 that contacts the sidewall of the second spacer 23.

[0113] A connecting conductive pattern 21 can be formed between two adjacent channel patterns 31 along the first direction D1 using a first etching process. The connecting conductive pattern 21 between two adjacent channel patterns 31 along the first direction D1 can be divided into two connecting conductive patterns 21 by a second etching process. A second sidewall portion 21a2 (see [reference]) can be formed by the second etching process of the connecting conductive pattern 21. ​ ).

[0114] Reference ​ , ​ , ​ and ​ An insulating layer 40 can be formed. Insertion portions 42 of the insulating layer 40 can be formed between the connecting conductive patterns 21. An upper portion 41 of the insulating layer 40 can be formed on the upper surface of the mask pattern MP.

[0115] After the covering insulating layer 40 is formed, a planarization process for the covering insulating layer 40 can be performed. For example, the covering insulating layer 40 can be planarized by a chemical mechanical polishing process. The planarization process of the covering insulating layer 40 can remove the upper part of the filling insulating layer 53, the upper part of the third portion 22c of the first spacer 22, and the upper part of the second spacer 23.

[0116] Reference ​ This can form active contacts AC1 and AC2, gate contact GC, and lower active contact LAC.

[0117] Since the preliminary gate layer pGE1 and the preliminary upper gate layer pGE2 are etched by a self-aligned etching process using a mask pattern MP in the method of manufacturing a semiconductor device according to some example embodiments, the process of cutting the preliminary gate layer pGE1 and the preliminary upper gate layer pGE2 can be omitted, and the method of manufacturing a semiconductor device can be simplified.

[0118] ​ , ​ and ​ This is a cross-sectional view of a semiconductor device according to some example embodiments. In addition to what will be described below, according to... ​ , ​ and ​ Semiconductor devices can be used with... ​ Similar to semiconductor devices.

[0119] Reference ​ , ​ and ​ The semiconductor device may include a gate pattern GEa, a gate insulating layer GIa, a channel pattern 231, and a mask pattern MPa that overlap with the insulating pattern 11 along the third direction D3.

[0120] The conductive patterns 221 spaced apart from each other in the first direction D1 may be provided therebetween an insulating pattern 11, a gate pattern GEa, a gate insulating layer GIa, a channel pattern 231 and a mask pattern MPa that overlap in the third direction D3.

[0121] An insulating layer 240 can be provided on the connecting conductive pattern 221 and the mask pattern MP. A first spacer 222 can be provided on the source / drain pattern SD and a second spacer 223 can be provided on the mask pattern MPa. An active contact ACa can contact the source / drain pattern SD. A filling insulating layer 253 can be provided on the first spacer 222.

[0122] A first separating insulating layer 251 and a second separating insulating layer 252 can be provided. The active contact ACa can be provided between the first separating insulating layers 251, or between the first separating insulating layers 251 and the second separating insulating layer 252.

[0123] ​ and ​ This is an enlarged cross-sectional view of a semiconductor device according to some example embodiments. In addition to what will be described below, according to... ​ and ​ Semiconductor devices can be used with... ​ Similar to semiconductor devices.

[0124] Reference ​ and ​ The gate insulating layer GIb may include a first layer 311 and a second layer 312. The first layer 311 may be in contact with the gate pattern GE1b or the upper gate pattern GE2b. The second layer 312 may be in contact with the channel pattern 31 or the upper channel pattern 32. The first layer 311 and the second layer 312 may each include different insulating materials. The first layer 311 may be a high-dielectric layer having a higher dielectric constant than the second layer 312.

[0125] The gate pattern GE1b may include a first conductive layer 321 and a second conductive layer 322 surrounding the first conductive layer 321. The first conductive layer 321 and the second conductive layer 322 may each have different work functions.

[0126] The upper gate pattern GE2b may include a third conductive layer 331 and a fourth conductive layer 332 surrounding the third conductive layer 331. The third conductive layer 331 and the fourth conductive layer 332 may each have different work functions.

[0127] ​ This is an enlarged cross-sectional view of a semiconductor device according to some example embodiments. In addition to what will be described below, according to... ​ Semiconductor devices can be used with... ​ Similar to semiconductor devices.

[0128] Reference ​ The first spacer 422 on the source / drain pattern SDc, the upper source / drain pattern USDc, and the second interlayer insulation pattern 444 may include a first portion 422b disposed between two source / drain patterns SDc that are adjacent to each other along the first direction D1 and between two upper source / drain patterns USDc that are adjacent to each other along the first direction D1.

[0129] The first portion 422b of the first spacer 422 may include a first side portion P1, a second side portion P2, and a connecting portion P3. The first side portion P1 and the second side portion P2 may be spaced apart from each other in a first direction D1. The first side portion P1 and the second side portion P2 may be connected to each other through the connecting portion P3. Each of the first side portion P1 and the second side portion P2 may contact the source / drain pattern SDc and the upper source / drain pattern USDc.

[0130] A filler insulating layer 453 may be partially disposed on the connecting portion P3 between the first side portion P1 and the second side portion P2. A first separation insulating layer 451 may be disposed on the filler insulating layer 453 between the first side portion P1 and the second side portion P2. A second separation insulating layer 452 may be disposed between the first side portion P1 and the second side portion P2.

[0131] Since the semiconductor device according to some exemplary embodiments of the present invention includes a connected conductive pattern, the consistency of the threshold voltage of the unit transistor can be improved.

[0132] Since the semiconductor device according to some exemplary embodiments of the present invention includes interconnected conductive patterns, the size of the semiconductor device can be reduced and / or minimized.

[0133] Although some exemplary embodiments have been described with reference to the accompanying drawings, it should be understood that this disclosure is not intended to limit it to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the exemplary embodiments claimed in the appended claims. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and are not intended to be restrictive.

Claims

1. A semiconductor device, comprising: The first and second groove patterns overlap at least partially; A first gate pattern is located between the first channel pattern and the second channel pattern, and at least partially overlaps with the first channel pattern and the second channel pattern; A first connecting conductive pattern and a second connecting conductive pattern are spaced apart from each other in a first direction, and a first channel pattern, a second channel pattern and a first gate pattern are located between the first connecting conductive pattern and the second connecting conductive pattern. as well as A first source / drain pattern is connected to the first channel pattern and the second channel pattern. The first connecting conductive pattern and the second connecting conductive pattern are electrically connected to the first gate pattern.

2. The semiconductor device according to claim 1, wherein, The first and second conductive connection patterns comprise two-dimensional conductive materials.

3. The semiconductor device according to claim 1, wherein, The first and second channel patterns comprise two-dimensional semiconductor materials.

4. The semiconductor device according to claim 1, further comprising: The third channel pattern is spaced apart from the first channel pattern in the first direction; A fourth channel pattern, which is spaced apart from the second channel pattern in the first direction; A second gate pattern is located between the third channel pattern and the fourth channel pattern, and is spaced apart from the first gate pattern in the first direction; A third connecting conductive pattern and a fourth connecting conductive pattern are spaced apart from each other in the first direction, and a third channel pattern, a fourth channel pattern and a second gate pattern are located between the third connecting conductive pattern and the fourth connecting conductive pattern. as well as The second source / drain pattern is connected to the third and fourth channel patterns. The third and fourth connecting conductive patterns are electrically connected to the second gate pattern.

5. The semiconductor device according to claim 4, further comprising: An insulating layer is applied over the first to the fourth conductive connection patterns. The covering insulating layer includes an insertion portion between the second connecting conductive pattern and the third connecting conductive pattern.

6. The semiconductor device according to claim 5, wherein, The second conductive connection pattern includes: The first sidewall portion that contacts the first gate pattern The second sidewall portion connected to the first sidewall portion, and The second sidewall portions are spaced apart from each other in a second direction, which intersects the first direction.

7. The semiconductor device according to claim 6, wherein, The insertion portion includes: The first part contacts the sidewall of the first sidewall portion and the first sidewall of the second sidewall portion, and The second part, which respectively contacts the second sidewall of the second sidewall portion. The first portion of the insertion portion lies between the second portion of the insertion portion, and The width of the first portion of the insertion part in the first direction is greater than the width of each of the second portions of the insertion part in the first direction.

8. The semiconductor device according to claim 4, further comprising: A first spacer overlaps with both the first and second source / drain patterns. The first spacer includes: The first part is located between the first source / drain pattern and the second source / drain pattern. The second part, which is based on the first part, and A third portion, spaced apart from each other along a second direction on the second portion, wherein the second direction intersects the first direction, and The width of the first portion of the first spacer in the first direction is the same as the distance between the first source / drain pattern and the second source / drain pattern in the first direction.

9. A semiconductor device, comprising: The first and second groove patterns overlap at least partially; A first gate pattern is located between the first channel pattern and the second channel pattern, and overlaps with the first channel pattern and the second channel pattern; A first conductive pattern is spaced apart from the first channel pattern and the second channel pattern, and is electrically connected to the first gate pattern. as well as Source / drain patterns are connected to the first channel pattern and the second channel pattern. The first channel pattern, the second channel pattern, and the first gate pattern are located between the upper and lower surfaces of the first connecting conductive pattern.

10. The semiconductor device according to claim 9, wherein, The first conductive pattern comprises a conductive material that is different from the material of the first gate pattern.

11. The semiconductor device according to claim 9, wherein, The first gate pattern includes a first sidewall that contacts the sidewall of the first connected conductive pattern.

12. The semiconductor device of claim 11, further comprising: The second conductive pattern is in contact with the second sidewall of the first gate pattern. Wherein, the first sidewall and the second sidewall of the first gate pattern are opposite to each other, and The first conductive connection pattern and the second conductive connection pattern are spaced apart from each other.

13. The semiconductor device according to claim 12, wherein, The first channel pattern and the second channel pattern are located between the first connecting conductive pattern and the second connecting conductive pattern.

14. The semiconductor device of claim 9, further comprising: The third channel pattern at least partially overlaps with the first channel pattern, the first gate pattern, and the second channel pattern; A second gate pattern is located between the second channel pattern and the third channel pattern, and at least partially overlaps with the first channel pattern, the second channel pattern, the third channel pattern, and the first gate pattern. The second gate pattern is electrically connected to the first connecting conductive pattern.

15. The semiconductor device according to claim 9, further comprising: A mask pattern that at least partially overlaps with the first channel pattern, the second channel pattern, and the first gate pattern. The upper sidewall of the first conductive pattern is in contact with the sidewall of the mask pattern.

16. The semiconductor device according to claim 15, wherein, The lower sidewall of the first conductive pattern contacts the first gate pattern, and The lower sidewall of the first conductive pattern and the upper sidewall of the first conductive pattern intersect each other.

17. A semiconductor device, comprising: The first and second groove patterns overlap at least partially; A first gate pattern is located between the first channel pattern and the second channel pattern, and at least partially overlaps with the first channel pattern and the second channel pattern; A first connecting conductive pattern and a second connecting conductive pattern are spaced apart from each other in a first direction, and a first channel pattern, a second channel pattern and a first gate pattern are located between the first connecting conductive pattern and the second connecting conductive pattern. A first source / drain pattern is connected to the first channel pattern and the second channel pattern; The third channel pattern is spaced apart from the first channel pattern in the first direction; A fourth channel pattern, which is spaced apart from the second channel pattern in the first direction and overlaps with the third channel pattern; A second gate pattern, which overlaps with the third and fourth channel patterns between the third and fourth channel patterns, and is spaced apart from the first gate pattern in the first direction; A third connecting conductive pattern and a fourth connecting conductive pattern are spaced apart from each other in the first direction, and a third channel pattern, a fourth channel pattern and a second gate pattern are located between the third connecting conductive pattern and the fourth connecting conductive pattern. A second source / drain pattern is connected to the third channel pattern and the fourth channel pattern; A first spacer that at least partially overlaps with the first source / drain pattern and the second source / drain pattern; A first mask pattern that at least partially overlaps with the first channel pattern, the second channel pattern, and the first gate pattern; The second mask pattern at least partially overlaps with the third channel pattern, the fourth channel pattern and the second gate pattern; A second spacer is present on the first mask pattern, the second mask pattern, and the first spacer; as well as An insulating layer is applied over the first mask pattern, the second mask pattern, and the first connecting conductive pattern to the fourth connecting conductive pattern.

18. The semiconductor device according to claim 17, wherein, The first mask pattern is located between the first conductive connection pattern and the second conductive connection pattern.

19. The semiconductor device according to claim 17, wherein, The upper surface, lower surface, and sidewalls of the first channel pattern are in contact with the first source / drain pattern.

20. The semiconductor device of claim 17, further comprising: A first upper groove pattern and a second upper groove pattern, each of the first upper groove pattern and the second upper groove pattern at least partially overlaps with the first groove pattern and the second groove pattern; A first upper gate pattern is located between the first upper channel pattern and the second upper channel pattern; The third upper groove pattern and the fourth upper groove pattern overlap at least partially with the third groove pattern and the fourth groove pattern; A second upper gate pattern is located between the third upper channel pattern and the fourth upper channel pattern; A first upper source / drain pattern is connected to the first upper channel pattern and the second upper channel pattern; as well as The second upper source / drain pattern is connected to the third and fourth upper channel patterns. The first upper gate pattern is electrically connected to the first connection conductive pattern and the second connection conductive pattern. The second upper gate pattern is electrically connected to the third and fourth connection conductive patterns. The first upper channel pattern, the second upper channel pattern, and the first upper gate pattern are located between the first connection conductive pattern and the second connection conductive pattern, and The third upper channel pattern, the fourth upper channel pattern, and the second upper gate pattern are located between the third connecting conductive pattern and the fourth connecting conductive pattern.

Images