Semiconductor device, electronic apparatus, and method for manufacturing semiconductor device

Abstract

The present invention suppresses characteristic differences caused by process differences. A semiconductor device according to the present invention includes a semiconductor substrate, a plurality of element isolators, and a field effect transistor. In plan view, the field effect transistor is provided between an upper surface portion of a first element isolation portion and an upper surface portion of a second element isolation portion among the plurality of element isolation portions. The field effect transistor includes a gate electrode, a fin portion, a gate insulating film, and a convex portion. The convex portion is formed between the embedded portion of the gate electrode and a sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and has a width narrower than a width of the fin portion. The convex portion contains an impurity of an opposite conductivity type to the fin portion, and the impurity is distributed at an impurity concentration higher than an impurity concentration at other places of the semiconductor substrate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, an electronic device having a semiconductor device mounted thereon, and a method of manufacturing the semiconductor device. Background Technology

[0002] Solid-state imaging devices (light detection devices) include a source follower circuit that converts the charge obtained as a result of photoelectric conversion by a photoelectric conversion unit into a pixel signal based on that charge and outputs the pixel signal. Fin field-effect transistors (hereinafter referred to as Fin-FETs) are known to be commonly used to improve the characteristics of circuits within devices containing source follower circuits.

[0003] For example, Patent Document 1 discloses a transistor comprising: a gate electrode having a buried portion formed in such a way as to be buried from a planar portion formed in a planar manner on the surface of a semiconductor substrate toward the interior of the semiconductor substrate; and a channel region (fin) that contacts the side surface of the buried portion through an insulating film. List of existing technical documents Patent documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2017-183636 Summary of the Invention The problem the invention aims to solve

[0005] Among hole-gate FinFETs, especially those with shallow trenches drilled down to approximately 100 nm, the footprint is small, which is beneficial for miniaturization and allows for low-cost manufacturing with fewer steps. On the other hand, in cases where sharp bumps of silicon are formed between a tapered device isolation section (STI) and a silicon (Si) substrate, these bumps are considered tiny FinFETs and tend to act as parasitic transistors. Furthermore, the height and width of these bumps and the device isolation section vary due to process variations, resulting in differences in the transistor's conduction characteristics.

[0006] This disclosure is made in view of this situation, and the purpose of this disclosure is to provide a semiconductor device, electronic device, and method of manufacturing a semiconductor device capable of suppressing characteristic variations caused by process variations. Solution to the problem

[0007] One aspect of this disclosure is a semiconductor device comprising: a semiconductor substrate having a first surface portion and a second surface portion located opposite each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each of the element isolation portions having an upper surface portion and a sidewall portion disposed on the side of the first surface portion; and a field-effect transistor disposed in a planar view between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion, wherein the field-effect transistor includes: a gate electrode having a planar portion and one or more buried portions, the planar portion being planarly formed on the first surface portion of the semiconductor substrate. On a surface portion, the one or more buried portions are buried from the planar portion toward the interior of the semiconductor substrate; a fin is covered by the planar portion of the gate electrode and the one or more buried portions to form a channel; a gate insulating film is disposed between the gate electrode and the fin; and a protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin, and in the protrusion, impurities of the opposite conductivity type to those of the fin are distributed at a higher concentration than impurities contained in the interior of the semiconductor substrate outside the protrusion.

[0008] Another aspect of this disclosure is a semiconductor device comprising: a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each of the element isolation portions having an upper surface portion and a sidewall portion disposed on the side of the first surface portion; and a field-effect transistor disposed in a planar view between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion, wherein the field-effect transistor includes: a gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on the semiconductor substrate. On the first surface portion, the one or more buried portions are buried from the planar portion toward the interior of the semiconductor substrate; a fin is covered by the planar portion of the gate electrode and the one or more buried portions to form a channel; a gate insulating film is disposed between the gate electrode and the fin; a protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin; and a protrusion insulating film is disposed between the protrusion and the gate electrode, and the protrusion insulating film is thicker than the gate insulating film covering the fin.

[0009] Another aspect of this disclosure is an electronic device including a semiconductor device, the semiconductor device comprising: a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each of the element isolation portions having an upper surface portion and a sidewall portion disposed on the side of the first surface portion; and a field-effect transistor disposed in a planar view between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion, wherein the field-effect transistor includes: a gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on the semiconductor substrate. On the first surface portion, the one or more buried portions are buried from the planar portion toward the interior of the semiconductor substrate; a fin is covered by the planar portion of the gate electrode and the one or more buried portions to form a channel; a gate insulating film is disposed between the gate electrode and the fin; and a protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin, and in the protrusion, impurities of the opposite conductivity type to those of the fin are distributed at a higher concentration than impurities contained in the interior of the semiconductor substrate outside the protrusion.

[0010] Another aspect of this disclosure is an electronic device including a semiconductor device, the semiconductor device comprising: a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in a thickness direction; a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each of the element isolation portions having an upper surface portion and a sidewall portion disposed on the side of the first surface portion; and a field-effect transistor disposed in a planar view between the upper surface portion of the first element isolation portion and the upper surface portion of the second element isolation portion, wherein the field-effect transistor includes: a gate electrode having a planar portion and one or more buried portions, the planar portion being planarly formed in the semiconductor substrate. On the first surface portion of the substrate, one or more buried portions are embedded from the planar portion toward the interior of the semiconductor substrate; a fin is covered by the planar portion of the gate electrode and the one or more buried portions to form a channel; a gate insulating film is disposed between the gate electrode and the fin; a protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin; and a protrusion insulating film is disposed between the protrusion and the gate electrode, and the protrusion insulating film is thicker than the gate insulating film covering the fin.

[0011] Furthermore, another aspect of this disclosure is a method for manufacturing a semiconductor device, the method comprising the steps of: preparing a semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in a thickness direction; forming a plurality of element isolation portions extending in the thickness direction of the semiconductor substrate, each element isolation portion having an upper surface portion and a sidewall portion disposed on the side of the first surface portion; forming a recessed portion in the thickness direction from the first surface portion of the semiconductor substrate between the first element isolation portion and the second element isolation portion of the plurality of element isolation portions, and forming a fin of a field-effect transistor protruding from the recessed portion and a protrusion having a width smaller than the width of the fin; distributing impurities of a conductivity type opposite to that of the fin in the protrusion at a concentration higher than the concentration of impurities contained in the interior of the semiconductor substrate outside the protrusion; and forming a gate electrode of the field-effect transistor between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion, the gate electrode covering the fin through a gate insulating film. Attached Figure Description

[0012] Figure 1 This is a schematic plan view illustrating a construction example of a semiconductor device according to a first embodiment of the present disclosure. Figure 2 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a first embodiment of the present disclosure. Figure 3 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a second embodiment of the present disclosure. Figure 4 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a third embodiment of the present disclosure. Figure 5 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a fourth embodiment of the present disclosure. Figure 6 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a fifth embodiment of the present disclosure. Figure 7 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a sixth embodiment of the present disclosure. Figure 8 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a seventh embodiment of the present disclosure. Figure 9A This is a cross-sectional view (Part 1) showing the process steps of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. Figure 9BThis is a cross-sectional view (Part 2) showing the process steps of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. Figure 9C This is a cross-sectional view (Part 3) showing the process steps of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. Figure 9D This is a cross-sectional view (Part 4) showing the process steps of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. Figure 9E This is a cross-sectional view (Part 5) showing the process steps of a method for manufacturing a semiconductor device according to a seventh embodiment of the present disclosure. Figure 10 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to an eighth embodiment of the present disclosure. Figure 11 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a ninth embodiment of the present disclosure. Figure 12 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device according to a tenth embodiment of the present disclosure. Figure 13 This is a diagram illustrating a schematic construction of an example of a light detection device according to the eleventh embodiment of this disclosure. Figure 14 This is a diagram illustrating an example of a schematic construction of a light detection device according to a twelfth embodiment of the present disclosure. Figure 15 It shows Figure 14 The circuit diagram shown is an example of a sensor pixel and readout circuit. Figure 16 This is a block diagram illustrating an example of the construction of an electronic device. Figure 17 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system that utilizes this technology. Figure 18 It shows Figure 17 A block diagram illustrating an example of the functional construction of the camera head and CCU. Figure 19 This is a block diagram illustrating an example of a schematic construction of a vehicle control system to which this technology is applied. Figure 20 It shows Figure 19 An explanatory diagram showing an example of the installation location of the vehicle exterior information detection unit and the camera unit. Detailed Implementation

[0013] Embodiments of this disclosure will be described below with reference to the accompanying drawings. In the drawings referenced in the following description, identical or similar parts are given identical or similar reference numerals, and redundant descriptions are omitted. However, it should be noted that the drawings are schematic, and the relationships between thicknesses and planar dimensions, the thickness ratios of various devices or components, etc., may differ from reality. Therefore, the following description should be taken into consideration when determining specific thicknesses and dimensions. Furthermore, different drawings may naturally contain parts with different dimensional relationships and scales.

[0014] In this specification, "first conductivity type" refers to either p-type or n-type, and "second conductivity type" refers to another p-type or n-type that is different from "first conductivity type". Furthermore, the "+" or "-" added to "n" or "p" indicates a semiconductor region with a higher or lower impurity concentration than a semiconductor region without either "+" or "-". However, it should be noted that even semiconductor regions with the same "n" and "n" do not necessarily have identical impurity concentrations.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for illustrative purposes and do not limit the technical concept of this disclosure. For example, needless to say, when an object is rotated 90° and then observed, up and down will be converted to left and right; and when an object is rotated 180° and then observed, up and down will be reversed. Note that the effects described in this manual are merely illustrative and not restrictive, and other effects may also be provided.

[0016] <First Implementation Plan> (Example of semiconductor device construction) Figure 1 This is a schematic plan view illustrating a construction example of a semiconductor device 1 according to a first embodiment of the present disclosure. Figure 2 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1 according to a first embodiment of the present disclosure. Figure 2 The diagram shows the section cut along line A-A'. Figure 1 A cross-section of the plan view.

[0017] like Figure 1 and Figure 2 As shown, the semiconductor device 1 according to the first embodiment includes: a semiconductor substrate 2, a metal-oxide-semiconductor (MOS) transistor 3 (an example of a "field-effect transistor" of this disclosure) disposed on the semiconductor substrate 2, and a structure in the thickness direction of the semiconductor substrate 2. Figure 1 Multiple element isolation sections 5 extending in the direction indicated by the middle arrow Z.

[0018] The semiconductor substrate 2 is made of, for example, monocrystalline silicon. The semiconductor substrate 2 has a front side 2a (an example of the "first surface portion" in this disclosure) and a back side 2b (the "second surface portion" in this disclosure) located on the opposite side of the front side 2a. A MOS transistor 3 is disposed on the front side 2a of the semiconductor substrate 2. The element isolation portion 5 is an insulating film for electrically isolating elements adjacent to each other in the horizontal direction, and is, for example, made of a silicon oxide film buried in a trench. The MOS transistor 3 is disposed between a first element isolation portion 51 and a second element isolation portion 52 among a plurality of element isolation portions 5. The first element isolation portion 51 has a positive conical structure and has an upper surface portion 51a located on the front side 2a of the semiconductor substrate 2 and a lower surface portion 51a in the thickness direction of the semiconductor substrate 2. Figure 2 The sidewall portion 51b extends in the direction indicated by the middle arrow Z. The second element isolation portion 52 has a positive conical structure and has an upper surface portion 52a located on the front side 2a of the semiconductor substrate 2 and a sidewall portion 52b extending in the thickness direction of the semiconductor substrate 2. Note that the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 are not at the same height as the surface 2a of the semiconductor substrate 2. Specifically, the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 may be higher than the surface 2a of the semiconductor substrate 2. The MOS transistor 3 is arranged between the upper surface portion 51a of the first element isolation portion 51 and the upper surface portion 52a of the second element isolation portion 52 in the plan view.

[0019] The MOS transistor 3 includes: a fin 10 with a channel, a gate insulating film 20, a gate electrode 30, and a source region 41 and a drain region 42 disposed in the semiconductor substrate 2.

[0020] Fin 10 is, for example, part of semiconductor substrate 2 and is made of monocrystalline silicon. The conductivity type of fin 10 is, for example, n-type. Gate insulating film 20 is provided to cover the upper and side surfaces of fin 10. The upper surface of fin 10 is part of surface 2a of semiconductor substrate 2. Gate insulating film 20 is, for example, made of silicon oxide film. Fin 10 is, for example, long in the Y-axis direction and short in the X-axis direction.

[0021] The gate electrode 30 has a planar portion 31 and at least one buried portion 32, and covers the fin portion 10 through a gate insulating film 20. For example, the gate electrode 30 is arranged facing the upper and side surfaces of the fin portion 10 through the gate insulating film 20. Therefore, the gate electrode 30 can simultaneously apply a gate voltage to the upper and side surfaces of the fin portion 10. That is, the gate electrode 30 can simultaneously apply a gate voltage to the fin portion 10 from three directions: the upper side, the left side, and the right side. Therefore, the gate electrode 30 can completely deplete the fin portion 10. Note that the gate electrode 30 is, for example, made of a polysilicon (Poly-Si) film doped with impurities.

[0022] The planar portion 31 of the gate electrode 30 is formed flatly on the front surface 2a of the semiconductor substrate 2, a portion of the upper surface portion 51a of the first element isolation portion 51, and a portion of the upper surface portion 52a of the second element isolation portion 52. Among the plurality of buried portions 32, the first buried portion 321 is located on the side of the first element isolation portion 51 and is buried from the planar portion 31 toward the interior of the semiconductor substrate 2. The second buried portion 322 is located on the side of the second element isolation portion 52 and is buried from the planar portion 31 toward the interior of the semiconductor substrate 2.

[0023] The source region 41 is disposed on and near the front side 2a of the semiconductor substrate 2. Figure 1 In the Y-axis direction, the source region 41 is connected to one side of the fin 10. The drain region 42 is disposed on and near the front surface 2a of the semiconductor substrate 2. Figure 1 In the Y-axis direction, the drain region 42 is connected to the other side of the fin 10. When the gate voltage applied to the gate electrode 30 exceeds the threshold voltage, a channel is formed between the source region 41 and the drain region 42.

[0024] Meanwhile, in the first embodiment, from the upper surface portion 51a of the first element isolation portion 51 in the thickness direction of the semiconductor substrate 2 ( Figure 2 A dug portion 51c is formed in the direction shown in the middle (Z), and a dug portion 52c is also formed in the thickness direction of the semiconductor substrate 2 from the upper surface portion 52a of the second element isolation portion 52. A first buried portion 321 of the gate electrode 30 is buried in the dug portion 51c. A second buried portion 322 of the gate electrode 30 is buried in the dug portion 52c. A protrusion 621 with a width narrower than the width of the fin portion 10 is formed between the dug portion 51c and the semiconductor substrate 2. Furthermore, a protrusion 622 with a width narrower than the width of the fin portion 10 is formed between the dug portion 52c and the semiconductor substrate 2. A gate insulating film 20 is arranged around the protrusions 621 and 622. In addition, the height of the top of the protrusions 621 and 622 is lower than the upper surface portion of the fin portion 10, and higher than the bottom of each of the dug portions 51c and 52c.

[0025] These protrusions 621 and 622 are considered as miniature Fin-FETs and easily function as parasitic transistors. Furthermore, the height and width of the element isolation portion 5 vary due to process differences, resulting in variations in the transistor's conduction characteristics. Therefore, in the first embodiment of this disclosure, each of the protrusions 621 and 622 is doped with an impurity of a second conductivity type (e.g., p-type) opposite to the first conductivity type (e.g., n-type) of the fin 10 to form a high-concentration second conductivity type region 63. In this high-concentration second conductivity type region 63, the impurities are distributed at a higher concentration than in the second conductivity type region 61 contained within the semiconductor substrate 2 outside the protrusions 621 and 622. This promotes the movement of charge carriers from the second conductivity type region 61 of the semiconductor substrate 2 to the fin 10 and suppresses the movement of charge carriers to the protrusions 621 and 622. Therefore, characteristic differences caused by process variations can be suppressed.

[0026] <The Role and Effects of the First Implementation Plan> As described above, according to the first embodiment, since each of the protrusions 621 and 622 is doped with impurities of a second conductivity type opposite to the first conductivity type of the fin 10, a high-concentration second conductivity type region 63 is formed. Furthermore, in the high-concentration second conductivity type region 63, the impurities are distributed at a higher concentration than in the second conductivity type region 61 contained within the semiconductor substrate 2 outside of the protrusions 621 and 622. Therefore, it is possible to prevent the preferential formation of an inversion layer in the protrusions 621 and 621 compared to the fin 10. This promotes the movement of charge carriers from the second conductivity type region 61 of the semiconductor substrate 2 to the fin 10 and suppresses the movement of charge carriers to the protrusions 621 and 622. Thus, characteristic differences caused by process variations can be suppressed.

[0027] <Second Implementation Plan> Figure 3 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1A according to a second embodiment of the present disclosure. Figure 3 In the middle, with the above Figure 2 The same parts are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0028] In a second embodiment of this disclosure, the gate electrode 30A of the MOS transistor 3A further includes a third buried portion 323. The third buried portion 323 is formed between the first buried portion 321 and the second buried portion 322. Additionally, a first fin 11 is formed between the first buried portion 321 and the third buried portion 323. A second fin 12 is formed between the second buried portion 322 and the third buried portion 323. Therefore, the gate electrode 30A can simultaneously apply a gate voltage to the upper surface and side surface of each of the first fin 11 and the second fin 12 in three directions.

[0029] <The Role and Effects of the Second Implementation Plan> As described above, according to the second embodiment, since it can produce similar effects as the first embodiment, and the gate electrode 30A can simultaneously apply gate voltage to the upper surface and side surface of each of the first fin 11 and the second fin 12 in three directions, a transistor with high driving capability can be realized.

[0030] <Third Implementation Plan> Figure 4 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1B according to a third embodiment of the present disclosure. Figure 4 In the middle, with the above Figure 2 The same parts are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0031] In the third embodiment of this disclosure, the first element isolation portion 51 has a recessed portion 51d, the recessed portion 51d being in the thickness direction of the semiconductor substrate 2 ( Figure 4 The first buried portion 321, which is formed from the upper surface portion 51a in the direction indicated by the middle arrow Z, has the gate electrode 30 buried in the buried portion 51d. In addition, the second element isolation portion 52 has a buried portion 52d, which is formed from the upper surface portion 52a in the thickness direction of the semiconductor substrate 2, and has the gate electrode 30 buried in the buried portion 32d.

[0032] The bottom of the recess 51d is higher than the top of the protrusion 621. Additionally, the bottom of the recess 52d is higher than the top of the protrusion 622. In the third embodiment of this disclosure, similar to the first embodiment, each of the protrusions 621 and 622 is also doped with impurities of a second conductivity type opposite to the first conductivity type of the fin 10 to form a high-concentration second conductivity type region 63. Furthermore, the high-concentration second conductivity type region 63 contains impurities at a higher concentration than those in the second conductivity type region 61 contained in the semiconductor substrate 2 outside the protrusions 621 and 622.

[0033] <The Role and Effects of the Third Implementation Plan> As described above, the third embodiment can also produce the same effects as the first embodiment.

[0034] <Fourth Implementation Plan> Figure 5 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1C according to a fourth embodiment of the present disclosure. Figure 5 In the middle, with the above Figure 2 The same parts are given the same reference numerals, and their detailed descriptions are omitted. In a fourth embodiment of this disclosure, a raised insulating film 71 is disposed between the raised portion 621 and the first buried portion 321 of the gate electrode 30. Furthermore, a raised insulating film 72 is disposed between the raised portion 622 and the second buried portion 322 of the gate electrode 30. The raised insulating films 71 and 72 are at least 1 nm thicker than the gate insulating film 20 covering the fin 10 over the entire outer periphery of the raised portions 621 and 622.

[0035] <The Role and Effects of the Fourth Implementation Plan> As described above, according to the fourth embodiment, the convex insulating films 71 and 72 are disposed between the convex portions 621 and 622 and the gate electrode 30, and the convex insulating films 70 and 72 are formed to be thicker than the gate insulating film 20 covering the fin 10, thereby preventing the inversion layer from being formed preferentially in the convex portions 621 and 622 instead of in the fin 10. Therefore, characteristic differences caused by process variations can be suppressed.

[0036] <Fifth Implementation Plan> Figure 6 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1D according to a fifth embodiment of the present disclosure. Figure 6 In the middle, with the above Figure 2 and Figure 5 The same parts are given the same reference numerals, and their detailed descriptions are omitted.

[0037] In the fifth embodiment of this disclosure, similar effects as those in the fourth embodiment can be achieved, and since the gate electrode 30A can simultaneously apply gate voltage to the upper and side surfaces of each of the first fin 11 and the second fin 12 in three directions, a transistor with high drive capability can be realized.

[0038] <Sixth Implementation Plan> Figure 7 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1E according to a sixth embodiment of the present disclosure. Figure 7 In the middle, with the above Figure 4 and Figure 5 The same parts are given the same reference numerals, and their detailed descriptions are omitted.

[0039] In the sixth embodiment of this disclosure, similar effects and functions as in the third and fourth embodiments can be achieved.

[0040] <Seventh Implementation Plan> Figure 8 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1F according to a seventh embodiment of the present disclosure. Figure 8 In the middle, with the above Figure 2 and Figure 5 The same parts are given the same reference numerals, and their detailed descriptions are omitted.

[0041] In the seventh embodiment of this disclosure, no high-concentration second conductivity type region 63 or any second conductivity type region is formed inside the protrusions 621 and 622. Furthermore, since the tops of the protrusions 621 and 622 are higher than the bottoms of the recesses 51c and 52c, the protrusions are oxidized from all directions. Therefore, the insulating films 71 and 72 of the protrusions can be easily thickened.

[0042] (Method for manufacturing semiconductor devices) Figures 9A to 9E This is a cross-sectional view showing the process steps of a method for manufacturing a semiconductor device 1F according to a seventh embodiment of the present disclosure. Note that the semiconductor device 1F is manufactured using various apparatuses such as film deposition apparatuses (including chemical vapor deposition (CVD) apparatuses and sputtering apparatuses), ion implantation apparatuses, thermal processing apparatuses, etching apparatuses, chemical mechanical polishing (CMP) apparatuses, and bonding apparatuses. These apparatuses are collectively referred to as manufacturing apparatuses.

[0043] exist Figure 9A In the process, a single-crystal silicon semiconductor substrate 2 is prepared. For example... Figure 9B As shown, the manufacturing apparatus forms multiple element isolation portions 5 on the semiconductor substrate 2. Next, in Figure 9C In this process, an anti-reflective film 81 is formed on the front side 2a of the semiconductor substrate 2, the upper surface 51a of the first element isolation portion 51, and the upper surface 52a of the second element isolation portion 52. During the photolithography process, a photoresist is patterned on the anti-reflective film 81, and trenches 821 and 822 are formed in a manner that overlaps with the upper surface 51a of the first element isolation portion 51 and the upper surface 52a of the second element isolation portion 52. As a result, fins 10 and protrusions 621 and 622 are formed.

[0044] Next, in Figure 9D In (1), the manufacturing apparatus removes the anti-reflective film 81 and the resist in a dry etching process, forms a gate insulating film 20 on the upper and side surfaces of the fin 10, forms a protrusion insulating film 71 around the protrusion 621, and forms a protrusion insulating film 721 around the protrusion 622. At this time, as... Figure 9D As shown in (2), for example, an insulating material is formed on the protrusion 622, and a resist mask is formed on the insulating material using a known photolithography technique. Then, an insulating material is deposited in the opening of the resist mask such that the thickness of the insulating material is greater than the thickness of the gate insulating film 20. Then, the resist mask is removed.

[0045] Next, in Figure 9EIn this process, the manufacturing apparatus forms a gate electrode 30 on the recess 51c of the first element isolation portion 51, the recess 52c of the second element isolation portion 52, and the surface 2a of the semiconductor substrate 2.

[0046] <The Role and Effects of the Seventh Implementation Plan> As described above, according to the seventh embodiment, the protrusion insulating films 71 and 72 are disposed between the protrusions 621 and 622 and the gate electrode 30, and the protrusion insulating films 71 and 72 are formed to be thicker than the gate insulating film 20 covering the fin 10, thereby preventing the inversion layer from being formed in the protrusions 621 and 622 rather than in the fin 10. Therefore, characteristic differences caused by process variations can be suppressed.

[0047] <Eighth Implementation Plan> Figure 10 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1G according to an eighth embodiment of the present disclosure. Figure 8 In the middle, with the above Figure 2 and Figure 5 The same parts are given the same reference numerals, and their detailed descriptions are omitted.

[0048] In the eighth embodiment of this disclosure, similar effects as those in the seventh embodiment can be achieved, and since the gate electrode 30A can simultaneously apply gate voltage to the upper and side surfaces of each of the first fin 11 and the second fin 12 in three directions, a transistor with high drive capability can be realized.

[0049] <Ninth Implementation Plan> Figure 11 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1H according to a ninth embodiment of the present disclosure. Figure 11 In the middle, with the above Figure 4 and Figure 8 The same parts are given the same reference numerals, and their detailed descriptions are omitted.

[0050] In the ninth embodiment of this disclosure, similar effects and functions as in the third and seventh embodiments can be achieved.

[0051] <Tenth Implementation Plan> Figure 12 This is a schematic cross-sectional view illustrating a construction example of a semiconductor device 1I according to a tenth embodiment of the present disclosure. Figure 12 In the middle, with the above Figure 11 The same parts are given the same reference numerals, and their detailed descriptions are omitted.

[0052] In a tenth embodiment of this disclosure, a raised insulating film 91 is disposed between the raised portion 621 and the first embedded portion 321 of the gate electrode 30. Furthermore, a raised insulating film 92 is disposed between the raised portion 622 and the second embedded portion 322 of the gate electrode 30. The raised insulating film 91 includes: a first portion 911, which is thicker than the gate insulating film 20 covering the fin 10 and has a maximum first thickness at its top; and a second portion 912, which has a thickness less than the first thickness. Moreover, the raised insulating film 91 gradually thickens from the second portion 912 towards the first portion 911.

[0053] The raised insulating film 92 includes: a first portion 921, which is thicker than the gate insulating film 20 covering the fin 10 and has a maximum first thickness at its top; and a second portion 922, which has a thickness less than the first thickness. Moreover, the raised insulating film 92 gradually thickens from the second portion 922 toward the first portion 921.

[0054] In the tenth embodiment of this disclosure, similar effects and functions as in the seventh embodiment can be achieved.

[0055] <Eleventh Implementation Plan> (Example of the first optical detection device) The semiconductor device 1 according to the first embodiment, the semiconductor device 1A according to the second embodiment, the semiconductor device 1B according to the third embodiment, the conductor device 1C according to the fourth embodiment, the semiconductor device 1D according to the fifth embodiment, the semiconductor device 1E according to the sixth embodiment, the semiconductor device 1F according to the seventh embodiment, the semiconductor device 1G according to the eighth embodiment, the semiconductor device 1H according to the ninth embodiment, and the semiconductor device 1I according to the tenth embodiment are all applicable to the first optical detection device. Examples of the first optical detection device employing semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, or 1I will be described below.

[0056] Figure 13 A schematic construction of an example of a light detection device according to the eleventh embodiment of this disclosure is shown. Figure 13As shown, the light detection device 1-1 of this example includes: a semiconductor substrate 11-1; a pixel region (so-called imaging region) 3-1, including pixels 2-1 of multiple photoelectric conversion elements arranged regularly in two dimensions on the silicon substrate; and a peripheral circuit section. Each pixel 2-1 includes, for example, a photodiode used as a photoelectric conversion element and multiple pixel transistors (so-called MOS transistors). The multiple pixel transistors may include three types of transistors, namely, for example, a transfer transistor, a reset transistor, and an amplification transistor. Additionally, by adding a selection transistor, the multiple pixel transistors may include four types of transistors. Since the equivalent circuit of a unit pixel is similar to common circuits, its detailed description is omitted. Pixels 2-1 may have a shared pixel structure. In the third embodiment of this disclosure, the MOS transistor 3 described in the first embodiment or the MOS transistor 3A described in the second embodiment is used as one or more of the multiple pixel transistors.

[0057] The shared pixel structure includes multiple photodiodes, multiple transmission transistors, a shared floating diffuser, and various other shared pixel transistors.

[0058] The peripheral circuit section includes a vertical drive circuit 4-1, a column signal processing circuit 5-1, a horizontal drive circuit 6-1, an output circuit 7-1, and a control circuit 8-1.

[0059] The control circuit 8-1 receives data such as the input clock and specified operating mode, and outputs data such as internal information of the solid-state imaging device. Specifically, the control circuit 8-1 generates clock signals and control signals based on the vertical synchronization signal, horizontal synchronization signal, and master clock, which serve as references for the operation of the vertical drive circuit 4-1, column signal processing circuit 5-1, horizontal drive circuit 6-1, etc. These signals are then input to the vertical drive circuit 4-1, column signal processing circuit 5-1, horizontal drive circuit 6-1, etc.

[0060] The vertical drive circuit 4-1 includes, for example, a shift register, selects a pixel drive line, supplies pulses to the selected pixel drive line for driving the pixel, and drives the pixel row by row. That is, the vertical drive circuit 4-1 sequentially and selectively scans the pixels 2-1 in the pixel region 3-1 in the vertical direction row by row, and supplies the pixel signal based on the signal charge generated corresponding to the amount of light received in, for example, a photodiode used as the photoelectric conversion element of each pixel 2-1 to the corresponding column signal processing circuit 5-1 through the vertical signal line 9-1.

[0061] The column signal processing circuit 5-1 is arranged, for example, corresponding to the column of pixel 2-1, and performs signal processing such as noise removal on the signal output from pixel 2-1 in a row for each pixel column. That is, the column signal processing circuit 5-1 performs signal processing such as CDS for removing fixed-pattern noise specific to pixel 2-1, signal amplification, and AD conversion. A horizontal selection switch (not shown) is connected and disposed between the output stage of the column signal processing circuit 5-1 and the horizontal signal line 10-1.

[0062] The horizontal drive circuit 6-1 includes, for example, a shift register, which sequentially selects the column signal processing circuit 5-1 by outputting horizontal scan pulses in sequence, and causes the column signal processing circuit 5-1 to output pixel signals to the horizontal signal line 10-1.

[0063] Output circuit 7-1 processes the signals sequentially supplied to column signal processing circuit 5-1 via horizontal signal line 10-1 and outputs the processed signal. For example, it may perform buffering only, or it may perform black level adjustment, column offset correction, various types of digital signal processing, etc. Input / output terminal 12-1 exchanges signals with external devices.

[0064] As described above, according to the eleventh embodiment, even when the semiconductor device is applied to the photodetector 1-1, it can produce similar effects and functions as those in the first to tenth embodiments.

[0065] <Twelfth Implementation Plan> (Application example of the second optical detection device) Any one of the semiconductor device 1 according to the first embodiment, the semiconductor device 1A according to the second embodiment, the semiconductor device 1B according to the third embodiment, the semiconductor device 1C according to the fourth embodiment, the semiconductor device 1D according to the fifth embodiment, the semiconductor device 1E according to the sixth embodiment, the semiconductor device 1F according to the seventh embodiment, the semiconductor device 1G according to the eighth embodiment, the semiconductor device 1H according to the ninth embodiment, and the semiconductor device 1I according to the tenth embodiment is applicable to the second optical detection device. Examples of second optical detection devices using semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, or 1I will be described below.

[0066] Figure 14An example of a schematic construction of a light detection device 1-2 according to a twelfth embodiment of the present disclosure is shown. The light detection device 1-2 includes three substrates (a first substrate 10-2, a second substrate 20-2, and a third substrate 30-2). The light detection device 1-2 has a three-dimensional structure formed by bonding the three substrates (the first substrate 10-2, the second substrate 20-2, and the third substrate 30-2) together. The first substrate 10-2, the second substrate 20-2, and the third substrate 30-2 are stacked sequentially.

[0067] The first substrate 10-2 includes a plurality of sensor pixels 12-2 performing photoelectric conversion on a semiconductor substrate 11-2. The plurality of sensor pixels 12-2 are arranged in a matrix in pixel regions 13-2 of the first substrate 10-2. The second substrate 20-2 includes a readout circuit 22-2 on a semiconductor substrate 21-2 for every four sensor pixels 12-2. The readout circuit 22-2 outputs a pixel signal based on the charge output from the sensor pixels 12-2. The second substrate 20-2 includes a plurality of pixel driving lines 23-2 extending in the row direction and a plurality of vertical signal lines 24-2 extending in the column direction. The third substrate 30-2 includes logic circuitry 32-2 for processing the pixel signals on the semiconductor substrate 31-2. Logic circuitry 32-2 includes, for example, a vertical driving circuitry 33-2, a column signal processing circuitry 34-2, a horizontal driving circuitry 35-2, and a system control circuitry 36-2. Logic circuitry 32-2 (specifically, horizontal driving circuitry 35-2) outputs the output voltage Vout of each sensor pixel 12-2 to the outside. In logic circuit 32-2, for example, a low-resistance region containing silicide formed using a self-aligned silicide (silicide) process with CoSi2, NiSi, etc., can be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0068] For example, the vertical drive circuit 33-2 sequentially selects multiple sensor pixels 12-2 row by row. For example, the column signal processing circuit 34-2 performs correlated double sampling (CDS) processing on the pixel signals output by each sensor pixel 12-2 in the row selected by the vertical drive circuit 33-2. The column signal processing circuit 34-2 extracts the signal level of the pixel signals, for example, by performing CDS processing, and maintains pixel data based on the amount of light received by each sensor pixel 12-2. For example, the horizontal drive circuit 35-2 sequentially outputs the pixel data maintained in the column signal processing circuit 34-2 to the outside. The system control circuit 36-2 controls, for example, the driving of each block in the logic circuit 32-2 (vertical drive circuit 33-2, column signal processing circuit 34-2, and horizontal drive circuit 35-2).

[0069] Figure 15 An example of sensor pixel 12-2 and readout circuit 22-2 is shown. In the following description, as... Figure 15 The diagram illustrates the case where four sensor pixels 12-2 share a single readout circuit 22-2. Here, "shared" means that the outputs of the four sensor pixels 12-2 are input to the same readout circuit 22-2.

[0070] Each sensor pixel 12-2 shares a common component. Figure 15 In this context, identification numbers (1, 2, 3, and 4) are added to the end of the reference numerals of the components of sensor pixel 12-2 to distinguish them from each other. In the following description, when it is necessary to distinguish the components of sensor pixel 12-2 from each other, the identification numbers are assigned to the end of the reference numerals of the components of sensor pixel 12-2; however, when it is not necessary to distinguish the components of sensor pixel 12-2 from each other, the identification numbers at the end of the reference numerals of the components of sensor pixel 12-2 are omitted.

[0071] Each sensor pixel 12-2 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffuser FD temporarily holding the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD generates charge based on the amount of received light by performing photoelectric conversion. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffuser FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23-2. The transfer transistor TR is, for example, a complementary metal-oxide-semiconductor (CMOS) transistor.

[0072] The floating diffusers FD of sensor pixels 12-2, sharing a common readout circuit 22-2, are electrically connected to each other and to the input of the common readout circuit 22-2. The readout circuit 22-2 includes, for example, a reset transistor RST, a select transistor SEL, and an amplifying transistor AMP. Note that the select transistor SEL can be omitted if necessary. The source of the reset transistor RST (the input of the readout circuit 22-2) is electrically connected to the floating diffuser FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplifying transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23-2 (see reference). Figure 14 The source of the amplifying transistor AMP is electrically connected to the drain of the select transistor SEL, and the gate of the amplifying transistor AMP is electrically connected to the source of the reset transistor RST. The source of the select transistor SEL (output of the readout circuit 22-2) is electrically connected to the vertical signal line 24-2, and the gate of the select transistor SEL is electrically connected to the pixel drive line 23-2 (see reference). Figure 8 ).

[0073] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffuser FD. The reset transistor RST resets the potential of the floating diffuser FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffuser FD is reset to the potential of the power supply line VDD. The select transistor SEL controls the output timing of the pixel signal from the readout circuit 22-2. The amplifying transistor AMP generates a voltage signal as a pixel signal based on the level of charge held in each floating diffuser FD. The amplifying transistor AMP constitutes a source follower type amplifier and outputs a pixel signal having a voltage based on the level of charge generated in each photodiode PD. When the select transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of each floating diffuser FD and outputs a voltage corresponding to that potential through the nematic signal processing circuit 34-2 via the vertical signal line 24-2. The reset transistor RST, the amplifying transistor AMP, and the select transistor SEL are, for example, CMOS transistors. In the fourth embodiment of this disclosure, the MOS transistor 3 described in the first embodiment or the MOS transistor 3A described in the second embodiment is used as one or more of a plurality of pixel transistors.

[0074] <Other Implementation Plans> As described above, the present technology has been illustrated according to the first to twelfth embodiments, but it should not be construed as limiting the present technology by the description and drawings that form part of this disclosure. It will be apparent to those skilled in the art that, when they understand the essential points of the technical content disclosed in one of the above embodiments, the present technology can include various alternative embodiments, examples, and operational techniques. Furthermore, the constructions disclosed in the first to twelfth embodiments can be appropriately combined without creating contradictions. For example, constructions disclosed in multiple different embodiments can be combined, or constructions disclosed in multiple different variations of the same embodiment can be combined.

[0075] <Examples of Electronic Device Applications> Furthermore, the aforementioned light detection device can be applied to various electronic devices, including camera systems such as digital cameras and digital video cameras, mobile phones with camera functions, and other devices with camera functions.

[0076] Figure 16 This is a block diagram illustrating an example of the construction of an electronic device. like Figure 16As shown, the electronic device 1010 includes an optical system 1020, a light detection device 1030, and a digital signal processor (DSP) 1040, and is configured by connecting the DSP 1040, a display device 1050, an operating system 1060, a memory 1080, a storage device 1090, and a power supply system 1100 via a bus 1070, and is capable of capturing still images and moving images.

[0077] The optical system 1020 includes one or more lenses that guide image light (incident light) from the subject to the light detection device 1030 and form an image on the light receiving surface (sensor unit) of the light detection device 1030.

[0078] As the light detection device 1030, any of the light detection devices described in the above-described structural examples is applicable. In the light detection device 1030, electrons are accumulated over a certain period of time based on the image formed on the light receiving surface via the optical system 1020. Then, a signal based on the electrons accumulated in the light detection device 1030 is supplied to the DSP 1040.

[0079] The DSP 1040 performs various types of signal processing on the signal from the photodetector 1030 to obtain an image, and temporarily stores the image data in the memory 1080. The image data stored in the memory 1080 is either stored in the storage device 1090 or supplied to the display device 1050 to display the image. Additionally, the operating system 1060 receives various user operations and supplies operation signals to the various components of the electronic device 1010; the power supply system 1100 supplies the power required to drive the various components of the electronic device 1010.

[0080] <Examples of the Application of Endoscopic Surgical Systems> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be applied to endoscopic surgical systems.

[0081] Figure 17 This is a diagram illustrating an example of a schematic configuration of an endoscopic surgical system to which the technology (the present technology) can be applied. Figure 17 The illustration shows a surgeon (physician) 11131 using an endoscopic surgery system 11000 to perform surgery on a patient 11132 in bed 11133. As shown, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 (such as a pneumoperitoneum tube 11111 and an energy device 11112), a support arm assembly 11120 (on which the endoscope 11100 is supported), and a trolley 11200 (on which various devices for endoscopic surgery are mounted).

[0082] Endoscope 11100 includes a tube 11101 and a camera 11102 connected to the proximal end of the tube 11101. The tube 11101 has a region of predetermined length from its distal end for insertion into a body cavity of a patient 11132. In the illustrated example, endoscope 11100 is described as an endoscope constructed as a so-called rigid endoscope having a rigid tube 11101. However, endoscope 11100 may also be constructed as a flexible endoscope having a flexible tube 11101.

[0083] The endoscope tube 11101 has an opening at its distal end for mounting an objective lens. A light source device 11203 is connected to the endoscope 11100, such that light generated by the light source device 11203 is guided through a light guide extending inside the endoscope tube 11101 to the distal end of the endoscope tube 11101 and illuminates the target for observation within the body cavity of the patient 11132 via the objective lens. It should be noted that the endoscope 11100 can be a forward-looking endoscope, or a slant-looking endoscope, or a lateral-looking endoscope.

[0084] An optical system and an image sensor are installed inside the camera 11102, so that reflected light (observation light) from the observed target is focused onto the image sensor by the optical system. The image sensor performs photoelectric conversion on the observation light to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. This image signal is transmitted as raw data (RAW) to the CCU (camera control unit) 11201.

[0085] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), and comprehensively controls the operation of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives image signals from the camera 11102 and performs various image processing on the image signals for displaying images based on the image signals, such as image processing (de-mosaic processing). The display device 11202 displays an image based on an image signal that has been image processed by the CCU 11201 under the control of the CCU 11201.

[0086] The light source device 11203 includes, for example, a light source such as a light-emitting diode (LED) and supplies illumination light to the endoscope 11100 for imaging the surgical area, etc. Input device 11204 is an input interface for endoscopic surgical system 11000. Users can input various types of information or commands into endoscopic surgical system 11000 via input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (type of illumination light, magnification, or focal length, etc.).

[0087] Treatment tool control device 11205 controls the drive of energy device 11112 used for cauterizing or cutting tissue, sealing blood vessels, etc. Pneumoperitoneum device 11206 delivers gas into the patient's body cavity 11132 via pneumoperitoneum tube 11111 to inflate the cavity, ensuring the field of vision of endoscope 11100 and ensuring the surgeon's working space. Recorder 11207 is a device capable of recording various types of information related to the surgery. Printer 11208 is a device capable of printing various types of information related to the surgery in various formats (e.g., text, images, or graphics).

[0088] It should be noted that the light source device 11203, which provides illumination to the endoscope 11100 when the surgical area is to be imaged, may include a white light source such as an LED, a laser light source, or a combination thereof. When the white light source includes a combination of red, green, and blue (RGB) laser light sources, the white balance adjustment of the image being captured can be performed by the light source device 11203 because the output intensity and timing of each color (each wavelength) can be controlled with high precision. Furthermore, in this case, if the laser beams from each RGB laser light source are irradiated onto the observation target in a time-division manner, and the driving of the imaging element of the camera 11102 is controlled synchronously with the irradiation timing, images corresponding to each of the R, G, and B colors can also be captured in a time-division manner. According to this method, color images can be obtained even without setting a color filter for the imaging element.

[0089] Furthermore, the light source device 11203 can be controlled to change the intensity of the light to be output at predetermined intervals. By controlling the driving of the camera device 11102 in sync with the timing of the change in light intensity, images can be acquired in a time-division manner and these images can be synthesized, enabling the creation of high dynamic range images without underexposed shadows and overexposed highlights.

[0090] Furthermore, the light source device 11203 can be configured to provide light of a predetermined wavelength band suitable for special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in human tissue, irradiating light with a narrower wavelength band compared to the irradiation light used in ordinary observation (i.e., white light), narrow-band imaging with high contrast of predetermined tissues such as blood vessels in the mucosal surface can be performed. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, fluorescence from body tissue can be observed by irradiating body tissue with excitation light (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) and irradiating human tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for special light observation as described above.

[0091] Figure 18 It shows Figure 17 A block diagram illustrating an example of the functional configuration of the camera 11102 and CCU 11201. Camera 11102 includes a lens unit 11401, an image capture unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are connected to each other via a transmission cable 11400 for communication.

[0092] Lens unit 11401 is an optical system disposed at the connection position with lens barrel 11101. Observation light captured from the distal end of lens barrel 11101 is guided to camera 11102 and introduced into lens unit 11401. Lens unit 11401 includes a combination of multiple lenses, including zoom lenses and focusing lenses.

[0093] The camera unit 11402 includes camera elements. The number of camera elements included in the camera unit 11402 can be one (single-plate type) or multiple (multi-plate type). For example, when the camera unit 11402 is configured as a multi-plate type, image signals corresponding to R, G, and B are generated by the camera elements, and these image signals can be synthesized to obtain a color image. Alternatively, the camera unit 11402 may include a pair of camera elements for acquiring right-eye and left-eye image signals compatible with three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately understand the depth of living tissue in the surgical area. It should be noted that when the camera unit 11402 is configured as a multi-plate type camera unit, multiple systems of lens units 11401 are provided corresponding to each camera element.

[0094] Furthermore, the camera unit 11402 does not necessarily have to be mounted on the camera 11102. For example, the camera unit 11402 can be mounted inside the lens barrel 11101, immediately behind the objective lens. The drive unit 11403 includes an actuator and, under the control of the camera control unit 11405, moves the zoom lens and focusing lens of the lens unit 11401 along the optical axis by a predetermined distance. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0095] The communication unit 11404 includes communication devices for sending various types of information to the CCU 11201 and receiving various types of information from the CCU 11201. The communication unit 11404 transmits image signals acquired from the camera unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0096] Additionally, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera 11102 and provides these control signals to the camera control unit 11405. The control information includes, for example, information related to shooting conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during shooting, and / or information specifying the magnification and focus of the captured image.

[0097] It should be noted that imaging conditions such as frame rate, exposure value, magnification, or focus can be specified by the user or automatically set by the control unit 11413 of CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 has automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions.

[0098] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 via the communication unit 11404. The communication unit 11411 includes communication devices for sending various types of information to and receiving various types of information from the camera 11102. The communication unit 11411 receives image signals sent to it from the camera 11102 via the transmission cable 11400.

[0099] In addition, the communication unit 11411 sends control signals to the camera 11102 to control the driving of the camera 11102. The image signal and the control signal can be transmitted via electrical communication or optical communication, etc. The image processing unit 11412 performs various image processing operations on the image signal in RAW data form sent to it from the camera 11102.

[0100] The control unit 11413 performs various types of control related to imaging the surgical area, etc., by the endoscope 11100 and displaying the captured images obtained by imaging the surgical area, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera 11102.

[0101] Furthermore, the control unit 11413 controls the display device 11202 to display captured images of the surgical area, etc., based on image signals that have already been processed by the image processing unit 11412. Therefore, the control unit 11413 can use various image recognition techniques to identify various objects in the captured images. For example, the control unit 11413 can identify surgical tools such as forceps, specific living areas, bleeding, fog when the energy device 11112 is used, etc., by detecting the shape, color, etc., of the edges of objects contained in the captured images. When the control unit 11413 controls the display device 11202 to display the captured images, the control unit 11413 can use the recognition results to display various types of surgical support information in an overlapping manner with the image of the surgical area. When surgical support information is displayed in an overlapping manner and presented to the surgeon 11131, the workload of the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery with confidence.

[0102] The transmission cable 11400 connecting the camera 11102 and the CCU 11201 is an electrical signal cable capable of electrical signal communication, an optical fiber capable of optical communication, or a composite cable capable of both electrical and optical communication. Here, although communication is performed via wired communication using transmission cable 11400 in the example shown, communication between camera 11102 and CCU 11201 can also be performed via wireless communication.

[0103] Examples of endoscopic surgical systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied, for example, to the endoscope 11100, the imaging unit 11402 of the camera 11102, and the image processing unit 11412 of the CCU 11201 in the above-described configuration. Specifically, Figure 1 The semiconductor device 1 in the image sensor 10402 can be applied to the camera unit. Note that an endoscopic surgical system has been described here as an example, but the techniques according to this disclosure can be applied to, for example, microsurgical systems.

[0104] <Examples of applications of moving objects> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body such as a car, electric car, hybrid electric car, motorcycle, bicycle, personal mobile device, airplane, drone, ship or robot.

[0105] Figure 19 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure can be applied. The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 19 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as functional components of the comprehensive control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0106] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for devices such as an internal combustion engine or drive motor for generating vehicle driving force, a drive force transmission mechanism for transmitting driving force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating vehicle braking force.

[0107] The body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, or fog lights. In this case, radio waves or signals of various types of switches sent from a keyless entry device can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locks, power windows, lights, etc.

[0108] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, the exterior information detection unit 12030 is connected to the camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform detection processing of objects such as people, vehicles, obstacles, signs, or characters on the road surface, or can perform distance detection processing of the objects.

[0109] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or invisible light such as infrared light.

[0110] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0111] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the exterior or interior of the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing advanced driver assistance system (ADAS) functions, including collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, or lane departure warning.

[0112] Furthermore, by controlling the drive force generating device, steering mechanism, or braking device based on information about the exterior or interior of the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, the microcomputer 12051 can perform cooperative control aimed at achieving autonomous driving, etc., so that the vehicle can drive autonomously without relying on the driver's operation.

[0113] Furthermore, based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, the microcomputer 12051 can, for instance, perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beam to low beam, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0114] The audio-visual output unit 12052 sends an output signal of at least one of audio and visual information to an output device capable of visually or audibly notifying passengers of the vehicle or external to the vehicle. Figure 16 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0115] Figure 20 This is a diagram showing an example of the mounting position of the camera unit 12031. exist Figure 20In the vehicle 12100, camera units 12101, 12102, 12103, 12104 and 12105 are used as camera unit 12031.

[0116] Cameras 12101, 12102, 12103, 12104, and 12105 are installed on the vehicle 12100 at locations such as the front nose, rearview mirrors, rear bumper, rear door, and the upper part of the windshield inside the passenger compartment. Camera 12101, installed on the front nose, and camera 12105, installed on the upper part of the windshield inside the passenger compartment, primarily acquire images of the front of the vehicle 12100. Cameras 12102 and 12103, installed on the rearview mirrors, primarily acquire images of the sides of the vehicle 12100. Camera 12104, installed on the rear bumper or rear door, primarily acquires images of the rear of the vehicle 12100. The images of the front acquired by cameras 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, and lanes ahead.

[0117] Notice, Figure 20 Examples of the camera ranges of camera units 12101 to 12104 are shown. Camera range 12111 represents the camera range of camera unit 12101 located at the front nose. Camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 located at the rearview mirrors, respectively. Camera range 12114 represents the camera range of camera unit 12104 located at the rear bumper or rear door. For example, by overlaying image data captured by camera units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above is obtained.

[0118] At least one of the camera units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple camera elements, or may be a camera element having pixels for phase difference detection.

[0119] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12051 can determine the distances of various three-dimensional objects within the camera ranges 12111 to 12114 and the time-varying distances (relative speeds to vehicle 12100), thereby extracting the nearest three-dimensional object as the vehicle ahead, particularly the nearest three-dimensional object existing on the driving path of vehicle 12100 and traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as vehicle 12100. Furthermore, microcomputer 12051 can preset the vehicle-to-the-front distance to be maintained and execute automatic braking control (including stop-and-go control) or automatic acceleration control (including start-and-go control), etc. Therefore, it is possible to perform cooperative control such as autonomous driving, which aims to enable the vehicle to drive autonomously without relying on driver operation.

[0120] For example, based on distance information obtained from cameras 12101 to 12104, microcomputer 12501 can classify three-dimensional object data into three-dimensional object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines a collision risk to indicate the degree of risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is therefore a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collisions.

[0121] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the captured images of the camera units 12101 to 12104. For example, this pedestrian identification is performed by the following steps: extracting feature points from the captured images of the camera units 12101 to 12104, which are infrared cameras; and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound image output unit 12052 can also control the display unit 12062 to display an icon or similar symbol representing a pedestrian at a desired location.

[0122] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied to, for example, the camera unit 12031 in the above-described configuration. Specifically, the technology according to this disclosure can be applied to... Figure 1 Semiconductor device 1 in the middle.

[0123] Note that this disclosure may also have the following construction. (1) A semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; A plurality of element isolation portions extend in the thickness direction of the semiconductor substrate, and each element isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; and A field-effect transistor, which, in a plan view, is disposed between the upper surface of a first element isolation portion and the upper surface of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film disposed between the gate electrode and the fin; and A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. In the protrusion, impurities of the opposite conductivity type to those in the fin are distributed at a higher concentration than impurities contained in the interior of the semiconductor substrate outside the protrusion. (2) According to the semiconductor device of (1), the height of the protrusion is lower than that of the fin. (3) According to the semiconductor device of (1), the protrusion is formed between the bottom of the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion. (4) According to the semiconductor device described in (1), wherein, The gate electrode includes: A first embedded portion is formed on the side of the first element isolation portion among the plurality of embedded portions; The second embedded portion is formed on the side of the second element isolation portion; and The third embedment is formed between the first embedment and the second embedment. It has multiple fins, and Among the plurality of fins, a first fin is formed between the first embedded portion and the third embedded portion, and a second fin is formed between the second embedded portion and the third embedded portion. (5) According to the semiconductor device of (1), the first element isolation portion and the second element isolation portion each include a recessed portion formed in the thickness direction from the upper surface portion and in which the gate electrode is embedded. (6) According to the semiconductor device of (5), the bottom of the recess is lower than the top of the protrusion. (7) According to the semiconductor device of (5), the bottom of the recess is higher than the top of the protrusion. (8) The semiconductor device according to (1) further includes a protrusion insulating film disposed between the protrusion and the gate electrode, wherein, The insulating film on the protrusion is thicker than the gate insulating film covering the fin. (9) According to the semiconductor device of (8), the protrusion insulating film is at least 1 nm thicker than the gate insulating film covering the fin over the entire outer periphery of the protrusion. (10) According to the semiconductor device of (8), the protrusion insulating film has a first thickness at the top of the protrusion and a second thickness smaller than the first thickness at the portion outside the top of the protrusion, and gradually increases in thickness from the second thickness to the first thickness. (11) A semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; A plurality of element isolation portions extend in the thickness direction of the semiconductor substrate, and each element isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; and A field-effect transistor, which, in a plan view, is disposed between the upper surface of a first element isolation portion and the upper surface of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film is disposed between the gate electrode and the fin; A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. A protrusion insulating film is disposed between the protrusion and the gate electrode, and The insulating film on the protrusion is thicker than the gate insulating film covering the fin. (12) According to the semiconductor device of (11), the protrusion insulating film is at least 1 nm thicker than the gate insulating film covering the fin over the entire outer periphery of the protrusion. (13) According to the semiconductor device of (11), the protrusion insulating film has a first thickness at the top of the protrusion and a second thickness smaller than the first thickness at the portion outside the top of the protrusion, and gradually increases in thickness from the second thickness to the first thickness. (14) An electronic device comprising a semiconductor device, the semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; A plurality of element isolation portions extend in the thickness direction of the semiconductor substrate, and each element isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; and A field-effect transistor, which, in a plan view, is disposed between the upper surface of a first element isolation portion and the upper surface of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film disposed between the gate electrode and the fin; and A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. In the protrusion, impurities of the opposite conductivity type to those in the fin are distributed at a higher concentration than impurities contained in the interior of the semiconductor substrate outside the protrusion. (15) An electronic device comprising a semiconductor device, the semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; A plurality of element isolation portions extend in the thickness direction of the semiconductor substrate, and each element isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; and A field-effect transistor, which, in a plan view, is disposed between the upper surface of a first element isolation portion and the upper surface of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film is disposed between the gate electrode and the fin; A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. A protrusion insulating film is disposed between the protrusion and the gate electrode, and The insulating film on the protrusion is thicker than the gate insulating film covering the fin. (16) A method for manufacturing a semiconductor device, the method comprising the following steps: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction is prepared; A plurality of element isolation portions are formed extending in the thickness direction of the semiconductor substrate, each element isolation portion having an upper surface portion and a sidewall portion disposed on the first surface portion side; A recess is formed on the first surface portion of the semiconductor substrate in the thickness direction between the first element isolation portion and the second element isolation portion of the plurality of element isolation portions, and a fin of a field-effect transistor protruding from the recess and a protrusion with a width smaller than the width of the fin are formed. Impurities of the opposite conductivity type to those of the fins are distributed in the protrusions at a higher concentration than those contained within the interior of the semiconductor substrate outside the protrusions; and The gate electrode of the field-effect transistor is formed between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion, and the gate electrode covers the fin portion through a gate insulating film. (17) A method for manufacturing a semiconductor device, the method comprising the following steps: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction is prepared; A plurality of element isolation portions are formed extending in the thickness direction of the semiconductor substrate, each element isolation portion having an upper surface portion and a sidewall portion disposed on the first surface portion side; A recess is formed in the thickness direction from the first surface portion of the semiconductor substrate between the first and second element isolation portions of the plurality of element isolation portions, and a fin of a field-effect transistor protruding from the recess and a protrusion with a width smaller than the width of the fin are formed; and The gate electrode of the field-effect transistor is formed between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion. The gate electrode covers the fin portion through a gate insulating film, and the gate electrode covers the protrusion portion through a protrusion insulating film that is thicker than the gate insulating film. List of reference numerals

[0124] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 11-1, 11-2, 21-2, 31-2 Semiconductor Devices 1-1, 1-2 Optical Detection Device 2 Semiconductor substrate 2-1 pixels 2a Front 2b Back 3. 3A (Metal-Oxide-Semiconductor) Transistor 3-1 pixel area 4-1 Vertical Drive Circuit 5. Component isolation section 5-1 Signal Processing Circuit 6-1 Horizontal Drive Circuit 7-1 Output Circuit 8-1 Control Circuit 9-1 Vertical signal line 10 Fins 11 First fin 12 Second fin 10-1 Horizontal Signal Line 10-2 First substrate 12-2 sensor pixels 13-2 pixel area 20 Gate insulating film 20-2 Second substrate 22-2 Readout Circuit 23-2 pixel drive line 24-2 Vertical Signal Line 30, 30A gate electrode 30-2 Third substrate 32-2 Logic Circuits 33-2 Vertical Drive Circuit 34-2 Signal Processing Circuits 35-2 Horizontal Drive Circuit 36-2 System Control Circuit 41 Source Region 42 Drain region 51 First Component Isolation Section 51a, 52a upper surface 51b, 52b sidewall portion 51c, 52c, 51d, 52d, 641, 642 Excavation sections 52 Second Component Isolation Section 61 Second conductivity type region 621, 622 convex part 63 High-concentration second conductivity type region 71, 91, 92 Raised part insulating film 81 Anti-reflective film 821, 822 trenches 1010 Electronic Devices 1020 Optical System 1030 Optical Detection Device 1050 display device 1060 operating system 1070 bus 1080 memory 1090 storage device 1100 power supply system 10402 Camera Department 11000 Endoscopic Surgical System 11100 Endoscope 11101 Lens tube 11102 Camera 11110 Surgical Instruments 11111 Pneumoperitoneum tube 11112 Energy Device 11120 Support Arm Device 11131 Surgeon (Doctor) Patient 11132 Bed 11133 11200 strollers 11201 Camera Control Unit (CCU) 11202 Display Device 11203 Light Source Device 11204 Input Device 11205 Treatment Tool Control Device 11206 Pneumoperitoneum device 11207 recorder 11208 printer 11400 transmission cable 11401 Lens Unit Camera Department 11402, 12031 11403 Drive Unit 11404, 11411 Ministry of Communications 11405 Camera Control Department 11412 Image Processing Department 11413 Control Department 12000 Vehicle Control System 12001 Communication Network 12010 Drive System Control Unit 12020 Body System Control Unit 12030 External Information Detection Unit 12040 In-vehicle Information Detection Unit 12041 Driver Status Monitoring Department 12050 Integrated Control Unit 12051 Microcomputer 12052 Audio and Image Output Unit 12061 Audio Speaker 12062 Display Unit 12063 Dashboard Vehicle 12100 Camera Department (12101, 12102, 12103, 12104, 12105) Camera range of 12111, 12112, 12113, 12114

Claims

1. A semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; A plurality of element isolation portions extend in the thickness direction of the semiconductor substrate, and each element isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; as well as A field-effect transistor, which is disposed in a plan view between the upper surface portion of a first element isolation portion and the upper surface portion of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film disposed between the gate electrode and the fin; and A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. In the protrusion, impurities of the opposite conductivity type to those in the fin are distributed at a higher concentration than impurities contained in the interior of the semiconductor substrate outside the protrusion.

2. The semiconductor device according to claim 1, wherein, The protrusion is lower than the height of the fin.

3. The semiconductor device according to claim 1, wherein, The protrusion is formed between the bottom of one or more embedded portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion.

4. The semiconductor device according to claim 1, wherein, The gate electrode includes: A first embedded portion is formed on the side of the first element isolation portion among the plurality of embedded portions; The second embedded portion is formed on the side of the second element isolation portion; and The third embedment is formed between the first embedment and the second embedment. It has multiple fins, and Among the plurality of fins, a first fin is formed between the first embedded portion and the third embedded portion, and a second fin is formed between the second embedded portion and the third embedded portion.

5. The semiconductor device according to claim 1, wherein, The first element isolation portion and the second element isolation portion each include a recessed portion formed in the thickness direction from the upper surface portion and in which the gate electrode is embedded.

6. The semiconductor device according to claim 5, wherein, The bottom of the excavated portion is lower than the top of the protrusion.

7. The semiconductor device according to claim 5, wherein, The bottom of the excavated portion is higher than the top of the protrusion.

8. The semiconductor device of claim 1, further comprising a protrusion insulating film disposed between the protrusion and the gate electrode, wherein, The insulating film on the protrusion is thicker than the gate insulating film covering the fin.

9. The semiconductor device according to claim 8, wherein, The protrusion insulating film is at least 1 nm thicker than the gate insulating film covering the fin over the entire outer periphery of the protrusion.

10. The semiconductor device according to claim 8, wherein, The convex insulating film has a first thickness at the top of the convex portion, and a second thickness smaller than the first thickness at the portion outside the top of the convex portion, and gradually increases in thickness from the second thickness to the first thickness.

11. A semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; Multiple component isolation portions extend in the thickness direction of the semiconductor substrate, and each component isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; and A field-effect transistor, which, in a plan view, is disposed between the upper surface of a first element isolation portion and the upper surface of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film is disposed between the gate electrode and the fin; A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. A protrusion insulating film is disposed between the protrusion and the gate electrode, and The insulating film on the protrusion is thicker than the gate insulating film covering the fin.

12. The semiconductor device according to claim 11, wherein, The protrusion insulating film is at least 1 nm thicker than the gate insulating film covering the fin over the entire outer periphery of the protrusion.

13. The semiconductor device according to claim 11, wherein, The convex insulating film has a first thickness at the top of the convex portion, and a second thickness smaller than the first thickness at the portion outside the top of the convex portion, and gradually increases in thickness from the second thickness to the first thickness.

14. An electronic device comprising a semiconductor device, the semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; A plurality of element isolation portions extend in the thickness direction of the semiconductor substrate, and each element isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; as well as A field-effect transistor, which is disposed in a plan view between the upper surface portion of a first element isolation portion and the upper surface portion of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film disposed between the gate electrode and the fin; and A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. In the protrusion, impurities of the opposite conductivity type to those in the fin are distributed at a higher concentration than impurities contained in the interior of the semiconductor substrate outside the protrusion.

15. An electronic device comprising a semiconductor device, the semiconductor device comprising: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction; Multiple component isolation portions extend in the thickness direction of the semiconductor substrate, and each component isolation portion has an upper surface portion and a sidewall portion disposed on the first surface portion side; and A field-effect transistor, which, in a plan view, is disposed between the upper surface of a first element isolation portion and the upper surface of a second element isolation portion among the plurality of element isolation portions, wherein... The field-effect transistor includes: A gate electrode having a planar portion and one or more embedded portions, the planar portion being planarly formed on a first surface portion of the semiconductor substrate, and the one or more embedded portions being embedded from the planar portion toward the interior of the semiconductor substrate; The fin is covered by the planar portion of the gate electrode and the one or more embedded portions to form a channel; A gate insulating film is disposed between the gate electrode and the fin; A protrusion is formed between the one or more buried portions of the gate electrode and the sidewall portion of at least one of the first element isolation portion and the second element isolation portion, and the width of the protrusion is smaller than the width of the fin. A protrusion insulating film is disposed between the protrusion and the gate electrode, and The insulating film on the protrusion is thicker than the gate insulating film covering the fin.

16. A method for manufacturing a semiconductor device, the method comprising the following steps: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction is prepared. A plurality of element isolation portions are formed extending in the thickness direction of the semiconductor substrate, each element isolation portion having an upper surface portion and a sidewall portion disposed on the first surface portion side; A recess is formed on the first surface portion of the semiconductor substrate in the thickness direction between the first element isolation portion and the second element isolation portion of the plurality of element isolation portions, and a fin of a field-effect transistor protruding from the recess and a protrusion with a width smaller than the width of the fin are formed. Impurities of the opposite conductivity type to those of the fins are distributed in the protrusion at a higher concentration than those contained in the interior of the semiconductor substrate outside the protrusion. and The gate electrode of the field-effect transistor is formed between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion, and the gate electrode covers the fin portion through a gate insulating film.

17. A method for manufacturing a semiconductor device, the method comprising the following steps: A semiconductor substrate having a first surface portion and a second surface portion located on opposite sides of each other in the thickness direction is prepared. A plurality of element isolation portions are formed extending in the thickness direction of the semiconductor substrate, each element isolation portion having an upper surface portion and a sidewall portion disposed on the first surface portion side; A recess is formed on the first surface portion of the semiconductor substrate in the thickness direction between the first element isolation portion and the second element isolation portion of the plurality of element isolation portions, and a fin of a field-effect transistor protruding from the recess and a protrusion with a width smaller than the width of the fin are formed. as well as The gate electrode of the field-effect transistor is formed between the sidewall portion of the first element isolation portion and the sidewall portion of the second element isolation portion. The gate electrode covers the fin portion through a gate insulating film, and the gate electrode covers the protrusion portion through a protrusion insulating film that is thicker than the gate insulating film.

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