Photovoltaic panel anti-theft control circuit

Abstract

The invention relates to the technical field of anti-theft of photovoltaic panels, in particular to an anti-theft control circuit of a photovoltaic panel. A second pin and a sixth pin of a trigger U5 in a plurality of triggers are connected with a third pin of a trigger U6, a third pin of the trigger U5 is connected with a fourteenth pin of a counter U10, and a fifth pin of the trigger U5 is connected with one end of a resistor R8 and a sixteenth pin of a gating chip U2; a second pin of the trigger U6 is connected with a sixth pin of the trigger U6, and a fifth pin of the trigger U6 is connected with one end of the resistor R10 and a first pin of the gating chip U2; the fourth pin to the seventh pin of the gating chip U2 are correspondingly connected with the Vref1 end to the Vref4 end respectively, and the eighth pin of the gating chip U2 is connected with one end of the resistor R3; the other end of the resistor R3 is connected with one end of a resistor R5 and the Port1 end; and a left side output pin of the counter U10 is connected with a right side pin of the P1. According to the invention, real-time monitoring and accurate prevention of theft behaviors can be realized, the wiring cost can be reduced, the work is stable, and electromagnetic interference, signal shielding or malicious relay attack are not easily caused.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic panel theft prevention, and more particularly, to a photovoltaic panel theft prevention control circuit. BACKGROUND

[0002] Photovoltaic power stations are usually widely distributed and located in remote areas. Their scattered layout and open-air installation characteristics make them easy targets for theft, especially high-value components such as photovoltaic panels, cables, and combiner boxes. Traditional theft prevention methods mainly rely on passive protection measures such as video surveillance, infrared sensing, or physical fences. However, these methods have problems such as response lag, susceptibility to environmental interference (e.g., adverse weather affecting camera visibility), and high false alarm rates, making it difficult to achieve real-time monitoring and precise prevention of theft. In terms of electrical monitoring, the current mainstream solution is to use a parallel sensor network to monitor changes in current, voltage, or impedance of each branch to identify abnormalities. However, this approach has problems. Due to the signal independence of the parallel structure, thieves can use external pseudo-loads or bypass devices to fake normal electrical parameters, causing the system to falsely identify no abnormalities. In addition, some monitoring solutions based on wireless transmission (such as ZigBee or LoRa) can reduce wiring costs but are susceptible to electromagnetic interference, signal shielding, or malicious relay attacks. SUMMARY

[0003] The present application aims to at least partially solve one of the problems in the related art. To this end, the present application aims to provide a photovoltaic panel theft prevention control circuit that can solve the problem of difficulty in achieving real-time monitoring and precise prevention of theft, susceptibility to electromagnetic interference, signal shielding, or malicious relay attacks.

[0004] To achieve the above object and other related objects, the present application provides a photovoltaic panel anti-theft control circuit, comprising a master control unit and a sub-control unit, the master control unit comprising a plurality of flip-flops, a plurality of connectors, a plurality of resistors, a gating chip and a counter, the second pin and the sixth pin of a flip-flop in the plurality of flip-flops being connected to the third pin of a flip-flop U6, the third pin of the flip-flop U5 being connected to the fourteenth pin of the counter U10, the fifth pin of the flip-flop U5 being connected to one end of the resistor R8 and the sixteenth pin of the gating chip U2; the second pin of the flip-flop U6 being connected to the sixth pin of the flip-flop U6, the fifth pin of the flip-flop U6 being connected to one end of the resistor R10 and the first pin of the gating chip U2; the fourth pin to the seventh pin of the gating chip U2 being connected to Vref1 end to Vref4 end respectively, the eighth pin of the gating chip U2 being connected to one end of the resistor R3; the other end of the resistor R3 being connected to one end of the resistor R5 and Port1 end; the left output pin of the counter U10 and the right pin of P1 being connected, the fifteenth pin of the counter U10 being connected to one end of the resistor R13 and the second pin of the connector P2; the nineteenth pin of the connector P1 being connected to the first pin of the connector P2; the first pin and the fourth pin of the flip-flop U5, the first pin and the fourth pin of the flip-flop U6, the second pin and the fourteenth pin of the gating chip U2, the sixteenth pin of the counter U10 being connected to a power supply; the third pin and the fifteenth pin of the gating chip U2, the eighth pin and the thirteenth pin of the counter U10, the other end of the resistor R5, the other end of the resistor R8, the other end of the resistor R10, the other end of the resistor R13 being connected to ground.

[0005] In an embodiment of the present application, the sub-control unit comprises multiple operational amplifiers, multiple inverters, multiple transistors, multiple resistors, a flip-flop, a diode, and a capacitor. An operational amplifier U13 in the multiple operational amplifiers is connected to the same-phase end of an operational amplifier U14, a Port 1, an end of a resistor R15, a collector of a transistor Q1, and another end of the resistor R15. The operational amplifier U14 is connected to an end of a capacitor C1, an end of a resistor R19, an end of a resistor R20, an end of a resistor R21, and an input of an inverter U16. The transistor Q1 is connected to an end of a resistor R17, an end of a resistor R18, an anode of a diode D1, and an end of a resistor R16. The transistor Q2 is connected to a second pin and a sixth pin of a flip-flop U15, and another end of the resistor R19. The transistor Q3 is connected to a J1 and a Port 2, and another end of the resistor R20. The flip-flop U15 is connected to a Port 3, an output of the inverter U16, another end of the resistor R18, a Port 5, and an input of an inverter U17. The inverter U17 is connected to a J2. The diode D1 is connected to a Port 4. The transistor Q3 and a fourth pin of the flip-flop U15 are connected to a power supply. The transistor Q2, another end of the capacitor C1, another end of the resistor R16, another end of the resistor R17, and another end of the resistor R21 are connected to ground.

[0006] In one embodiment of the present invention, the main control unit further includes multiple operational amplifiers, multiple resistors, triggers, AND gates, inverters, and switches. Among the multiple operational amplifiers, the non-inverting input of operational amplifier U1 is connected to Port1, the inverting input of operational amplifier U1 is connected to one end of resistor R1, and the output of operational amplifier U1 is connected to the other end of resistor R1, one end of resistor R4, and one end of resistor R9. The non-inverting input of operational amplifier U4 is connected to one end of resistor R2 and the other end of resistor R4, the inverting input of operational amplifier U4 is connected to one end of resistor R6 and one end of resistor R7, and the output of operational amplifier U4 is connected to the non-inverting input of operational amplifier U11 and the other end of resistor R7. The non-inverting input of operational amplifier U7 is connected to the other end of resistor R9 and one end of resistor R11, the inverting input of operational amplifier U7 is connected to one end of resistor R12 and one end of resistor R14, and the output of operational amplifier U7 is connected to the inverting input of operational amplifier U8. The other end of resistor R12 is connected to the non-inverting input of operational amplifier U8, the inverting input of operational amplifier U11, and the Port4 input. The output of operational amplifier U8 is connected to the first input of AND gate U9. The second input of AND gate U9 is connected to the output of operational amplifier U11, and the output of AND gate U9 is connected to the third pin of flip-flop U5. The second pin of flip-flop U3 is connected to the sixth pin, the third pin of flip-flop U3 is connected to one end of switch S1, and the fifth pin of flip-flop U3 is connected to the Port2 input. The input of inverter U12 is connected to the second pin of connector P2, and the output of inverter U12 is connected to the Port3 input. The other ends of resistor R6 and resistor R11 are connected to Vref5. The other end of switch S1, the first pin of flip-flop U3, and the fourth pin are connected to the power supply. The other ends of resistor R2 and resistor R14 are grounded.

[0007] In one embodiment of the present invention, the main control unit further includes multiple counters, multiple inverters, and resistors. The eleventh and fifteenth pins of counter U20 are connected to the fifteenth pin of counter U21 and one end of resistor R22. The thirteenth pin of counter U20 is connected to the output of inverter U18 and the input of inverter U19. The fourteenth pin of counter U20 is connected to the fourteenth pin of counter U21. The eleventh pin of counter U21 is connected to the input of inverter U18. The thirteenth pin of counter U21 is connected to the output of inverter U19. The sixteenth pins of counter U20 and counter U21 are connected to the power supply. The eighth pin of counter U20, the eighth pin of counter U21, and the other end of resistor R22 are grounded.

[0008] In one embodiment of the present invention, the main control unit further includes a connector P3, wherein the first pin of the connector P3 is connected to the third pin of the trigger U5, and the second pin of the connector P3 is connected to the Port5 terminal.

[0009] In one embodiment of the present invention, a processor is also included, which is connected to the left side pin of counter U10 or the left side pin of counter P1, and the processor provides feedback indication signal when a break occurs in the continuous signal.

[0010] In one embodiment of the present invention, an indicator circuit is also included, the indicator circuit including an LED group, and the indicator circuit is connected to the left side of the counter U10 or the left side pin of the connector P1.

[0011] In one embodiment of the present invention, the capacitor C1 is an adjustable capacitor used to adjust the dwell time of the Port2 signal.

[0012] As described above, the photovoltaic panel anti-theft control circuit of the present invention has the following beneficial effects: The present invention provides a photovoltaic panel anti-theft control circuit that can achieve real-time monitoring and precise prevention of theft, reduce wiring costs, operate stably, and is not easily affected by electromagnetic interference, signal shielding, or malicious relay attacks.

[0013] The present invention discloses a photovoltaic panel anti-theft control circuit that can monitor the continuity of the electrical signal of the photovoltaic panel in real time through a serial verification anti-theft monitoring method. Once physical damage or signal discontinuity is detected, the circuit will locate the breakpoint.

[0014] The photovoltaic panel anti-theft control circuit of the present invention also supports anti-fraud, and changes the verification voltage once for each verification signal received during the verification process to prevent the signal from being forged to deceive the monitoring. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the main control unit circuit of a photovoltaic panel anti-theft control circuit according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a sub-control unit circuit of a photovoltaic panel anti-theft control circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the monitoring bit circuit in the main control unit of a photovoltaic panel anti-theft control circuit according to an embodiment of the present invention. Detailed Implementation

[0016] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0017] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0018] Terms such as "first" or "second" may be used to describe various components, but these components are not limited by the terms described above. The terms described above are used to distinguish one component from another; for example, without departing from the scope of the concept according to this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0019] Furthermore, "connected / linked" indicates that one component is directly electrically connected to another component or indirectly electrically connected through another component. Unless otherwise explicitly stated in the sentence, the singular form may include the plural form. Additionally, the terms "comprising / including" or "containing / including" as used in this specification indicate the presence or addition of one or more components, steps, operations, and elements. Specific structural or functional descriptions of examples of embodiments of the concepts disclosed in this specification are merely illustrative to describe examples of embodiments of the concepts, and examples of embodiments of the concepts can be implemented in various forms, but these descriptions are not limited to the examples of embodiments described in this specification.

[0020] Based on the concept, various modifications and changes can be applied to examples of embodiments, such that examples of embodiments will be illustrated in the accompanying drawings and described in the specification. However, examples of embodiments based on the concept are not limited to specific embodiments, but include all changes, equivalents, or substitutions included within the spirit and scope of this disclosure.

[0021] It should be understood that when describing an element as "connected" or "linked" to another element, the element may be directly connected or linked to the other element, or it may be connected or linked to the other element via a third element. Conversely, it should be understood that when an element is described as "directly connected to" or "directly linked to" another element, no other element is placed between them. Other expressions describing relationships between components (i.e., "between" and "directly between" or "adjacent to" and "directly adjacent to") need to be interpreted in the same way.

[0022] The terminology used in this specification is for the purpose of describing specific examples of implementations only and is not intended to limit this disclosure. The singular form may include the plural form unless there is an explicit contrary meaning in the context. It should be understood in this specification that the terms "comprising" or "having" indicate the presence of the features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0023] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. If a term is not clearly defined in a common dictionary in this specification, it shall be interpreted as having the same meaning as in the context of the relevant art, and not as an ideal or overly formal meaning.

[0024] Descriptions of known components and processing techniques may be omitted to avoid unnecessarily obscuring the embodiments of this disclosure.

[0025] Throughout this specification, the same reference numerals refer to the same elements. Therefore, even if a reference numeral is not mentioned or described with reference to one drawing, it may be mentioned or described with reference to another drawing. Furthermore, even if a reference numeral is not shown in one drawing, it may be mentioned or described with reference to another drawing.

[0026] Additionally, the logic level of a signal may be different from or opposite to the logic level described. For example, a signal described as having a logic "high" level may optionally have a logic "low" level, and a signal described as having a logic "low" level may optionally have a logic "high" level.

[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] Please see Figure 1 , Figure 1 This is a schematic diagram of the main control unit circuit of a photovoltaic panel anti-theft control circuit according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a sub-control unit circuit of a photovoltaic panel anti-theft control circuit according to an embodiment of the present invention; Figure 3This is a schematic diagram of the monitoring bit circuit in the main control unit of a photovoltaic panel anti-theft control circuit according to an embodiment of the present invention. The present invention provides a photovoltaic panel anti-theft control circuit, including: a main control unit and a sub-control unit. The main control unit includes multiple triggers, multiple connectors, multiple resistors, a gating chip, and a counter. The second and sixth pins of trigger U5 are connected to the third pin of trigger U6, the third pin of trigger U5 is connected to the fourteenth pin of counter U10, and the fifth pin of trigger U5 is connected to one end of resistor R8 and the sixteenth pin of gating chip U2. The second pin of trigger U6 is connected to the sixth pin of trigger U6, and the fifth pin of trigger U6 is connected to one end of resistor R10 and the first pin of gating chip U2. The fourth to seventh pins of gating chip U2 are respectively connected to terminals Vref1 to Vref4. The eight pins are connected to one end of resistor R3; the other end of resistor R3 is connected to one end of resistor R5 and Port1; the left output pin of counter U10 is connected to the right pin of P1; the fifteenth pin of counter U10 is connected to one end of resistor R13 and the second pin of connector P2; the nineteenth pin of connector P1 is connected to the first pin of connector P2; the first and fourth pins of trigger U5, the first and fourth pins of trigger U6, the second and fourteenth pins of gating chip U2, and the sixteenth pin of counter U10 are connected to the power supply; the third and fifteenth pins of gating chip U2, the eighth and thirteenth pins of counter U10, the other end of resistor R5, the other end of resistor R8, the other end of resistor R10, and the other end of resistor R13 are grounded.

[0029] Specifically, the sub-control unit includes multiple operational amplifiers, multiple inverters, multiple transistors, multiple resistors, triggers, diodes, and capacitors. Among the multiple operational amplifiers, the non-inverting input of operational amplifier U13 is connected to the non-inverting input and Port1 of operational amplifier U14; the inverting input of operational amplifier U13 is connected to one end of resistor R15; and the output of operational amplifier U13 is connected to the collector of transistor Q1 and the other end of resistor R15. The inverting input of operational amplifier U14 is connected to one end of capacitor C1, one end of resistor R19, one end of resistor R20, and one end of resistor R21; and the output of operational amplifier U14 is connected to the input of inverter U16. The base of transistor Q1 is connected to one end of resistor R17 and one end of resistor R18; the emitter of transistor Q1 is connected to the anode of diode D1 and one end of resistor R16; and the base of transistor Q2 is connected to trigger U14. Pins 15, 2 and 6, connect the collector of transistor Q2 to the other end of resistor R19; the base of transistor Q3 is connected to port 2 via J1, and the emitter of transistor Q3 is connected to the other end of resistor R20; the first pin of trigger U15 is connected to port 3, the third pin of trigger U15 is connected to the output of inverter U16, the other end of resistor R18, and port 5, and the fifth pin of trigger U15 is connected to the input of inverter U17; the output of inverter U17 is connected to J2; the cathode of diode D1 is connected to port 4; the collector of transistor Q3 and the fourth pin of trigger U15 are connected to the power supply; the emitter of transistor Q2, the other end of capacitor C1, the other end of resistor R16, the other end of resistor R17, and the other end of resistor R21 are grounded.

[0030] Specifically, the main control unit also includes multiple operational amplifiers, multiple resistors, triggers, AND gates, inverters, and switches. Among the multiple operational amplifiers, the non-inverting input of operational amplifier U1 is connected to Port1, the inverting input of operational amplifier U1 is connected to one end of resistor R1, and the output of operational amplifier U1 is connected to the other end of resistor R1, one end of resistor R4, and one end of resistor R9. The non-inverting input of operational amplifier U4 is connected to one end of resistor R2 and the other end of resistor R4, the inverting input of operational amplifier U4 is connected to one end of resistor R6 and one end of resistor R7, and the output of operational amplifier U4 is connected to the non-inverting input of operational amplifier U11 and the other end of resistor R7. The non-inverting input of operational amplifier U7 is connected to the other end of resistor R9 and one end of resistor R11, the inverting input of operational amplifier U7 is connected to one end of resistor R12 and one end of resistor R14, and the output of operational amplifier U7 is connected to the inverting input of operational amplifier U8 and resistor R11. The other end of R12; the non-inverting input of operational amplifier U8 is connected to the inverting input and Port4 of operational amplifier U11, and the output is connected to the first input of AND gate U9; the second input of AND gate U9 is connected to the output of operational amplifier U11, and the output of AND gate U9 is connected to the third pin of flip-flop U5; the second pin of flip-flop U3 is connected to the sixth pin, the third pin of flip-flop U3 is connected to one end of switch S1, and the fifth pin of flip-flop U3 is connected to Port2; the input of inverter U12 is connected to the second pin of connector P2, and the output of inverter U12 is connected to Port3; the other ends of resistor R6 and resistor R11 are connected to Vref5; the other end of switch S1, the first pin and the fourth pin of flip-flop U3 are connected to the power supply; the other ends of resistor R2 and resistor R14 are grounded.

[0031] Specifically, the main control unit also includes multiple counters, multiple inverters, and resistors. Among the multiple counters, the eleventh and fifteenth pins of counter U20 are connected to the fifteenth pin of counter U21 and one end of resistor R22; the thirteenth pin of counter U20 is connected to the output of inverter U18 and the input of inverter U19; the fourteenth pin of counter U20 is connected to the fourteenth pin of counter U21; the eleventh pin of counter U21 is connected to the input of inverter U18; the thirteenth pin of counter U21 is connected to the output of inverter U19; the sixteenth pins of counter U20 and counter U21 are connected to the power supply; and the other end of the eighth pin of counter U20, the eighth pin of counter U21, and resistor R22 is grounded.

[0032] Specifically, the main control unit also includes connector P3, the first pin of connector P3 is connected to the third pin of trigger U5, and the second pin of connector P3 is connected to Port5.

[0033] Specifically, a photovoltaic panel anti-theft control circuit also includes a processor, which is connected to the left side pin of counter U10 or the left side pin of counter P1. The processor provides feedback indication signal when a break occurs in the continuous signal.

[0034] Specifically, a photovoltaic panel anti-theft control circuit also includes an indicator circuit, which includes an LED light group and is connected to the left side of the counter U10 or the left side pin of the connector P1.

[0035] Specifically, capacitor C1 is an adjustable capacitor used to adjust the dwell time of the Port2 signal.

[0036] In one embodiment of the present invention, a tag for a photovoltaic panel anti-theft control circuit is described. Vref1 to Vref4 are different voltage verification reference signal inputs, used to provide different verification parameters to different sub-control units during monitoring. These can be provided by voltage divider or adjustable power supply. Port1 outputs any one of the reference voltages Vref1 to Vref4 to the sub-control unit and waits for feedback from Port4. Vref5 is the verification range reference voltage input of the Port4 signal. Port2 is the sub-control unit start signal, Port3 is the reset signal, Port4 is the range verification feedback signal, and Port5 is another verification signal. The first sub-control unit J1 is connected to Port2, and the J2 of the remaining sub-control units is connected to the J1 of the next sub-control unit. Upon power-up, the main control unit first generates an initial two-bit decoding signal to the strobe via flip-flops U5 and U6. Pins 1 and 16 of chip U2 select signals Vref1 to Vref4 to pin 8 and output Port1 signal to the sub-control unit. The sub-control unit first delays the signal and then generates Port4 corresponding to port1 signal to return to the main control unit. The main control unit performs continuous signal verification against spoofing through operational amplifier U11 and subsequent circuitry, or connects Port5 and U10 of the sub-control unit through P3 to perform continuous signal monitoring independently. When the main control unit detects signal forgery and breakpoint destruction, the output pin of counter U10 will be positioned on the corresponding pin according to the breakpoint, and then fed back to the processor or indicator circuit by connector P1. The processor or indicator circuit indicates the operator according to the dwell position of counter U10. The circuit can change the number of verification bits by changing the connection position of the left pin header of connector P1 and pin 1 of connector P2 through jumper.

[0037] In one embodiment of the present invention, the signal control process for anti-fraud and breakpoint monitoring in the main control unit of the photovoltaic panel anti-theft control circuit is as follows: First, switch S1 is closed to start the monitoring cycle. Then, pin 5 of trigger U3 outputs the Port2 signal to the sub-control unit. The sub-control unit first performs a time delay and then generates the corresponding verification signal Port4 for Port1 back to the main control unit. At the same time, the output of pin 8 of the main control unit selection chip U2 is divided by resistors R3 and R5, and one path is input to the sub-control unit via Port1. The other path is input to the non-inverting input of operational amplifier U1. Operational amplifier U1 and resistor R1 form a follower circuit. The signal isolation input first prevents the voltage of Port1 from being pulled down when the subsequent circuit operates. At this time, one output of operational amplifier U1 is connected to resistor R1 via resistor R2. 4. After the grounding loop of resistor R2, the signal is fed back to the non-inverting input of operational amplifier U4. Another path is input to the non-inverting input of operational amplifier U7 via resistor R9. The Vref5 signal is input to the inverting input of operational amplifier U4 and the non-inverting input of operational amplifier U7 via resistors R6 and R11, respectively. The output signal of operational amplifier U4 is fed back to the inverting input of operational amplifier U4 via resistor R7. The voltages at the differential non-inverting and inverting inputs are then used to generate the lower limit voltage, which is input to operational amplifier U11. The output of operational amplifier U7 is fed back to the inverting input of operational amplifier U7 via the proportional loop of resistors R12 and R14. The voltages at the output of operational amplifier U1 and Vref5 are then superimposed to generate the upper limit voltage, which is fed back to the inverting input of operational amplifier U8. When Port4 of the sub-control unit is input, the non-inverting input of operational amplifier U8 and the inverting input of operational amplifier U11 will receive the signal from Port4. The signals are compared. When the signal falls within the upper and lower limits generated by op-amps U7 and U4, op-amps U8 and U11 output high-level signals to AND gate U9. The input condition of AND gate U9 is then true, and its output sends a signal to pin 3 of flip-flop U5 and pin 14 of counter U10. The output of pin 3 of counter U10 is converted to pin 2, completing the verification and waiting for the input Port4 signal from the second sub-control unit. After all verifications are complete, when pin 11 of counter U10 outputs, the signal is fed back to pin 15 of counter U10 and inverter U12 via connectors P1 and P2. Inverter U12 outputs the Port3 signal to the sub-control unit, and counter U10 is reset. During the verification process, the AND gate... Each time U9 outputs, the signal is fed back to pin 3 of trigger U5. Pin 5 or pin 6 of trigger U5 is set to 1 or 0. When pin 6 of trigger U5 is set to 1, a high-level signal is input to pin 3 of trigger U6. Pin 5 or pin 6 of trigger U6 is then set to 1 or 0. Pin 5 of trigger U5 and trigger U6 are input to the selection chip U2 to select other Vref voltages. After each verification of a sub-control unit is completed, the Port1 voltage is switched once to prevent fake signals from deceiving the verification. The Vref5 setting method is that the required upper and lower range voltages are equal to the set range voltage minus the voltage drop of diode D1, the on-state voltage drop of transistor Q1, plus the value of the high-level voltage of inverter U16 divided by resistors R18 and R17.

[0038] In one embodiment of the present invention, the specific control and connection process of the sub-control unit of the photovoltaic panel anti-theft control circuit is as follows: the first Port2 is fed back to transistor Q3 through J1, and the remaining sub-control units are connected to the front sub-control unit J2 and the rear sub-control unit J1. When Port2 is input, transistor Q3 is turned on. The VDD1 power supply is input to capacitor C1 through the collector of transistor Q3, the emitter of transistor Q3, and resistor R20 for signal retention. Retention is to avoid interference faults in the analog circuit. During retention, capacitor C1 and resistor R20 will integrate. When the voltage of capacitor C1 is greater than that of Port1, operational amplifier U14 compares and outputs a low-potential signal to inverter U16. Inverter U16 is used to convert the output signal of operational amplifier U14 into a level signal. Resistors R18 and R17 are used to set the high-level output of inverter U16 to the fixed conduction voltage of transistor Q1 base to prevent transistor Q1 from appearing in the saturation region. Operational amplifier U13 and resistor R15 are used for isolation and tracking. Port1 output prevents a voltage drop when transistor Q1 is turned on. When transistor Q1 is turned on, the potential signal output by operational amplifier U13 is output to Port4 via the collector and emitter of transistor Q1 and diode D1. Upon initial power-up, pin 5 of trigger U15 outputs a high level to inverter U17. After inversion, inverter U17 inputs to J2. When inverter U16 outputs a high level signal, pin 5 of trigger U15 outputs a low level, and inverter U17 outputs a high level to the base of transistor Q3 in the next sub-control unit. This circuit process repeats. Simultaneously, pin 6 of trigger U15 outputs a high level signal to the base of transistor Q2. Capacitor C1 is reset via resistor R19, the collector and emitter of transistor Q2, and ground. Operational amplifier U14 outputs a high potential signal, and inverter U16 outputs a low level signal again. After waiting for the input signal from Port3, it is reset. Resistor R21 is a pull-down resistor used to pull down the potential of capacitor C1 during initial power-up.

[0039] In one embodiment of the present invention, the appendix can be referenced when increasing the maximum number of verifications. Figure 3 , and appendix Figure 1The difference is that pin 13 of counter U21 is no longer directly grounded. Instead, pin 11 is inverted twice by inverters U18 and U19 to obtain a low-level signal, while pin 13 of counter U20 obtains a high-level signal. When pin 14 outputs with Port5 or AND gate U9 (the attached diagram does not show the connection between pin 14 of counter U21 and counter U20 and AND gate U9 or Port5, or the connection between pin 15 of counter U20 and inverter U12), counter U20 will be in an interrupt state. Counter U21 will wait for verification by the sub-control unit according to the above control until pin 11 of counter U21 outputs, after which inverters U18 and U19 invert again, pin 13 of counter U21 will be at a high level for interruption, and pin 13 of counter U20 will be at a low level for start-up. When pin 11 of counter U20 outputs, all are reset.

[0040] In summary, the photovoltaic panel anti-theft control circuit of this invention can achieve real-time monitoring and precise prevention of theft, while reducing wiring costs, ensuring stable operation, and resisting electromagnetic interference, signal shielding, or malicious relay attacks. It can monitor the continuity of the photovoltaic panel's electrical signals in real time through a serial verification anti-theft monitoring method. Once physical damage or signal discontinuity is detected, the circuit will locate the breakpoint. It also supports anti-spoofing; during the verification process, the verification voltage is changed each time a verification signal is received to prevent the signal from being forged to deceive monitoring.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A photovoltaic panel anti-theft control circuit, characterized in that, include: The main control unit comprises a main control unit and sub-control units. The main control unit includes multiple triggers, multiple connectors, multiple resistors, a gating chip, and a counter. The second and sixth pins of trigger U5 are connected to the third pin of trigger U6. The third pin of trigger U5 is connected to the fourteenth pin of counter U10. The fifth pin of trigger U5 is connected to one end of resistor R8 and the sixteenth pin of gating chip U2. The second pin of trigger U6 is connected to the sixth pin of trigger U6. The fifth pin of trigger U6 is connected to one end of resistor R10 and the first pin of gating chip U2. The fourth to seventh pins of gating chip U2 are respectively connected to terminals Vref1 to Vref4. The eighth pin of gating chip U2 is connected to one end of resistor R3. The resistor R3 is connected to one end of resistor R5 and Port1. The left output pin of counter U10 is connected to the right pin of P1. The fifteenth pin of counter U10 is connected to one end of resistor R13 and the second pin of connector P2. The nineteenth pin of connector P1 is connected to the first pin of connector P2. The first and fourth pins of trigger U5, the first and fourth pins of trigger U6, the second and fourteenth pins of strobe chip U2, and the sixteenth pin of counter U10 are connected to the power supply. The third and fifteenth pins of strobe chip U2, the eighth and thirteenth pins of counter U10, the other end of resistor R5, the other end of resistor R8, the other end of resistor R10, and the other end of resistor R13 are grounded.

2. The photovoltaic panel anti-theft control circuit according to claim 1, characterized in that: The control unit includes multiple operational amplifiers, multiple inverters, multiple transistors, multiple resistors, triggers, diodes, and capacitors. Operational amplifier U13's non-inverting input is connected to the non-inverting input and Port1 of operational amplifier U14. Operational amplifier U13's inverting input is connected to one end of resistor R15, and its output is connected to the collector of transistor Q1 and the other end of resistor R15. Operational amplifier U14's inverting input is connected to one end of capacitor C1, one end of resistor R19, one end of resistor R20, and one end of resistor R21. Its output is connected to the input of inverter U16. Transistor Q1's base is connected to one end of resistor R17 and one end of resistor R18, and its emitter is connected to the anode of diode D1 and one end of resistor R16. Transistor Q2's base is connected to trigger U15. The second and sixth pins are connected to the collector of transistor Q2 and the other end of resistor R19; the base of transistor Q3 is connected to port 2 via terminal J1, and the emitter of transistor Q3 is connected to the other end of resistor R20; the first pin of trigger U15 is connected to port 3, the third pin of trigger U15 is connected to the output of inverter U16, the other end of resistor R18, and port 5, and the fifth pin of trigger U15 is connected to the input of inverter U17; the output of inverter U17 is connected to terminal J2; the cathode of diode D1 is connected to port 4; the collector of transistor Q3 and the fourth pin of trigger U15 are connected to the power supply; the emitter of transistor Q2, the other end of capacitor C1, the other end of resistor R16, the other end of resistor R17, and the other end of resistor R21 are grounded.

3. The photovoltaic panel anti-theft control circuit according to claim 2, characterized in that: The main control unit also includes multiple operational amplifiers, multiple resistors, triggers, AND gates, inverters, and switches. Among the multiple operational amplifiers, the non-inverting input of operational amplifier U1 is connected to Port1, the inverting input of operational amplifier U1 is connected to one end of resistor R1, and the output of operational amplifier U1 is connected to the other end of resistor R1, one end of resistor R4, and one end of resistor R9. The non-inverting input of operational amplifier U4 is connected to one end of resistor R2 and the other end of resistor R4, the inverting input of operational amplifier U4 is connected to one end of resistor R6 and one end of resistor R7, and the output of operational amplifier U4 is connected to the non-inverting input of operational amplifier U11 and the other end of resistor R7. The non-inverting input of operational amplifier U7 is connected to the other end of resistor R9 and one end of resistor R11, the inverting input of operational amplifier U7 is connected to one end of resistor R12 and one end of resistor R14, and the output of operational amplifier U7 is connected to the inverting input of operational amplifier U8 and resistor R1.

2. On the other end; the non-inverting input of operational amplifier U8 is connected to the inverting input and Port4 of operational amplifier U11, and the output is connected to the first input of AND gate U9; the second input of AND gate U9 is connected to the output of operational amplifier U11, and the output of AND gate U9 is connected to the third pin of flip-flop U5; the second pin of flip-flop U3 is connected to the sixth pin, the third pin of flip-flop U3 is connected to one end of switch S1, and the fifth pin of flip-flop U3 is connected to Port2; the input of inverter U12 is connected to the second pin of connector P2, and the output of inverter U12 is connected to Port3; the other end of resistor R6 and the other end of resistor R11 are connected to Vref5; the other end of switch S1, the first pin and the fourth pin of flip-flop U3 are connected to the power supply; the other end of resistor R2 and the other end of resistor R14 are grounded.

4. The photovoltaic panel anti-theft control circuit according to claim 3, characterized in that: The main control unit also includes multiple counters, multiple inverters, and resistors. Among the multiple counters, the eleventh and fifteenth pins of counter U20 are connected to the fifteenth pin of counter U21 and one end of resistor R22. The thirteenth pin of counter U20 is connected to the output of inverter U18 and the input of inverter U19. The fourteenth pin of counter U20 is connected to the fourteenth pin of counter U21. The eleventh pin of counter U21 is connected to the input of inverter U18. The thirteenth pin of counter U21 is connected to the output of inverter U19. The sixteenth pins of counter U20 and counter U21 are connected to the power supply. The eighth pin of counter U20, the eighth pin of counter U21, and the other end of resistor R22 are grounded.

5. The photovoltaic panel anti-theft control circuit according to claim 2, characterized in that: The main control unit also includes connector P3, the first pin of connector P3 is connected to the third pin of trigger U5, and the second pin of connector P3 is connected to Port5.

6. The photovoltaic panel anti-theft control circuit according to claim 2, characterized in that: It also includes a processor, which is connected to the left side pin of counter U10 or the left side pin of counter P1, and the processor provides a feedback indication signal when a break occurs in the continuous signal.

7. The photovoltaic panel anti-theft control circuit according to claim 2, characterized in that: It also includes an indicator circuit, which includes an LED group, and the indicator circuit is connected to the left side of the counter U10 or the left side pin of the connector P1.

8. The photovoltaic panel anti-theft control circuit according to claim 2, characterized in that: The capacitor C1 is an adjustable capacitor used to adjust the dwell time of the Port2 signal.

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