Read interference test method of memory, test equipment and computer program product

Abstract

The embodiment of the invention discloses a read interference test method and test equipment for a memory and a computer program product. The read interference test method for the memory comprises the following steps: acquiring an original bit error rate corresponding to each word line; constructing a word line robustness continuous function representing the mapping relation between each word line and the original bit error rate; dividing a storage area to be tested into a plurality of robustness intervals according to the word line robustness continuous function, wherein the internal robustness of each robustness interval tends to be consistent; and selecting word line samples from the plurality of robustness intervals according to a preset sampling condition, and executing a read interference test on the word line samples. According to the invention, the test accuracy and test efficiency of the read interference characteristic can be effectively improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of memory devices, and in particular to a read disturb test method of a memory, a test device and a computer program product. BACKGROUND

[0002] The data of a memory device such as a solid state drive (SSD) or an embedded memory is mainly stored in a non-volatile storage medium such as a NAND flash. With the continuous miniaturization of the memory device process and the widespread application of multi-value storage technology (such as TLC, QLC, etc.), the reliability of the storage medium is facing increasingly severe challenges. Read disturb (RD) is one of the core factors leading to data errors in the flash memory.

[0003] Therefore, in the research and production test process of the memory device, in order to comprehensively evaluate the read disturb characteristics of the memory (SSD, embedded memory device, etc.), large-scale read disturb tests need to be performed.

[0004] The read disturb test of the prior art basically adopts a uniform traversal or random sampling read operation form, without considering the differences in read disturb characteristics between different word lines, so the test accuracy and test efficiency are not high. SUMMARY

[0005] Embodiments of the present application provide a read disturb test method of a memory, a test device and a computer program product to effectively improve the test accuracy and test efficiency of the read disturb characteristics.

[0006] In a first aspect, embodiments of the present application provide a read disturb test method of a memory, the method comprising: collecting an original bit error rate corresponding to each word line; constructing a word line robustness continuous function representing a mapping relationship between the each word line and the original bit error rate; dividing a storage area to be tested into a plurality of robustness intervals according to the word line robustness continuous function, the robustness inside each robustness interval tending to be consistent; selecting word line samples from the plurality of robustness intervals according to a preset sampling condition, and performing read disturb test on the word line samples.

[0007] By implementing the embodiments of the present application, sampling test is performed based on robustness differences, thereby maximizing the exposure of potential read disturb risks under limited test resources and significantly improving the test efficiency.

[0008] In at least one possible implementation, the selecting word line samples from the plurality of robustness intervals according to a preset sampling condition, and performing read disturb test on the selected word line samples specifically comprises: According to the strength of the robustness of each robustness interval, the risk attribute is set as a fragile region, a robust region, or a third attribute; The fragile region is taken as a key test area, and other robustness intervals are taken as basic test areas, and M rounds of read disturb test cycles are performed.

[0009] The embodiment of the present application divides the robustness interval into different risk levels (fragile region / robust region / third attribute), and sets the fragile region as the key test area, so as to realize the accurate focus of the test focus by differentiating the allocation of test resources. The fragile region is taken as the key test area, and the other regions are kept as the basic monitoring. This "focus + sampling" strategy not only ensures sufficient stress test of the high-risk area and improves the test efficiency, but also takes into account the comprehensive coverage and avoids missing.

[0010] In at least one possible implementation, in the M rounds of cycle test, the number of word line samples selected from the key test area is not less than the sum of the number of samples selected from all the basic test areas.

[0011] In at least one possible implementation, after the M rounds of cycle test are performed, the method further includes: Switching the key test area to the robust region, and taking other robustness intervals as basic test areas to perform N rounds of read disturb test cycles.

[0012] The embodiment of the present application makes the read stress of the fragile region as the absolute dominant when the fragile region is taken as the key test area, so as to ensure that the fragile region can accumulate enough stress in a limited number of test rounds, thereby accelerating the exposure of potential failure.

[0013] The embodiment of the present application switches the test focus from the fragile region to the robust region, verifies whether the robust region will fail unexpectedly under long-term stress, avoids ignoring the potential degradation risk of other regions due to long-term focus on high-risk areas, and improves the comprehensiveness and reliability of the test.

[0014] In at least one possible implementation, after the N rounds of read disturb test cycles are performed, the method further includes: Switching to a uniform traversal mode for all robustness intervals of the storage area to be tested to perform P rounds of read disturb test cycles.

[0015] The embodiment of the present application introduces the uniform traversal mode to perform comprehensive scanning on all regions without preference, so as to ensure that no region is ignored for a long time, and forms a complete polling mechanism of "fragile region focus→robust region verification→uniform traversal of all regions", which takes into account the test efficiency and comprehensiveness.

[0016] In at least one possible implementation, the maximum proportion of word line samples is selected from the key test area, and a smaller proportion of word line samples are selected from the basic test area; and / or, M, Q, and P are positive integers, and M≥Q≥P; and / or, the number of samples selected from the robust region in the N-round read interference test cycle is less than the number of samples selected from the vulnerable region in the M-round read interference test cycle.

[0017] By implementing the embodiments of this application, the differences in testing pressure borne by different regions are quantified by clarifying the sample ratio relationship (maximum in key areas), the round relationship (M≥Q≥P), and the sample quantity relationship (less samples in robust areas than in vulnerable areas), thus ensuring the scientific and rational allocation of testing resources.

[0018] In at least one possible implementation, after performing the read interference test on the word line sample, the method further includes: Starting from the original bit error rate corresponding to each word line, the above steps are re-executed to obtain the updated robustness interval and word line samples. Several round-robin interference tests are then performed on the updated word line samples.

[0019] By implementing the embodiments of this application, the testing strategy is adaptively adjusted to the aging of the storage medium by periodically rescanning the RBER, updating the robustness model, and testing samples: as the number of erase / write cycles increases, the originally robust WL may degrade, and its RBER will increase, causing it to be reclassified into the vulnerable area, thus obtaining a higher testing weight. This closed-loop dynamic update mechanism ensures that the test is always consistent with the real-time state of the storage medium.

[0020] In at least one possible implementation, constructing the word line robustness continuity function characterizing the mapping relationship between each word line and the original bit error rate specifically includes: Establish a discrete dataset D={(i, r_i) | i=0,1,...,N-1} of word line index numbers and the original bit error rates, where i is the word line number, r_i is the corresponding original bit error rate, and N is the total number of word lines contained in each physical block; A smooth fit is performed on the discrete dataset D to obtain a word line robustness continuous function f(i) that represents the mapping relationship between word line index number and original bit error rate.

[0021] In at least one possible implementation, the smoothing fit employs at least one of moving average filtering, local weighted regression scatter smoothing, or piecewise cubic spline interpolation.

[0022] By implementing the embodiments of this application, the discrete RBER sampling points are smoothly fitted to a continuous function, which on the one hand eliminates the influence of single measurement noise, and on the other hand provides a high-quality mathematical foundation for subsequent gradient calculation and automatic partitioning.

[0023] In at least one possible implementation, dividing the storage region to be tested into several robust intervals according to the word line robustness continuity function specifically includes: Calculate the first derivative or gradient of the word line robustness continuity function, and identify points where the absolute value of the first derivative or gradient exceeds a preset threshold as abrupt change points; The word line interval between adjacent mutation points is used as a robustness interval.

[0024] By implementing the embodiments of this application, adaptive partitioning based on measured data is achieved by calculating the gradient of a continuous function and identifying gradient abrupt change points, avoiding subjective biases caused by manually setting thresholds; the robustness within the interval between adjacent abrupt change points tends to be consistent, providing a scientific basis for subsequent differential testing.

[0025] In at least one possible implementation, the acquisition of the raw bit error rate corresponding to each word line specifically includes: Preset test data is sequentially written to the storage area to be tested, so that all its physical pages are in a programmed state; A fine-grained scan read operation is performed on all the memory areas to be tested, and the raw bit error rate is calculated based on the number of errors on each word line.

[0026] By implementing the embodiments of this application, the entire disk is sequentially written to ensure that all physical pages are in a programmed state, thus ensuring that subsequent scans can fully reflect the true robustness of each WL; fine-grained scans (such as grouping 2 or 3 WLs or other numbers of WLs as needed) balance acquisition accuracy and efficiency.

[0027] In at least one possible implementation, the reading interference test specifically includes repeatedly performing the following steps until a preset stopping condition is met: Map the selected word line samples to the logical block address space to generate a list of non-contiguous offset addresses; Under a set temperature environment, read commands are issued in the order of the non-contiguous offset address list, and the amount of data read each time is greater than the cache capacity of the memory under test; After traversing the list of non-contiguous offset addresses once, a set delay is waited for the charge remaining from the on-state voltage applied during the read operation to accumulate.

[0028] By implementing the embodiments of this application, the physical WL sample is mapped to a list of non-contiguous offset addresses of LBA (Logical Block Address), thus decoupling the physical address from the logical address. This allows read operations to be distributed in a "jumping" manner in physical space, avoiding the resetting of the circuit by adjacent read operations. The amount of data read is greater than the cache capacity, which ensures that each read actually accesses the physical medium rather than the cache. The active resting after traversal allows the residual charge of Vpass to be maintained and gradually accumulated, accurately reproducing the cumulative effect caused by the interval of read operations in real-world scenarios.

[0029] In at least one possible implementation, the preset stop condition is reaching the set total test duration or triggering an uncorrectable error; and / or, the set temperature is an accelerated aging temperature higher than room temperature, such as 50°C, or adjusted according to actual needs; and / or, the read command is a non-continuous read command.

[0030] By implementing the embodiments of this application, the failure time is shortened and the testing efficiency is improved by accelerating the test at high temperatures (e.g., 50℃-85℃); the total test duration or uncorrectable errors are used as the stopping condition, which takes into account both test integrity and abnormal termination handling.

[0031] Secondly, embodiments of this application provide a testing device including a processor and a memory, the memory being coupled to the processor, the memory being used to store computer program code, the computer program code including computer instructions, and when the processor reads the computer instructions from the memory, causing the processor to execute the steps in the memory read interference testing method as described in the first aspect.

[0032] Thirdly, embodiments of this application provide a computer program product, characterized in that the computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the steps in the memory read interference test method described in the first aspect.

[0033] The beneficial effects of this application are: The core of this application's embodiments lies in treating RBER as a continuous attribute of WL. By collecting the RBER of each word line, a continuous mapping relationship between the WL index and RBER is established, and a continuous function model of word line robustness is constructed. This enables automatic identification of WL robustness and division of robustness intervals. Based on WL robustness difference sampling, potential read interference risks are exposed to the greatest extent under limited test resources, significantly improving test efficiency. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a state diagram of a read operation.

[0036] Figure 2 This is a flowchart illustrating the read interference testing method for a memory according to an embodiment of this application.

[0037] Figure 3 This is a flowchart illustrating the read interference testing method for a memory according to an embodiment of this application.

[0038] Figure 4 This is a schematic diagram of the word line robustness continuity function construction process according to an embodiment of this application.

[0039] Figure 5 This is a schematic diagram of the robust interval partitioning process in an embodiment of this application.

[0040] Figure 6 This is a schematic diagram of the original bit error rate acquisition process according to an embodiment of this application.

[0041] Figure 7 This is a schematic flowchart illustrating the read interference test execution process according to an embodiment of this application.

[0042] Figure 8 This is a schematic diagram of the structure of the test equipment according to an embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] It should be noted that: throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions; in the description of this application, the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; in the description of this application, "first," "second," etc., are only used to distinguish each other, and do not indicate their degree of importance or order, etc.

[0045] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, movable connections, or detachable connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components, etc. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0046] When performing a read operation on a memory cell (Page), a pass voltage (Vpass) needs to be applied to the transistors of its adjacent memory cells to turn them on. Please refer to [reference needed]. Figure 1 If it is necessary to obtain the electronic state of the target unit transistor (the intersection of word line WL1 and bit line BL1), the peripheral circuit state needs to be initialized first. A Vpass voltage is applied to word line WL0 and word line WL2 to make all devices on the link in the on state. After applying the read voltage to word line WL1, it is necessary to determine whether bit line BL1 is discharged to confirm the data state.

[0047] However, this on-state voltage may cause a small amount of electrons to be written to these transistors. When this operation intensifies or accumulates, it may lead to the modification of the original data. Read interference is this phenomenon where frequent read operations in flash memory cause data corruption in adjacent memory cells.

[0048] Due to subtle differences in manufacturing processes, the physical robustness of different word lines (WL) within the same die varies significantly. Some word lines, due to factors such as uneven oxide layer thickness and changes in doping concentration gradients caused by process fluctuations, inherently exhibit a higher raw bit error rate (RBER) and are more sensitive to read interference effects; while other word lines, with stable process conditions, have a lower RBER and exhibit stronger robustness.

[0049] Word lines with higher RBER values ​​are less robust and more prone to accumulating charge and experiencing threshold voltage drift under read interference, thus triggering Uncorrectable Error Correction Code (UECC). In contrast, word lines with lower RBER values ​​can usually be repaired by the error correction code (ECC) logic built into the NAND flash memory itself. The SSD firmware (FW) may not even be aware of the existence of such micro-errors and therefore will not trigger any exception handling process.

[0050] However, from a testing and verification perspective, what is needed are test scenarios that can actively trigger anomalies, allowing the SSD firmware to intervene and perform corresponding anomaly handling (such as data refresh, reread, voltage adjustment, etc.), thereby verifying the firmware's response correctness and data validity assurance capabilities under real-world failure scenarios. If anomalies cannot be triggered during the test, the effectiveness of the firmware's anomaly handling mechanism cannot be evaluated, nor can the product's reliability in real-world usage scenarios be verified.

[0051] Existing technologies employing uniform traversal testing or random sampling testing methods apply the same read stress to word lines with varying robustness, failing to differentiate between the physical characteristics of different word lines. This indiscriminate testing strategy results in a significant waste of testing resources on robust word lines with low RBER, which are unlikely to generate firmware-intervention-required anomalies under read interference. Conversely, vulnerable word lines with high RBER fail to receive sufficient read stress, and their potential failure risks are not fully exposed within the limited testing time. Therefore, existing testing methods suffer from low testing efficiency and high failure risk miss rates, making it difficult to meet the comprehensive verification requirements for read interference characteristics in high-reliability storage products.

[0052] Therefore, this application provides a method for testing read interference in memory, aiming to accurately locate test resources and improve testing efficiency and accuracy based on WL robustness sampling testing. Please refer to... Figure 2 The read interference test method for the memory includes: In step S100, the raw bit error rate (RBER) corresponding to each word line is collected. In step S200, a word line robustness continuous function f(i) is constructed to characterize the mapping relationship between each word line and the original bit error rate; In step S300, the storage region to be tested is divided into several robustness zones according to the word line robustness continuity function, and the robustness within each robustness zone tends to be consistent. In step S400, word line samples are selected from the plurality of robustness intervals according to preset sampling conditions, and read interference tests are performed on the word line samples.

[0053] RBER is a core metric for measuring read read robustness. A higher RBER indicates a more fragile read read robustness and greater sensitivity to read interference. This application innovatively treats RBER as a continuous attribute of the read read robustness. By collecting the RBER of each word line, a continuous mapping relationship between the read read robustness index and RBER is established, constructing a continuous function model for read read robustness. This enables automatic identification of read read robustness and division of robustness intervals. Based on robustness difference sampling, potential read interference risks are exposed to the greatest extent possible with limited testing resources, significantly improving testing efficiency.

[0054] Please refer to Figure 3 In at least one possible implementation, the step of selecting the word line to be tested from the plurality of robustness intervals according to preset sampling conditions and performing read interference testing on the selected word line specifically includes: In step S401, the risk attribute of each robustness interval is set as a vulnerable zone, a robust zone, or a third attribute based on the degree of robustness of each robustness interval. In step S402, the vulnerable area is used as the key test area and other robust areas are used as the basic test areas, and M rounds of cyclic reading interference test are performed.

[0055] By implementing the embodiments of this application, the robustness interval is divided into different risk levels (vulnerable area / robust area / third attribute), and the vulnerable area is set as the key testing area, achieving differentiated allocation of testing resources based on WL robustness: the vulnerable area is used as the key testing area, thus bearing higher intensity read pressure, while other areas maintain basic monitoring. This "focus + sampling" strategy ensures sufficient stress testing of high-risk areas, improving testing efficiency, while also taking into account comprehensive coverage and avoiding missed tests.

[0056] The robust region refers to the area with a low RBER in the word line robustness continuity function f(i), typically located in the middle of the physical block. In NAND Flash manufacturing processes, the robust region corresponds to the WL (Work Level) in the region with optimal process conditions. The robust region is located in the uniform region of chemical mechanical polishing (CMP), with high oxide layer thickness consistency and uniform doping concentration distribution. In a typical 128-word-line structure, the robust region is usually located within the WL index range of 40-90 (the specific range varies depending on the process technology).

[0057] Vulnerable regions refer to areas with high RBER in the word line robustness continuity function f(i), typically located at the ends of the physical block. In NAND Flash manufacturing processes, the WL corresponding to vulnerable regions is located in the edge effect region of chemical mechanical polishing (CMP), exhibiting poor oxide layer thickness uniformity, gradient doping concentration distribution, and large fluctuations in interlayer dielectric thickness. In a typical 128-word-line structure, vulnerable regions are usually located at WL indices 0-20 (source side) and 100-127 (drain side).

[0058] The third attribute refers to a transitional region in the WL robustness partitioning that belongs neither to a clearly defined high-risk vulnerable zone nor a clearly defined low-risk robust zone. It is an intermediate state region between the vulnerable and robust zones. The third attribute region can be one or more intervals with essentially the same robustness, or it can be further divided into multiple more refined sub-attribute intervals based on the RBER distribution characteristics of the word line robustness continuity function f(i), according to actual testing needs. Each sub-attribute interval has a further risk level and testing weight. For example, based on its RBER distribution characteristics, it can be divided into a high-risk transition zone, a medium-risk transition zone, and a low-risk transition zone, with the sample selection ratio of each sub-attribute interval being the same or decreasing sequentially.

[0059] In a typical robust partitioning result of a 128-line chart, there are usually 5-7 zones, as shown in Table 1 below: Vulnerable regions: RBER is the highest, usually located at the two ends of the WL index (such as Zone 0 and Zone 4); Robust zone: RBER is the lowest, usually located in the middle of the WL index (such as Zone 2). The third attribute: the transition zone between the vulnerable zone and the robust zone (such as Zone 1 and Zone 3).

[0060] Table 1. List of Robustness Intervals

[0061] In at least one possible implementation, in the M-round cyclic test, the number of word line samples selected from the key test area is not less than the sum of the number of samples selected from all the basic test areas.

[0062] Implementing the embodiments of this application ensures that when the vulnerable area is the focus of testing, the reading pressure it bears dominates, ensuring that the vulnerable area can accumulate sufficient stress within a limited number of test rounds, thereby accelerating the exposure of potential failure risks.

[0063] In at least one possible implementation, after the execution of the M-round cyclic test, the following is further included: In step S403, the key test area is switched to the robust area and other robust intervals as the basic test area, and the Q-round read interference test loop is executed.

[0064] As the number of write cycles increases, the characteristics of the storage medium change: the originally robust write level (WL) may gradually degrade, while the originally fragile WL may deteriorate further. Implementing the embodiments of this application, by shifting the testing focus from fragile areas to robust areas, verifies whether robust areas will unexpectedly fail under long-term stress, avoiding the neglect of potential degradation risks in other areas due to long-term focus on high-risk areas (fragile areas), and further improving the comprehensiveness and reliability of the test.

[0065] In at least one possible implementation, after the N-round read interference test cycle is executed, the method further includes: In step S404, switch to the uniform traversal mode of all robust intervals of the storage area to be tested, and execute the P-round read interference test loop.

[0066] By implementing the embodiments of this application, a uniform traversal mode is introduced to perform a comprehensive, unbiased scan of all regions, preventing regions from being neglected for a long time and accumulating failure risks. This forms a complete polling mechanism with clear priorities and comprehensiveness, consisting of "focusing on vulnerable areas → verifying robust areas → uniform traversal of the entire region," which balances testing efficiency with the prevention of potential risks.

[0067] In at least one possible implementation, the maximum proportion of character line samples is selected from the key test area, and a smaller proportion of character line samples is selected from the basic test area.

[0068] In at least one possible implementation, M, Q, and P are positive integers, and M ≥ Q ≥ P.

[0069] In at least one possible implementation, the number of samples selected from the robust region in the Q-round interference test cycle is less than the number of samples selected from the vulnerable region in the M-round interference test cycle.

[0070] By implementing the embodiments of this application, the differences in testing pressure borne by different regions are quantified by clarifying the sample ratio relationship (maximum in key areas), the round relationship (M≥Q≥P), and the sample quantity relationship (less samples in robust areas than in vulnerable areas), thereby further ensuring the clear priority of testing resource allocation and effectively guaranteeing testing efficiency.

[0071] Please refer to Figure 1 In at least one possible implementation, after performing the read interference test on the word line sample, the method further includes: In step S500, starting from the original bit error rate corresponding to each word line, the above steps are re-executed to obtain the updated robustness interval and word line samples. Several round-robin interference tests are then performed on the updated word line samples.

[0072] By implementing the embodiments of this application, the testing strategy is adaptively adjusted to the aging of the storage medium by periodically rescanning the RBER, updating the robustness model, and testing samples: as the number of erase / write cycles increases, the originally robust WL may degrade, and its RBER will increase, thus being classified into the vulnerable area and receiving a higher testing weight. This closed-loop dynamic update mechanism ensures that the test is always consistent with the real-time state of the storage medium.

[0073] Please refer to Figure 4 In at least one possible implementation, constructing the word line robustness continuity function characterizing the mapping relationship between each word line and the original bit error rate specifically includes: In step S201, a discrete dataset D={(i, r_i) | i=0,1,...,N-1} is established for word line index numbers and the original bit error rate, where i is the word line number, r_i is the corresponding RBER value, and N is the total number of word lines contained in each physical block. In step S202, the discrete dataset D is smoothly fitted to obtain the word line robustness continuous function f(i) that characterizes the mapping relationship between the word line index number and the original bit error rate.

[0074] In at least one possible implementation, the smoothing fit employs at least one of moving average filtering, local weighted regression scatter smoothing, or piecewise cubic spline interpolation.

[0075] By implementing the embodiments of this application, the discrete RBER sampling points are smoothly fitted to a continuous function, which on the one hand eliminates the influence of single measurement noise, and on the other hand provides a high-quality mathematical foundation for subsequent gradient calculation and automatic partitioning.

[0076] Please refer to Figure 5 In at least one possible implementation, dividing the storage region to be tested into several robust intervals according to the word line robustness continuity function specifically includes: In step S301, the first derivative or gradient of the word line robustness continuity function f(i) is calculated, and points where the absolute value of the first derivative or gradient exceeds a preset threshold are identified as mutation points. In step S302, the word line interval between adjacent mutation points is used as a robustness interval.

[0077] By implementing the embodiments of this application, adaptive partitioning based on measured data is achieved by calculating the gradient of the WL robustness continuous function and identifying gradient abrupt change points, thus avoiding the subjective bias of manually setting thresholds.

[0078] Please refer to Figure 6 In at least one possible implementation, the acquisition of the raw bit error rate corresponding to each word line specifically includes: In step S101, preset test data is sequentially written to the storage area to be tested, so that all its physical pages are in a programmed state. In step S102, a fine-grained scan read operation is performed on all the memory areas to be tested, and the corresponding raw bit error rate is calculated based on the number of errors for each word line.

[0079] By implementing the embodiments of this application, all physical pages are made into a programmed state by sequentially writing to the entire disk, ensuring that subsequent scans can fully reflect the true robustness of each WL; fine-grained scans (such as grouping every 2 WLs) take into account both acquisition accuracy and efficiency.

[0080] Please refer to Figure 7 In at least one possible implementation, the reading interference test specifically includes repeatedly executing the following steps until a preset stopping condition is met: In step S4001, the selected word line samples are mapped to the logical block address space to generate a list of non-contiguous offset addresses; In step S4002, under a set temperature environment, read commands are issued in the order of the non-contiguous offset address list, and the amount of data read each time is greater than the cache capacity of the memory under test. In step S4003, after traversing the non-contiguous offset address list once, a set delay is waited for the charge remaining from the conduction voltage applied during the read operation to accumulate.

[0081] In the R&D and production testing process of storage devices, the common verification method to address the aforementioned read interference problem is to perform long-term read operations on one or more specified memory areas. NAND flash memory typically provides a threshold to indicate that there is a data risk after a certain number of reads of a memory area. When the number of reads exceeds the threshold, the accuracy of surrounding data needs to be checked. Because the threshold is relatively large, continuous read operations are usually performed. The data fabrication server (FW) also needs to take measures to ensure data accuracy, such as data migration after the number of reads of a memory area reaches or approaches the NAND flash memory's specified threshold.

[0082] However, in real-world storage applications, read operations on a single memory cell are often not continuous. Furthermore, some current firmware (FW) solutions combined with NAND flash memory do not promptly clean the peripheral circuitry (eliminating voltage at locations such as the BL / WL of the memory cell) after a read operation. In such scenarios, the lingering Vpass after a read operation increases read interference. Although the read operation count may not reach the NAND flash memory's specified threshold, the data becomes unreliable. The firmware, based on its original threshold judgment logic, fails to shift or correct the data, ultimately leading to data inconsistency for the user. Existing testing methods, due to continuous read operations, initialize the circuitry before each read operation, thus failing to intercept this type of scenario and posing a risk of product failure.

[0083] By implementing the embodiments of this application, physical WL samples are mapped to a non-contiguous LBA list, thus decoupling physical addresses from logical addresses. This allows read operations to exhibit a "jumping" distribution in physical space, avoiding the risk of product failure caused by adjacent read operations resetting the circuit. Furthermore, by actively allowing the Vpass residual charge to accumulate gradually after traversal, the cumulative effect caused by read operation intervals in real-world scenarios is accurately reproduced. The combination of "non-contiguous read + active stabilization" is the core innovation in simulating the Vpass residual accumulation failure path.

[0084] In implementing the embodiments of this application, the amount of data read is greater than the cache capacity, ensuring that each read actually accesses the physical medium rather than the cache.

[0085] In at least one possible implementation, the preset stopping condition is either reaching the set total test duration or triggering an uncorrectable error.

[0086] In at least one possible implementation, the set temperature is an accelerated aging temperature above room temperature; and / or In at least one possible implementation, the read command is a non-continuous read command.

[0087] By implementing the embodiments of this application, the failure time is shortened and the testing efficiency is improved by accelerating the test at high temperatures (such as 50°C, or adjusting according to actual needs); the total test duration or uncorrectable errors are used as the stopping condition, which takes into account both test integrity and abnormal termination handling.

[0088] The following describes in detail the read interference testing method of this application embodiment with specific examples. This example aims to achieve the following objectives, including: Establish the mapping relationship between RBER and WL_index to realize the modeling of WL robustness continuous function; Automatically identify high-risk WL areas and dynamically generate a targeted test address list to improve test coverage and efficiency, maximizing the exposure of potential read interference risks within a limited time. By combining the "non-continuous read + active rest" mechanism, the actual failure path of Vpass residual accumulation is reproduced.

[0089] This example uses an SSD as the test object to explain in detail the method flow of the embodiments of this application.

[0090] Full disk initialization and baseline data writing: After initializing the SSD firmware for testing, unique and verifiable test data (such as random data generated by FIO) is written to the full capacity of the SSD in a sequential write manner to ensure that all physical pages are in a programmed state (Full Block).

[0091] Low-intensity scan reads and RBER acquisition: Perform a low-intensity scan read operation on the entire disk and collect the RBER corresponding to each WL.

[0092] For example, fine-grained scanning is performed by grouping two WLs together, counting the number of error bits for each WL within each group, and calculating the RBER value. Assuming each block contains 128 WLs, and there are 1000 blocks in total, the total number of sampling points is 128 × 1000 = 128000.

[0093] Create a discrete dataset D={(i, r_i) | i=0,1,...,N-1} with WL index number and RBER, where i is the global WL index (unified numbering across blocks), r_i is the corresponding RBER value, and N is the total number of WLs.

[0094] Construction of robust continuous functions in WL: By performing a smooth fit on the discrete dataset D, we obtain the WL robust continuous function f(i) that represents the mapping relationship between WL index numbers and RBER.

[0095] This example uses piecewise cubic spline interpolation for smooth fitting, which has the advantage of accurately passing through each sampling point and ensuring the second-order continuity and smoothness of the curve, providing a high-quality foundation for subsequent gradient calculations. Alternatively, local weighted regression or moving average filtering can be used for smooth fitting depending on the specific situation. Since the above are all commonly used smooth fitting methods in existing technologies, they will not be elaborated upon here.

[0096] Automatic partitioning based on gradient detection: Calculate the first derivative f'(i) of the continuous function f(i), i.e., the gradient. The magnitude of the gradient reflects the degree of change in RBER with WL index.

[0097] Set a gradient threshold T_grad (e.g., 0.05) and identify points where |f'(i)|>T_grad as robustness mutation points. These mutation points mark the boundary where RBER changes from slow to rapid.

[0098] The WL interval between adjacent mutation points is used as a robustness zone. As shown in Table 1 above, this example identified a total of 4 mutation points, dividing the storage area to be tested into 5 zones, numbered Zone0-Zone4. Among them, Zone0 and Zone4 have higher RBER and are marked as vulnerable zones; Zone2 has lower RBER and is marked as a robust zone; Zone1 and Zone3 are marked as transition zones with a third attribute.

[0099] High-risk WL test address list generation: Different sample selection ratios are set based on the robustness of each Zone: Vulnerable zones (Zone 0, Zone 4): 70% of the Vulnerable Zones (WL) were selected as representative samples; Transition zones (Zone 1, Zone 3): 20% of the WL were selected as representative samples; Robust Zone (Zone2): 10% of the WL are selected as representative samples.

[0100] The selected WL samples are mapped to the Logical Block Address (LBA) space, generating a list of non-contiguous offset addresses. For example, WL #5 in Zone 0 is mapped to LBA 1048576, WL #32 in Zone 2 is mapped to LBA 2097152, and WL #120 in Zone 4 is mapped to LBA 3145728, etc. These LBAs are distributed in a skip-like manner in the logical address space, creating conditions for implementing non-contiguous reads.

[0101] Execute the enhanced read interference test loop: Place the SSD in a temperature-controlled chamber at a high temperature (e.g., 50°C) and start the read interference test cycle. The test cycle can be found in [reference needed]. Figure 3 This includes the following sub-steps: High-risk areas focus on rounds (rounds 1-10) This phase focuses on the vulnerable zones (Zone0, Zone4) in List B as the primary testing areas, with other Zone samples serving as the basic testing areas. The read command issuance strategy is as follows: 85% of read commands were selected from the vulnerable region sample; 15% of the read commands were selected evenly from other Zone samples.

[0102] Each read command is issued in the order of a non-contiguous offset address list, and the amount of data read each time is greater than the NAND cache capacity, ensuring that each read actually accesses the physical medium rather than the cache.

[0103] After traversing the list of non-contiguous offset addresses, the system is left to stand still for 5 seconds, allowing the residual charge in Vpass to be maintained and gradually accumulated.

[0104] Repeat the above operation 10 times.

[0105] Validation rounds in the robust zone (rounds 11-20) Switch the primary test zone to the robust zone (Zone2), and use other zones as basic test zones. The read command distribution strategy is as follows: 60%-70% of read commands are selected from the robust region sample; 30%-20% of read commands are selected from vulnerable area samples (high-risk areas are continuously monitored); 10% of read commands are selected from the transition zone sample.

[0106] Similarly, after each round of traversal, the process is paused for 5 seconds. A total of 10 rounds are executed.

[0107] The entire region is traversed evenly in rounds (rounds 21-30). Switch to uniform traversal mode, where samples from all zones are selected with equal probability. The read command issuance strategy is as follows: Each zone is allocated 20%-30% of the read commands.

[0108] After each iteration, the process is paused for 5 seconds. A total of 10 iterations are performed.

[0109] Loop and Stopping Conditions After completing rounds 21-30, repeat the above polling sequence until the preset total test duration (e.g., 7 days) is reached or an Uncorrectable Error (UECC) is triggered. During the test, monitor the RBER change trend of each read in real time, and record the number of reads and the read position when the first UECC occurs.

[0110] Dynamic update mechanism After every 30 rounds of testing (i.e., one complete polling sequence), the low-intensity scan reads described above are re-executed to collect the latest RBER data.

[0111] Based on the latest RBER data, the WL robustness continuity function f'(i) is reconstructed, mutation points are re-identified, Zone boundaries are redefined, and a new list of non-continuous offset test addresses is generated.

[0112] Starting from round 31, testing continues using the updated list of non-contiguous offset addresses.

[0113] This dynamic update mechanism ensures that the test always keeps in line with the real-time state of the test object: as the number of erase and write cycles increases, the originally robust WL may degenerate, and its RBER increases and it is reclassified into the vulnerable area, thus gaining a higher test weight.

[0114] Result determination and log output After the test is completed, read back all the data and verify whether it is consistent with the test data initially written.

[0115] Output test logs containing the following information: List of invalid WL locations (WL indexes where UECC occurs); Trend graph of RBER over time for each failed WL; Temperature profile during the test; Dynamically updated records (Zone partitioning after each update).

[0116] The following beneficial effects were achieved through the implementation of this example: Effect 1: Significantly improved testing efficiency Traditional uniform traversal testing requires 7 days to complete one round of full-disk read interference testing. This example focuses on vulnerable areas, applying more than 3 times the read pressure to high-risk areas within the same time frame, thus exposing the failure of vulnerable areas earlier and improving testing efficiency by more than 200%.

[0117] Effect 2: Significantly enhanced ability to reproduce failures By introducing the "non-continuous read + active static" mechanism, the Vpass residual accumulation failure that could not be triggered by existing read interference tests was successfully reproduced. During the test, it was observed that some WLs could withstand 1 million read operations in continuous read mode, but in the "non-continuous read + static" mode of this method, UECC occurred after only 300,000 operations, verifying the real existence of Vpass residual accumulation.

[0118] Effect 3: Adaptive capability fully verified During the 14-day test, three dynamic updates were triggered. After the first update, some WLs (Work Levels) in Zone 2 were moved to Zone 1 (transition zone) due to increased RBER (Recovery Percentage). After the second update, these WLs were further moved to Zone 0 (vulnerable zone). This change accurately reflects the gradual aging process of the media and verifies the effectiveness of the adaptive mechanism.

[0119] Effect 4: Comprehensive Protection By employing a polling mechanism (focusing on high-risk vulnerable areas → validating low-risk robust areas → uniformly traversing the entire region), both sufficient stress testing of vulnerable areas and the potential degradation risk of robust areas were ensured. During testing, it was observed that a certain robust area WL began to show an abnormal increase in RBER starting in the 15th round (the robust area validation round), which was promptly captured and recorded.

[0120] This application's embodiments achieve precise focusing of test resources on high-risk areas through the WL robustness continuous function quantization model, ensure comprehensive testing through a dynamic polling mechanism, achieve adaptive adjustment to media aging through periodic model updates, and reproduce the real failure path of Vpass residual accumulation through "non-continuous reads + active resting". The organic combination of the above technical features forms a complete, efficient, and accurate read interference testing solution, which can quickly and accurately evaluate the read interference characteristics of NAND in large-scale storage testing or production environments, significantly improving testing efficiency, reducing the risk of missed tests, and ensuring product quality.

[0121] Please refer to Figure 8 This application also provides a testing device, including a processor 100 and a memory 200, wherein the memory 200 is coupled to the processor 100 and is used to store computer program code, the computer program code including computer instructions, wherein when the processor 100 reads the computer instructions from the memory 200, the processor 100 performs the steps of the method in any possible implementation of any of the foregoing embodiments.

[0122] This application also provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to perform the steps of the method in any of the possible implementations of the foregoing embodiments.

[0123] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0124] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for testing read interference in a memory, characterized in that, The read interference test method for the memory includes: Collect the raw bit error rate corresponding to each word line; Construct a word line robustness continuity function that characterizes the mapping relationship between each word line and the original bit error rate; The memory region to be tested is divided into several robust intervals according to the word line robustness continuity function, and the robustness within each robust interval tends to be consistent. According to preset sampling conditions, word line samples are selected from the several robustness intervals, and read interference tests are performed on the word line samples.

2. The method for testing read interference of a memory according to claim 1, characterized in that, The step of selecting word lines to be tested from the plurality of robustness intervals according to preset sampling conditions and performing read interference testing on the selected word lines specifically includes: Based on the strength of robustness in each robustness interval, its risk attribute is set as a vulnerable zone, a robust zone, or a third attribute; The vulnerable area was selected as the key test area, and other robust areas were selected as the basic test areas. M rounds of cyclic read interference test were performed.

3. The method for testing read interference of a memory according to claim 2, characterized in that, After performing the M-round cyclic test, the following is also included: Switch the key test area to the robust region and other robust intervals as the basic test areas, and execute the Q-round read interference test loop; and / or In the M-round cyclic test, the number of word line samples selected from the key test area is not less than the sum of the number of samples selected from all the basic test areas.

4. The method for testing read interference of a memory according to claim 3, characterized in that, Following the execution of the Q-round read interference test loop, the following is also included: Switch to the uniform traversal mode of all robust intervals of the storage area to be tested, and execute the P-round read interference test loop.

5. The read interference testing method for a memory as described in claim 4, characterized in that, Select the largest proportion of character line samples from the key test area, and select a smaller proportion of character line samples from the basic test area; and / or M, Q, and P are positive integers, and M ≥ Q ≥ P; and / or The number of samples selected from the robust region in the Q-round interference test cycle is less than the number of samples selected from the vulnerable region in the M-round interference test cycle.

6. The method for testing read interference of a memory according to any one of claims 1-5, characterized in that, After performing the read interference test on the word line sample, the method further includes: Starting from the original bit error rate corresponding to each word line, the above steps are re-executed to obtain the updated robustness interval and word line samples. Several round-robin interference tests are then performed on the updated word line samples.

7. The method for testing read interference of a memory as described in any one of claims 1-5, characterized in that, The construction of the word line robustness continuity function, which characterizes the mapping relationship between each word line and the original bit error rate, specifically includes: Establish a discrete dataset D={(i, r_i) | i=0,1,...,N-1} of word line index numbers and the original bit error rates, where i is the word line number, r_i is the corresponding original bit error rate, and N is the total number of word lines contained in each physical block; A smooth fit is performed on the discrete dataset D to obtain a word line robustness continuous function that characterizes the mapping relationship between word line index and the original bit error rate.

8. The read interference testing method for a memory as described in claim 7, characterized in that, The smoothing fit employs at least one of the following: moving average filtering, local weighted regression scatter smoothing, or piecewise cubic spline interpolation.

9. The method for testing read interference of a memory according to any one of claims 1-5, characterized in that, The step of dividing the storage region to be tested into several robust intervals according to the word line robustness continuity function specifically includes: Calculate the first derivative or gradient of the word line robustness continuity function, and identify points where the absolute value of the first derivative or gradient exceeds a preset threshold as abrupt change points; The word line interval between adjacent mutation points is used as a robustness interval.

10. The method for testing read interference of a memory as described in any one of claims 1-5, characterized in that, The specific steps of collecting the raw bit error rate corresponding to each word line include: Preset test data is sequentially written to the storage area to be tested, so that all its physical pages are in a programmed state; A fine-grained scan read operation is performed on all the memory areas to be tested, and the raw bit error rate is calculated based on the number of errors on each word line.

11. The method for testing read interference of a memory according to any one of claims 1-5, characterized in that, The read interference test specifically includes repeatedly executing the following steps until a preset stopping condition is met: Map the selected word line samples to the logical block address space to generate a list of non-contiguous offset addresses; Under a set temperature environment, read commands are issued in the order of the non-contiguous offset address list, and the amount of data read each time is greater than the cache capacity of the memory under test; After traversing the list of non-contiguous offset addresses once, a set delay is waited for the charge remaining from the on-state voltage applied during the read operation to accumulate.

12. The method for testing read interference of a memory according to claim 11, characterized in that: The preset stopping condition is that the set total test time is reached or an uncorrectable error is triggered; and / or The set temperature is an accelerated aging temperature higher than room temperature; and / or The read command is a non-continuous read command.

13. A testing device, characterized in that, It includes a processor and a memory coupled to the processor. The memory is used to store computer program code, the computer program code including computer instructions, which, when the processor reads from the memory, cause the processor to perform the steps in the memory testing method as described in any one of claims 1-12.

14. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the steps of the memory testing method as described in any one of claims 1-12.

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