Inductor structure with loop for temperature compensation of receiver analog

Abstract

The invention relates to an inductor structure with a loop for temperature compensation of a receiver analog front end (RX) AFE. Techniques for providing temperature compensation in a receiver analog front end (RX AFE) are described. A receiver device includes an RX AFE circuit having at least one load component and at least one load inductor structure having a closed loop. The RX AFE circuit is affected by changes in circuit parameters over a temperature range, resulting in temperature drift in the receiver device. The closed loop reduces the effective inductance of the at least one load inductor structure by generating eddy current to reduce the temperature drift. The eddy current depends on an equivalent series resistance (ESR) of the closed loop.

Description

TECHNICAL FIELD

[0001] At least one embodiment relates generally to communication systems, and more particularly, but not exclusively, to a looped inductor structure for temperature compensation in a receiver analog front-end (RX AFE). BACKGROUND

[0002] Communication systems transmit and receive signals at high data rates (e.g., up to 200 gigabits / sec (Gbits / sec)). High speed transmissions exhibit significant noise properties (e.g., due to the transmission medium), requiring the use of communication devices (e.g., transmitters and receivers) configured to perform digital pre-processing by the transmitter device and post-processing by the receiver device. Variations in circuit characteristics with temperature can result in temperature drift, which is undesirable for stable operation of the communication devices. BRIEF DESCRIPTION OF DRAWINGS

[0003] Various embodiments according to the present disclosure will be described in reference to the drawings, wherein:

[0004] Figure 1A An example communication system is shown having a load inductor structure with a closed ring 140, in accordance with at least some embodiments.

[0005] Figure 1B is a block diagram of a communication system employing a load inductor structure with a closed ring 140 in a receiver device, in accordance with at least one embodiment.

[0006] Figure 2 is a circuit diagram of an RX AFE circuit having a continuous time linear equalizer (CTLE) and a load inductor structure, in accordance with at least one embodiment.

[0007] Figure 3 An example load inductor structure is shown, in accordance with at least one embodiment.

[0008] Figure 4 is a circuit diagram of an equivalent circuit representing a load inductor structure of Figure 3 , in accordance with at least one embodiment.

[0009] Figure 5 is a plot showing a CTLE transfer function temperature drift comparison, in accordance with at least one embodiment.

[0010] Figure 6 is a circuit diagram of an RX AFE circuit having a variable gain amplifier (VGA) and a load inductor structure, in accordance with at least one embodiment.

[0011] Figure 7This is a graph showing a comparison of temperature drift of the VGA transfer function according to at least one embodiment.

[0012] Figure 8 This is a flowchart of a method for the initial design of a load inductor structure having a closed loop, according to at least one embodiment.

[0013] Figure 9 This is a flowchart of a method for iteratively designing a load inductor structure with a closed loop, according to at least one embodiment.

[0014] Figure 10 This is a flowchart of a method for manufacturing a load inductor structure having a closed loop, according to at least one embodiment.

[0015] Figure 11 An example computer system according to at least some embodiments is shown, including instructions for designing a load inductor structure with a closed loop for an RX AFE circuit.

[0016] Figure 12 It is a block diagram of a computing system having two processing devices coupled to each other and multiple networks according to at least one embodiment.

[0017] Figure 13 It is a block diagram of a computing system having a central processing unit (CPU) and a graphics processing unit (GPU) in a single integrated circuit according to at least one embodiment.

[0018] Figure 14 It is a block diagram of a computing system having a tensor core graphics processing unit (GPU) according to at least one embodiment. Detailed Implementation

[0019] One type of communication interface is the serializer / deserializer (SerDes) interface. SerDes designs need to meet temperature range requirements in certain applications, such as 0°C to 105°C for data center applications and -40°C to 125°C for automotive applications. Changes in circuit characteristics with temperature, such as transconductance, capacitance, and output impedance, can cause temperature drift in the transfer function of the receiver analog front-end (RX AFE). This temperature drift is undesirable for the stable operation of the receiver device. For example, the receiver device may be susceptible to RX AFE temperature drift. RX AFE temperature drift refers to the change in the performance characteristics of the analog front-end circuitry in the receiver due to temperature variations. Without any compensation, the temperature drift can exceed 2dB. This temperature drift is primarily caused by the sensitivity of components such as transistors, resistors, and capacitors to temperature fluctuations, which can alter their electrical characteristics. Additionally, thermal expansion of materials and self-heating of components during operation can also contribute to these performance changes. The effects of temperature drift can include signal distortion, increased noise, gain variations, and changes in filter characteristics, all of which reduce overall signal integrity. Mitigating these effects involves implementing temperature compensation techniques, robust thermal management, and regular calibration to ensure consistent performance across different temperature environments.

[0020] Conventional solutions rely on temperature-based bias current adjustment (i.e., bias current with a temperature slope) or active compensation circuitry. Active temperature compensation techniques come at the cost of area, power, linearity, or noise. For example, at lower temperatures, bias current adjustment typically introduces linearity losses. Active compensation circuitry generally increases noise and complexity, as well as circuit variability.

[0021] The aspects and embodiments of this disclosure address the aforementioned and other drawbacks by providing a load inductor structure with a closed loop, which reduces temperature drift by generating eddy currents to decrease the effective inductance of the load inductor structure. The magnitude of these eddy currents is affected by the equivalent series resistance (ESR) associated with the closed loop. In various embodiments, the receiver device may include an RX AFE circuit (also referred to as an RX AFE block or sub-block) comprising at least one load component and at least one load inductor structure with a closed loop. This RX AFE circuit may be susceptible to temperature variations, resulting in parameter variations at different temperatures, which may lead to temperature drift within the receiver device. To mitigate this problem, the closed loop is designed to generate eddy currents that effectively reduce the effective inductance of at least one load inductor structure.

[0022] The aspects and embodiments of this disclosure employ a closed loop within the inductor as a temperature compensation technique involving only passive circuitry. These aspects and embodiments can be used as an empirical flow for initial design development, and then modified for fine-tuning in later design cycles. The aspects and embodiments of this disclosure are applicable to any high-speed RX AFE that already has inductors for bandwidth extension or higher boost. The aspects and embodiments of this disclosure can limit the temperature drift per block to less than 1 dB or even 0.5 dB.

[0023] The aspects and embodiments of this disclosure achieve temperature drift suppression or compensation in RX AFE circuits through a fully passive circuit layout including an inductor with an inner loop. This structure generates eddy currents via mutual coupling, thereby affecting the effective inductance of the ring-based ESR. Utilizing the positive temperature coefficient of the wiring metal, eddy currents increase at lower temperatures and decrease at higher temperatures, adjusting the inductance accordingly to counteract the temperature drift. That is, eddy currents are higher at lower temperatures and lower at higher temperatures, meaning a lower effective inductance at lower temperatures and a higher effective inductance at higher temperatures. This is typically required for temperature drift compensation. The aspects and embodiments of this disclosure can achieve a significant temperature drift improvement of at least 1 dB.

[0024] The aspects and embodiments of this disclosure can rely entirely on passive circuit elements, which do not suffer from the same drawbacks or additional noise encountered in earlier solutions. Passive design also allows for greater flexibility throughout the design cycle. That is, adjustments can be made later in the circuit layout process to accommodate more precise temperature drift characterization.

[0025] The aspects and embodiments of this disclosure can be used in RX AFE circuits where minimizing temperature drift is required. The aspects and embodiments of this disclosure can have an inductor layout with a short-circuited portion of the internal trace, forming a closed loop as part of the inductor layout. This temperature drift is lower than with an inductor without a closed loop. The inductor layout with a closed loop causes the closed loop to be mutually coupled to the rest of the inductor, and the closed loop has a positive temperature coefficient associated with the closed loop's ESR. Due to the mutual coupling, the closed loop generates eddy currents, reducing the effective inductance. Because the closed loop's ESR has a positive temperature coefficient, the eddy currents are higher at lower temperatures and lower at higher temperatures, meaning a lower effective inductance at lower temperatures and a higher effective inductance at higher temperatures. This is typically required to compensate for temperature drift. As described herein, temperature compensation schemes are a trade-off with effective inductance. Temperature compensation can be fine-tuned by the position of the loop within the inductor and the width of the closed loop. RXAFE circuits can be used in different types of front-end circuits, such as continuous-time linear equalizers (CTLEs) or variable-gain amplifiers (VGAs).

[0026] Therefore, the advantages of receivers, systems, and methods implemented according to some embodiments of this disclosure include, but are not limited to, allowing for adjustment of compensation throughout the design cycle, providing design flexibility, and reducing additional circuit complexity and impairment overhead. Other advantages will be apparent to those skilled in the art of signal processing, and will be discussed below.

[0027] Figure 1A An example communication system 100 with a load inductor structure having a closed loop 140 is illustrated according to at least some embodiments. System 100 includes device 110, a communication network 108 including a communication channel 109, and device 112. In at least one example embodiment, device 110 and device 112 correspond to one or more of a personal computer (PC), a laptop, a tablet, a smartphone, a server, a server cluster, etc. In some embodiments, device 110 and device 112 may correspond to any suitable type of device communicating with other devices also connected to a general-type communication network 108. According to embodiments, receiver 104A, receiver 104B of device 110 or device 112 may correspond to a graphics processing unit (GPU), a switch (e.g., a high-speed network switch), a network adapter, a central processing unit (CPU), a data processing unit (DPU), an NVLink switch, etc. As another specific but non-limiting example, device 110 and device 112 may correspond to a server providing information resources, services, and / or applications to user devices, client devices, or other hosts in system 100.

[0028] Examples of communication networks 108 that can be used to connect devices 110 and 112 include Internet Protocol (IP) networks, Ethernet, InfiniBand (IB) networks, Fibre Channel networks, the Internet, cellular communication networks, wireless communication networks, combinations thereof (e.g., Ethernet Fibre Channel), variations thereof, etc. In other embodiments, communication network 108 may be a Fast Peripheral Component Interconnect (PCIe) interconnect. PCIe is a high-speed interface standard for connecting various hardware components. It can be an interconnect of devices such as graphics cards (GPUs), solid-state drives (SSDs), network interface cards (NICs), and other peripherals. PCIe provides scalable, high-speed, point-to-point connectivity between devices, including CPUs, GPUs, memory, etc. In other embodiments, communication network 108 may be a high-speed interconnect, such as an interconnect deploying NVLink technology. NVLink interconnects can be GPU-GPU interconnects used between GPUs, CPU-GPU interconnects between GPUs and CPUs, or interconnects used between other devices. NVLink provides higher bandwidth and lower latency than traditional PCIe connections, which are typically used for computing hardware. NVLink is particularly useful in scenarios requiring massively parallel processing, such as artificial intelligence (AI), machine learning, deep learning, high-performance computing (HPC), and data analytics. For example, in NVIDIA's DGX systems and high-end gaming or AI workstations, NVLink helps GPUs exchange data at the speeds required for demanding tasks such as real-time ray tracing or training neural networks. NVLink capacity allows more GPUs to communicate through it. In a specific but non-limiting example, communication network 108 is a network capable of transmitting data between devices 110 and 112 using data signals (e.g., digital signals, optical signals, wireless signals). The embodiments described herein can be used in systems with high-speed, scalable switches, such as switches using NVSwitch technology. NVSwitch is a high-speed, scalable switch developed by NVIDIA that facilitates data communication between multiple GPUs in a system, allowing them to work together more efficiently by providing high-bandwidth, low-latency interconnects. NVSwitch acts as a central hub or high-bandwidth structure, interconnecting all GPUs in a system, enabling each GPU to communicate quickly and efficiently with other GPUs. NVSwitch can also couple between other types of devices, such as CPUs, accelerators, and memory. NVSwitch can be used for tasks requiring intensive computation and collaboration between multiple GPUs, such as AI model training, scientific simulations, and large-scale data processing. The embodiments described herein can be used in high-performance computing systems, such as computing systems modeled on NVIDIA DGX systems, which are designed for artificial intelligence (AI), deep learning, and high-performance computing (HPC) workloads.The DGX system is optimized for large-scale GPU computing and parallel processing, integrating multiple GPUs, high-bandwidth interconnects, and a software framework tailored for AI and HPC tasks. In at least one embodiment, the system for high-speed network communication includes a processing unit and a network interface comprising a receiver or transceiver with a closed-loop load inductor structure, as described herein. The processing unit may include a CPU, GPU, DPU, network adapter, network switch, NVLink switch, etc.

[0029] Other examples of the communication network 108 may include other chip-to-chip or die-to-die interconnects, such as GRS, LPI (Low Power Interface), or LLI (Low Latency Interface).

[0030] Device 110 includes a transceiver 116 for transmitting and receiving signals (e.g., data signals). The data signal may be a digital signal modulated with data or an optical signal, or other suitable signal for carrying data. Transceiver 116 may include a digital data source 120, a transmitter 102, a receiver 104A, and processing circuitry 132 for controlling transceiver 116. Digital data source 120 may include suitable hardware and / or software for outputting data in a digital format (e.g., binary code and / or thermometer code). Digital data output from digital data source 120 may be retrieved from a memory (not shown) or generated based on input (e.g., user input).

[0031] Transmitter 102 includes suitable software and / or hardware for receiving digital data from digital data source 120 and outputting data signals based on the digital data for transmission to receiver 104B of device 112 via communication network 108.

[0032] Receivers 104A and 104B of devices 110 and 112 may include suitable hardware and / or software for receiving signals (e.g., data signals from communication network 108). For example, receivers 104A and 104B may include components for receiving and processing signals to extract data for storage in memory. In at least one embodiment, receiver 104B includes an RX AFE circuit with a load inductor structure having a closed loop 140B. In another embodiment, receiver 104A also includes an RX AFE circuit with a load inductor structure having a closed loop 140A. Receiver 104B receives incoming signals and samples the incoming signals to generate samples, such as using an analog-to-digital converter (ADC). The RX AFE circuit including the load inductor structure with closed loop 140B may be coupled between a terminal or node and the ADC. Reference is made below. Figure 2 Additional details of the load inductor structure with closed loop 140 are discussed in more detail.

[0033] Processing circuitry 132 may include software, hardware, or a combination thereof. For example, processing circuitry 132 may include a memory containing executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory may correspond to any suitable type of memory device or collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that may be used include flash memory, random access memory (RAM), read-only memory (ROM), variations thereof, combinations thereof, etc. In some embodiments, the memory and processor may be integrated into a general-purpose device (e.g., a microprocessor may include integrated memory). Additionally or alternatively, processing circuitry 132 may include hardware such as application-specific integrated circuits (ASICs). Other non-limiting examples of processing circuitry 132 include integrated circuit (IC) chips, CPUs, GPUs, DPUs, microprocessors, field-programmable gate arrays (FPGAs), collections of logic gates or transistors, resistors, capacitors, inductors, diodes, etc. Some or all of processing circuitry 132 may be disposed on a printed circuit board (PCB) or an assembly of PCBs. It should be understood that any suitable type of electronic component or collection of electronic components is suitable for inclusion in processing circuitry 132. The processing circuit 132 can send signals to and / or receive signals from other components of the transceiver 116 to control the overall operation of the transceiver 116.

[0034] Transceiver 116 or selected elements thereof may take the form of a pluggable card or controller for device 110. For example, transceiver 116 or selected elements thereof may be implemented on a network interface card (NIC).

[0035] Device 112 may include transceiver 136 for transmitting and receiving signals, such as data signals, via channel 109 of communication network 108. Channel 109 may be PCIe, NVLink, Ethernet, InfiniBand, Ground Reference Signal (GRS), Chip-to-Chip (C2C), Die-to-Die (D2D), etc. The same or similar structure as transceiver 116 can be applied to transceiver 136; therefore, the structure of transceiver 136 will not be described separately.

[0036] Although not explicitly shown, it should be understood that devices 110 and 112, as well as transceivers 116 and 136, may include other processing devices, storage devices, and / or communication interfaces typically associated with computing tasks such as sending and receiving data.

[0037] Figure 1BA block diagram of an example communication system 150, according to at least one embodiment, employs a load inductor structure with a closed loop 140 in receiver 104. Figure 1B In the example shown, a PAM4 modulation scheme is used for transmitting signals (e.g., digitally encoded data) from transmitter (TX) 102 to receiver (RX) 104 via communication channel 106 (e.g., a transmission medium). Communication channel 106 can be PCIe, NVLink, Ethernet, InfiniBand, GRS, C2C, D2D, etc. In this example, transmitter 102 receives 101 input data (i.e., input data at time n denoted as "a(n)"), which is modulated according to a modulation scheme (e.g., PAM4) and transmits a signal a(n) comprising a set of data symbols (e.g., symbols -3, -1, 1, 3, where the symbols represent encoded binary data). It should be noted that while the use of the PAM4 modulation scheme has been described by way of example herein, other data modulation schemes, including, for example, non-return-to-zero (NRZ) modulation schemes, PAM3, PAM7, PAM8, PAM16, etc., can be used according to embodiments of this disclosure. For example, in NRZ-based systems, transmitted data symbols consist of symbols -1 and 1, with each symbol value representing a binary bit. This is also known as PAM2 or PAM2 system because the transmitted symbol has two unique values. Typically, binary bit 0 is encoded as -1, and bit 1101 is encoded as 1 as the PAM2 value.

[0038] In the example shown, the PAM4 modulation scheme uses four (4) unique values ​​for the transmission symbols to achieve higher efficiency and performance. These four levels are represented by symbol values ​​-3, -1, 1, and 3, with each symbol representing a unique combination of corresponding binary bits (e.g., 00, 01, 10, 11).

[0039] Communication channel 106 is a destructive medium because it acts as a low-pass filter, which attenuates high frequencies more than low frequencies, introducing inter-symbol interference (ISI) and noise from crosstalk, power supply, electromagnetic interference (EMI), or other sources. Communication channel 106 can be used via serial links (e.g., cables, PCB traces, copper cables, fiber optics, etc.), read channels for data storage (e.g., hard drives, flash solid-state drives (SSDs), high-speed serial links, deep space satellite communication channels, applications, etc.).

[0040] As described above, in some communication systems, transmitter 102 transmits signal 103 as a data signal, with or without using a transmitter clock for generating the data signal. Receiver (RX) 104 receives input signal 105 via communication channel 106. Input signal 105 can be degraded and attenuated by communication channel 106 and includes noise. Receiver 104 can output received signal 107 "v(n)", including a set of data symbols (e.g., symbols -3, -1, 1, 3, where the symbols represent encoded binary data). A load inductor structure with closed loop 140 can be used to compensate for temperature drift in receiver 104. Receiver 104 may include RX AFE circuitry, such as a continuous-time linear equalizer (CTLE) or a variable-gain amplifier (VGA). The load inductor structure with closed loop 140 can be coupled in series with at least one load component of the CTLE (e.g., a load resistor or a load transistor). Similarly, the load inductor structure with closed loop 140 can be coupled in series with at least one load component of the VGA (e.g., a load resistor or a load transistor). The following reference Figure 2 (CTLE) and Figure 6 (VGA) Further details of the load inductor structure with closed loop 140 are discussed in more detail.

[0041] Figure 2 This is a circuit diagram of an RX AFE circuit having a CTLE 200 and load inductor structures 202 and 204 according to at least one embodiment. The CTLE 200 is an analog circuit used to compensate for signal degradation, particularly in high-speed communication systems. Signal degradation (such as signal attenuation and distortion) occurs as a signal travels through a medium (such as PCB traces, cables, or optical fibers), especially at higher frequencies. The CTLE 200 is designed to counteract these effects by providing frequency-dependent gain to the signal. The RX AFE circuit can use load inductor structures 202 and 204, connected in series with load components 206 and 208, to increase bandwidth.

[0042] like Figure 2 As shown, the CTLE 200 includes differential input terminals 210 (labeled "term_vp" and "term_vn") and differential output terminals 212 (labeled "ctle_vn" and "ctle_vp"). The CTLE 200 includes a first load component 206 coupled to a first output terminal 214 in the differential output terminals 212, and a second load component 208 coupled to a second output terminal 216 in the differential output terminals 212. Figure 2As shown, load components 206 and 208 are load resistors. In other embodiments, load components 206 and 208 may be load transistors. CTLE 200 includes a first load inductor structure 202 coupled in series with the first load component 206 and a second load inductor structure 204 coupled in series with the second load component 208.

[0043] As described herein, the RX AFE circuit may be affected by variations in circuit parameters over a temperature range, resulting in temperature drift within the RX AFE circuit. Load inductor structure 202 and load inductor structure 204 may each include a closed loop. The closed loop can reduce temperature drift by generating eddy currents to decrease the effective inductance of load inductor structure 201 and load inductor structure 204. The magnitude of the eddy currents depends on the equivalent series resistance (ESR) of the closed loops of load inductor structure 202 and load inductor structure 204. In at least one embodiment, load inductor structure 202 (or load inductor structure 204) includes a set of one or more turns, wherein at least one turn is short-circuited to form a closed loop. In at least one embodiment, load inductor structure 202 (or load inductor structure 204) is a conductive trace structure in a PCB or integrated circuit process. Load inductor structure 202 (or load inductor structure 204) can be implemented as a PCB inductor (also known as a planar inductor). PCB inductors are defined by their physical structure, including trace pattern, trace width, spacing, and layer usage. Similarly, inductors in ICs are also defined by their physical structure, including trace pattern, trace width, spacing, and layer usage. Changing the physical dimensions of these components alters the inductor's inductance, resistance, and parasitic characteristics. By carefully tuning these parameters, designers can customize inductors to meet specific performance requirements, balancing factors such as inductance value, Q-factor, component footprint, and frequency response. In at least one embodiment, load inductor structure 202 (or load inductor structure 204) includes several dimensions for designing itself for a specific frequency value and a specific inductance value required for a particular design. In at least one embodiment, load inductor structure 202 (or load inductor structure 204) may include dimensions based on a specified inductance value and closed-loop positions based on a specified temperature compensation value. The closed loop may include a trace width based on a specified frequency value. See below for reference. Figure 3 , Figure 4 and Figure 6 Additional details describe the load inductor structure 202 (and load inductor structure 204). Examples of the load inductor structure 202 (or load inductor structure 204) are shown and described in more detail below.

[0044] although Figure 2A differential CTLE is shown, but in another embodiment, CTLE 200 can be a single-ended CTLE. In this embodiment, CTLE 200 includes a single-ended input terminal and a single-ended output terminal. A load component (such as load component 206 (load resistor or load transistor)) is coupled to the single-ended output terminal. A load inductor structure (such as load inductor structure 202) is coupled in series with load component 206.

[0045] Figure 3 An example load inductor structure 300 according to at least one embodiment is shown. The load inductor structure 300 may be the load inductor structure of FIG1 with a closed loop 140. The load inductor structure 300 may be... Figure 2 The load inductor structure 300 can be either structure 202 or structure 204. As described above, the physical structure of the load inductor structure 300 can be implemented as a PCB inductor (also known as a planar inductor), such as... Figure 3 As shown. Alternatively, the load inductor structure 300 can be implemented as conductive traces on one or more layers of an integrated circuit (IC). The conductive traces can be designed as helical or toroidal traces on one or more layers of the IC or PCB. Helical or toroidal traces can have one or more "turns". In the case of an inductor coil implemented in an IC or PCB, a "turn" refers to a single complete loop of the conductive trace forming the coil. In some cases, turns can be defined fractionally based on changes in direction, such as when turns do not form complete loops. In ICs and PCBs, inductors are typically implemented as planar helical coils. The "turns" of an inductor coil are designed using conductive traces (typically copper or aluminum) laid out on one or more layers of the substrate. The design and arrangement of these turns affect the inductance and performance of the inductor. In a single-layer design, the inductor coil comprises conductive traces of multiple turns arranged in a flat helical pattern on a single layer. The helix can be circular or square in shape to maximize space utilization. The traces begin at the center of the helix and wrap outwards. In some cases, inductors can span multiple layers of a PCB or IC, using through-holes (vertical interconnects) to connect the layers. This allows for more compact designs and the total inductance can be increased by increasing the number of turns without consuming additional horizontal space. The number of turns in a spiral coil directly affects the inductance. More turns generally increase inductance, but resistance also increases due to the longer trace length. The spacing between adjacent turns also affects the characteristics of the inductor. If the turns are too close together, the parasitic capacitance between the turns increases, which degrades the inductor's performance, especially at higher frequencies. The trace width and the distance between turns are typically optimized for the target frequency and the desired inductance. The load inductor structure 300 may include a collection of one or more turns. One of the turns is short-circuited at a short-circuit point 306 to form a closed loop 308.

[0046] As described above, the physical dimensions of the physical structure of the load inductor structure 300, including trace pattern, trace width, spacing, and layer usage, can be altered to change the inductance, resistance, and parasitic characteristics of the load inductor structure 200. More specifically, spiral or toroidal traces (i.e., turns) are typically formed by routing copper traces in a spiral or toroidal pattern on an IC layer. The number of turns in the spiral and the spacing between turns are key factors determining the inductance. Careful control of the trace width, the spacing between turns, and the total area covered by the spiral is necessary to achieve the desired inductance value. Inductors can be implemented on a single layer of an IC or PCB or across multiple layers. Multilayer designs can increase inductance by stacking spirals on top of each other and connecting them via vias (i.e., vertical interconnects). The PCB material, typically FR4 or a high-frequency substrate like Rogers, affects the inductance due to its dielectric properties. The substrate thickness between layers also affects the coupling between turns or layers. Adding more turns increases the inductance because the magnetic field generated by each turn constructively increases the total magnetic flux. However, this also increases the inductor's series resistance, thus affecting the Q factor and introducing more losses. Reducing the number of turns decreases inductance and can reduce resistance, increasing the Q factor, but potentially leading to insufficient inductance for the intended application. Increasing the trace width reduces the inductor's DC resistance, thus increasing the Q factor and reducing power losses. However, wider traces also slightly reduce inductance because they reduce the turns density. Narrower traces slightly increase inductance but at the cost of higher resistance, which can degrade the inductor's performance at high frequencies due to increased losses. Increasing the spacing between turns reduces the mutual inductance between adjacent turns, thus reducing the overall inductance. This helps reduce coupling with nearby components or traces, but may require more area. Reducing the spacing increases inductance by enhancing coupling between adjacent turns. However, this also increases the risk of capacitive coupling between turns, which can lead to parasitic capacitance and affect high-frequency performance. The inductor area can also be modified according to the desired design. Increasing the area of ​​the helix (increasing the outer diameter) increases inductance because the magnetic field lines have a larger loop to circulate, which increases the total flux. However, this also increases the size of the inductor, which may be impractical for space-constrained designs. Reducing the area lowers the inductance and makes the component more compact, but may result in lower efficiency in the intended application. Using multilayers connected via vias can significantly increase the inductance without increasing the component package size. This is because the magnetic fields from the stacked layers are combined. However, this also increases design complexity and the possibility of parasitic capacitance and interlayer coupling. Fewer layers reduce inductance but also simplify the design and can reduce parasitic effects. Increasing the substrate thickness between layers in a multilayer can reduce interlayer coupling, thus slightly reducing the inductance. If the magnetic flux extends to a larger volume, the effective inductance can also be increased. A higher dielectric constant in the substrate increases the parasitic capacitance between turns, which may lower the inductor's self-resonant frequency.

[0047] In addition to the physical dimensions mentioned above, some physical dimensions or properties of the load inductor structure 300 can also be selected for the closed loop 308. Specifically, the placement of the closed loop 308 can be based on a specified temperature compensation value. The placement of the closed loop 308 can be modified by changing the location of the short-circuit point 306 to any of the turns 302. The closed loop 308 can have a trace width. The trace width of the closed loop 308 can be based on a specified frequency value. The load inductor structure 300 can be represented as an equivalent circuit diagram, as shown below. Figure 4 As shown and described.

[0048] Figure 4 It means according to at least one embodiment Figure 3 The circuit diagram shows the equivalent circuit 400 of the load inductor structure 300. The equivalent circuit 400 is a simplified representation of the actual electrical circuit that captures the basic behavior of the load inductor structure 300 using idealized components. The diagram uses basic electrical components such as resistors, capacitors, inductors, voltage sources, and current sources as models of the actual circuit behavior under specific conditions. An inductor structure typically includes an inductor (L), a capacitor (C), and a resistor (R). The equivalent circuit 400 representing the load inductor structure 300 short-circuits one turn, forming an inductor structure with a first inductor 402, a first resistor 406, and a capacitor 410, and a closed loop 412 (i.e., closed loop 308) with a second inductor 404 and a second resistor 408. The first inductor 402 represents... Figure 3 A set of one or more turns 302, the second inductor 404 represents Figure 3 The closed loop 308 is described below. A first inductor 402 includes a first inductance (L1), and a second inductor 404 includes a second inductance (L2). As described herein, the first inductor 402 and the second inductor 404 are coupled to each other. The first inductor 402 is coupled in series with a first resistor 406 having a first resistance (R1). The second inductor 404 is coupled in series with a second resistor 408 having a second resistance (R2). The first inductor 402 and the first resistor 406 are coupled in parallel with a capacitor 410. During operation, a first current 414 flowing through the first inductor 402 induces an induced current 416 in the closed loop 412. The following is an example script of the equivalent inductance and impedance of the equivalent circuit 400. For this example, the following example values ​​are used: L1 = 820e-12; L2 = 21.6e-12; M = 82.2e-12; C1 = 6.93 = 15; T = 125; Tbase = -40; R1 = 14.2 * (1 + 0.0045 * (T - Tbase)); R2 = 1.4 * (1 + 0.0045 * (T - Tbase));

[0049] freq = 100e6:100e6:100e9;

[0050] omega = 2.3.1415 * freq

[0051] The ratio of the induced current in the secondary coil to the current in the primary coil (inductance + resistance).

[0052] i2_over_i1=-li*omega*M. / (li*omega*L2+R2);

[0053] The induced voltage in the primary coil is due to the induced current in the secondary coil.

[0054] v1_l2induced=li*omega.*M.*i2_over_i1;

[0055] %Check% the equivalent impedance of the entire transformer except for C1

[0056] L1_ind_impedance=li*omega*L1+vl_l2induced+R1;

[0057] %L1_ind_impedance=li*omega*L1+R1;

[0058] %C1 impedance

[0059] L1_cap_impedance=1. / (*li*omega*C1);

[0060] % Calculate total impedance

[0061] L1_total_impedance=

[0062] L1_ind_impedance.*L1_cap_impedance. / (L1_ind_impedance+L1_cap_impedance);

[0063] % Calculation of apparent effective inductance

[0064] appar_ind=imag(L1_total_impedance). / omega;

[0065] Example scripts can be used to simulate equivalent circuit 400 to compare the temperature drift of the CTLE transfer function, such as... Figure 5 The curve is shown in the figure.

[0066] Figure 5This is a graph 500 showing a temperature drift comparison of the CTLE transfer function according to at least one embodiment. Graph 500 shows a first transfer function 502 for a CTLE without a load inductor structure with a closed loop at a first temperature (e.g., -40°C) and a second transfer function 504 for a CTLE with a load inductor structure with a closed loop at the first temperature. Graph 500 shows a third transfer function 506 for a CTLE without a load inductor structure with a closed loop at a second temperature (e.g., 125°C), and a fourth transfer function 508 for a CTLE with a load inductor structure with a closed loop at the second high temperature. Figure 5 As shown, using a load inductor structure with a closed loop, the temperature drift can be reduced from 1.2 dB to 0.2 dB. Alternatively, a load inductor structure with a closed loop can achieve other amounts of temperature drift reduction.

[0067] Figure 6This is a circuit diagram of an RX AFE circuit with a VGA 600 and a load inductor structure 602, according to at least one embodiment. In many AFE circuits, the strength of the incoming signal can vary significantly due to factors such as distance, interference, or environmental conditions. The VGA 600 helps manage these variations by adjusting its gain in real time, ensuring that the output signal maintains a consistent amplitude suitable for further processing. The VGA 600 is an electronic amplifier whose gain can be dynamically adjusted, meaning it can amplify the input signal by different amounts depending on the control input. The VGA 600 allows for electronic adjustment of the gain (amplification factor) of the analog signal, which is crucial for maintaining signal integrity under varying signal strengths and conditions. The VGA 600 can be part of an automatic gain control (AGC) loop. The AGC circuit dynamically adjusts the gain of the VGA to maintain a constant output level, even as the input signal changes. By optimizing the gain, the VGA 600 helps maintain a high signal-to-noise ratio (SNR). If the signal is too weak, increasing the gain can help amplify the signal above the noise floor. Conversely, if the signal is too strong, decreasing the gain can prevent distortion and saturation in subsequent stages of the AFE. The VGA 600 can be designed with linear or logarithmic gain control characteristics. A linear VGA adjusts the gain linearly, meaning a linear change in the control signal results in a linear change in the gain. A logarithmic VGA adjusts the gain on a logarithmic scale, which is very useful in applications where the signal level changes exponentially. The gain of the VGA 600 can be controlled by an analog control voltage (analog-controlled VGA) or a digital signal (digital-controlled VGA, also known as a digital variable gain amplifier or DVGA). Analog-controlled VGAs provide continuous gain adjustment, while digital VGAs provide discrete gain adjustment steps. In an AFE circuit, the VGA 600 is typically located after the initial low-noise amplifier (LNA) and any necessary filtering stages. The VGA 600 can adjust the signal level before the signal is sent to the analog-to-digital converter (ADC). By adjusting the signal level, the VGA 600 ensures that the ADC operates within its optimal input range, avoiding clipping or underutilization of the ADC's dynamic range. The RX AFE circuit can use a load inductor structure 602 connected in series with a load component 604 (e.g., a load resistor or load transistor) to increase bandwidth.

[0068] like Figure 6 As shown, the VGA 600 includes input terminals (labeled "Vctle") and output terminals (labeled "Vfvf"). The VGA 600 includes a load component 604 coupled in series with a load inductor structure 602 and an AC ground wire (labeled "AC gnd"). Figure 6 As shown, load component 604 is a load resistor. In other embodiments, load component 604 is a load transistor.

[0069] As described herein, the RX AFE circuit may be affected by variations in circuit parameters within a certain temperature range, resulting in temperature drift within the RX AFE circuit. The load inductor structure 602 may include a closed loop. The closed loop can reduce the effective inductance of the load inductor structure 602 by generating eddy currents, thereby reducing temperature drift. The magnitude of the eddy currents depends on the ESR of the closed loop of the load inductor structure 602. In at least one embodiment, the load inductor structure 602 includes a collection of one or more turns, wherein at least one turn is short-circuited to form a closed loop. In at least one embodiment, the load inductor structure 602 is a conductive trace structure in a PCB or integrated circuit process. The load inductor structure 602 may be implemented as a PCB inductor (also known as a planar inductor). Alternatively, the load inductor structure 602 may be implemented in one or more layers of an IC. In at least one embodiment, the load inductor structure 602 includes several dimensions for designing itself for specific frequency values ​​and specific inductance values ​​required for a particular design. In at least one embodiment, the load inductor structure 602 may include dimensions based on a specified inductance value and a closed-loop position based on a specified temperature compensation value. The closed loop may include a trace width based on a specified frequency value. (See above references.) Figure 3 An example of load inductor structure 602 is shown and described.

[0070] although Figure 6 A single-ended VGA is shown, but in another embodiment, VGA 600 may be a differential VGA. In this embodiment, VGA 600 includes differential input terminals and differential output terminals. A load component, such as load component 604 (load resistor or load transistor), is coupled to each differential output terminal.

[0071] Figure 7 This is a graph 700 showing a temperature drift comparison of the transfer function of a VGA according to at least one embodiment. Graph 700 shows a first transfer function 702 for a VGA without a load inductor structure with a closed loop at a first temperature (e.g., -40°C) and a second transfer function 704 for a VGA with a load inductor structure with a closed loop at the first temperature. Graph 700 shows a third transfer function 706 for a VGA without a load inductor structure with a closed loop at a second temperature (e.g., 125°C), and a fourth transfer function 708 for a VGA with a load inductor structure with a closed loop at the second high temperature. Figure 7 As shown, using a load inductor structure with a closed loop, the temperature drift can be reduced from 1.95 dB to 1.1 dB. Alternatively, a load inductor structure with a closed loop can achieve reductions in other amounts of temperature drift.

[0072] Figure 8This is a flowchart of a method 800 for the initial design of a load inductor structure with a closed loop, according to at least one embodiment. Method 800 can be executed by processing logic including hardware, software, firmware, or any combination thereof. For example, method 800 can be executed by a computing system having one or more processing devices and one or more computer-readable storage media. Method 800 can be implemented as instructions stored in one or more computer-readable storage media, which, when executed by one or more processing devices, can perform the operations of method 800. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible. In at least one embodiment, method 800 is executed manually.

[0073] In at least one embodiment, method 800 may be executed by multiple processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In at least one embodiment, the processing threads implementing method 800 may be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization logic). Alternatively, the processing threads implementing method 800 may execute asynchronously relative to each other. Various operations of method 800 may differ from... Figure 8 The methods are executed in the order shown. Some operations of these methods can be performed concurrently with other operations. In at least one embodiment, Figure 8 One or more of the operations shown may not always be performed.

[0074] refer to Figure 8 The processing logic begins by determining the placement of the closed loop based on temperature compensation (block 802). The processing logic then modifies the loop trace width of the closed loop according to the frequency required for compensation (block 804).

[0075] Figure 9This is a flowchart of a method 900 for iteratively designing an initial structure of a load inductor with a closed loop, according to at least one embodiment. Method 900 can be executed by processing logic including hardware, software, firmware, or any combination thereof. For example, method 900 can be executed by a computing system having one or more processing devices and one or more computer-readable storage media. Method 900 can be implemented as instructions stored in one or more computer-readable storage media, which, when executed by one or more processing devices, can perform the operations of method 900. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0076] In at least one embodiment, method 900 may be executed by multiple processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In at least one embodiment, the processing threads implementing method 900 may be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization logic). Alternatively, the processing threads implementing method 900 may execute asynchronously relative to each other. Various operations of method 900 may differ from... Figure 9 The methods are executed in the order shown. Some operations of these methods can be performed concurrently with other operations. In at least one embodiment, Figure 9 One or more of the operations shown may not always be performed.

[0077] refer to Figure 9 The processing logic begins by scaling the inductor structure with a closed loop to a specified inductance (block 902). The processing logic can modify the loop placement for temperature compensation (block 904). The processing logic can modify the loop trace width based on the frequency required for compensation (block 906). The processing logic can repeat the operations at blocks 902, 904, and 906 in multiple iterations to achieve the desired load inductor structure with a closed loop.

[0078] Figure 10This is a flowchart of a method 1000 for iteratively designing a load inductor structure with a closed loop according to at least one embodiment. Method 1000 can be executed by processing logic including hardware, software, firmware, or any combination thereof. For example, method 1000 can be executed by a computing system having one or more processing devices and one or more computer-readable storage media. Method 1000 can be implemented as instructions stored in one or more computer-readable storage media, which, when executed by one or more processing devices, can perform the operations of method 1000. Although shown in a specific order or sequence, the order of processes can be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0079] In at least one embodiment, method 1000 may be executed by multiple processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In at least one embodiment, the processing threads implementing method 1000 may be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization logic). Alternatively, the processing threads implementing method 1000 may execute asynchronously relative to each other. Various operations of method 1000 may differ from... Figure 10 The methods are executed in the order shown. Some operations of these methods can be performed concurrently with other operations. In at least one embodiment, Figure 10 One or more of the operations shown may not always be performed.

[0080] Reference Figure 10 The processing logic begins by determining the dimensions of the load inductor structure using a specified inductance value. At block 1004, the processing logic uses a specified temperature compensation value to determine the location of a closed loop within a plurality of turns of the load inductor structure. The load inductor structure comprises a set of one or more turns, wherein at least one turn is short-circuited at that location to form a closed loop. At block 1006, the processing logic uses a specified frequency value to determine the trace width of the load inductor structure.

[0081] Figure 11An example computer system 1100 according to at least some embodiments is illustrated, including instructions for designing a load inductor structure having a closed loop 140 for an RX AFE circuit. In at least one embodiment, the computer system 1100 may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof. In at least one embodiment, the computer system 1100 is configured with a processor 1105, which may include an execution unit for executing instructions. In at least one embodiment, the computer system 1100 may include, but is not limited to, components (such as processor 1105) for using the execution unit, including logic, to execute algorithms for processing data. In at least one embodiment, the computer system 1100 may include a processor, such as those provided by Intel Corporation (located in Santa Clara, California). Processor series, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM The microprocessor can be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors can also be used. In at least one embodiment, the computer system 1100 can execute a version of the Windows operating system provided by Microsoft Corporation (located in Redmond, Washington), although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0082] In at least one embodiment, the computer system 1100 can be used with other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors (DSPs), SoCs, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system capable of executing one or more instructions. In one embodiment, the computer system 1100 can be used with network devices such as graphics processing units (GPUs), network adapters, central processing units, and switches such as switches (e.g., high-speed direct GPU-to-GPU interconnects such as NVIDIA GH100NVLINK or NVIDIA Quantum 2 64-port InfiniBand NDR switches)).

[0083] In at least one embodiment, the computer system 1100 may include, but is not limited to, a processor 1105, which may include, but is not limited to, one or more execution units 1107, which may be configured to execute a Computing Unified Device Architecture (“CUDA”). The program is developed by NVIDIA Corporation, located in Santa Clara, California. In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 1100 is a single-processor desktop or server system. In at least one embodiment, the computer system 1100 may be a multiprocessor system. In at least one embodiment, the processor 1105 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, and a processor that implements a combination of instruction sets, or any other processor device (e.g., a digital signal processor). In at least one embodiment, the processor 1105 may be coupled to a processor bus 1110, which may transmit data signals between the processor 1105 and other components in the computer system 1100.

[0084] In at least one embodiment, processor 1105 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1128. In at least one embodiment, processor 1105 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may be located external to processor 1105. In at least one embodiment, processor 1105 may also include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0085] In at least one embodiment, execution unit 1107 (including, but not limited to, logic for performing integer and floating-point operations) is also located in processor 1105. Processor 1105 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, execution unit 1107 may include logic for disposing of packaged instruction set 1109. In at least one embodiment, by including packaged instruction set 1109 in the instruction set of general-purpose processor 1105, along with associated circuitry for executing instructions, operations used by many multimedia applications can be performed using packaged data in general-purpose processor 1105. In at least one embodiment, many multimedia applications can be accelerated and performed more efficiently by using the full width of the processor data bus to perform operations on packaged data, which eliminates the need to transfer smaller data units across the processor data bus to perform one or more operations on one data element at a time.

[0086] In at least one embodiment, the execution unit 1107 may also be used as a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1100 may include, but is not limited to, memory 1115. In at least one embodiment, memory 1115 may be implemented as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or other storage device. Memory 1115 may store one or more instructions 1130 and / or data 1116 represented by data signals, which may be executed by processor 1105.

[0087] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1115. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1113, and processor 1105 may communicate with MCH 1113 via processor bus 1110. In at least one embodiment, MCH 1113 may provide a high-bandwidth memory path 1114 to memory 1115 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1113 may direct data signals between processor 1105, memory 1115, and other components in computer system 1100, and may bridge data signals between processor bus 1110, memory 1115, and system I / O 1132. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1113 can be coupled to memory 1115 via high-bandwidth memory path 1114, and graphics card / video card 1111 can be coupled to MCH 1113 via Accelerated Graphics Port (“AGP”) interconnect 1112.

[0088] In at least one embodiment, the computer system 1100 may use system I / O 1132 as a proprietary hub interface bus to couple MCH 1113 to I / O controller hub (“ICH”) 1123. In at least one embodiment, ICH 1123 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1115, chipset, and processor 1105. Examples may include, but are not limited to, an audio controller 1122, a firmware hub (“flash BIOS”) 1134, a wireless transceiver 1120, a data storage device 1118, a conventional I / O controller 1117 including a user input interface 1119, a keyboard interface, a serial expansion port 1121 (such as USB), and a network controller 1124. The data storage device 1118 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0089] In at least one embodiment, Figure 11 A system including interconnected hardware devices or "chips" is shown, in at least one embodiment, Figure 11 An exemplary SoC may be shown. In at least one embodiment, Figure 11The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1104 are interconnected using a compute fast link (“CXL”) interconnect.

[0090] Figure 12 This is a block diagram of a computing system 1200 having two processing devices coupled to each other and multiple networks according to at least one embodiment. The computing system 1200 is designed with multiple integrated circuits (referred to as processing devices), each including a CPU and two GPUs, forming a powerful and flexible architecture. These processing devices are interconnected via NVLink (or other high-speed interconnects) to enable high-speed communication between the processing devices and are also connected via network interface cards (NICs) or data processing units (DPUs) to ensure efficient data transfer across the computing system 1200. Coupling the processing devices via NVLink enables seamless data exchange and parallel processing, thereby improving overall computing performance. Additionally, these processing devices are connected to multiple networks via one or more network interface cards (NICs) or DPUs, enabling the system to handle complex multi-network tasks with high bandwidth and low latency. This configuration makes the computing system digital data source 1200 ideal for demanding applications requiring significant processing power, such as artificial intelligence (AI), machine learning (ML), and data-intensive computing, while ensuring robust connectivity and scalability across various network environments. The integrated circuits of the computing system 1200 may include one or more CPUs and one or more GPUs. Figure 12 An example architecture for a multi-GPU architecture is shown in the figure.

[0091] like Figure 12 As shown, the computing system 1200 includes a processing device 1202 with a multi-GPU architecture. Specifically, the processing device 1202 includes a CPU 1206, a GPU 1208, and a GPU 1210. The CPU 1206 can be coupled to the GPU 1208 via a die-to-die (D2D) or chip-to-chip (C2C) interconnect 1212 (such as a ground reference signal interconnect (GRS interconnect)). The CPU 1206 can be coupled to the GPU 1210 via a D2D or C2C interconnect 1214. The CPU 1206 can also be coupled to the GPU 1208 and GPU 1210 via a PCIe interconnect. The CPU 1206 can be coupled to one or more network interface cards (NICs) or data processing units (DPUs), which are coupled to one or more networks. For example, as Figure 12As shown, CPU 1206 is coupled to a first NIC / DPU 1226, which in turn is coupled to network 1230. CPU 1206 is also coupled to a second NIC / DPU 1228, which in turn is coupled to network 1230. NIC / DPU 1226 and NIC / DPU 1228 can be coupled to network 1230 via Ethernet (ETH), NVLINK, or InfiniBand (IB) connections.

[0092] The computing system 1200 also includes a processing device 1204 with a multi-GPU architecture. Specifically, the processing device 1204 includes a CPU 1216, a GPU 1218, and a GPU 1220. The CPU 1216 can be coupled to the GPU 1218 via a D2D or C2C interconnect 1222. The CPU 1216 can be coupled to the GPU 1220 via a D2D or C2C interconnect 1224. The CPU 1216 can also be coupled to the GPU 1218 and GPU 1220 via a PCIe interconnect. The CPU 1216 can be coupled to one or more NICs or DPUs, which are coupled to one or more networks. For example, as... Figure 12 As shown, CPU 1216 is coupled to a first NIC / DPU 1232, which is coupled to network 1236. CPU 1216 is also coupled to a second NIC / DPU 1234, which is coupled to network 1236. NIC / DPU 1232 and NIC / DPU 1234 can be coupled to network 1236 via Ethernet (ETH), NVLINK, or InfiniBand (IB) connections.

[0093] In at least one embodiment, processing device 1202 and processing device 1204 can communicate with each other via NIC / DPU 1238, such as via PCIe interconnect. Processing device 1202 and processing device 1204 can also communicate with each other via high-bandwidth communication interconnect 1240 (such as NVLink interconnect or other high-speed interconnect).

[0094] The computing system 1200 includes various types of interconnects. Each interconnect includes various RX AFE circuits (also referred to as RXAFE sub-blocks). These RX AFE circuits may include load inductor structures, as described herein.

[0095] In at least one embodiment, the RX AFE circuit is part of a serializer / deserializer circuit (SerDes circuit). The SerDes circuit can be a transceiver that converts parallel data to serial data and vice versa. The SerDes circuit facilitates transmission between two devices via a serial stream, reducing the number of data paths, wires / traces, terminals, etc. The SerDes circuit may include one or more RX AFE circuits coupled between terminals of the SerDes circuit and the analog-to-digital converter (ADC). The SerDes circuit may also include other components such as a clock recovery circuit, an equalization block, and a symbol detector. In at least one embodiment, the clock recovery circuit includes a feedback loop having a phase detector, a filter, and a controlled oscillator (CO) in a closed feedback loop. The CO may be a digitally controlled oscillator (DCO), a voltage-controlled oscillator (VCO), etc., as described herein. The ADC generates samples of the incoming data signal. The equalization block can determine the current data based on the samples and provide an equalized output. The phase detector can use the equalized output to determine phase information. The phase detector can measure the phase offset corresponding to the current data. The filter can filter the phase offset and control the CO based on the filtered phase offset.

[0096] Figure 13This is a block diagram of a computing system 1300 having a CPU 1302 and a GPU 1304 on a single integrated circuit, according to at least one embodiment. The computing system 1300 can be a highly integrated design where the CPU 1302 and GPU 1304 are connected on a single integrated circuit, utilizing NVLink C2C (chip-to-chip) interconnect 1306 to achieve fast, low-latency communication between the two processing units. This tight integration allows for efficient data transfer and parallel processing between the CPU 1302 and GPU 1304, optimizing the performance of complex computing tasks. The GPU elements within the computing system 1300 can be interconnected using an NVLink network, allowing for scalability of up to 256 GPU elements, creating a robust, unified processing environment ideal for large-scale AI, ML, and high-performance computing applications. The NVLink network can be a GPU architecture with a high-bandwidth communication interconnect 1310. Additionally, the computing system 1300 can be designed to interface with high-speed I / O via a PCIe interconnect 1308, ensuring fast data transfer with external devices, further enhancing the system's ability to handle data-intensive tasks and providing robust connectivity for peripheral components. It should be noted that since the CPU 1302 and GPU 1304 reside on the same integrated circuit, the C2C interconnect 1306 can be considered a D2D interconnect. The integrated circuit may include CPU memory (also called main memory) and GPU memory, which can be accessed by the CPU 1302 and GPU 1304 via a high-speed interconnect. The computing system 1300 can combine the performance of the GPU 1304 with the versatility of the CPU 1302. The CPU 1302 can be connected to the high-bandwidth and memory-consistent C2C interconnect 1306 within a single integrated circuit. The computing system 1300 can support a link-switching system.

[0097] The computing system 1300 includes various types of interconnects. Each interconnect includes various RX AFE circuits (also referred to as RXAFE sub-blocks). These RX AFE circuits may include load inductor structures, as described herein.

[0098] Figure 14 This is a block diagram of a computing system 1400 having a Tensor Core GPU 1408 according to at least one embodiment. The computing system 1400 may be a DBX H100 system, a high-performance computing platform designed to meet the needs of AI, ML, and deep learning (DL) workloads. The computing system 1400 may include multiple Tensor Core GPUs 1408 (e.g., NVIDIA H100 Tensor Core GPUs). Each of the Tensor Core GPUs 1408 may be one of the aforementioned... Figure 13One of the integrated circuits described. The Tensor Core GPU 1408 is optimized for AI / ML / DL applications, delivering superior performance for deep learning training, inference, and high-performance computing tasks. The Tensor Core GPUs 1408 within the computing system 1400 are interconnected using high-speed communication interfaces such as NVLinks, enabling rapid data transfer between them, which is crucial for processing large-scale AI models and datasets with low latency. The computing system 1400 is designed for scalability, allowing for the integration of additional GPUs as needed, providing sufficient flexibility for research, development, and deployment in data centers to handle production AI workloads. Each GPU is equipped with a Tensor Core, a dedicated processing unit that accelerates matrix operations and is a fundamental component of AI and deep learning algorithms. These Tensor Cores enable the system to perform mixed-precision computations efficiently, balancing speed and accuracy. Considering the power consumption and heat generation of multiple Tensor Core GPUs 1408, the computing system 1400 may include advanced cooling solutions and power management features to ensure safe operation while maintaining peak performance. It is supported by a comprehensive software ecosystem, including NVIDIA's CUDA programming model, AI frameworks such as TensorFlow and PyTorch, and other HPC and AI software tools that enable developers and researchers to leverage the full capabilities of the Tensor Core GPU 1408 for their specific applications. The Computing System 1400 is ideally suited for large-scale AI model training, real-time inference, scientific simulations, data analysis, and other computationally intensive tasks requiring significant parallel processing power.

[0099] The Tensor Core GPU 1408 can be coupled to multiple CPUs (such as CPU 1402 and CPU 1404) using a switch 1406 (e.g., a CX7 HCA / NIC with a PCIe switch). The Tensor Core GPU 1408 can be coupled to each other via a switch 1410 (e.g., NVSwitches). Switches 1406 and 1410 can be coupled to a high-speed transceiver module 1412. The high-speed transceiver module 1412 can be an eight-channel small form factor pluggable (OSFP) module. OSFP modules are high-speed transceiver modules designed for fast data communication, especially in environments requiring high bandwidth, such as data centers and high-performance computing systems. These modules support extremely high data rates, typically up to 400 Gbps per module, with future capabilities expanding to 800 Gbps or higher. OSFP modules connect to the system via a PCIe interface, enabling fast and efficient data transfer between the integrated CPU-GPU components and external networks or other connected systems. Their hot-swappable nature allows for easy insertion or removal without powering down the system, providing flexibility and maintainability crucial in critical uptime environments. Additionally, OSFP modules are designed for high density, maximizing the number of high-speed connections within limited space, such as in dense server racks. By complying with the latest networking standards, OSFP modules ensure that the Compute System 1400 can still meet ever-growing data demands and can be upgraded to support future network speed increases, thus contributing to improved overall system performance and scalability.

[0100] In at least one embodiment, the computing system 1400 can be viewed as a data network configuration with full-bandwidth in-server NVLinks. In this example, all eight tensor core GPUs 1408 can simultaneously saturate eighteen NVLinks to other GPUs within the server. Bandwidth is limited by oversubscription from multiple other GPUs. In another embodiment, the data network configuration can be half-bandwidth in-server NVLinks. In this example, all eight tensor core GPUs 1408 can half-subscribe eighteen NVLinks to GPUs in other servers. Four tensor core GPUs 1408 can saturate eighteen NVLinks to GPUs in other servers. This is equivalent to full bandwidth on a global reduction (AllReduce) with a Scalable Hierarchical Aggregation and Reduction Protocol (SHARP). The reduction in all-to-all (All2All) bandwidth is a trade-off between server complexity and cost. In at least one embodiment, all eight Tensor Core GPU 1408s can independently transmit data via their own dedicated switches (e.g., 400Gb / s HCA / NICs) in a multi-track InfiniBand / Ethernet configuration using the Remote Direct Memory Access (RDMA) protocol. In this example, the aggregate full-duplex rate of the non-NVLink network devices is 800Gbps.

[0101] The computing system 1400 includes various types of interconnects. Each interconnect includes various RX AFE circuits (also referred to as RXAFE sub-blocks). These RX AFE circuits may include load inductor structures, as described herein.

[0102] Other variations are within the spirit of this disclosure. Therefore, although the disclosed technology is readily adaptable to various modifications and alternative constructions, certain embodiments thereof are illustrated in the accompanying drawings and have been described in detail above. However, it should be understood that the disclosure is not intended to be limited to one or more specific forms disclosed, but rather, it is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure as defined in the appended claims.

[0103] Unless otherwise stated or obviously contradicted by the context, the terms “a,” “an,” and “the,” and similar pronouns, used in the context of describing the disclosed embodiments (particularly in the context of the appended claims), should be interpreted as encompassing both singular and plural forms, rather than as definitions of the terms. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” should be interpreted as open-ended terms (meaning “including, but not limited to”). The term “connection” (wherein it is not modified, it refers to a physical connection) should be interpreted as partially or wholly included, attached to, or connected together, even with some intervening elements. Unless otherwise indicated herein, references to numerical ranges herein are intended only as a way of abbreviating each individual value falling within that range, and each individual value is incorporated into the specification as if it were separately described herein. In at least one embodiment, unless otherwise indicated or contradicted by the context, the use of the terms “set” (e.g., “item set”) or “subset” should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by the context, the term “subset” of the corresponding set does not necessarily mean an appropriate subset of the corresponding set, but rather that the subset and the corresponding set can be equal.

[0104] Unless otherwise explicitly stated or clearly contradicted by the context, connective phrases such as “at least one of A, B, and C” or “at least one of A, B, and C” are understood in the context to generally refer to items, terms, etc., which can be A or B or C, or any non-empty subset of the set A, B, and C. For example, in an illustrative example of a set with three members, the connective phrases “at least one of A, B, and C” and “at least one of A, B, and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such connective language is generally not intended to imply that some embodiments require the presence of each of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise stated or contradicted by the context, the term “multiple” indicates a plural state (e.g., “multiple items” indicates multiple items). In at least one embodiment, the number of items in the multiple items is at least two, but may be more if explicitly indicated or indicated by the context. Furthermore, unless otherwise stated or clearly understood from the context, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0105] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations thereof and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) executed jointly by hardware or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored on one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, which, when executed by one or more processors of a computer system (i.e., as a result of execution), cause the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media comprises a plurality of non-transitory computer-readable storage media, and one or more of the various non-transitory computer-readable storage media lack all the code, but the plurality of non-transitory computer-readable storage media collectively store the entire code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors.

[0106] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that perform the processes described herein individually or collectively, and such a computer system is configured with suitable hardware and / or software to enable the performance of the operations. Further, the computer system implementing at least one embodiment of this disclosure is a single device, and in another embodiment it is a distributed computer system comprising multiple devices operating differently, such that the distributed computer system performs the operations described herein, and that no single device performs all operations.

[0107] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of this disclosure and does not impose a limitation on the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosure.

[0108] All references cited in this article, including publications, patent applications and patents, are incorporated herein by reference to the same extent that each reference, individually and specifically, is incorporated herein by reference and fully elaborated.

[0109] The terms “coupled” and “connected”, and their derivatives, may be used in the specification and claims. It should be understood that these terms may not be intended to be synonyms with each other. Rather, in certain examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0110] Unless otherwise expressly stated, it will be understood that throughout this specification, terms such as “processing,” “calculation,” “operation,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or convert data represented as physical quantities (such as electronic quantities) in the registers and / or memory of the computing system into other data similarly represented as physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0111] Similarly, the term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" can be a network device or a MACsec device. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process can refer to multiple processes that execute instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" are used interchangeably herein, provided that a system can embody one or more methods, and a method can be considered a system.

[0112] In this document, reference may be made to acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of acquiring, receiving, or inputting analog and digital data can be accomplished in various ways, such as by receiving data as a parameter to a function call or a call to an application programming interface. In at least one embodiment, the process of acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In at least one embodiment, the process of acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In at least one embodiment, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be implemented by transmitting data as an input or output parameter to a function call, an application programming interface, or an inter-process communication mechanism.

[0113] While this document describes example implementations of the described technologies, other architectures can be used to implement the described functionality and are intended to fall within the scope of this disclosure. Furthermore, although specific assignments of responsibilities have been defined above for descriptive purposes, various functions and responsibilities may be assigned and divided in different ways depending on the circumstances.

[0114] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or actions described. Rather, specific features and actions are disclosed as exemplary forms for implementing the claims.

Claims

1. A receiver device, comprising: A receiver analog front-end RX AFE circuit includes at least one load component and at least one load inductor structure with a closed loop. The RX AFE circuit is affected by variations in circuit parameters over a temperature range, causing temperature drift in the receiver device. The closed loop is used to reduce the temperature drift by generating eddy currents to reduce the effective inductance of the at least one load inductor structure. The eddy currents depend on the equivalent series resistance ESR of the closed loop.

2. The receiver device as claimed in claim 1, wherein, The at least one load inductor structure includes a set of one or more turns, wherein at least one turn is short-circuited to form the closed loop.

3. The receiver device as claimed in claim 2, wherein, The at least one load inductor structure includes a conductive trace structure in one or more layers of an integrated circuit containing the receiver device.

4. The receiver device as claimed in claim 3, wherein: The at least one load inductor structure includes dimensions based on a specified inductance value; The position of the closed loop is based on a specified temperature compensation value; and The closed loop includes a trace width based on a specified frequency value.

5. The receiver device as claimed in claim 1, wherein, The RX AFE circuit is a continuous-time linear equalizer (CTLE), wherein at least one load inductor structure is coupled in series with at least one load component of the CTLE.

6. The receiver device as claimed in claim 5, wherein: The CTLE includes differential input terminals and differential output terminals; The at least one load component includes: A first load component, the first load component being coupled to a first output terminal in the differential output terminals; and A second load component, the second load component being coupled to a second output terminal in the differential output terminals; and The at least one load inductor structure includes: A first load inductor structure, wherein the first load inductor structure is coupled in series with the first load component; and The second load inductor structure is coupled in series with the second load component.

7. The receiver device as claimed in claim 5, wherein: The CTLE includes a single-ended input terminal and a single-ended output terminal; The at least one load component includes: A first load component, the first load component being coupled to the single-ended output terminal; and The at least one load inductor structure includes: A first load inductor structure is coupled to the first load component.

8. The receiver device as claimed in claim 1, wherein, The RX AFE circuit is a variable gain amplifier (VGA), wherein at least one load inductor structure is coupled in series with at least one load component of the VGA.

9. The receiver device as claimed in claim 8, wherein: The VGA includes a single-ended input terminal and a single-ended output terminal; The at least one load component includes: A first load component, the first load component being coupled to the single-ended input terminal; and The at least one load inductor structure includes: A first load inductor structure is coupled to the first load component.

10. The receiver device as claimed in claim 8, wherein: The VGA includes differential input terminals and differential output terminals; The at least one load component includes: A first load component, the first load component being coupled to a first output terminal in the differential output terminals; and A second load component, the second load component being coupled to a second output terminal in the differential output terminals; and The at least one load inductor structure includes: A first load inductor structure, the first load inductor structure being coupled to the first load component; and The second load inductor structure is coupled to the second load component.

11. A serializer / deserializer (SerDes) circuit, comprising: Serializer; Deserializer; as well as A receiver comprising an analog front-end (AFE) circuit, the AFE circuit including at least one load inductor structure with a closed loop, wherein the AFE circuit is affected by variations in circuit parameters over a temperature range, causing temperature drift in the SerDes circuit, wherein the closed loop is used to reduce the temperature drift by generating eddy currents to reduce the effective inductance of the at least one load inductor structure, the eddy currents depending on the equivalent series resistance (ESR) of the closed loop.

12. The SerDes circuit as described in claim 11, wherein, The at least one load inductor structure includes a set of one or more turns, wherein at least one turn is short-circuited to form the closed loop.

13. The SerDes circuit as described in claim 12, wherein, The at least one load inductor structure includes a conductive trace structure in one or more layers of an integrated circuit containing the SerDes circuit.

14. The SerDes circuit as described in claim 11, wherein, The AFE circuit is a continuous-time linear equalizer (CTLE), wherein at least one load inductor structure is coupled in series with at least one load component of the CTLE.

15. The SerDes circuit as described in claim 14, wherein: The CTLE includes differential input terminals and differential output terminals; The at least one load component includes: A first load component, the first load component being coupled to a first output terminal in the differential output terminals; and A second load component, the second load component being coupled to a second output terminal in the differential output terminals; and The at least one load inductor structure includes: A first load inductor structure, the first load inductor structure being coupled to the first load component; and The second load inductor structure is coupled to the second load component.

16. The SerDes circuit as described in claim 14, wherein: The CTLE includes a single-ended input terminal and a single-ended output terminal; The at least one load component includes: A first load component, the first load component being coupled to the single-ended output terminal; and The at least one load inductor structure includes: A first load inductor structure is coupled to the first load component.

17. The SerDes circuit as claimed in claim 11, wherein, The AFE circuit is a variable gain amplifier (VGA), wherein at least one load inductor structure is coupled in series with at least one load component of the VGA.

18. The SerDes circuit as described in claim 17, wherein: The VGA includes a single-ended input terminal and a single-ended output terminal; The at least one load component includes: A first load component, the first load component being coupled to the single-ended input terminal; and The at least one load inductor structure includes: A first load inductor structure is coupled to the first load component.

19. The SerDes circuit as described in claim 17, wherein: The VGA includes differential input terminals and differential output terminals; The at least one load component includes: A first load component, the first load component being coupled to a first output terminal in the differential output terminals; and A second load component, the second load component being coupled to a second output terminal in the differential output terminals; and The at least one load inductor structure includes: A first load inductor structure, the first load inductor structure being coupled to the first load component; and The second load inductor structure is coupled to the second load component.

20. A method for designing a load inductor structure with a closed loop in an analog front-end AFE circuit, the method comprising: The dimensions of the load inductor structure are determined using a specified inductance value; The location of the closed loop within a plurality of turns of the load inductor structure is determined using a specified temperature compensation value. The load inductor structure includes a set of one or more turns, wherein at least one turn is short-circuited at the location to form the closed loop. as well as The trace width of the closed loop is determined using a specified frequency value.

21. A system for high-speed network communication, the system comprising: Processing unit; and A network interface coupled to the processing unit, wherein the network interface includes a receiver device, the receiver device comprising: A receiver analog front-end RX AFE circuit includes at least one load component and at least one load inductor structure with a closed loop. The RX AFE circuit is affected by variations in circuit parameters over a temperature range, causing temperature drift in the receiver device. The closed loop is used to reduce the temperature drift by generating eddy currents to reduce the effective inductance of the at least one load inductor structure. The eddy currents depend on the equivalent series resistance ESR of the closed loop.

22. The system of claim 21, wherein, The processing unit includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a network adapter, a network switch, or an NVLink switch.

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