Loop bus communication method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a loop bus communication method and device, electronic equipment and a storage medium, and relates to the technical field of industrial automation and intelligent control, and the method comprises the steps: carrying out the initialization of Master and Slave equipment through setting a current pulse signal threshold value, a return code data representation mode and a high-low voltage pulse width standard; the Master equipment sends downlink data by modifying a low-voltage pulse duty ratio and indicates a return code state by using a high-level pulse duty ratio, and the Slave equipment realizes full-duplex communication by changing a bus current return code. For address conflicts possibly caused by simultaneous code returning of multiple Slave devices, the Master device automatically triggers an address redistribution process by detecting the size of code returning current and a sequential relationship. A low-power-consumption timer is used for controlling the Slave device to be awakened only when a communication request is requested, and the Master device dynamically adjusts transmission parameters and speed by monitoring bus signal quality. According to the invention, the problems of low transmission efficiency and incapability of real-time arbitration and address conflict detection in the prior art are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of industrial automation and intelligent control technology, and in particular to a loop bus communication method, device, electronic device and storage medium. Background Technology

[0002] With the continuous improvement of industrial automation and intelligence, loop bus communication technology is increasingly widely used in fields such as automatic fire alarm systems, building automation, and security monitoring.

[0003] However, traditional loop bus communication methods, such as those employing "voltage-current hybrid modulation" technology, have gradually revealed numerous limitations when facing multi-node, long-distance, and high-reliability application scenarios. Traditional methods mainly rely on a master-slave asynchronous half-duplex communication mode, where the controller communicates with terminal devices sequentially through polling. This method is not only inefficient in transmission but also cannot enable simultaneous communication by multiple devices, limiting system response speed and device capacity.

[0004] Meanwhile, the lack of effective address conflict detection and bus arbitration mechanisms makes the equipment installation and debugging process complex and prone to communication conflicts and failures.

[0005] Furthermore, traditional methods have significant shortcomings in power consumption control. Slave devices often remain in standby mode, resulting in high power consumption and impacting the overall system energy efficiency ratio and device battery life. This power consumption issue is particularly pronounced in scenarios requiring the connection of a large number of devices.

[0006] Therefore, there is an urgent need for a loop bus communication method that can improve system transmission efficiency, device response speed and capacity, while simplifying the deployment process, reducing power consumption and being highly efficient and reliable. Summary of the Invention

[0007] The embodiments of the present invention provide a loop bus communication method to solve the problems of low transmission efficiency, inability to allow simultaneous communication of multiple devices, lack of address conflict detection and bus arbitration mechanism, complex installation and debugging, and high power consumption in the prior art. The technical solution is as follows: According to one aspect of the present invention, a loop bus communication method includes: determining basic parameters by setting a threshold for a current pulse signal, setting a representation method for return code data, and defining standards for high-voltage and low-voltage pulse widths; initializing and configuring a Master device and a Slave device according to the basic parameters; using the Master device to send downlink data by modifying the duty cycle of the low-voltage pulse and using the duty cycle of the high-level pulse to indicate the return code status; using the Slave device to receive and parse the data and send return code data by changing the bus current; when multiple Slave devices simultaneously return codes, the Master device detects the magnitude and timing relationship of the return code current according to a preset threshold to determine whether there is an address conflict; when an address conflict exists, the Master device automatically triggers an address reallocation process to allocate a new unique address to the conflicting device; using a low-power timer to control the Slave device to wake up only when it receives a communication request from the Master device; dynamically adjusting transmission parameters by monitoring bus signal quality; and dynamically adjusting the transmission rate according to the actual communication distance and environmental conditions.

[0008] In one embodiment, basic parameters are determined by setting a threshold for the current pulse signal, setting the representation method of the return code data, and defining the standards for high-voltage and low-voltage pulse widths. The initialization configuration of the Master and Slave devices based on these basic parameters is achieved through the following steps: setting a threshold for the current pulse signal to distinguish different return code states, defining the standards for high-voltage and low-voltage pulse widths, and initializing the Master and Slave devices based on the set parameters. The initialization configuration includes communication baud rate, address allocation, and operating mode. The address allocation includes preset and automatic allocation.

[0009] In one embodiment, the Master device transmits downlink data by modifying the duty cycle of the low-voltage pulse and uses the duty cycle of the high-level pulse to indicate the return code status. The Slave device receives and parses the data and sends out return code data by changing the bus current. This is achieved through the following steps: The Master device encodes different data bits by adjusting the duration of the low-voltage pulse and uses the duty cycle of the high-level pulse to indicate the status of the received Slave return code data; the Slave device receives the data sent by the Master device and parses it according to preset logic; when a return code is needed, the Slave device sends out return code data by changing the bus current; and the Master device is controlled to continuously monitor the bus current and receive return code data while transmitting data.

[0010] In one embodiment, when multiple slave devices simultaneously return codes, the master device detects the magnitude and timing relationship of the return code current based on a preset threshold to determine whether an address conflict exists. If an address conflict exists, the master device automatically triggers an address reallocation process to assign a new unique address to the conflicting device. This is achieved through the following steps: When multiple slave devices simultaneously return codes, the master device detects the magnitude and timing relationship of the return code current to determine whether an address conflict exists; if an address conflict is detected, the master device triggers an address reallocation process to assign a new unique address to the conflicting device using an algorithm or preset rules, ensuring that each device has an independent communication identifier.

[0011] In one embodiment, controlling the Slave device to wake up only when it receives a communication request from the Master device using a low-power timer is achieved through the following steps: using a low-power timer LPTMR to control the sleep and wake-up logic of the Slave device, ensuring that the Slave device only wakes up when it receives a communication request, and remains in a low-power sleep state at other times; configuring the interrupt signal I / O port caused by bus voltage changes as a double-edge wake-up through hardware configuration, so that the Slave device can be woken up instantly by voltage changes.

[0012] In one embodiment, the transmission parameters are dynamically adjusted by monitoring the bus signal quality, and the transmission rate is dynamically adjusted according to the actual communication distance and environmental conditions through the following steps: the transmission parameters are dynamically adjusted by the Master device by monitoring the bus signal quality, and the transmission rate is dynamically adjusted by the Master device according to the actual communication distance and environmental conditions; the signal quality includes signal-to-noise ratio and bit error rate; the transmission parameters include modulation method and coding efficiency.

[0013] In one embodiment, the method further includes the following steps: adopting an ultra-low power design for the Slave device, and combining it with a low-power timer and a wake-up mechanism, so that the Slave device can maximize its battery life while ensuring communication performance; the ultra-low power design includes using low-power components and optimizing circuit layout.

[0014] According to one aspect of the present invention, a loop bus communication device includes: a parameter setting and initialization module, configured to determine basic parameters by setting a threshold for a current pulse signal, setting a representation method for return code data, and defining standards for high-voltage and low-voltage pulse widths, and to initialize and configure a Master device and a Slave device according to the basic parameters; a full-duplex data communication module, configured to use the Master device to send downlink data by modifying the duty cycle of the low-voltage pulse and to use the duty cycle of the high-level pulse to indicate the return code status, use the Slave device to receive and parse the data, and send return code data by changing the bus current; an address conflict detection and processing module, configured to determine whether there is an address conflict when multiple Slave devices return codes simultaneously, by having the Master device detect the magnitude and timing relationship of the return code current according to a preset threshold, and when an address conflict exists, by having the Master device automatically trigger an address reassignment process to assign a new unique address to the conflicting device; and a dynamic adjustment and low-power control module, configured to use a low-power timer to control the Slave device to wake up and work only when it receives a communication request from the Master device, dynamically adjust transmission parameters by monitoring bus signal quality, and dynamically adjust the transmission rate according to the actual communication distance and environmental conditions.

[0015] According to one aspect of the present invention, an electronic device includes at least one processor and at least one memory, wherein computer-readable instructions are stored on the memory; the computer-readable instructions are executed by one or more of the processors to cause the electronic device to implement the loop bus communication method as described above.

[0016] According to one aspect of the present invention, a storage medium has computer-readable instructions stored thereon, which are executed by one or more processors to implement the loop bus communication method as described above.

[0017] The beneficial effects of the technical solution provided by this invention are: In the above technical solution, this invention initializes and configures the Master and Slave devices by setting current pulse signal thresholds, return code data representation methods, and high and low voltage pulse width standards. The Master device sends downlink data by modifying the duty cycle of the low voltage pulse and uses the duty cycle of the high-level pulse to indicate the return code status. The Slave device achieves full-duplex communication by changing the bus current return code. To address address conflicts that may arise from simultaneous return codes from multiple Slave devices, the Master device automatically triggers an address reallocation process by detecting the magnitude and timing relationship of the return code current, ensuring communication uniqueness. Simultaneously, a low-power timer is used to control the Slave device to wake up only when communication requests are requested, combined with a dual-edge wake-up mechanism, significantly reducing power consumption. Furthermore, the Master device dynamically adjusts transmission parameters and rates by monitoring bus signal quality to adapt to different communication distances and environmental conditions. This invention not only improves communication efficiency and device response speed but also enhances system reliability and energy efficiency, effectively solving the application challenges of traditional methods in multi-node, long-distance, and high-reliability scenarios. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a loop bus communication method according to an exemplary embodiment; Figure 2 This is an interactive diagram of a loop bus communication method in an application scenario; Figure 3 This is a block diagram of a loop bus communication device according to an exemplary embodiment; Figure 4 This is a hardware structure diagram of an electronic device according to an exemplary embodiment; Figure 5 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this disclosure means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0022] This invention provides a loop bus communication method that achieves efficient and reliable communication in a loop bus system through a full-duplex communication mechanism, dynamic address conflict detection and automatic reallocation, ultra-low power consumption design, and adaptive transmission rate adjustment. It solves the problems of traditional methods in terms of transmission efficiency, device capacity, power consumption control, and deployment complexity. This loop bus communication method is applicable to loop bus communication devices, which can be electronic devices. The loop bus communication method in this invention can be applied to various scenarios, such as loop bus communication.

[0023] Please see Figure 1 This invention provides a loop bus communication method applicable to electronic devices.

[0024] In the following method embodiments, for ease of description, the execution subject of each step of the method is an electronic device, but this does not constitute a specific limitation.

[0025] like Figure 1 As shown, the method may include the following steps: Step 110: Determine the basic parameters by setting the threshold of the current pulse signal, setting the representation method of the return code data, and defining the standard for high voltage and low voltage pulse widths. Then, initialize and configure the Master device and Slave device based on the basic parameters.

[0026] In one possible implementation, a threshold for the current pulse signal is set to distinguish different return code states, a standard for the pulse width of high voltage and low voltage is defined, and the Master device and Slave device are initialized and configured according to the set parameters.

[0027] The initial configuration includes communication baud rate, address allocation, working mode, etc. Address allocation includes preset, automatic allocation, etc., none of which are specified here.

[0028] Specifically, different current pulse signal thresholds are set to distinguish between return code data 0 and 1. For example, A+20mA represents return code data 1, and AmA represents return code data 0. The specific time standards for high-voltage and low-voltage pulse widths are defined, such as t for data 0, 2t for data 1, 4t for the end of transmission, and 6t for the start of transmission. Based on these parameters, the Master and Slave devices are initialized and configured, including communication baud rate, address allocation (preset or automatic allocation), and operating mode.

[0029] Initialization parameter configuration is fundamental to ensuring normal system operation. Precisely setting the current pulse signal threshold and high / low voltage pulse width standards provides a reliable basis for encoding and decoding subsequent data transmission. Simultaneously, initializing the devices ensures that the Master and Slave devices can accurately identify and process data during communication.

[0030] In the above process, the embodiments of the present invention ensure the accuracy and reliability of system communication by accurately setting the current pulse signal threshold and the high and low voltage pulse width standards, and by initializing the device, thus laying a solid foundation for subsequent data transmission.

[0031] Step 120: The Master device sends downlink data by modifying the duty cycle of the low-voltage pulse and uses the duty cycle of the high-level pulse to indicate the return code status. The Slave device receives and parses the data and sends out the return code data by changing the bus current.

[0032] In one possible implementation, the Master device encodes different data bits by adjusting the duration of low-voltage pulses, and uses the duty cycle of high-level pulses to indicate the status of received Slave response data. The Slave device receives data sent by the Master device and parses it according to preset logic. When a response is needed, the Slave device sends response data by changing the bus current, and controls the Master device to continuously monitor the bus current and receive response data while sending data.

[0033] Specifically, the Master device encodes different data bits by modifying the duty cycle of low-voltage pulses, while using the duty cycle of high-level pulses to indicate the status of received Slave response data. The Slave device receives data sent by the Master device and parses it according to preset logic. When a response is needed, the Slave device sends response data by changing the bus current, while the Master device continuously monitors the bus current to receive the response data while sending data.

[0034] Full-duplex data communication enables simultaneous data transmission and reception by both Master and Slave devices, significantly improving transmission efficiency. The Master device encodes data by adjusting the duty cycle of low-voltage pulses, while simultaneously using the duty cycle of high-level pulses to provide feedback on the code status, allowing the Slave device to monitor data reception in real time. Upon receiving data, the Slave device parses it according to preset logic and, when necessary, adjusts the bus current to provide feedback, thus achieving bidirectional communication.

[0035] In the above process, the embodiments of the present invention realize the simultaneous transmission and reception of data by the Master and Slave devices through the full-duplex data communication mechanism, which significantly improves the transmission efficiency and enhances the real-time performance and response speed of the system.

[0036] Step 130: When multiple slave devices return codes simultaneously, the master device detects the magnitude and timing relationship of the return code current based on a preset threshold to determine whether there is an address conflict. When an address conflict exists, the master device automatically triggers an address reallocation process to allocate a new unique address to the conflicting device.

[0037] In one possible implementation, when multiple slave devices return codes simultaneously, the master device determines whether there is an address conflict by detecting the magnitude and timing relationship of the return code current. If an address conflict is detected, the master device triggers an address reallocation process, which assigns a new unique address to the conflicting device using an algorithm or preset rules, ensuring that each device has an independent communication identifier.

[0038] Specifically, when multiple slave devices return codes simultaneously, the master device determines whether an address conflict exists by detecting the magnitude and timing relationship of the return code current. If an address conflict is detected, the master device automatically triggers an address reallocation process, assigning a new unique address to the conflicting device using an algorithm or preset rules.

[0039] Address conflicts are a common problem in multi-node communication, and traditional methods often fail to resolve them effectively. This invention, by detecting the magnitude and timing relationship of the return code current, can accurately determine whether an address conflict exists and automatically trigger an address reallocation process upon detection. This mechanism ensures that each device has an independent communication identifier, avoiding communication conflicts and improving system stability and reliability.

[0040] In the above process, the embodiments of the present invention realize the automatic detection and reallocation of address conflicts by detecting the magnitude and timing relationship of the return code current, ensuring that each device has an independent communication identifier, effectively avoiding communication conflicts, and improving the stability and reliability of the system.

[0041] Step 140: Use a low-power timer to control the Slave device to wake up and work only when it receives a communication request from the Master device. Dynamically adjust the transmission parameters by monitoring the bus signal quality and dynamically adjust the transmission rate according to the actual communication distance and environmental conditions.

[0042] In one possible implementation, a low-power timer LPTMR is used to control the sleep and wake-up logic of the slave device, ensuring that the slave device only wakes up to work when it receives a communication request, and remains in a low-power sleep state at other times; the interrupt signal I / O port caused by bus voltage changes is configured as a double-edge wake-up through hardware configuration, so that the slave device can be woken up at the moment of voltage change.

[0043] In one possible implementation, the Master device dynamically adjusts the transmission parameters by monitoring the bus signal quality, and dynamically adjusts the transmission rate based on the actual communication distance and environmental conditions.

[0044] One possible implementation involves using an ultra-low power design for the slave device, combined with a low-power timer and wake-up mechanism, to maximize the device's battery life while ensuring communication performance.

[0045] Signal quality includes signal-to-noise ratio, bit error rate, etc., transmission parameters include modulation method, coding efficiency, etc., and ultra-low power design includes using low-power components, optimizing circuit layout, etc., none of which are specified here.

[0046] Specifically, the slave device employs an ultra-low power design, combined with low-power timers and a wake-up mechanism, enabling the slave device to maximize its battery life while ensuring communication performance. By monitoring bus signal quality (such as signal-to-noise ratio and bit error rate), the master device dynamically adjusts transmission parameters (such as modulation scheme and coding efficiency) and transmission rate to adapt to different communication distances and environmental conditions.

[0047] By employing low-power components, optimizing circuit layout, and combining low-power timers and wake-up mechanisms, the Slave device can maximize battery life while ensuring communication performance. Meanwhile, the Master device monitors bus signal quality and dynamically adjusts transmission parameters and rates to ensure system stability and reliability under varying communication distances and environmental conditions.

[0048] In the above process, the embodiments of the present invention achieve long battery life for the slave device and stable and reliable communication of the system through ultra-low power consumption design and dynamic parameter adjustment mechanism. This mechanism not only reduces system power consumption but also improves the system's adaptability and flexibility, meeting the needs of modern industrial automation and intelligent development.

[0049] Through the above process, this embodiment of the invention achieves efficient and stable communication by configuring initialization parameters, full-duplex data communication, address conflict detection and automatic reallocation, and ultra-low power consumption and dynamic parameter adjustment. This method not only improves transmission efficiency and device response speed but also solves the problems of traditional methods in address conflict detection, power consumption control, and deployment complexity, providing strong support for the development of modern industrial automation and intelligence.

[0050] In an exemplary embodiment, the master-slave asynchronous full-duplex communication method provided by the present invention is used in a loop bus communication system to achieve efficient, stable, and low-power data transmission through specific interactions between the master controller (Master) and the slave device (Slave) based on specific pulse width modulation coding and the meaning of current pulse signals.

[0051] The meaning of low voltage pulse width encoding includes: when the low voltage pulse width is t, it represents data 0.

[0052] A low-voltage pulse width of 2t indicates data 1. A low-voltage pulse width of 4t indicates the end of transmission. A low-voltage pulse width of 6t indicates the start of transmission (preamble).

[0053] The meaning of high-voltage pulse width encoding includes: when the high-voltage pulse width is t, it serves as uplink data feedback, indicating that data 0 has been received. When the high-voltage pulse width is 2t, it serves as uplink data feedback, indicating that data 1 has been received.

[0054] The meanings of the current pulse signal are as follows: a current pulse signal of A+20mA indicates a return code data of 1. A current pulse signal of AmA indicates a return code data of 0.

[0055] Specifically, the Master (main controller) operation process includes: initializing the timer; to ensure time accuracy, the Master uses a microsecond-level timer for all counting operations. Pulse-related I / O operations are handled in the interrupt handling callback to ensure timeliness and accuracy.

[0056] Furthermore, in data transmission preparation, when data needs to be transmitted, the Master first sends a 6t low-voltage pulse preamble indicating the start of transmission, then pulls down the bus voltage and resets the timer interrupt cycle to 6t to prepare for data transmission.

[0057] Furthermore, in data transmission, after a timer interrupt is triggered, the Master pulls the bus voltage high and resets the timer period to 1t. Upon triggering the timer interrupt again, the Master pulls the bus voltage low and begins sending data bit by bit. If the data bit is 1, the timer interrupt period is reset to 2t according to the encoding rules; if it is 0, it is reset to 1t.

[0058] Furthermore, during data transmission, the Master continuously monitors the bus current to receive response data from the Slave. After pulling the bus voltage low, the Master uses DMA+ADC functionality to quickly acquire the supply current on the bus, with a sampling time less than t, to improve efficiency.

[0059] Based on the sampling results and the meaning of the current pulse signal, the Master determines the return code data: if the current is AmA, that is, the current is less than (A+10mA (an intermediate value is assumed here for differentiation, and the actual value is determined according to the specific current range)) mA (to accurately correspond to the meaning), then the return code data is 0; if the current is A+20mA, that is, the current is ≥ (A+10) mA, then the return code data is 1; if the current is ≥ 1.5~2 times the relevant current value (estimated based on A+20mA), then it is determined that two Slaves are simultaneously returning code 1, and an address conflict has occurred.

[0060] Furthermore, regarding period adjustment and continued transmission, after the timer interrupt is triggered again, the Master adjusts the timer period based on the sampling results and the meaning of the high-voltage pulse width encoding: if the feedback data corresponds to the received data 0, i.e., the feedback data is equivalent to a feedback data of 0, then the period is reset to t; if it corresponds to the received data 1, i.e., the feedback data is 1, then it is reset to 2t. If the data transmission is not complete, it jumps back to the data transmission step to continue transmitting.

[0061] Furthermore, after data transmission is complete, the Master sends a 4t low-voltage pulse end code to indicate the end of transmission, pulls the bus voltage low, and resets the timer period to 4t. Upon triggering a timer interrupt, the bus voltage is pulled high, ending the transmission process.

[0062] Specifically, the Slave operation process includes: low-power initialization. The Slave uses a microsecond-level low-power timer to ensure that it is only woken up during communication and remains in sleep mode the rest of the time to reduce power consumption.

[0063] Furthermore, in terms of interrupt wake-up configuration, the hardware configures the interrupt signal I / O port caused by bus voltage changes as a double-edge wake-up, so as to respond quickly when the voltage changes.

[0064] Furthermore, regarding timestamp recording and sleep mode, each time the slave is woken up, it only records the timestamp of the wake-up and then immediately enters sleep mode, reducing unnecessary power consumption.

[0065] Furthermore, pulse width detection and data recording are performed. Each time the slave is woken up by a falling edge, it records the high-level pulse width and uses the low-voltage pulse width encoding to determine the received data. When woken up by a rising edge, it records the low-level pulse width and combines it with the high-voltage pulse width encoding to parse the data feedback sent by the master.

[0066] Furthermore, data return codes and collision avoidance are implemented. Upon receiving the start symbol (6t low-voltage pulse), the slave begins recording data. If a return code is needed, the current is adjusted to the corresponding value after the next falling edge to return the code data. If the return code data is 1, the current is set to A+20mA; if the return code data is 0, the current is set to AmA.

[0067] If the slave is currently sending a response code, after waking up on the rising edge, it compares the received code data with the width of the high-level pulse to determine if other devices are sending responses simultaneously, thus avoiding communication conflicts. For example, if its own response code is 1, the normal high-level pulse width should be 2t, corresponding to the received data 1. If the detected high-level pulse width does not match, it is determined that another device is sending data.

[0068] Further, data parsing and response. Upon receiving the end-of-transmission marker (4t low-voltage pulse), the slave parses the received data. If a return code is required, a return code data frame is generated, and preparation for the next communication is made.

[0069] Through the above process, this embodiment of the invention, combining explicit pulse width modulation coding and the meaning of current pulse signals, achieves efficient, low-power full-duplex communication between the Master and Slave. The Master can accurately send data according to the coding rules and accurately receive the Slave's response codes and feedback based on current and high-voltage pulse conditions, while effectively detecting address conflicts; the Slave can quickly respond to the Master's communication requests with extremely low power consumption, parse data according to the coding, and correctly respond with response codes, ensuring the stability and reliability of the entire system. This embodiment effectively improves the performance of the loop bus communication system and is suitable for multi-node, long-distance, and high-reliability application scenarios.

[0070] In one application scenario, the loop bus communication method of the present invention is used for loop bus communication.

[0071] like Figure 2 The diagram illustrates the data interaction between the Master and Slave. The left side shows the connection between the Master and Slave, and labels the voltage and current characteristics. The voltage range is from 19V to 24V, and the current characteristics range from amA to a+20mA. Figure 2The middle and right sides respectively illustrate the process of the Master sending data to the Slave and the Slave sending data to the Master. The yellow background represents the signals sent by the Master, indicated by yellow "0" and "1"; the cyan background represents the signals sent by the Slave. Figure 2 In this code, red data represents the return code signal, and black text represents the reflected signal. For example, when the Master sends the signal “0”, “1”, “1”, “0”, the Slave will return the corresponding return code signal “0”, “0”, “0”, “0” (red data), along with a reflected signal (black text).

[0072] In this configuration, the master transmits data to the slave via a low-level signal and indicates to the slave via a high-level signal that it received a response from the slave at the previous moment. When transmitting data, the master needs to check the current change on the bus when its voltage is pulled low to detect if the slave has responded. It then sends the received data out by changing the following high-level signal width.

[0073] Furthermore, the slave transmits data to the master by changing the current during low-level periods; the slave needs to simultaneously detect both the low-level and high-level widths. The low-level width indicates the data actively transmitted by the master, while the high-level width indicates the data received by the master from the slave's response.

[0074] Furthermore, each time a slave replies with a bit, it needs to check the following high-level width. If the detected data is different from the data it transmitted, it indicates that another slave is using the bus for transmission. Transmission needs to be stopped, and bus control privileges need to be released.

[0075] Furthermore, when receiving response codes, the master needs to detect the magnitude of the low-level response code current. If the current exceeds twice the response code current of a single device, it can be determined that more than one device is simultaneously responding, thus indicating an address conflict. When an address conflict is detected, the conflicting addresses can be automatically redistributed through arbitration, eliminating the need for manual handling and reducing deployment complexity.

[0076] Furthermore, the master can transmit specific frames, and the slave, upon receiving the frame, will reply with the same data. The master can dynamically detect the return data during transmission and adjust the transmission rate accordingly based on the received data, thus improving communication success rate. When the transmission distance is too long, the transmission rate can be dynamically reduced to increase the communication success rate; when the transmission distance is short, the transmission rate can be dynamically increased to improve response speed and device capacity.

[0077] Furthermore, software processing ensures that the slave device only wakes up and operates for a brief moment during communication. From the start to the end of each communication session, the slave device operates for only milliseconds, with average power consumption kept below 10uA. It also maintains pulse measurement accuracy while balancing ultra-low power consumption.

[0078] This invention employs master-slave asynchronous full-duplex communication, allowing both the master and slave to send and receive data simultaneously, thus improving transmission efficiency. Queries and responses can be transmitted concurrently. The master transmits data by modifying the low-voltage duty cycle, while simultaneously modifying the high-level duty cycle to indicate the received response data from the slave. This signal serves as both the data signal and the slave's clock signal.

[0079] When a slave receives a query command from the master, if it needs to reply with an acknowledgment frame, it must reply when the master initiates the next transmission. Asynchronous full-duplex communication between the master and slave can be achieved by changing the bus current response code during low voltage periods, thus reducing bus overhead.

[0080] While transmitting data, the master needs to enable receive detection and check the remaining length of the received frame to determine if it exceeds the remaining length of the transmitted frame. If the remaining transmitted frame length is less than the received acknowledgment frame length, additional transmission is required to make up the transmission length (because the transmitted frame serves as both a data signal and a clock signal, so the transmitted frame length cannot be less than the received frame length). In this transmission method, the slave can also arbitrate by checking the return code data when sending data, and the master can also detect address conflicts by detecting the return code current.

[0081] Ultra-low power consumption: Because the bus is a one-to-many communication system, every time the master initiates communication, all slave devices receive a signal. Receiving the signal also wakes up all slave devices, putting them into working mode. In this situation, the slave device sleep time is shortened, and power consumption increases. This indirectly reduces the number of slave devices in the entire system.

[0082] Specifically, if there are 100 devices (slave1-slave100) connected to the bus, when the master needs to query sequentially, it first queries slave1. If no device responds, it then queries slave2 while slave1 responds. This process continues until slave100 responds, completing the polling of all 100 devices in just 101 frame transmission cycles. In contrast, a typical half-duplex transmission would require 200 frame transmission cycles. This significantly reduces bus occupancy time and communication response speed.

[0083] Through the above process, this embodiment of the invention employs master-slave asynchronous full-duplex communication, allowing the Master and Slave to simultaneously send and receive data, improving transmission efficiency and reducing bus overhead. Specific pulse width modulation and current variation rules ensure accurate data transmission and address conflict detection, and the rate can be dynamically adjusted based on transmission distance to guarantee communication success. Ultra-low power consumption is a major highlight; the slave device only wakes up during communication, with average power consumption remaining below 10uA, balancing power consumption and communication speed. In multi-device polling scenarios, compared to ordinary half-duplex transmission methods, this method significantly shortens bus occupancy time and communication response speed; for example, polling 100 devices requires only 101 frame transmission cycles. This method effectively improves the performance and reliability of the loop bus communication system and is suitable for multi-node scenarios.

[0084] In another application scenario, an automatic fire alarm system is used. The system mainly includes a master controller and multiple fire detectors (slaves). Data interaction and control are achieved through a loop bus to ensure a rapid response and appropriate measures can be taken when a fire occurs.

[0085] Specifically, the master controller is first physically connected to multiple fire detectors via a loop bus to ensure that each detector can communicate with the master controller via the bus.

[0086] Parameter settings: Current pulse signal threshold: Set A+20mA to represent retrieval code data 1, and AmA to represent retrieval code data 0, to ensure data transmission accuracy. Voltage pulse width standard: Define the standard for high voltage and low voltage pulse widths. For example, t width represents data 0 or received data 0 in the uplink data feedback, and 2t width represents data 1 or received data 1 in the uplink data feedback. Communication mode setting: Set the main controller and detector to full-duplex communication mode to enable bidirectional data transmission.

[0087] Address Allocation: Preset Address: A unique address is preset for each detector to ensure accurate identification of each device during communication. Automatic Allocation: When the system starts up, the main controller can also automatically allocate addresses to the detectors through a specific protocol, improving deployment efficiency.

[0088] Furthermore, full-duplex data communication includes: Data transmission: The master controller sends query commands to each fire detector (slave) sequentially according to the preset inspection logic. The master controller encodes different data bits by modifying the duty cycle of the low-voltage pulse; for example, it represents the data "0" or "1" by adjusting the duration of the low-voltage pulse.

[0089] Meanwhile, the duty cycle of the high-level pulse is used to indicate the status of the received Slave response data, thereby achieving synchronization of bidirectional data transmission.

[0090] Further, regarding data reception and feedback: The fire detector (Slave) receives data from the main controller and parses it according to its internal preset logic. If the detector detects that fire-related parameters (such as smoke concentration, temperature, etc.) exceed preset thresholds, it sends feedback data by changing the bus current when feedback is required, feeding back the fire alarm information to the main controller. The main controller (Master) continuously monitors the bus current while sending data to receive feedback data from the detector. By detecting changes in current, the main controller can accurately parse the feedback information sent by the detector.

[0091] Furthermore, address conflict detection and automatic reallocation include: Conflict detection: During system operation, when multiple fire detectors simultaneously send response codes to the main controller, the main controller determines whether an address conflict exists by detecting the magnitude and timing relationship of the response code current. For example, if the amplitude or time interval of the response code current does not conform to the preset response code characteristics of a single device, an address conflict is determined to exist.

[0092] Furthermore, automatic reassignment: If an address conflict is detected, the main controller automatically triggers the address reassignment process. Based on internally preset algorithms or rules, the main controller assigns a new, unique address to the conflicting detector, ensuring that each detector has an independent communication identifier and avoiding communication chaos.

[0093] Furthermore, the ultra-low power design and dynamic parameter adjustment include: Ultra-low power design: Hardware selection: Selecting low-power electronic components, optimizing circuit layout, and reducing leakage current in the circuit. Wake-up mechanism: Combining a low-power timer and a wake-up mechanism, the detector is in a low-power sleep state most of the time, and only when it receives a communication request from the main controller is the wake-up mechanism triggered by the low-power timer, causing the detector to wake up instantly and enter the working state.

[0094] Furthermore, dynamic parameter adjustment includes: Transmission parameter adjustment: The main controller monitors bus signal quality, such as signal-to-noise ratio and bit error rate, and dynamically adjusts transmission parameters, including modulation method and coding efficiency, to improve the accuracy and stability of data transmission. Transmission rate adjustment: Based on the actual communication distance and environmental conditions, such as bus length and electromagnetic interference, the transmission rate is dynamically adjusted to ensure the real-time performance and reliability of data transmission.

[0095] Through the above process, this embodiment of the invention achieves efficient and reliable communication between the main controller and detectors in an automatic fire alarm system. The full-duplex communication mechanism improves communication efficiency and real-time performance, the address conflict detection and automatic reassignment mechanism ensures the stability of multi-device communication, the ultra-low power consumption design extends device battery life, and dynamic parameter adjustment improves the system's adaptability and communication reliability in different environments. This method effectively improves the performance of the automatic fire alarm system, providing strong support for protecting the lives and property of personnel.

[0096] The following are embodiments of the apparatus of the present invention, which can be used to execute the loop bus communication method involved in the present invention. For details not disclosed in the embodiments of the apparatus of the present invention, please refer to the method embodiments of the loop bus communication method involved in the present invention.

[0097] Please see Figure 3 This invention provides a loop bus communication device 800.

[0098] The loop bus communication device 800 includes, but is not limited to: a parameter setting and initialization module 810, a full-duplex data communication module 830, an address conflict detection and processing module 850, and a dynamic adjustment and low-power control module 870.

[0099] The parameter setting and initialization module 810 is used to determine basic parameters by setting the threshold of the current pulse signal, setting the representation method of the return code data, and defining the standard for high voltage and low voltage pulse widths, and to initialize and configure the Master device and Slave device according to the basic parameters.

[0100] The full-duplex data communication module 830 is used to send downlink data by modifying the duty cycle of the low voltage pulse using a Master device, and to indicate the return code status by using the duty cycle of the high-level pulse. The Slave device receives and parses the data, and sends out the return code data by changing the bus current.

[0101] The address conflict detection and processing module 850 is used to determine whether there is an address conflict when multiple slave devices return codes at the same time. The master device detects the magnitude and timing relationship of the code return current according to a preset threshold. When an address conflict exists, the master device automatically triggers the address reallocation process to allocate a new unique address to the conflicting device.

[0102] The dynamic adjustment and low-power control module 870 is used to control the slave device to wake up and work only when it receives a communication request from the master device using a low-power timer. It dynamically adjusts the transmission parameters by monitoring the bus signal quality and dynamically adjusts the transmission rate according to the actual communication distance and environmental conditions.

[0103] It should be noted that the loop bus communication provided in the above embodiments is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the loop bus communication device will be divided into different functional modules to complete all or part of the functions described above.

[0104] Furthermore, the loop bus communication device and loop bus communication method embodiments provided in the above embodiments belong to the same concept, and the specific way in which each module performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0105] Figure 4 A schematic diagram of the structure of an electronic device according to an exemplary embodiment is shown.

[0106] It should be noted that this electronic device is merely an example adapted to the present invention and should not be construed as providing any limitation on the scope of use of the present invention. Furthermore, this electronic device should not be interpreted as requiring or depending on having... Figure 4 One or more components of the exemplary electronic device 2000 shown.

[0107] The hardware structure of electronic devices 2000 can vary significantly due to differences in configuration or performance, such as... Figure 4 As shown, the electronic device 2000 includes: a power supply 210, an interface 230, at least one memory 250, and at least one central processing unit (CPU) 270.

[0108] Specifically, power supply 210 is used to provide operating voltage for various hardware devices on electronic device 2000.

[0109] Interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. Of course, in other examples adapted to this invention, interface 230 may further include at least one serial-to-parallel conversion interface 233, at least one input / output interface 235, and at least one USB interface 237, etc. Figure 4 As shown, this does not constitute a specific limitation.

[0110] The memory 250 serves as a carrier for resource storage and can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it include the operating system 251, application programs 253, and data 255, etc., and the storage method can be temporary storage or permanent storage.

[0111] The operating system 251 is used to manage and control the various hardware devices and application programs 253 on the electronic device 2000, so as to enable the central processing unit 270 to perform calculations and processing on the massive data 255 in the memory 250. It can be Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0112] Application 253 is a computer-readable instruction based on operating system 251 that performs at least one specific task, and may include at least one module ( Figure 4 (Not shown), each module may contain computer-readable instructions for electronic device 2000. For example, the loop bus communication device can be considered as application program 253 deployed on electronic device 2000.

[0113] Data 255 may be signal information, etc., and is stored in memory 250.

[0114] The central processing unit 270 may include one or more processors and is configured to communicate with the memory 250 via at least one communication bus to read computer-readable instructions stored in the memory 250, thereby performing operations and processing on massive amounts of data 255 stored in the memory 250. For example, the loop bus communication method can be implemented by the central processing unit 270 reading a series of computer-readable instructions stored in the memory 250.

[0115] Furthermore, the present invention can also be implemented through hardware circuits or a combination of hardware circuits and software. Therefore, the implementation of the present invention is not limited to any specific hardware circuit, software, or combination thereof.

[0116] Please see Figure 5 This invention provides an electronic device 4000, which may include: a desktop computer, a laptop computer, a server, etc., with sensor recognition capabilities.

[0117] exist Figure 5 In this context, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.

[0118] The data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0119] Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0120] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0121] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program instructions or code in the form of instructions or data structures and accessible by the electronic device 4000, but not limited thereto.

[0122] The memory 4003 stores computer-readable instructions, and the processor 4001 can read the computer-readable instructions stored in the memory 4003 through the communication bus 4002.

[0123] The computer-readable instructions are executed by one or more processors 4001 to implement the loop bus communication methods in the above embodiments.

[0124] Furthermore, this embodiment of the invention provides a storage medium storing computer-readable instructions, which are executed by one or more processors to implement the loop bus communication method described above.

[0125] This invention provides a computer program product, which includes computer-readable instructions stored in a storage medium. One or more processors of an electronic device read the computer-readable instructions from the storage medium, load and execute the computer-readable instructions, thereby enabling the electronic device to implement the loop bus communication method as described above.

[0126] Compared with related technologies, the beneficial effects of the present invention are: 1. This invention can improve communication efficiency and real-time performance; by adopting a full-duplex communication mechanism, the Master device and the Slave device can send and receive data simultaneously, which changes the inefficient mode of the controller polling the terminal devices sequentially in the traditional master-slave asynchronous half-duplex communication, greatly shortens the data transmission cycle, realizes real-time bidirectional data transmission, and allows the Master to obtain the Slave status information and issue instructions in a timely manner.

[0127] 2. This invention has precise address conflict resolution capabilities; it determines whether an address conflict exists by detecting the magnitude and timing relationship of the return code current through the Master device, and automatically triggers the address reallocation process when a conflict is detected, allocating a new unique address to the conflicting device according to the algorithm or preset rules, ensuring that each device has an independent communication identifier, effectively avoiding communication chaos, and ensuring the stability of multi-device communication.

[0128] 3. This invention enables ultra-low power operation; by adopting an ultra-low power design for the slave device, selecting low-power components, optimizing circuit layout, and combining a low-power timer and wake-up mechanism, the slave device is in a low-power sleep state most of the time, only waking up instantly when a communication request is received, which greatly reduces device power consumption, extends device battery life, and meets the requirements for long-term stable operation of the system.

[0129] 4. This invention has dynamic adaptability; by monitoring bus signal quality, such as signal-to-noise ratio and bit error rate, through the Master device, the transmission parameters (modulation method, coding efficiency) and transmission rate are dynamically adjusted to adapt to different communication distances and environmental conditions, ensuring the accuracy and stability of data transmission, and improving the system's adaptability and reliability in complex environments.

[0130] 5. This invention enhances the convenience of system deployment; it supports automatic address allocation, which can automatically allocate addresses to Slave devices during system initialization or when adding new devices, reducing the workload and error probability of manual configuration, simplifying the system deployment process, and improving deployment efficiency.

[0131] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0132] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A loop bus communication method, characterized in that, The method includes: The basic parameters are determined by setting the threshold of the current pulse signal, setting the representation method of the return code data, and defining the standard for high voltage and low voltage pulse width. The Master device and Slave device are then initialized and configured based on the basic parameters. The Master device sends downlink data by modifying the duty cycle of the low-voltage pulse and uses the duty cycle of the high-level pulse to indicate the return code status. The Slave device receives and parses the data and sends out the return code data by changing the bus current. When multiple Slave devices return codes simultaneously, the Master device detects the magnitude and timing relationship of the return code current based on a preset threshold to determine whether there is an address conflict. If an address conflict exists, the Master device automatically triggers an address reallocation process to allocate a new unique address to the conflicting device. The slave device is controlled to wake up and work only when it receives a communication request from the master device. The transmission parameters are dynamically adjusted by monitoring the bus signal quality, and the transmission rate is dynamically adjusted according to the actual communication distance and environmental conditions.

2. The loop bus communication method as described in claim 1, characterized in that, The process involves determining basic parameters by setting a threshold for the current pulse signal, defining the representation method for the return code data, and defining standards for high-voltage and low-voltage pulse widths. Based on these basic parameters, the Master and Slave devices are initialized and configured, including: A threshold for the current pulse signal is set to distinguish different return code states, and standards for high-voltage and low-voltage pulse widths are defined. The Master and Slave devices are initialized and configured according to the set parameters. The initialization configuration includes communication baud rate, address allocation, and working mode. The address allocation includes preset and automatic allocation.

3. The loop bus communication method as described in claim 1, characterized in that, The process involves the Master device transmitting downlink data by modifying the duty cycle of low-voltage pulses and using the duty cycle of high-level pulses to indicate the return code status. The Slave device receives and parses the data and transmits return code data by changing the bus current. This includes: The Master device uses the duration of the low-voltage pulse to encode different data bits and the duty cycle of the high-level pulse to indicate the status of the received Slave response data. The Slave device receives data sent by the Master device and parses it according to preset logic. When a response code is needed, the Slave device sends the response code data by changing the bus current. The Master device is controlled to continuously monitor the bus current and receive the response code data while sending data.

4. The loop bus communication method as described in claim 1, characterized in that, When multiple slave devices simultaneously return codes, the master device detects the magnitude and timing relationship of the return code current based on a preset threshold to determine whether an address conflict exists. If an address conflict exists, the master device automatically triggers an address reallocation process to allocate a new unique address to the conflicting device, including: When multiple slave devices return codes simultaneously, the master device determines whether there is an address conflict by detecting the magnitude and timing relationship of the return code current. If an address conflict is detected, the address reallocation process is triggered through the Master device, which assigns a new unique address to the conflicting device using an algorithm or preset rules, ensuring that each device has an independent communication identifier.

5. The loop bus communication method as described in claim 1, characterized in that, The method of using a low-power timer to control the Slave device to wake up and operate only when it receives a communication request from the Master device includes: The sleep and wake-up logic of the slave device is controlled by a low-power timer LPTMR to ensure that the slave device only wakes up to work when it receives a communication request, and is in a low-power sleep state at other times. By configuring the interrupt signal I / O port caused by bus voltage changes to be double-edge wake-up via hardware configuration, the Slave device can be woken up instantly by voltage changes.

6. The loop bus communication method as described in claim 1, characterized in that, The method of dynamically adjusting transmission parameters by monitoring bus signal quality and dynamically adjusting the transmission rate according to the actual communication distance and environmental conditions includes: The Master device dynamically adjusts transmission parameters by monitoring bus signal quality, and dynamically adjusts the transmission rate according to the actual communication distance and environmental conditions; the signal quality includes signal-to-noise ratio and bit error rate; the transmission parameters include modulation method and coding efficiency.

7. The loop bus communication method as described in claim 1, characterized in that, The method further includes: The Slave device employs an ultra-low power design, combined with a low-power timer and wake-up mechanism, to maximize the device's battery life while ensuring communication performance. The ultra-low power design includes the use of low-power components and optimized circuit layout.

8. A loop bus communication device, characterized in that, The device includes: The parameter setting and initialization module is used to determine basic parameters by setting the threshold of the current pulse signal, setting the representation method of the return code data, and defining the standard for high voltage and low voltage pulse widths, and to initialize and configure the Master device and Slave device according to the basic parameters. The full-duplex data communication module is used to send downlink data by modifying the duty cycle of the low voltage pulse using the Master device, and to indicate the return code status by using the duty cycle of the high level pulse. The Slave device receives and parses the data, and sends out the return code data by changing the bus current. The address conflict detection and processing module is used to determine whether there is an address conflict when multiple Slave devices return codes simultaneously. The Master device detects the magnitude and timing relationship of the return code current according to a preset threshold. When an address conflict exists, the Master device automatically triggers an address reallocation process to allocate a new unique address to the conflicting device. The dynamic adjustment and low-power control module is used to control the Slave device to wake up and work only when it receives a communication request from the Master device using a low-power timer. It dynamically adjusts the transmission parameters by monitoring the bus signal quality and dynamically adjusts the transmission rate according to the actual communication distance and environmental conditions.

9. An electronic device, characterized in that, include: At least one processor and at least one memory, wherein, The memory stores computer-readable instructions; The computer-readable instructions are executed by one or more of the processors, causing the electronic device to implement the loop bus communication method as described in any one of claims 1 to 7.

10. A storage medium having computer-readable instructions stored thereon, characterized in that, The computer-readable instructions are executed by one or more processors to implement the loop bus communication method as described in any one of claims 1 to 7.

Images