Packaging structure of double-sided heat dissipation module with high heat dissipation and low parasitic inductance and manufacturing method thereof

Abstract

The invention discloses a packaging structure of a double-sided heat dissipation module with high heat dissipation and low parasitic inductance and a manufacturing method of the packaging structure. Comprising a bottom layer power chip and a top layer power chip which are arranged in an interlayer staggered manner; the middle layer PCB of the multi-layer PCB provided with the metal through holes is adopted; a middle-layer cushion block is correspondingly embedded in each metal via hole, the middle-layer cushion blocks are electrically connected with the inner walls of the via holes, the upper ends of the middle-layer cushion blocks are electrically connected with the top-layer DBC substrate or the power chip, and the lower ends of the middle-layer cushion blocks are electrically connected with the bottom-layer DBC substrate or the power chip, so that a power circuit is formed; a drain electrode of each power chip is electrically connected with the DBC substrate where the power chip is located, a source electrode of each power chip is electrically connected with a middle layer cushion block corresponding to the power chip, each bridge arm of the power loop comprises a bottom layer power chip and a top layer power chip, and the two power chips are adjacent in the horizontal direction. According to the invention, the parasitic inductance can be obviously reduced, and the advantages of low coupling thermal resistance, uniform heat distribution, low thermal stress concentration and the like are realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a packaging structure of a double-sided heat dissipation module with high heat dissipation and low parasitic inductance and a manufacturing method thereof. BACKGROUND

[0002] Power semiconductor devices, as the core components of power electronic converters, are widely used in new energy system inverters, battery management, electric drive systems, and industrial control fields. With the popularization of third-generation semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN), the switching frequency and power density of power chips have been significantly improved, but the high-power operation also brings greater heat accumulation and parasitic inductance problems. Therefore, people have proposed double-sided (double DBC) heat dissipation structure modules with better heat dissipation capacity than traditional single-sided (single DBC) heat dissipation modules. However, the traditional double-sided heat dissipation power module has a long commutation path, resulting in large parasitic inductance and unbalanced current sharing, which seriously affects the reliability and performance of the device. Moreover, the chips distributed on the same side in the existing double-sided module technology have serious thermal coupling, and the unreasonable structure layout design causes unbalanced current sharing, and the parasitic inductance needs to be further reduced, which is difficult to meet the needs of high-power density scenarios. Therefore, there is an urgent need for a low-parasitic inductance, high-heat dissipation, and small-sized power packaging structure to solve the problem. SUMMARY

[0003] In order to solve the problems in the background art, the present application provides a packaging structure of a double-sided heat dissipation module with high heat dissipation and low parasitic inductance and a manufacturing method thereof, to realize the improvement of the layout structure of the double-sided heat dissipation module, so that the module has lower parasitic inductance, and the thermal coupling between chips is improved through structure, to achieve the technical purpose of improving the heat dissipation capacity of the module.

[0004] The technical scheme adopted by the present application is as follows: One, a packaging structure of a double-sided heat dissipation module with high heat dissipation and low parasitic inductance The packaging structure comprises a bottom DBC substrate, an intermediate layer PCB board, a top DBC substrate, a bottom power chip, a top power chip, and a plurality of intermediate layer spacers.

[0005] The bottom DBC substrate and the top DBC substrate are respectively attached with the bottom power chip and the top power chip on the opposite surfaces thereof, and the bottom power chip and the top power chip are arranged in an interlayer staggered manner.

[0006] The intermediate layer PCB board is arranged between the bottom DBC substrate and the top DBC substrate, and the intermediate layer PCB board adopts a multi-layer PCB board structure with a plurality of metal vias.

[0007] An intermediate layer pad is embedded in each metal via hole, the intermediate layer pad is electrically connected with the inner wall of the via hole, the upper end of the intermediate layer pad is electrically connected with the top DBC substrate or the top power chip, and the lower end is electrically connected with the bottom DBC substrate or the bottom power chip, thereby forming a power circuit, each bridge arm of the power circuit includes a bottom power chip and a top power chip, the two power chips are connected in parallel and adjacent in the horizontal direction.

[0008] In the power circuit, the drain of each power chip is electrically connected with the DBC substrate, and the source of each power chip is electrically connected with the corresponding intermediate layer pad, so that the vertical current paths formed in the intermediate layer pads corresponding to the two power chips adjacent in the horizontal direction have opposite current flow directions.

[0009] The multi-layer PCB structure of the intermediate layer PCB includes a plurality of circuit layers arranged in sequence in the thickness direction, the circuit layers are electrically isolated, each circuit layer is divided into a plurality of conductive regions insulated from each other, the metal via hole in the same conductive region and the intermediate layer pad in the metal via hole are electrically connected, forming a current path in the horizontal direction; the two circuit layers adjacent in the thickness direction have different conductive region distributions, so that the current paths in the two circuit layers have opposite or staggered current flow directions, thereby reducing the parasitic inductance of the module by enhancing the mutual inductance cancellation effect.

[0010] Preferably, the bottom power chip includes a bottom upper bridge chip and a bottom lower bridge chip; the top power chip includes a top upper bridge chip and a top lower bridge chip; the bottom upper bridge chip, the top upper bridge chip, the bottom lower bridge chip, and the top lower bridge chip are arranged side by side in sequence; the conductive copper layer on the top surface of the bottom DBC substrate is divided into a first upper copper layer, a second upper copper layer, and a third upper copper layer; the conductive copper layer on the bottom surface of the top DBC substrate includes a first lower copper layer, a second lower copper layer, a third lower copper layer, and a fourth lower copper layer arranged in parallel and side by side in the horizontal direction; the first upper copper layer is electrically connected with the source of the top lower bridge chip, the third lower copper layer, respectively; the second upper copper layer is electrically connected with the drain of the bottom lower bridge chip, the source of the top upper bridge chip, the first lower copper layer, the fourth lower copper layer, and an external load device, respectively; the third upper copper layer is electrically connected with the drain of the bottom upper bridge chip, the second lower copper layer; the first lower copper layer is electrically connected with the source of the bottom upper bridge chip; the second lower copper layer is electrically connected with the drain of the top upper bridge chip; the third lower copper layer is electrically connected with the source of the bottom lower bridge chip; and the fourth lower copper layer is electrically connected with the drain of the top lower bridge chip.

[0011] Preferably, the packaging structure includes eight metal vias and eight intermediate layer pads, which are designated as pad 1 to pad 8. The lower end of pad 1 is electrically connected to the third upper copper layer of the bottom DBC substrate, and the upper end is electrically connected to the second lower copper layer of the top DBC substrate; the lower end of pad 2 is electrically connected to the second upper copper layer of the bottom DBC substrate, and the upper end is electrically connected to the first lower copper layer of the top DBC substrate; the lower end of pad 3 is electrically connected to the source of the bottom upper bridge chip, and the upper end is electrically connected to the first lower copper layer of the top DBC substrate; the lower end of pad 4 is electrically connected to the second upper copper layer of the bottom DBC substrate, and the upper end is electrically connected to the source of the top upper bridge chip. The lower end of the fifth pad is electrically connected to the source of the bottom-layer bridge chip, and the upper end is electrically connected to the third lower copper layer of the top-layer DBC substrate; the lower end of the sixth pad is electrically connected to the first upper copper layer of the bottom-layer DBC substrate, and the upper end is electrically connected to the source of the top-layer bridge chip; the lower end of the seventh pad is electrically connected to the second upper copper layer of the bottom-layer DBC substrate, and the upper end is electrically connected to the fourth lower copper layer of the top-layer DBC substrate; the lower end of the eighth pad is electrically connected to the first upper copper layer of the bottom-layer DBC substrate, and the upper end is electrically connected to the third lower copper layer of the top-layer DBC substrate.

[0012] Preferably, the intermediate PCB board includes an even number of circuit layers, each circuit layer having two different conductive area distribution patterns arranged alternately along the thickness direction; the two conductive area distribution patterns are a first conductive area distribution pattern and a second conductive area distribution pattern; the first conductive area distribution pattern is divided into a first DC positive electrode region, a first AC output region, and a first DC negative electrode region, the first DC positive electrode region being electrically connected to a first pad, the first AC output region being electrically connected to a second pad, a third pad, and a seventh pad, and the first DC negative electrode region being electrically connected to a fifth pad, a sixth pad, and an eighth pad; in the outermost circuit layer, the first DC positive electrode region is electrically connected to the positive terminal of the DC power supply; the second conductive area distribution pattern is divided into a second AC output region and a second DC negative electrode region, the second AC output region being electrically connected to a second pad, a third pad, and a fourth pad; the second DC negative electrode region is electrically connected to a fifth pad, a sixth pad, and an eighth pad; in the outermost circuit layer, the second DC negative electrode region is electrically connected to the negative terminal of the DC power supply.

[0013] Preferably, the cross-section of the metal via is rectangular or square, and the inner wall of the via is a copper layer.

[0014] II. A method for fabricating the packaging structure of the above-mentioned double-sided heat dissipation module with high heat dissipation and low parasitic inductance. The preparation method includes the following steps: Step S1) Use nano silver solder paste to burn the intermediate layer pad.

[0015] In step S1, the firing is carried out under the following conditions: sintering temperature: 180~250℃; pressureless sintering; holding time: 10~30min.

[0016] Step S2) First sintering: Use nano silver solder paste to mount the bottom power chip and the top power chip onto the top surface of the bottom DBC substrate and the bottom surface of the top DBC substrate, respectively.

[0017] Step S3) Second sintering: Use nano silver solder paste to attach each intermediate layer pad onto the bottom DBC substrate.

[0018] Step S4) Third sintering: Use nano silver solder paste to connect the intermediate layer PCB board to each intermediate layer pad, and connect the intermediate layer pad to the top layer DBC substrate.

[0019] In steps S2 to S4, the sintering process parameters are: sintering temperature: 220~250℃; sintering pressure: 0~10MPa; holding time: 10~30min; coating thickness: 60~120μm.

[0020] In step S4, pressureless sintering is used to connect the intermediate layer PCB board and each intermediate layer pad, and pressure-assisted sintering is used to connect the intermediate layer pad and the top layer DBC substrate. The sintering pressure is 2~10MPa.

[0021] The beneficial effects of this invention are: 1. Significantly reduce parasitic inductance: The structure proposed in this invention, through module layout settings and the introduction of intermediate layers in the PCB, respectively realizes current paths with opposite current flows for two adjacent chips in the vertical direction and current paths with opposite or intersecting current flows for two adjacent circuit layers in the horizontal direction. Both enhance the mutual inductance cancellation effect and significantly reduce the overall parasitic inductance of the module.

[0022] 2. Low coupling thermal resistance and uniform heat distribution: The structure proposed in this invention allows the chips to be flipped and arranged, with adjacent chips mounted on the upper and lower DBC substrates respectively, significantly improving the thermal coupling between chips. This achieves low coupling thermal resistance and uniform heat distribution.

[0023] 3. Low thermal stress concentration: The sintered silver pad used in this invention eliminates the CTE mismatch between the sintered layer and the pad, effectively reducing the thermal stress concentration between the pad and the sintered layer. Attached Figure Description

[0024] Figure 1 This is the circuit diagram of a half-bridge power module; Figure 2 Exploded view of the modular assembly structure; Figure 3 The following is a schematic diagram of the DBC substrate structure; Figure 4 This is a schematic diagram of the upper DBC substrate structure; Figure 5 This is a diagram showing the circuit structure and current path of each layer of the intermediate PCB. Figure 6 These are the opposite current paths of adjacent chips in the vertical direction; Figure 7 Layout the heat transfer path for chip flipping.

[0025] Figure 8 Exploded view of the DC terminal and busbar connection structure; Figure 9 The diagrams are schematic diagrams of each step in the dynamic and static testing process; (a) is a three-dimensional structural model, (b) is a schematic diagram in ANSYS Q3D software, (c) is a schematic diagram of setting the DC excitation source, (d) is a schematic diagram of setting the DC excitation sink, and (e) is a schematic diagram of mesh generation. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] This invention provides a packaging structure for a double-sided heat dissipation module with high heat dissipation and low parasitic inductance. The double-sided heat dissipation module refers to a packaging structure that sandwiches a power semiconductor chip between two thermally conductive insulating substrates, simultaneously establishing heat dissipation paths on both the front and back sides of the chip. This structure allows the heat generated by the chip during operation to be conducted parallel to the external cooling system via the upper and lower surfaces, achieving higher heat dissipation efficiency per unit volume.

[0028] like Figures 2-4 As shown, the packaging structure includes a bottom DBC substrate 1, a bottom power chip, an intermediate PCB board 3, a top DBC substrate 2, a top power chip, and several intermediate pads 4.

[0029] Specifically, the bottom DBC substrate 1 and the top DBC substrate 2 are arranged at intervals relative to each other, and conductive copper layers are provided on their respective surfaces. At least one bottom power chip and at least one top power chip are respectively mounted on them. The bottom power chip and the top power chip are arranged in a staggered manner in three-dimensional space. Adjacent chips are respectively mounted on the top and bottom DBC substrates, thereby improving the thermal coupling between chips.

[0030] Specifically, an intermediate layer PCB board 3 is arranged between the bottom DBC substrate 1 and the top DBC substrate 2. The intermediate layer PCB board 3 adopts a multilayer PCB board structure with several metal vias. An intermediate layer pad 4 is embedded in each metal via. The intermediate layer pad 4 is electrically connected to the inner wall of the via. The intermediate layer pad 4 is conductive. Its upper end is electrically connected to the conductive copper layer or the top power chip on the top DBC substrate 2, and its lower end is electrically connected to the conductive copper layer or the bottom power chip on the bottom DBC substrate 1, thereby forming a power circuit.

[0031] likeFigure 6 As shown, each arm of the power circuit includes a bottom power chip and a top power chip, which are electrically connected in parallel and adjacent in the horizontal direction. For each bottom and top power chip in the package structure, the drain on the back of each power chip is electrically connected to the conductive copper layer on the DBC substrate, and the source on the front of each power chip is electrically connected to a corresponding intermediate layer pad 4. This ensures that the vertical current paths formed in the intermediate layer pads 4 corresponding to two adjacent power chips in the horizontal direction have opposite current flows. This arrangement enhances the mutual inductance cancellation effect, thereby reducing the parasitic inductance of the module.

[0032] Specifically, the power chip and the DBC substrate, the intermediate layer pad 4 and the power chip, the DBC substrate and the intermediate layer pad 4, and the intermediate layer pad 4 and the metal vias on the intermediate layer PCB are all connected by sintered nano-silver.

[0033] Preferably, the coating thickness of the sintered nano-silver is 60~120μm.

[0034] like Figure 5 As shown, the multilayer PCB structure of the intermediate layer PCB board 3 includes multiple circuit layers arranged sequentially along the thickness (vertical) direction, with electrical isolation between each circuit layer achieved through an insulating layer. Each circuit layer is divided into multiple mutually insulated conductive regions. Metal vias within the same conductive region and intermediate layer pads 4 within the metal vias are electrically connected, forming a current path in the horizontal direction. Two adjacent circuit layers in the thickness (vertical) direction have different conductive region distributions, causing some current paths in the two circuit layers to have opposite or interleaved current flows, thereby reducing the parasitic inductance of the module by enhancing the mutual inductance cancellation effect.

[0035] In practical implementation, the power circuit can be a half-bridge power circuit, which includes two upper-bridge chips and two lower-bridge chips. The circuit topology is shown in the figure below. Figure 1 As shown in the diagram. In the package structure, the bottom power chip includes a bottom upper bridge chip M1 and a bottom lower bridge chip M3; the top power chip includes a top upper bridge chip M2 and a top lower bridge chip M4. In horizontal projection, the bottom upper bridge chip M1, the top upper bridge chip M2, the bottom lower bridge chip M3, and the top lower bridge chip M4 are arranged in parallel side by side. The conductive copper layer on the top surface of the bottom DBC substrate 1 is the upper copper layer, which is divided into a first upper copper layer 11, a second upper copper layer 12, and a third upper copper layer 13 that are electrically isolated from each other. The conductive copper layer on the bottom surface of the top DBC substrate 2 is the lower copper layer, which includes a first lower copper layer 21, a second lower copper layer 22, a third lower copper layer 23, and a fourth lower copper layer 24 that are electrically isolated from each other and arranged in parallel side by side in the horizontal direction.

[0036] In the above specific embodiments, the first upper copper layer 11 is electrically connected to the source of the top-level lower bridge chip M4 and the third lower copper layer 23, respectively; the second upper copper layer 12 is electrically connected to the drain of the bottom-level lower bridge chip M3, the source of the top-level upper bridge chip M2, the first lower copper layer 21, the fourth lower copper layer 24 and the external load device, respectively; the third upper copper layer 13 is electrically connected to the drain of the bottom-level upper bridge chip M1 and the second lower copper layer 22; the first lower copper layer 21 is electrically connected to the source of the bottom-level upper bridge chip M1, the second lower copper layer 22 is electrically connected to the drain of the top-level upper bridge chip M2, and the fourth lower copper layer 24 is electrically connected to the drain of the top-level lower bridge chip M4.

[0037] In the above specific embodiment, the packaging structure includes eight metal vias and eight intermediate layer pads 4. The eight metal vias are identified as first metal vias 301 to eighth metal vias 308, and the eight intermediate layer pads 4 are identified as first pads 401 to eighth pads 408. The lower end of the first pad 401 is electrically connected to the third upper copper layer 13 of the bottom DBC substrate 1, and the upper end is electrically connected to the second lower copper layer 22 of the top DBC substrate 2. The lower end of the second pad 402 is electrically connected to the second upper copper layer 12 of the bottom DBC substrate 1, and the upper end is electrically connected to the first lower copper layer 21 of the top DBC substrate 2. The lower end of the third pad 403 is electrically connected to the source of the bottom bridge chip M1, and the upper end is electrically connected to the first lower copper layer 21 of the top DBC substrate 2. The lower end of the fourth pad 404 is electrically connected to the second upper copper layer 12 of the bottom DBC substrate 1, and the upper end is electrically connected to the source of the top bridge chip M2. The lower end of the fifth pad 405 is electrically connected to the source of the bottom bridge chip M3, and the upper end is electrically connected to the third lower copper layer 23 of the top DBC substrate 2. The lower end of the sixth pad 406 is electrically connected to the first upper copper layer 11 of the bottom DBC substrate 1, and the upper end is electrically connected to the source of the top lower bridge chip M4. The lower end of the seventh pad 407 is electrically connected to the second upper copper layer 12 of the bottom DBC substrate 1, and the upper end is electrically connected to the fourth lower copper layer 24 of the top DBC substrate 2. The lower end of the eighth pad 408 is electrically connected to the first upper copper layer 11 of the bottom DBC substrate 1, and the upper end is electrically connected to the third lower copper layer 23 of the top DBC substrate 2.

[0038] Specifically, the intermediate layer PCB board 3 includes an even number of circuit layers, each circuit layer is arranged alternately along the thickness direction with two different conductive area distribution patterns; the two conductive area distribution patterns are the first conductive area distribution pattern and the second conductive area distribution pattern.

[0039] Preferably, the first conductive area distribution pattern is divided into a first DC positive electrode area, a first AC output area, and a first DC negative electrode area. The first DC positive electrode area is electrically connected to the first pad 401, the first AC output area is electrically connected to the second pad 402, the third pad 403, and the seventh pad 407, and the first DC negative electrode area is electrically connected to the fifth pad 405, the sixth pad 406, and the eighth pad 408. In the outermost circuit layer, the first DC positive electrode area is electrically connected to the positive electrode of the DC power supply.

[0040] Preferably, the second conductive area distribution pattern is divided into a second AC output area and a second DC negative area. The second AC output area is electrically connected to the second pad 402, the third pad 403, and the fourth pad 404, respectively. The second DC negative area is electrically connected to the fifth pad 405, the sixth pad 406, and the eighth pad 408, respectively. In the outermost circuit layer, the second DC negative area is electrically connected to the negative terminal of the DC power supply.

[0041] In a specific embodiment of the present invention, the intermediate layer PCB board 3 includes four circuit layers, which are the first to fourth circuit layers from top to bottom. The conductive area distribution pattern of each circuit layer is as follows: Figure 5 As shown: The first circuit layer and the third circuit layer adopt a first conductive area distribution pattern. In the first circuit layer, the first DC positive electrode area is electrically connected to the positive electrode of the DC power supply. The second and fourth circuit layers adopt a second conductive area distribution pattern. In the fourth circuit layer, the second DC negative electrode area is electrically connected to the negative electrode of the DC power supply.

[0042] Furthermore, the packaging structure also includes a DC positive terminal 5 and a DC negative terminal 6; a circular non-metallized hole is provided on one side of the intermediate layer PCB board 3, and the DC positive terminal 5 and the DC negative terminal 6 are respectively provided on the upper and lower sides of the non-metallized hole; the DC positive terminal 5 is electrically connected to the first DC positive region of the top layer circuit layer through the DC positive pad 501; the DC negative terminal 6 is electrically connected to the second DC negative region of the bottom layer circuit layer through the DC negative pad 601; the DC positive terminal 5 and the DC negative terminal 6 form a PCB stacked DC terminal structure, which is electrically connected to the external power supply equipment through the DC bus connection structure.

[0043] Specifically, such as Figure 8 As shown, the DC busbar connection structure includes an insulating screw 9, an insulating washer 10, a DC positive busbar 11, a DC negative busbar 12, and an insulating nut 13. All components are connected by bolt crimping.

[0044] Furthermore, the package structure also includes an AC terminal 7, which is electrically connected to the second upper copper layer 12 for electrical connection with an external load device.

[0045] Furthermore, the packaging structure also includes control terminals 8. Multiple control terminals 8 are provided on both the bottom DBC substrate 1 and the top DBC substrate 2. The control terminals 8 are electrically connected to the gate and source of the corresponding power chip by wire bonding, for electrical connection with external driving devices.

[0046] Preferably, the cross-section of the metal via is rectangular or square, and the inner wall of the via is a copper layer.

[0047] This invention also provides a method for fabricating a packaging structure for a double-sided heat dissipation module with high heat dissipation and low parasitic inductance, comprising the following steps: Step S1) Use nano silver solder paste to burn the intermediate layer pad 4.

[0048] Preferably, after slotting the graphite mold, nano-silver paste is extruded. The slot width is equal to the height of the pad, and the slot depth depends on the width of the pad. After firing, the sintered silver pad is cut to the required size according to the length of the pad. The nano-silver paste is selected from nano-silver paste with a multi-peak particle size distribution. Its conductive phase is composed of silver particles with a particle size range of 50nm to 7μm, so as to achieve low-temperature dense sintering through the gradation of nano- and micro-sized particles.

[0049] Preferably, the intermediate layer pad 4 is fired at a sintering temperature of 180~250℃, under pressureless sintering conditions, and with a holding time of 10~30min.

[0050] Step S2) First sintering: Use nano silver solder paste to mount the bottom power chip and the top power chip onto the top surface of the bottom DBC substrate 1 and the bottom surface of the top DBC substrate 2, respectively.

[0051] Step S3) Second sintering: Use nano silver solder paste to attach each intermediate layer pad 4 onto the bottom DBC substrate 1.

[0052] Step S4) Third sintering: Use nano silver solder paste to connect the intermediate layer PCB board 3 to each intermediate layer pad 4, and connect the intermediate layer pad 4 to the top layer DBC substrate 2.

[0053] Preferably, in steps S2 to S4, the sintering process parameters are: sintering temperature: 220~250℃; sintering pressure: 0~10MPa; holding time: 10~30min; and coating thickness: 60~120μm.

[0054] Preferably, pressureless sintering is used to connect the intermediate layer PCB board 3 to each intermediate layer pad 4, and pressure-assisted sintering is used to connect the intermediate layer pad 4 to the top layer DBC substrate 2, with a sintering pressure of 2~10MPa. This is because the porous structure of the sintered silver pad makes it prone to deformation during pressure-assisted sintering. In the third sintering, appropriate pressure should be applied during the sintering of the pad and the top layer DBC substrate, and the slight deformation of the sintered silver pad is used to reliably connect the pad to the square metal via.

[0055] Preferably, the component connection sintering uses silver solder paste with silver particles having a particle size of 50~200nm.

[0056] Specific embodiments of the present invention are as follows: Example This embodiment provides a packaging structure for a half-bridge power module with overall dimensions of 24×24.5×3.82 mm. The packaging structure includes: a bottom DBC substrate 1, a top DBC substrate 2, an intermediate PCB board 3, an intermediate pad 4, and a power chip mounted on the bottom DBC substrate 1 or the top DBC substrate 2.

[0057] The circuit diagram and exploded view of the specific structure assembly of the half-bridge power module are as follows: Figure 1 and Figure 2 As shown. The power chip includes two parallel-connected upper-bridge MOSFET chips M1 and M2, and two parallel-connected lower-bridge MOSFET chips M3 and M4. The copper layers on the bottom DBC substrate 1 include a first upper copper layer 11, a second upper copper layer 12, and a third upper copper layer 13. The copper layers on the top DBC substrate 2 include a first lower copper layer 21, a second lower copper layer 22, a third lower copper layer 23, and a fourth lower copper layer 24.

[0058] The drains of the upper-bridge MOSFET chips M1 and M2 are connected to the third upper copper layer 13 and the second lower copper layer 22, respectively. The drains of the lower-bridge MOSFET chips M3 and M4 are connected to the second upper copper layer 12 and the fourth lower copper layer 24, respectively.

[0059] Among them, the DC positive terminal 5 and the DC negative terminal 6 are located on the upper and lower sides of the circular non-metallized hole of the intermediate layer PCB board 3, respectively; the AC terminal 7 is located on the second upper copper layer 12; and the control terminal 8 is located on the bottom DBC substrate 1 and the top DBC substrate 2.

[0060] In this embodiment, the shapes of the upper and lower DBC copper layers, the pads, and the specific placement of the chip are as follows: Figure 2 , 3 As shown. With this layout, the chips are flipped so that adjacent chips in the vertical direction form current paths with opposite current flows, as... Figure 6As shown, the mutual inductance cancellation effect is enhanced, thereby reducing the module's parasitic inductance. Simultaneously, adjacent chips are mounted on the upper and lower DBC substrates respectively, improving inter-chip thermal coupling, as shown... Figure 7 As shown.

[0061] In this embodiment, the intermediate layer PCB board 3 is electrically connected to the side of the pad block through square metal vias. The intermediate layer PCB board is a four-layer PCB, and the circuit layer structure of each layer is as follows: Figure 5 The diagram shows the connections between the numbered square metal vias and their corresponding pads. The square metal vias (301, 302, 303, 304, 305, 306, 307, 308) correspond to the pads (401, 402, 403, 404, 405, 406, 407, 408), respectively. The circular non-metallized vias have openings on their upper and lower pads (501, 601) corresponding to the DC positive terminal 5 and the DC negative terminal 6, respectively. Different circuit layers are also electrically connected via these square metal vias. The PCB layer structure design shortens the current loop path, and adjacent horizontal circuit layers form current paths with opposite or intersecting current flows, enhancing mutual inductance cancellation and reducing the module's parasitic inductance.

[0062] In terms of the assembly and connection process of the module components, the power chip and the DBC substrate, the intermediate layer pad and the power chip, the DBC substrate and the intermediate layer pad, and the intermediate layer pad and the intermediate layer PCB are all connected by sintered nano-silver. The AC terminal 7 and the control terminal 8 are ultrasonically soldered to the DBC substrate, and the chip gate and source are led out to the control terminal 8 through aluminum bonding wires.

[0063] In this embodiment, sintered silver is specifically used as the pad material. Nano-silver paste is extruded into the graphite mold after grooving. The groove width is 1.7mm above the pad height, and the groove depth depends on the pad width of 2.9mm. After sintering, the sintered silver pads are cut to the required size according to the pad length of 2.9mm. The nano-silver sintering process parameters are: sintering temperature: 240℃; pressureless sintering; holding time: 15min. A high-temperature resistant polyimide PCB board is selected, with a temperature resistance up to 280℃.

[0064] In this embodiment, a milling process is used to custom-process a square metal via with a via size of 3.1×3.1mm. Space is left between the pad and the square metal via of the intermediate PCB board for the application of nano silver solder paste.

[0065] The module assembly and connection sintering process consists of three sintering processes in a strictly sequential order: The first sintering process involves sintering the bottom and top DBC substrates with the chip. The second sintering process involves sintering the intermediate layer pad 8 with the bottom DBC substrate 1. The third sintering process involves pressureless sintering of the intermediate layer pad 8 and the intermediate layer PCB board 3, and sintering of the intermediate layer pad and the top layer DBC substrate 2.

[0066] Specifically, due to the porous structure of the sintered silver pad, it is prone to deformation during pressure-assisted sintering. In the third sintering process, a pressure of 2 MPa is applied between the pad and the top-layer DBC substrate. This slight deformation of the sintered silver pad ensures a reliable connection between the pad and the square metal via. The component connection sintering uses silver solder paste with silver particles of 50 nm in diameter. The sintering process parameters are: sintering temperature: 245℃; sintering pressure: 2 MPa (with the intermediate layer pad 8 and intermediate layer PCB board 3 being pressureless sintering in the third sintering); holding time: 15 min.

[0067] After the module is assembled, extract the parasitic inductance of the module's power loop according to the following process: Use Solidworks modules to build a three-dimensional structural model of the package structure ( Figure 9 (a) is imported into ANSYS Q3D software. Figure 9 (b) ), set DC excitation source ( Figure 9 (c) ), Sink ( Figure 9 (d)), perform mesh generation ( Figure 9 (e) is used to solve the module parasitic inductance at a frequency of 20MHz.

[0068] The results show that the parasitic inductance of the module's power loop is as low as 1.47nH.

[0069] The above specific embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

[0070] The above description is only a preferred embodiment of the present invention. Therefore, all equivalent changes or modifications made to the structure, features and principles described in the claims of this patent application are included in the scope of this patent application.

Claims

1. A packaging structure for a double-sided heat dissipation module with high heat dissipation and low parasitic inductance, characterized in that: The packaging structure includes a bottom DBC substrate (1), an intermediate PCB board (3), a top DBC substrate (2), a bottom power chip, a top power chip, and several intermediate pads (4). The bottom DBC substrate (1) and the top DBC substrate (2) are respectively mounted on their opposing surfaces, and the bottom power chip and the top power chip are arranged in a staggered interlayer configuration. The intermediate layer PCB board (3) is arranged between the bottom DBC substrate (1) and the top DBC substrate (2). The intermediate layer PCB board (3) adopts a multilayer PCB board structure with a number of metal vias. Each metal via is fitted with an intermediate layer pad (4). The intermediate layer pad (4) is electrically connected to the inner wall of the via. The upper end of the intermediate layer pad (4) is electrically connected to the top DBC substrate (2) or the top power chip, and the lower end is electrically connected to the bottom DBC substrate (1) or the bottom power chip, thereby forming a power circuit. Each bridge arm of the power circuit includes a bottom power chip and a top power chip. The two power chips are connected in parallel and are adjacent in the horizontal direction. In the power circuit, the drain of each power chip is electrically connected to the DBC substrate, and the source of each power chip is electrically connected to a corresponding intermediate layer pad (4).

2. The packaging structure of the double-sided heat dissipation module with high heat dissipation and low parasitic inductance according to claim 1, characterized in that: The multilayer PCB structure of the intermediate layer PCB board (3) includes multiple circuit layers arranged sequentially along the thickness direction. Each circuit layer is electrically isolated from the others. Each circuit layer is divided into multiple mutually insulated conductive areas. The metal vias in the same conductive area and the intermediate layer pads (4) in the metal vias are electrically connected to form a current path in the horizontal direction. Two adjacent circuit layers in the thickness direction have different conductive regions, which makes the current paths in the two circuit layers have opposite or intersecting current flows.

3. The packaging structure of the double-sided heat dissipation module with high heat dissipation and low parasitic inductance according to claim 1, characterized in that: The bottom power chip includes a bottom upper bridge chip (M1) and a bottom lower bridge chip (M3); the top power chip includes a top upper bridge chip (M2) and a top lower bridge chip (M4); the bottom upper bridge chip (M1), the top upper bridge chip (M2), the bottom lower bridge chip (M3), and the top lower bridge chip (M4) are arranged side by side in sequence; The conductive copper layer on the top surface of the bottom DBC substrate (1) is divided into a first upper copper layer (11), a second upper copper layer (12) and a third upper copper layer (13); the conductive copper layer on the bottom surface of the top DBC substrate (2) includes a first lower copper layer (21), a second lower copper layer (22), a third lower copper layer (23) and a fourth lower copper layer (24) arranged in parallel. The first upper copper layer (11) is electrically connected to the source of the top-level lower bridge chip (M4) and the third lower copper layer (23), respectively; the second upper copper layer (12) is electrically connected to the drain of the bottom lower bridge chip (M3), the source of the top-level upper bridge chip (M2), the first lower copper layer (21), the fourth lower copper layer (24) and the external load device, respectively; the third upper copper layer (13) is electrically connected to the drain of the bottom upper bridge chip (M1) and the second lower copper layer (22); The first lower copper layer (21) is electrically connected to the source of the bottom upper bridge chip (M1), the second lower copper layer (22) is electrically connected to the drain of the top upper bridge chip (M2), the third lower copper layer (23) is electrically connected to the source of the bottom lower bridge chip (M3), and the fourth lower copper layer (24) is electrically connected to the drain of the top lower bridge chip (M4).

4. The packaging structure of the double-sided heat dissipation module with high heat dissipation and low parasitic inductance according to claim 3, characterized in that: The encapsulation structure includes eight metal vias and eight intermediate layer pads (4), the eight intermediate layer pads (4) being the first pad (401) to the eighth pad (408). The lower end of the first pad (401) is electrically connected to the third upper copper layer (13) of the bottom DBC substrate (1), and the upper end is electrically connected to the second lower copper layer (22) of the top DBC substrate (2); the lower end of the second pad (402) is electrically connected to the second upper copper layer (12) of the bottom DBC substrate (1), and the upper end is electrically connected to the first lower copper layer (21) of the top DBC substrate (2); the lower end of the third pad (403) is electrically connected to the source of the bottom upper bridge chip (M1), and the upper end is electrically connected to the first lower copper layer (21) of the top DBC substrate (2); the lower end of the fourth pad (404) is electrically connected to the second upper copper layer (12) of the bottom DBC substrate (1), and the upper end is electrically connected to the source of the top upper bridge chip (M2); The lower end of the fifth pad (405) is electrically connected to the source of the bottom bridge chip (M3), and the upper end is electrically connected to the third lower copper layer (23) of the top DBC substrate (2); the lower end of the sixth pad (406) is electrically connected to the first upper copper layer (11) of the bottom DBC substrate (1), and the upper end is electrically connected to the source of the top bridge chip (M4); the lower end of the seventh pad (407) is electrically connected to the second upper copper layer (12) of the bottom DBC substrate (1), and the upper end is electrically connected to the fourth lower copper layer (24) of the top DBC substrate (2); the lower end of the eighth pad (408) is electrically connected to the first upper copper layer (11) of the bottom DBC substrate (1), and the upper end is electrically connected to the third lower copper layer (23) of the top DBC substrate (2).

5. The packaging structure of the double-sided heat dissipation module with high heat dissipation and low parasitic inductance according to claim 4, characterized in that: The intermediate layer PCB board (3) includes an even number of circuit layers, and each circuit layer is arranged alternately along the thickness direction with two different conductive area distribution patterns; the two conductive area distribution patterns are the first conductive area distribution pattern and the second conductive area distribution pattern, respectively. The first conductive area distribution pattern is divided into a first DC positive pole area, a first AC output area and a first DC negative pole area. The first DC positive pole area is electrically connected to the first pad (401) respectively. The first AC output area is electrically connected to the second pad (402), the third pad (403) and the seventh pad (407) respectively. The first DC negative pole area is electrically connected to the fifth pad (405), the sixth pad (406) and the eighth pad (408). In the outermost circuit layer, the first DC positive pole area is electrically connected to the positive pole of the DC power supply. The second conductive area distribution pattern is divided into a second AC output area and a second DC negative area. The second AC output area is electrically connected to the second pad (402), the third pad (403), and the fourth pad (404), respectively. The second DC negative area is electrically connected to the fifth pad (405), the sixth pad (406), and the eighth pad (408), respectively. In the outermost circuit layer, the second DC negative area is electrically connected to the negative terminal of the DC power supply.

6. The packaging structure of the double-sided heat dissipation module with high heat dissipation and low parasitic inductance according to claim 1, characterized in that: The cross-section of the metal via is rectangular or square, and the inner wall of the via is a copper layer.

7. A method for fabricating a packaging structure of a double-sided heat dissipation module with high heat dissipation and low parasitic inductance as described in any one of claims 1 to 6, characterized in that, Includes the following steps: Step S1) Use nano silver solder paste to burn the intermediate layer pad (4). Step S2) First sintering: Use nano silver solder paste to attach the bottom power chip and the top power chip to the top surface of the bottom DBC substrate (1) and the bottom surface of the top DBC substrate (2), respectively; Step S3) Second sintering: Use nano silver solder paste to attach each intermediate layer pad (4) onto the bottom DBC substrate (1); Step S4) Third sintering: Use nano silver solder paste to connect the intermediate layer PCB board (3) to each intermediate layer pad (4), and connect the intermediate layer pad (4) to the top layer DBC substrate (2).

8. The preparation method according to claim 6, characterized in that: In step S1, the firing is carried out under the following conditions: sintering temperature: 180~250℃; pressureless sintering; holding time: 10~30min.

9. The preparation method according to claim 5, characterized in that: In steps S2 to S4, the sintering process parameters are: sintering temperature: 220~250℃; sintering pressure: 0~10MPa; holding time: 10~30min; coating thickness: 60~120μm.

10. The preparation method according to claim 5, characterized in that: In step S4, pressureless sintering is used to connect the intermediate layer PCB board (3) and each intermediate layer pad (4), and pressure-assisted sintering is used to connect the intermediate layer pad (4) and the top layer DBC substrate (2). The sintering pressure is 2~10MPa.

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