10kV DC test load circuit

Abstract

The invention relates to the technical field of load testing, in particular to a 10kV direct current test load circuit which comprises a first port, a second port, an MOS tube Q1, an MOS tube Q2 and an MOS tube Q3. The first port is connected with the drain electrode of the MOS tube Q1; the source electrode of the MOS tube Q1 is connected with the drain electrode of the MOS tube Q2; the source electrode of the MOS tube Q2 is connected with the drain electrode of the MOS tube Q3; and the source electrode of the MOS tube Q3 is connected with the second port. Through the design of dual voltage sharing, synchronous driving and multiple protection, voltage balance, wide-range accurate current regulation and safe and reliable operation under 10kV high voltage are realized, static and dynamic voltage distribution is uniform, current regulation precision is high, fluctuation is small, and the device is suitable for performance testing of a high-voltage direct-current power supply, a power assembly and the like and is high in practicability.

Description

Technical Field

[0001] This invention relates to the field of load testing technology, and specifically to a 10kV DC test load circuit. Background Technology

[0002] With the rapid development of DC power transmission, high-voltage energy storage, and new energy power generation, the demand for performance testing of 10kV high-voltage DC power supplies, power components, and transmission equipment is becoming increasingly urgent. As a core testing device, the DC test load must possess core characteristics such as high-voltage withstand capability, adjustable current, stable operation, and safety and reliability to simulate load requirements under actual working conditions and verify the voltage withstand capability, stability, and overload capacity of the equipment under test.

[0003] However, existing 10kV DC test load circuits have many technical defects in practical applications, making it difficult to meet the testing requirements of high precision and high reliability. In 10kV high-voltage scenarios, the withstand voltage of a single MOSFET is limited (the withstand voltage of conventional high-voltage MOSFETs is mostly within 5kV), requiring a multi-MOSFET series connection to distribute the voltage. However, due to differences in leakage current (in the off state) and inconsistent switching speeds (during the dynamic process of conduction / turn-off), uneven static or dynamic voltage distribution is prone to occur in the series-connected MOSFETs, causing some MOSFETs to momentarily withstand over-rated voltage and break down, seriously affecting circuit reliability. In addition, traditional multi-MOSFET drives often use independent control signals, and differences in signal delay will exacerbate voltage imbalance. Furthermore, the lack of effective isolation between the low-voltage control terminal and the 10kV high-voltage power terminal results in a high risk of high-voltage crosstalk, which can easily damage the control unit. Summary of the Invention

[0004] The purpose of this invention is to address the aforementioned shortcomings in the prior art by providing a 10kV DC test load circuit.

[0005] The objective of this invention is achieved through the following technical solution: a 10kV DC test load circuit, comprising a first port, a second port, MOSFET Q1, MOSFET Q2, and MOSFET Q3; the first port is connected to the drain of MOSFET Q1; the source of MOSFET Q1 is connected to the drain of MOSFET Q2; the source of MOSFET Q2 is connected to the drain of MOSFET Q3; and the source of MOSFET Q3 is connected to the second port.

[0006] The present invention is further configured such that a resistor R13 is provided between the drain and source of the MOS transistor Q1; a resistor R15 is provided between the drain and source of the MOS transistor Q2; and a resistor R17 is provided between the drain and source of the MOS transistor Q3.

[0007] The present invention is further configured such that the 10kV DC test load circuit also includes a resistor R1; the first port is connected to the drain of the MOS transistor Q1 through the resistor R1.

[0008] The present invention is further configured such that the 10kV DC test load circuit also includes a capacitor C4 and a resistor R14; one end of the capacitor C4 is connected to the drain of the MOSFET Q1; the other end of the capacitor C4 is connected to the source of the MOSFET Q1 through the resistor R14. The 10kV DC test load circuit also includes capacitor C5 and resistor R16; one end of capacitor C5 is connected to the drain of MOSFET Q2; the other end of capacitor C5 is connected to the source of MOSFET Q2 through resistor R16. The 10kV DC test load circuit also includes a capacitor C6 and a resistor R18; one end of the capacitor C6 is connected to the drain of the MOSFET Q3; the other end of the capacitor C6 is connected to the source of the MOSFET Q3 through the resistor R18.

[0009] The present invention is further configured such that the 10kV DC test load circuit also includes a relay K1; the source of the MOS transistor Q3 is connected to the second port after passing through the switching terminal of the relay K1.

[0010] The present invention is further configured such that the 10kV DC test load circuit includes a transistor Q5, a diode D1, a resistor R11, and a resistor R12; the diode D1 is connected in parallel with the control terminal of the relay K1; the collector of the transistor Q5 is connected to the power supply after the control terminal of the relay K1; the emitter of the transistor Q5 is grounded; the base of the transistor Q5 is connected to the resistor R11; and the base of the transistor Q5 is connected to the emitter of the transistor Q5 after the resistor R12.

[0011] The present invention is further configured such that the 10kV DC test load circuit also includes optocoupler U1, optocoupler U2 and optocoupler U3; One end of the control terminal of the optocoupler U1 is connected to the power supply; the other end of the control terminal of the optocoupler U1 is connected to one end of the control terminal of the optocoupler U2; the other end of the control terminal of the optocoupler U2 is connected to one end of the control terminal of the optocoupler U3. One end of the switching terminal of optocoupler U1 is connected to the gate of MOSFET Q1; the other end of the switching terminal of optocoupler U1 is connected to the source of MOSFET Q1; one end of the switching terminal of optocoupler U2 is connected to the gate of MOSFET Q2; the other end of the switching terminal of optocoupler U2 is connected to the source of MOSFET Q2; one end of the switching terminal of optocoupler U3 is connected to the gate of MOSFET Q3; the other end of the switching terminal of optocoupler U3 is connected to the source of MOSFET Q3.

[0012] The present invention is further configured such that the 10kV DC test load circuit includes resistors R3, R5, and R7; one end of the switching terminal of the optocoupler U1 is connected to one end of resistor R3; the other end of resistor R3 is connected to the gate of MOSFET Q1; one end of the switching terminal of the optocoupler U2 is connected to one end of resistor R5; the other end of resistor R5 is connected to the gate of MOSFET Q2; one end of the switching terminal of the optocoupler U3 is connected to one end of resistor R7; the other end of resistor R7 is connected to the gate of MOSFET Q3.

[0013] The present invention is further configured such that the 10kV DC test load circuit also includes a resistor R4 and a capacitor C1; one end of the resistor R3 is connected to the source of the MOSFET Q1 through the resistor R4; the other end of the resistor R3 is connected to the source of the MOSFET Q1 through the capacitor C1. The 10kV DC test load circuit also includes a resistor R6 and a capacitor C2; one end of the resistor R5 is connected to the source of the MOSFET Q2 through the resistor R6; the other end of the resistor R5 is connected to the source of the MOSFET Q2 through the capacitor C2. The 10kV DC test load circuit also includes a resistor R8 and a capacitor C3; one end of the resistor R7 is connected to the source of the MOSFET Q3 through the resistor R8; the other end of the resistor R7 is connected to the source of the MOSFET Q3 through the capacitor C3.

[0014] The present invention is further configured such that the 10kV DC test load circuit includes a transistor Q4, a resistor R9, and a resistor R10; the collector of the transistor Q4 is connected to the other end of the control terminal of the optocoupler U3; the emitter of the transistor Q4 is grounded; the base of the transistor Q4 is connected to the resistor R9; and the base of the transistor Q4 is connected to the emitter of the transistor Q4 through the resistor R10.

[0015] The beneficial effects of this invention are as follows: This invention adopts a simple topology of three MOSFETs connected in series, the auxiliary circuit design is compact, no complex topology is required, and the circuit complexity and failure rate in high voltage scenarios are reduced; in addition, the three optocouplers share the same control signal, realize the synchronous control of the three optocouplers, the difference in drive delay is small, and ensure that the drive signals of the three MOSFETs are without deviation. Attached Figure Description

[0016] The invention will be further illustrated with reference to the accompanying drawings, but the embodiments in the drawings do not constitute any limitation on the invention. For those skilled in the art, other drawings can be obtained based on the following drawings without any creative effort.

[0017] Figure 1 This is the circuit schematic diagram of the present invention; Wherein: 1. First port; 2. Second port. Detailed Implementation

[0018] The present invention will be further described in conjunction with the following embodiments.

[0019] Depend on Figure 1 As can be seen, a 10kV DC test load circuit in this embodiment includes a first port 1, a second port 2, MOSFETs Q1, Q2, and Q3; the first port 1 is connected to the drain of MOSFET Q1; the source of MOSFET Q1 is connected to the drain of MOSFET Q2; the source of MOSFET Q2 is connected to the drain of MOSFET Q3; and the source of MOSFET Q3 is connected to the second port 2.

[0020] Specifically, a 10kV DC power supply is connected to the circuit through the first port 1. The current flows sequentially through the drain of MOSFET Q1, the source of MOSFET Q1, the drain of MOSFET Q2, the source of MOSFET Q2, the drain of MOSFET Q3, and the source of MOSFET Q3, and is finally output through the second port 2, forming a complete main power circuit. During the entire test, MOSFETs Q1, Q2, and Q3 are synchronously turned on or off, jointly bearing the 10kV high voltage and controlling the on and off of the output current.

[0021] In a 10kV high-voltage scenario, the voltage withstand capability of a single MOSFET cannot directly withstand the full voltage. This embodiment adopts a topology of three MOSFETs connected in series, which can evenly distribute the 10kV total voltage across each MOSFET. By utilizing the voltage sharing principle, the voltage withstand capability of a single MOSFET is overcome. At the same time, as a semiconductor switching element, the MOSFET can be controlled by the gate drive signal to control its conduction state, providing a basis for subsequent current regulation and loop control.

[0022] This embodiment solves the core problem of insufficient withstand voltage of a single MOSFET, enabling the circuit to adapt to 10kV high-voltage testing scenarios and preventing a single MOSFET from breaking down due to being subjected to full voltage. In addition, the series structure is simple and reliable, without the additional losses caused by complex topology, ensuring the transmission efficiency of the main power circuit and providing a stable power foundation for subsequent voltage equalization and driving functional modules.

[0023] In this embodiment of a 10kV DC test load circuit, a resistor R13 is provided between the drain and source of MOSFET Q1; a resistor R15 is provided between the drain and source of MOSFET Q2; and a resistor R17 is provided between the drain and source of MOSFET Q3.

[0024] Specifically, when the circuit is in standby mode or when MOSFETs Q1, Q2, and Q3 are turned off, after the 10kV high voltage is connected through the first port 1, a portion of the current will form a branch current through the resistors R13, R15, and R17 connected in parallel across each MOSFET. Since the resistance values ​​of R13, R15, and R17 are the same, the branch currents are the same, which forces the voltages across MOSFETs Q1, Q2, and Q3 to be evenly distributed.

[0025] Because MOSFETs have inherent leakage current when they are off, and the leakage current of different MOSFETs varies slightly, the voltage distribution across each MOSFET would be unbalanced if resistors R13, R15, and R17 were not used. Resistors R13, R15, and R17 act as high-resistance voltage equalization resistors, with resistances much larger than the equivalent resistance of the MOSFETs when they are off. According to the principle of voltage division by parallel resistors, resistors of the same resistance value can make the voltages across them tend to be consistent, thus balancing the voltage imbalance caused by the difference in leakage current.

[0026] This embodiment achieves voltage balance in a static state through the above settings, ensuring that the voltage deviation across MOSFETs Q1, Q2, and Q3 is controlled within the allowable range, thus avoiding MOSFET breakdown due to static voltage imbalance.

[0027] This embodiment provides a 10kV DC test load circuit, which further includes a resistor R1. The first port 1 is connected to the drain of the MOSFET Q1 through the resistor R1. After the 10kV DC power supply is output from the first port 1, it must first pass through the resistor R1 before flowing into the drain of the MOSFET Q1. When an abnormality occurs in the main circuit, causing a sudden increase in current, the voltage across the resistor R1 will increase with the increase in current, thereby limiting the maximum current of the main circuit and preventing current runaway.

[0028] This embodiment provides a 10kV DC test load circuit, which further includes a capacitor C4 and a resistor R14; one end of the capacitor C4 is connected to the drain of the MOSFET Q1; the other end of the capacitor C4 is connected to the source of the MOSFET Q1 through the resistor R14. The 10kV DC test load circuit also includes capacitor C5 and resistor R16; one end of capacitor C5 is connected to the drain of MOSFET Q2; the other end of capacitor C5 is connected to the source of MOSFET Q2 through resistor R16. The 10kV DC test load circuit also includes a capacitor C6 and a resistor R18; one end of the capacitor C6 is connected to the drain of the MOSFET Q3; the other end of the capacitor C6 is connected to the source of the MOSFET Q3 through the resistor R18.

[0029] Specifically, when MOSFETs Q1, Q2, and Q3 receive a turn-off command, the wiring inductance and load inductance in the main circuit will generate induced voltage spikes due to the sudden interruption of current. At this time, the RC series circuit connected in parallel with each MOSFET can respond quickly: capacitors C4, C5, and C6 instantly absorb the energy of the voltage spike, and then the absorbed energy is slowly dissipated through resistors R14, R16, and R18, causing the voltage spike to decay rapidly to a safe range. This prevents the voltage spike from damaging the MOSFETs and solves the risk of overvoltage during turn-off in high-voltage scenarios. In addition, the RC series circuit has a fast response speed, no additional delay, and does not affect the switching characteristics of the MOSFETs, ensuring the accuracy of current regulation. This embodiment provides a 10kV DC test load circuit, which further includes a relay K1; the source of the MOSFET Q3 is connected to the second port 2 via the switching terminal of the relay K1.

[0030] Specifically, even when MOSFETs Q1, Q2, and Q3 are in the off state, there will still be a small leakage current. Under 10kV high voltage, the leakage current will cause safety hazards and additional power consumption. Relay K1, as a mechanical switch, has extremely high insulation resistance when it is disconnected, which can completely cut off the main circuit and eliminate the leakage current flow path from a physical level. Unlike the electronic cutoff characteristics of MOSFETs, it can achieve zero leakage current control.

[0031] When the circuit is in standby mode or when MOSFETs Q1, Q2, and Q3 are off, the switch terminal of relay K1 remains open, disconnecting the connection between the source of MOSFET Q3 and the second port 2, and there is no current path in the main circuit. When the circuit enters the working state, the switch terminal of relay K1 closes, the main circuit is turned on, and the current can be output through the source of MOSFET Q3 - the switch terminal of relay K1 - the second port 2.

[0032] This embodiment provides a 10kV DC test load circuit, which further includes a transistor Q5, a diode D1, a resistor R11, and a resistor R12. The diode D1 is connected in parallel with the control terminal of the relay K1. The collector of the transistor Q5 is connected to the power supply after the control terminal of the relay K1. The emitter of the transistor Q5 is grounded. The base of the transistor Q5 is connected to the resistor R11. The base of the transistor Q5 is connected to the emitter of the transistor Q5 after the resistor R12. Specifically, when the control unit (microcontroller) outputs a high-level control signal, the signal is input to the base of transistor Q5 through resistor R11, transistor Q5 conducts, and the control terminal (coil) of relay K1 is powered. After the control terminal of relay K1 is energized, it drives the switch terminal of relay K1 to close. When the control unit outputs a low level, there is no driving current at the base of transistor Q5, transistor Q5 is cut off, the control terminal of relay K1 is de-energized, and the switch terminal of relay K1 is open. Diode D1 is connected in parallel with the control terminal of relay K1, and when the control terminal (coil) of relay K1 is de-energized, it can provide a freewheeling path for the induced current.

[0033] This embodiment provides a 10kV DC test load circuit, which further includes optocoupler U1, optocoupler U2, and optocoupler U3. One end of the control terminal of the optocoupler U1 is connected to the power supply; the other end of the control terminal of the optocoupler U1 is connected to one end of the control terminal of the optocoupler U2; the other end of the control terminal of the optocoupler U2 is connected to one end of the control terminal of the optocoupler U3. One end of the switching terminal of optocoupler U1 is connected to the gate of MOSFET Q1; the other end of the switching terminal of optocoupler U1 is connected to the source of MOSFET Q1; one end of the switching terminal of optocoupler U2 is connected to the gate of MOSFET Q2; the other end of the switching terminal of optocoupler U2 is connected to the source of MOSFET Q2; one end of the switching terminal of optocoupler U3 is connected to the gate of MOSFET Q3; the other end of the switching terminal of optocoupler U3 is connected to the source of MOSFET Q3.

[0034] Specifically, the control signal controls the conduction and cutoff of optocouplers U1, U2, and U3 through transistor Q4: When the control signal is valid, the control terminal (LED) of optocoupler U1 is energized and illuminates, driving its switching terminal (phototransistor) to conduct. At the same time, the control terminals of optocouplers U2 and U3 are also energized synchronously due to their series connection, and the switching terminals of optocouplers U2 and U3 are synchronously turned on. The three optocouplers output drive signals to the gates of MOSFETs Q1, Q2, and Q3, respectively. When the control signal is invalid, the control terminals of optocouplers U1, U2, and U3 are de-energized, and their switching terminals are synchronously cut off. The gates of MOSFETs Q1, Q2, and Q3 have no drive signal and remain cut off.

[0035] In this embodiment, by connecting the control terminals of optocoupler U1, optocoupler U2, and optocoupler U3 in series, it is ensured that the same control signal can synchronously trigger the three optocouplers, realizing synchronous control of the three optocouplers driven by one signal and avoiding differences in drive signal delay. The optocouplers can isolate the low-voltage control circuit from the 10kV high-voltage power circuit to prevent high voltage from entering the control terminal. At the same time, the optocouplers have a fast switching response speed, ensuring that the turn-on and turn-off times of the three MOSFETs are completely synchronized.

[0036] This embodiment provides a 10kV DC test load circuit, which further includes resistors R3, R5, and R7. One end of the switching terminal of optocoupler U1 is connected to one end of resistor R3; the other end of resistor R3 is connected to the gate of MOSFET Q1; one end of the switching terminal of optocoupler U2 is connected to one end of resistor R5; the other end of resistor R5 is connected to the gate of MOSFET Q2; one end of the switching terminal of optocoupler U3 is connected to one end of resistor R7; the other end of resistor R7 is connected to the gate of MOSFET Q3.

[0037] When the switching terminals of optocouplers U1, U2, and U3 are turned on, the drive current is output from the switching terminals of the optocouplers, and after being limited by resistors R3, R5, and R7 respectively, it flows into the gates of MOSFETs Q1, Q2, and Q3 to provide drive current for the gates; when the optocouplers are turned off, the gate current is released through the subsequent pull-down resistors, and MOSFETs Q1, Q2, and Q3 are turned off.

[0038] This embodiment provides a 10kV DC test load circuit, which further includes a resistor R4 and a capacitor C1; one end of the resistor R3 is connected to the source of the MOSFET Q1 through the resistor R4; the other end of the resistor R3 is connected to the source of the MOSFET Q1 through the capacitor C1. The 10kV DC test load circuit also includes a resistor R6 and a capacitor C2; one end of the resistor R5 is connected to the source of the MOSFET Q2 through the resistor R6; the other end of the resistor R5 is connected to the source of the MOSFET Q2 through the capacitor C2. The 10kV DC test load circuit also includes a resistor R8 and a capacitor C3; one end of the resistor R7 is connected to the source of the MOSFET Q3 through the resistor R8; the other end of the resistor R7 is connected to the source of the MOSFET Q3 through the capacitor C3.

[0039] Specifically, the drive signals output by optocouplers U1, U2, and U3 are passed through resistors R3, R5, and R7, respectively. Part of the current is filtered by capacitors C1, C2, and C3 to remove high-frequency interference, while the other part is pulled down to the source of MOSFETs Q1, Q2, and Q3 through resistors R4, R6, and R8. When there is no drive signal, resistors R4, R6, and R8 provide a reliable grounding path for the gates of MOSFETs Q1, Q2, and Q3, ensuring that the gate voltage is low and each MOSFET is reliably turned off.

[0040] This embodiment provides a 10kV DC test load circuit, which further includes a transistor Q4, a resistor R9, and a resistor R10. The collector of the transistor Q4 is connected to the other end of the control terminal of the optocoupler U3. The emitter of the transistor Q4 is grounded. The base of the transistor Q4 is connected to the resistor R9. The base of the transistor Q4 is connected to the emitter of the transistor Q4 through the resistor R10.

[0041] The control unit (microcontroller) outputs a PWM signal, which is input to the base of transistor Q4 through resistor R9 to adjust the duty cycle of transistor Q4: the larger the duty cycle, the longer the conduction time of transistor Q4, and the larger the average current at the control terminals of optocouplers U1, U2, and U3; the smaller the duty cycle, the shorter the conduction time of transistor Q4, and the smaller the average current at the control terminals of optocouplers U1, U2, and U3. The change in the current at the control terminals of optocouplers U1, U2, and U3 will change the conduction degree of the switching terminals of optocouplers U1, U2, and U3, thereby adjusting the drive voltage of the gates of MOSFETs Q1, Q2, and Q3.

[0042] Transistor Q4 operates in switching mode, and its duty cycle is determined by the PWM signal. By controlling the conduction time of transistor Q4, the current at the control terminals of optocouplers U1, U2, and U3 can be adjusted. The conduction degree of the switching terminals of optocouplers U1, U2, and U3 is positively correlated with the current at their control terminals. The larger the current at the control terminals of optocouplers U1, U2, and U3, the smaller the on-resistance at their switching terminals, and the higher the gate drive voltage of MOSFETs Q1, Q2, and Q3. When MOSFETs Q1, Q2, and Q3 operate in the saturation region, their conduction current is positively correlated with their gate drive voltage, ultimately achieving the purpose of adjusting the output current through the PWM duty cycle. Resistor R9 limits the base current of transistor Q4, and resistor R10 pulls down the base of transistor Q4 to ensure reliable cutoff of transistor Q4 when there is no PWM signal.

[0043] Specifically, the workflow of this embodiment is as follows: System initialization and static preparation: A 10kV DC power supply is connected to port 1. At this time, the control unit does not output a drive signal, and transistors Q4 and Q5 are both in the off state. Relay K1 remains open because its coil is not powered, and the main circuit is not fully connected. MOSFETs Q1, Q2, and Q3 are in the off state because their gates have no drive current. At this time, resistors R13, R15, and R17 begin to operate, using the voltage divider principle of parallel resistors to balance the leakage current differences of each MOSFET, ensuring that the voltage across MOSFETs Q1, Q2, and Q3 is evenly distributed, preventing static voltage imbalance that could lead to MOSFET breakdown.

[0044] Main circuit conduction control: When the system is ready to enter the test state, the control unit outputs a high-level signal to the base of transistor Q5. This signal, after being current-limited by resistor R11, triggers transistor Q5 to conduct. After transistor Q5 conducts, the control terminal (coil) of relay K1 is powered, and the energized coil generates magnetic force to drive the switch terminal to close, thus forming a complete main circuit: 10kV DC power supply - first port 1 - resistor R1 - drain of MOSFET Q1 - source of MOSFET Q1 - drain of MOSFET Q2 - source of MOSFET Q2 - drain of MOSFET Q3 - source of MOSFET Q3 - switch terminal of relay K1 - second port 2 - test load - negative power supply. The diode D1 connected in parallel with the control terminal of relay K1 provides a freewheeling path for the induced current when the coil is de-energized, preventing voltage spikes from damaging transistor Q5.

[0045] Synchronous Drive and Current Regulation: After the main circuit is turned on, the control unit outputs a PWM signal, which is current-limited by resistor R9 and then input to the base of transistor Q4 to adjust the duty cycle of transistor Q4. When transistor Q4 is turned on, the control terminals of optocouplers U1, U2, and U3 form a series current loop (power supply → control terminal of optocoupler U1 - control terminal of optocoupler U2 - control terminal of optocoupler U3 - collector of transistor Q4 - emitter of transistor Q4 - ground), and the three optocouplers are synchronously turned on; when transistor Q4 is turned off, there is no current at the control terminals of optocouplers U1, U2, and U3, and they are synchronously turned off. After the switching terminals of optocouplers U1, U2, and U3 are turned on, the drive current flows through resistors R3, R5, and R7 into the gates of MOSFETs Q1, Q2, and Q3 respectively, causing the three MOSFETs to be synchronously saturated and turned on. Meanwhile, resistors R4, R6, and R8 in the gate circuit, along with capacitors C1, C2, and C3, filter out high-frequency noise in the drive signal, ensuring a stable gate voltage and clamping the gate to a low level when there is no drive signal, guaranteeing reliable cutoff of the three MOSFETs. By adjusting the PWM duty cycle of transistor Q4, the average current at the optocoupler control terminal can be changed, thereby adjusting the magnitude of the MOSFET gate drive voltage. Ultimately, this allows for continuous adjustment of the saturation conduction current of MOSFETs Q1, Q2, and Q3, meeting the different current requirements of the test load.

[0046] Dynamic voltage equalization and operational protection: During circuit operation, the synchronous drive characteristics of optocouplers U1, U2, and U3 ensure that the turn-on and turn-off times of MOSFETs Q1, Q2, and Q3 are completely consistent, avoiding dynamic voltage imbalance caused by differences in switching speeds and achieving dynamic voltage equalization, ensuring that each MOSFET always bears a uniform voltage. If a short circuit or abnormal load occurs in the main circuit, causing a sudden increase in current, resistor R1 will generate a corresponding voltage drop according to Ohm's law, limiting the maximum current in the main circuit and protecting core components such as MOSFETs Q1, Q2, Q3, and relay K1 from burnout due to high current. When a MOSFET receives a turn-off command, the inductors in the main circuit (wiring inductance, load inductance) will generate induced voltage spikes. At this time, the RC snubber circuit connected in parallel with each MOSFET responds quickly, preventing device damage.

[0047] System Shutdown and Reset: After the test is completed, the control unit stops outputting the PWM signal and the base drive signal of transistor Q5. Transistors Q4 and Q5 are both cut off, the control terminals of optocouplers U1, U2, and U3 are de-energized, and the switching terminals are simultaneously disconnected. MOSFETs Q1, Q2, and Q3 have no drive current and are simultaneously cut off. The coil of relay K1 is de-energized, and the switching terminal is delayed in disconnecting (ensuring that the main circuit current is completely zero), completely cutting off the main circuit and eliminating the risk of leakage current when the MOSFETs are cut off. Resistors R13, R15, and R17 continue to work, balancing the residual voltage across MOSFETs Q1, Q2, and Q3 until the residual voltage drops to a safe range. The system then returns to the initialization standby state, waiting for the next test command.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A 10kV DC test load circuit, characterized in that: It includes a first port (1), a second port (2), MOS transistors Q1, Q2, and Q3; the first port (1) is connected to the drain of MOS transistor Q1; the source of MOS transistor Q1 is connected to the drain of MOS transistor Q2; the source of MOS transistor Q2 is connected to the drain of MOS transistor Q3; and the source of MOS transistor Q3 is connected to the second port (2).

2. The 10kV DC test load circuit according to claim 1, characterized in that: A resistor R13 is provided between the drain and source of MOSFET Q1; a resistor R15 is provided between the drain and source of MOSFET Q2; and a resistor R17 is provided between the drain and source of MOSFET Q3.

3. The 10kV DC test load circuit according to claim 1, characterized in that: The 10kV DC test load circuit also includes a resistor R1; the first port (1) is connected to the drain of the MOS transistor Q1 through the resistor R1.

4. The 10kV DC test load circuit according to claim 1, characterized in that: The 10kV DC test load circuit also includes a capacitor C4 and a resistor R14; one end of the capacitor C4 is connected to the drain of the MOSFET Q1; the other end of the capacitor C4 is connected to the source of the MOSFET Q1 through the resistor R14. The 10kV DC test load circuit also includes capacitor C5 and resistor R16; one end of capacitor C5 is connected to the drain of MOSFET Q2; the other end of capacitor C5 is connected to the source of MOSFET Q2 through resistor R16. The 10kV DC test load circuit also includes a capacitor C6 and a resistor R18; one end of the capacitor C6 is connected to the drain of the MOSFET Q3; the other end of the capacitor C6 is connected to the source of the MOSFET Q3 through the resistor R18.

5. A 10kV DC test load circuit according to claim 1, characterized in that: The 10kV DC test load circuit also includes a relay K1; the source of the MOS transistor Q3 is connected to the second port (2) after passing through the switching terminal of the relay K1.

6. A 10kV DC test load circuit according to claim 5, characterized in that: The 10kV DC test load circuit also includes a transistor Q5, a diode D1, a resistor R11, and a resistor R12; the diode D1 is connected in parallel with the control terminal of the relay K1; the collector of the transistor Q5 is connected to the power supply after the control terminal of the relay K1; the emitter of the transistor Q5 is grounded; the base of the transistor Q5 is connected to the resistor R11; and the base of the transistor Q5 is connected to the emitter of the transistor Q5 after the resistor R12.

7. A 10kV DC test load circuit according to claim 1, characterized in that: The 10kV DC test load circuit also includes optocoupler U1, optocoupler U2 and optocoupler U3; One end of the control terminal of the optocoupler U1 is connected to the power supply; the other end of the control terminal of the optocoupler U1 is connected to one end of the control terminal of the optocoupler U2; the other end of the control terminal of the optocoupler U2 is connected to one end of the control terminal of the optocoupler U3. One end of the switching terminal of optocoupler U1 is connected to the gate of MOSFET Q1; the other end of the switching terminal of optocoupler U1 is connected to the source of MOSFET Q1; one end of the switching terminal of optocoupler U2 is connected to the gate of MOSFET Q2; the other end of the switching terminal of optocoupler U2 is connected to the source of MOSFET Q2; one end of the switching terminal of optocoupler U3 is connected to the gate of MOSFET Q3; the other end of the switching terminal of optocoupler U3 is connected to the source of MOSFET Q3.

8. A 10kV DC test load circuit according to claim 7, characterized in that: The 10kV DC test load circuit also includes resistors R3, R5, and R7; one end of the switching terminal of optocoupler U1 is connected to one end of resistor R3; the other end of resistor R3 is connected to the gate of MOSFET Q1; one end of the switching terminal of optocoupler U2 is connected to one end of resistor R5; the other end of resistor R5 is connected to the gate of MOSFET Q2; one end of the switching terminal of optocoupler U3 is connected to one end of resistor R7; the other end of resistor R7 is connected to the gate of MOSFET Q3.

9. A 10kV DC test load circuit according to claim 8, characterized in that: The 10kV DC test load circuit also includes a resistor R4 and a capacitor C1; one end of the resistor R3 is connected to the source of the MOSFET Q1 through the resistor R4; the other end of the resistor R3 is connected to the source of the MOSFET Q1 through the capacitor C1. The 10kV DC test load circuit also includes a resistor R6 and a capacitor C2; one end of the resistor R5 is connected to the source of the MOSFET Q2 through the resistor R6; the other end of the resistor R5 is connected to the source of the MOSFET Q2 through the capacitor C2. The 10kV DC test load circuit also includes a resistor R8 and a capacitor C3; one end of the resistor R7 is connected to the source of the MOSFET Q3 through the resistor R8; the other end of the resistor R7 is connected to the source of the MOSFET Q3 through the capacitor C3.

10. A 10kV DC test load circuit according to claim 7, characterized in that: The 10kV DC test load circuit also includes a transistor Q4, a resistor R9, and a resistor R10; the collector of the transistor Q4 is connected to the other end of the control terminal of the optocoupler U3; the emitter of the transistor Q4 is grounded; the base of the transistor Q4 is connected to the resistor R9; and the base of the transistor Q4 is connected to the emitter of the transistor Q4 through the resistor R10.

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