High-efficiency DMA data transmission method and device

Abstract

The invention relates to the technical field of DMA data transmission, in particular to a high-efficiency DMA data transmission method and device. The method comprises the following steps: analyzing a plurality of data carrying requests, and obtaining a virtual address group of each data carrying request; writing the plurality of virtual address groups into a cache space, obtaining physical addresses of virtual addresses in the virtual address groups, and replacing the virtual addresses in the cache space with the physical addresses; and preferentially executing the returned data carrying requests meeting the configuration quantity so as to write the data acquired from the source end into the destination end. According to the method, the influence of MMU miss on DMA carrying tasks can be reduced on the premise of large-bit-width data carrying.

Description

Technical Field

[0001] This invention relates to the field of DMA data transmission technology, and in particular to a high-efficiency DMA data transmission method and apparatus. Background Technology

[0002] In hardware systems, Direct Memory Access (DMA) copies data from one address space to another, providing high-speed data transfer between peripherals and memory, or between memory locations. This significantly reduces the load on the Central Processing Unit (CPU), decreasing CPU wake-ups and allowing the CPU to operate in low-power modes more frequently, unaffected by data copying. However, DMA operations typically involve address translation, i.e., converting virtual addresses to physical addresses, to ensure data transfer accesses the correct memory location. A current DMA system's data transfer process, using data transfer between Double Data Rate (DDR) and Peripheral Component Interconnect Express (PCIe) as an example, is described in [reference needed]. Figure 1 When the DMA receives a data transfer request, it reads and parses the DMA instruction and executes it within the controller. The DMA sends an address translation request to the Memory Management Unit (MMU) to translate the source virtual address into a source physical address to access data in the DDR memory. After the MMU completes the address translation, it reads the required data from the DDR memory using the physical address. After acquiring the data, the DMA requests the MMU again to perform address translation based on the destination virtual address to obtain the destination physical address, and finally writes the data to the PCIe slot.

[0003] In the MMU, physical and virtual addresses are typically managed using a paging mechanism, with the mapping between virtual and physical addresses generally stored in DDR. Since accessing DDR has significant latency, often requiring hundreds of clock cycles, the MMU typically integrates a Translation Lookaside Buffer (TLB) to cache recently used virtual-to-physical address mappings to reduce address translation overhead. When performing address translation, the MMU first checks the TLB; if the required mapping is already cached in the TLB (i.e., a TLB hit), the physical address can be quickly obtained directly without accessing the page table in DDR. In this case, the address translation latency can be significantly reduced to a dozen or even just one or two clock cycles, thus significantly improving system performance.

[0004] MMU (Memory Management Unit) requests physical address space typically occur in page units, with pages typically being 4KB in size. When DMA handles large data transfer tasks, current DMA systems require re-allocating the physical address space for each cross-page access or task switch. This can lead to MMU misses, where the memory address to be accessed during a physical address request is not in the TLB (Telematics Block). An MMU miss necessitates accessing the page table in DDR (DDR memory) to obtain the address mapping, resulting in a delay of hundreds of clock cycles, which is quite time-consuming. This delay has a relatively small impact on the overall efficiency of DMA systems for small-bit-width (less than 64 bits) transfer tasks, as transferring a 4KB page of data under low bandwidth requires thousands of cycles, making the address allocation overhead relatively small. However, in high-frequency, large-bit-width (greater than 512 bits) transfer tasks, the data throughput is extremely high, and a 4KB page can be exhausted within tens of cycles. In this case, even if an MMU hit (TLB hit) only requires a dozen or so cycles of address translation latency, the address allocation overhead caused by frequent cross-page access or task switching significantly impacts the continuity of data transfer and overall efficiency, becoming a performance bottleneck.

[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention proposes a high-efficiency DMA data transfer method and apparatus, which can reduce the impact of MMU miss on DMA transfer tasks under the premise of large bit width data transfer.

[0007] The embodiments of the present invention adopt the following technical solutions: In a first aspect, the present invention provides a high-efficiency DMA data transfer method, specifically: parsing multiple data transfer requests to obtain a virtual address group for each data transfer request; Write multiple virtual address groups into a cache space, obtain the physical address of each virtual address in the virtual address group, and replace the virtual address in the cache space with the physical address; Prioritize data transfer requests that have returned a sufficient number of physical addresses to write data obtained from the source to the destination.

[0008] Preferably, the cache space includes a page cache, a transfer cache, and a prefetch cache, and the method further includes: The page cache stores the location of address translation requests and their responses; The prefetch buffer stores the status information of the prefetch task to which the current address translation request belongs; Page indexes and prefetch indexes are stored in the transport buffer to establish an association between address translation requests and prefetch tasks; and based on the association, the correct matching and distribution of address translation requests and prefetch tasks are achieved.

[0009] Preferably, the method further includes: In response to a data transfer request, a virtual address is obtained based on the page index, and a prefetch index corresponding to the page index is obtained based on the association relationship; An address translation request is initiated based on the virtual address to obtain the physical address corresponding to the virtual address; The physical address is stored in the page table entry corresponding to the page index, and the prefetch task to which the address translation request belongs is identified based on the prefetch index, and the status information of the prefetch task is modified.

[0010] Preferably, storing page indexes and prefetch indexes in the transport buffer to establish the association between address translation requests and prefetch tasks includes: A valid signal in response to an entry in the transmission buffer; Allocate a first free entry in the page cache for the entry, and record the page index of the first free entry in the entry; Allocate a second free entry in the prefetch buffer for the entry, and record the prefetch index of the second free entry in the entry.

[0011] Preferably, the method further includes: In response to a received data transfer request, allocate a free entry in the page cache. Set the allocation status signal of the free entry to the allocated status, and set the access attribute signal of the free entry to the private attribute; Parse the data transfer request to obtain the virtual address group of the data transfer request; Write the virtual address group into the page storage field of the free entry; The valid signal for the free entry is set to valid, and the ready signal is set to invalid, to indicate that the free entry has been occupied and the corresponding data is not yet ready.

[0012] Preferably, the method further includes: The virtual address is obtained based on the page index, and the prefetch index corresponding to the page index is obtained based on the association relationship; For each address translation request initiated based on a virtual address, the number of in-transit requests for the entry corresponding to the prefetch index is incremented by 1; Upon receiving the physical address corresponding to the virtual address, the number of pending requests for the entry corresponding to the prefetch index is decremented by 1.

[0013] Preferably, the request to be used includes a source address translation request and a destination address translation request, and the method further includes: Based on the aforementioned relationship, obtain the prefetch index corresponding to the page index; Obtain the number of source requests and the number of destination requests for the entry corresponding to the prefetch index; When the number of pending requests from the source is 0 and the number of pending requests from the destination is 0, the entry corresponding to the prefetch index is marked as invalid, indicating that all address translation requests for the prefetch task have been sent.

[0014] Preferably, the method further includes: Before initiating an address translation request based on a virtual address, obtain the value of the address type in the transport buffer; If the value of the address type is 0, then the source virtual address in the page cache is obtained, and an address translation request is issued based on the source virtual address; If the value of the address type is 1, then obtain the destination virtual address in the page cache and issue an address translation request according to the destination virtual address.

[0015] In a second aspect, the present invention provides a high-efficiency DMA data transfer apparatus, the apparatus comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the processor for performing the high-efficiency DMA data transfer method of the first aspect.

[0016] Thirdly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors to perform the method described in the first aspect.

[0017] Compared with existing technologies, the advantages of this invention are as follows: After receiving a data transfer request, the DMA provides a small-depth cache space to cache the source virtual address and destination virtual address of the data transfer request. Then, it continuously initiates address translation requests, prefetches the translated physical address, and replaces the virtual address in the cache space with the corresponding physical address. In the address translation request, the physical address that returns first can initiate the data transfer task first, reading the source data. After the source data is read, since the destination physical address has been prefetched, a write request can be directly initiated to write the data to the destination address. By obtaining the destination physical address in advance, it ensures that tasks with returned physical addresses can quickly execute read and write operations, reducing the impact of MMU misses on DMA transfer tasks under the premise of large-width data transfer tasks. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0019] Figure 1 This is a flowchart of a DMA data transfer method provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating a high-efficiency DMA data transfer method provided in an embodiment of the present invention; Figure 3 This is a flowchart of a method for transferring data from DDR to PCIe according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a cache space provided in an embodiment of the present invention; Figure 5 This is a flowchart illustrating the data transfer method using cache space provided in an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the difference in benefits for data transfer tasks when performing a prefetch operation and not performing a prefetch operation, as provided in an embodiment of the present invention. Figure 7 A schematic diagram of a high-efficiency DMA data transfer device provided in an embodiment of the present invention; The reference numerals in the attached figures are as follows: 21: Processor; 22: Memory. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0022] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0023] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.

[0024] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0025] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] like Figure 2 As shown, this embodiment of the invention provides a high-efficiency DMA data transfer method, which specifically includes the following steps: Step 101: Parse multiple data transfer requests and obtain the virtual address group for each data transfer request.

[0027] In one embodiment, a data transfer request includes a source start address, a destination start address, and the amount of data to be transferred. The source and destination start addresses are virtual addresses, which must be translated by the MMU (Memory Management Unit) to access physical memory. Since memory is managed in pages, when the data to be transferred spans multiple virtual memory pages, the start address of each virtual page needs to be independently queried from the page table to obtain its corresponding physical page frame. If the virtual page containing the source or destination address is not cached in the TLB (Transcript Level Buffer), each cross-page access may trigger an MMU page table traversal operation. Therefore, although only one data transfer request is initiated, multiple address translation requests may be sent to the MMU during actual execution. That is, one data transfer request corresponds to multiple address translation requests (including source and destination address translation requests). All address translation requests are pre-encapsulated into a unified processing unit, namely a virtual address group, by pairing the source and destination virtual addresses one-to-one. In this embodiment, all address translation requests are treated as a prefetch task; the prefetch task is considered complete only after all address translation requests have been issued. This design not only improves the flexibility and concurrency of data transfer, but also facilitates address translation and permission verification by the MMU, thereby improving the overall system performance and reliability.

[0028] Step 102: Write multiple virtual address groups into the cache space, obtain the physical address of each virtual address in the virtual address group, and replace the virtual address in the cache space with the physical address.

[0029] In one embodiment, the physical address includes the source physical address and the destination physical address. The cache space includes a page cache, a transport cache, and a prefetch cache. The page cache stores the location of address translation requests and their responses; the prefetch cache stores the status information of the prefetch task to which the current address translation request belongs; the transport cache stores page indexes and prefetch indexes to establish the association between address translation requests and prefetch tasks; and based on the association, the correct matching and distribution of address translation requests and prefetch tasks are achieved.

[0030] Step 103: Prioritize executing data transfer requests that have returned a sufficient number of physical addresses to write the data obtained from the source to the destination.

[0031] In one embodiment, a data transfer request corresponds to multiple address translation requests. Instead of waiting for all physical addresses to return before starting the data transfer operation, a portion of the address translation requests from the virtual address group can be issued first, based on the latency. Once all of these address translation requests have returned their physical addresses, a portion of the data can be transferred. During this data transfer process, other address translation requests from the virtual address group are issued. To ensure execution efficiency and logical order, the principle of "first-come, first-served" is followed; that is, the data transfer task corresponding to the address translation request whose physical address returns first is executed first. The initial portion of address translation requests must include at least one destination address translation request.

[0032] In one embodiment, the configured quantity is the number of initial partial address translation requests (PPAs). These PAs include source PAs and destination PAs. The number of source PAs is less than a first threshold, and the number of destination PAs is less than a second threshold. During partial data transfer, the number of subsequent source PAs is less than a third threshold, and the number of subsequent destination PAs is less than a fourth threshold. The first, second, third, and fourth thresholds can all be configured according to actual needs. For example, if four source PAs and one destination PAs are initially sent, and four source physical addresses and one destination physical address are returned, partial data transfer can begin. Alternatively, if the amount of data to be transferred is small (i.e., the number of PAs corresponding to the data transfer requests is less than four), data transfer can begin after all physical addresses have been returned.

[0033] In this embodiment, after receiving a data transfer request, the DMA provides a small-depth cache space to cache the source and destination virtual addresses of the data transfer request. Then, it continuously initiates address translation requests, prefetches the translated physical addresses, and replaces the virtual addresses in the cache space with the corresponding physical addresses. In the address translation requests, the physical address that returns first allows for priority initiation of the data transfer task, reading the source data. After the source data is read, since the destination physical address has been prefetched, a write request can be directly initiated to write the data to the destination address. By pre-fetching the destination physical address, tasks that have already returned physical addresses can quickly execute read and write operations, reducing the impact of MMU misses on the DMA transfer task under the premise of large-bit-width data transfer tasks.

[0034] The following example illustrates the data transfer process from DDR to PCIe. (See attached document for further details.) Figure 3 The data transfer process is as follows: When DDR needs to send data, it notifies the CPU via a DMA request; the CPU writes the instruction to the instruction cache (cmd_buffer) and configures the registers to prepare for the DMA operation; the DMA starts reading and parsing the instruction from the instruction cache; the DMA first parses the corresponding source and destination addresses from the instruction and caches them in the cache space (buffer); the pagefetch module initiates an MMU prefetch operation based on the virtual addresses in the cache space. This MMU prefetch operation includes source address translation requests and destination address translation requests. At this time, the prefetched destination physical address can be temporarily cached in the original cache space. When a certain number of source and destination physical addresses are fetched (e.g., 4 source physical addresses and 1 destination physical address), it indicates that they can be allocated. The task scheduling module allocates them to the corresponding idle DMA core so that the DMA core can perform read and write operations to transfer the data from DDR to PCIe. The CTRL module includes a cache, a page prefetch module, and a task scheduling module. Since each prefetch operation returns at a different time from the MMU, the cache ensures that the task whose physical address returns first is executed first. This way, even if an MMU miss occurs, the delay time will be consumed by the read / write time of the priority task. To prevent large tasks from affecting the execution of subsequent tasks, multiple DMA cores can be used to allocate tasks.

[0035] In one embodiment, see Figure 4 The cache space includes the page cache area ( Figure 4 Page buf), transfer buffer ( Figure 4 (trans buf) and prefetch buffer ( Figure 4 The fetch buffer (in the page cache) stores entries for the virtual address before the address translation request and the physical address after the response. Each entry includes fields such as valid, ready, private, page, and next page id. The valid field indicates whether the current entry has been allocated; the ready field indicates whether the current entry is ready (i.e., whether it has received the physical address corresponding to the virtual address); the private field indicates whether the current entry is private (i.e., the current entry belongs to a specific task and is not associated with other tasks); the page field stores the virtual address corresponding to the address translation request and the physical address corresponding to the virtual address; and the next page id field indicates the location of the next virtual address.

[0036] The entries in the prefetch buffer store the status information of the prefetch task. Each entry includes fields such as valid, ready, priority, task id, src req cnt, src rtn cnt, dst req cnt, and dst rtn cnt. The `valid` field indicates whether the current prefetch operation (i.e., address translation request) is valid; the `ready` field indicates whether the current task can be assigned; the `priority` field indicates the priority of the current task; the `task id` field indicates the current task identifier; the `src req cnt` field indicates the number of `src` address translation requests en route in the current prefetch operation (i.e., the number of source address translation requests sent); the `src rtn cnt` field indicates the number of `src` address translation requests to be used in the current prefetch operation (i.e., the number of source address translation requests not yet sent); the `dst req cnt` field indicates the number of `dst` address translation requests en route in the current prefetch operation (i.e., the number of destination address translation requests sent); and the `dst rtn cnt` field indicates the number of `dst` address translation requests to be used in the current prefetch operation (i.e., the number of destination address translation requests not yet sent).

[0037] The entries in the transport buffer store page indexes and prefetch indexes. Each entry includes fields such as valid, page id, attribute, and fetch id. The valid field indicates whether an address translation request has been issued. The page id points to the corresponding entry in the page buffer, the fetch id points to the corresponding entry in the prefetch buffer, and the value stored in the attribute field is used to distinguish whether the address of the current address translation request belongs to the source or the destination.

[0038] like Figure 5 As shown, this embodiment of the invention provides a method for data transfer using a cache space, which specifically includes the following steps: Step 201: In response to the data transfer request, obtain the virtual address based on the page index, and obtain the prefetch index corresponding to the page index according to the association relationship.

[0039] In one embodiment, each data transfer request corresponds to multiple virtual address groups. Before making an address translation request, to avoid mismatch between the data transfer request and the virtual address group, the page index and prefetch index are first associated in the transport buffer. That is, the page index and prefetch index are stored on the same entry. Specifically, in response to a valid signal of the entry in the transport buffer, a first free entry is allocated for the entry in the page buffer, and the page index of the first free entry is recorded in the entry; a second free entry is allocated for the entry in the prefetch buffer, and the prefetch index of the second free entry is recorded in the entry.

[0040] Specifically, in response to a data transfer request, the valid field of an entry in the transport buffer is set to valid, indicating that the prefetch operation has started. At this time, the first free entry with valid value 0 is searched in the page buffer, and the page index of the first free entry is written to the page id field of the transport buffer; the second free entry with valid value 0 is searched in the prefetch buffer, and the prefetch index of the second free entry is written to the fetch id field of the transport buffer.

[0041] In one embodiment, the process of writing a virtual address to a page cache is as follows: in response to a received data transfer request, a free entry is allocated in the page cache; the allocation status signal of the free entry is set to an allocated status, and the access attribute signal of the free entry is set to a private attribute; the data transfer request is parsed to obtain the virtual address group of the data transfer request; the virtual address group is written to the page storage field of the free entry; the validity signal of the free entry is set to valid, and the ready signal is set to invalid, to indicate that the free entry has been occupied and the corresponding data is not yet ready.

[0042] Specifically, in response to a received data transfer request, a free entry is allocated in the page cache. The valid field of the entry in the page cache is set to valid (i.e., set valid=1), indicating that the entry has been allocated. The private field of the entry is set to valid (i.e., set private=1), indicating that the entry is private to the current task, preventing it from being preempted or released by other tasks before all address translation requests are completed. A virtual address group is written to the page field of the entry, and the ready field of the entry is set to invalid (i.e., set ready=0), indicating that the physical address in the entry is not yet ready.

[0043] Step 202: Initiate an address translation request based on the virtual address to obtain the physical address corresponding to the virtual address.

[0044] In one embodiment, when initiating an address translation request, the system determines whether the current request is for obtaining the source physical address of the source virtual address or the destination physical address of the user's destination virtual address based on the attribute field in the transport buffer. Specifically, before initiating the address translation request based on the virtual address, the system obtains the address type value in the transport buffer; if the address type value is 0, the system obtains the source virtual address in the page buffer and issues an address translation request based on the source virtual address; if the address type value is 1, the system obtains the destination virtual address in the page buffer and issues an address translation request according to the destination virtual address.

[0045] Specifically, the value of the attribute field of the entry in the transport buffer is obtained. If the value is 0, the source virtual address in the corresponding page buffer is obtained, and an address translation request is issued based on the source virtual address. If the value is 1, the destination virtual address in the corresponding page buffer is obtained, and an address translation request is issued according to the destination virtual address.

[0046] Step 203: Store the physical address in the page table entry corresponding to the page index, identify the prefetch task to which the address translation request belongs based on the prefetch index, and modify the status information of the prefetch task.

[0047] In one embodiment, based on the page index, the virtual address stored in the page field of the entry is replaced with the physical address, and the ready signal in the entry is set to valid (i.e., ready=0), indicating that the physical address of the entry is ready. The corresponding entry in the prefetch cache is then located based on the prefetch index, and the information of the corresponding entry in the prefetch cache is modified. Specifically: the virtual address is obtained based on the page index, and the prefetch index corresponding to the page index is obtained according to the association relationship; for each address translation request initiated based on the virtual address, the number of in-transit requests for the entry corresponding to the prefetch index is incremented by 1; upon receiving the physical address corresponding to the virtual address, the number of pending requests for the entry corresponding to the prefetch index is decremented by 1. The number of in-transit requests includes the number of source in-transit requests and the number of destination in-transit requests; the number of pending requests includes the number of source pending requests and the number of destination pending requests.

[0048] Specifically, based on the type of address translation request, the information of the corresponding entry in the prefetch cache is modified. If it is a source address translation request, the src req cnt of the corresponding entry is incremented by 1, indicating that there is a source address translation request in transit; if it is a destination address translation request, the dst req cnt of the corresponding entry is incremented by 1, indicating that there is a destination address translation request in transit; when the physical address corresponding to the virtual address is received, if the received physical address is the source address, the src rtn cnt of the corresponding entry is decremented by 1, indicating that a source address translation request has been sent; if the received physical address is the destination address, the dst rtn cnt of the corresponding entry is decremented by 1, indicating that a destination address translation request has been sent.

[0049] In one embodiment, the `src rtn cnt` and `dst rtn cnt` fields are used to determine whether all address translation requests for a data transfer request have been issued. Specifically, this involves: obtaining the prefetch index corresponding to the page index based on the association relationship; obtaining the number of source requests and the number of destination requests for the entry corresponding to the prefetch index; when the number of source requests and the number of destination requests are both 0, marking the entry corresponding to the prefetch index as invalid to indicate that all address translation requests for the prefetch task have been issued. At this time, the `valid` and `ready` fields of the entry corresponding to the prefetch cache are set to invalid, releasing the resource of that entry. When both the `valid` and `private` fields of the page cache entry are cleared to zero, it indicates that the entry can be reassigned to other tasks.

[0050] Since prefetched physical addresses cannot be immediately consumed by the DMA unit, especially when multiple large tasks are executed concurrently, different tasks need to prefetch their own physical addresses. In this case, whether the source physical address or the destination physical address is prefetched depends on the specific task type and data flow, making the situation quite complex. To effectively manage the prefetching order and state among multiple tasks, the cache space uses a linked list structure to record the execution progress of each prefetching task. For data transfer tasks with a transfer size exceeding the page size (e.g., 4KB), multiple physical addresses need to be prefetched until all required physical addresses have been prefetched, at which point the prefetching task for the data transfer request is considered complete.

[0051] In one embodiment, the next page id field in the page cache points to the index of the next page to be requested by the prefetch task. If the prefetch task has not yet completed the physical address translation of all addresses, its private field in the page cache remains valid; only when the physical address corresponding to the last virtual address is successfully obtained is the private field set to invalid, indicating that all address prefetch requests for the task have been completed and the address prefetching process has officially ended.

[0052] In practical applications, multiple data transfer requests typically occur simultaneously. To ensure that these requests complete the prefetching operation in parallel, a cache can be used for prefetching. When a data transfer request arrives, its priority is determined by parsing the request. Priority is determined to ensure that higher-priority tasks are executed first, and tasks of the same priority are executed sequentially, with the priority of tasks being executed higher than those awaiting execution, thus reducing transfer time.

[0053] To enable prefetching and ensure data can be moved as quickly as possible, the overall data movement process can be divided into three phases: preparation, execution, and allocation. A data movement request can correspond to multiple address translation requests. Each address translation request includes a source address translation request and a destination address translation request. In the preparation phase, the address translation request corresponding to the highest priority data movement request is retrieved. All address translation requests are treated as a prefetch task, meaning one data movement request corresponds to one prefetch task. A portion of the address translation requests for this prefetch task are prepared and sent. Once all responses to these address translation requests are received, this portion of the movement task is allocated to the DMA core and executed. The execution phase then begins (i.e., during the execution of the movement task in the preparation phase), and the remaining address translation requests for the prefetch task are sent until all address translation requests for the prefetch task have been sent. In the allocation phase, the movement tasks corresponding to the address translation requests prepared in the preparation phase are allocated to the DMA core.

[0054] In one embodiment, the CPU issues a data transfer start signal, instructing the DMA to begin parsing the instructions in the cmd_buffer to obtain tasks 0 to 7 (i.e., corresponding to 8 data transfer requests), and the priority of each task, which are high, mid, low, high, mid, low, high, and low, respectively. To clearly describe the process of the preparation and execution phases, the following explanation uses task 0, which corresponds to 6 source address translation requests and 6 destination address translation requests (prefetch task), as an example. In the preparation phase, task 0 can issue a maximum of 4 source address translation requests and 1 destination address translation request; in the execution phase, task 0 can issue a maximum of 9 source address translation requests and 8 destination address translation requests; and 4 DMA cores can execute the data transfer tasks.

[0055] In one embodiment, tasks 0 through 7 are cached in their respective buffers. During the preparation phase of task 0, a free entry 1 is searched in the prefetch buffer. At this time, the ready and busy signals of free entry 1 are both invalid. Four source address translation requests and one destination address translation request are initiated sequentially. Accordingly, for each source address translation request, the src req cnt of free entry 1 is incremented by 1, and for each destination address translation request, the dst reqcnt of free entry 1 is incremented by 1. Upon receiving a response, for each source response corresponding to a source address translation request, the srcreq cnt of free entry 1 is decremented by 1, and the src rtn cnt of free entry 1 is incremented by 1. For each destination response corresponding to a destination address translation request, the dst req cnt of free entry 1 is decremented by 1, and the dst rtn cnt of free entry 1 is incremented by 1. If srcrtn cnt equals 4 and dst rtn cnt equals 4, the process is repeated. When cnt equals 1, the ready signal of idle entry 1 is set to valid, indicating that task 0 can be allocated. At this time, task 0 is allocated to an idle DMA core through a round-robin arbitration mechanism. The other tasks 1 to 7 are processed in the same way, resulting in multiple allocable tasks.

[0056] During the process of assigning data transfer tasks to DMA cores, the highest priority task is selected from all currently available tasks. A round-robin arbitration mechanism is used to assign the highest priority task to an idle DMA core, and the task's transfer information is sent to the DMA core for data transfer via the DMA channel. Specifically: The highest priority task is selected from all available tasks. If the address translation request for task 0 arrives before the address translation requests for tasks 3 and 6, task 0 will be assigned to the DMA core first. Then, it is checked which of the four DMA cores is idle. If core 0 is idle, task 0 is assigned to core 0, and so on. Task 3 is assigned to core 1, task 6 to core 2, and task 1 to core 3 (if task 1 enters the allocation phase before task 4). At this point, the execution phase begins.

[0057] During the execution phase, on the one hand, the source data in DDR is read according to the source physical address. After the data is read, the source data is written to the corresponding memory space according to the destination physical address. On the other hand, during the process of reading and writing data, the remaining source address translation requests and destination address translation requests in Task 0 are processed until all physical addresses of Task 0 are prefetched. This indicates that the prefetching task is over and the corresponding DMA core resources are released. For Task 0, at this point, the prefetch task has 2 remaining source address translation requests and 5 destination address translation requests yet to be issued. The specific execution phase of Task 0 is as follows: It searches for free entry 2 in the prefetch buffer. At this time, the ready and busy signals of free entry 2 are both invalid. It then sequentially initiates 2 source address translation requests and 5 destination address translation requests. Correspondingly, for each source address translation request, the src req cnt of free entry 2 is incremented by 1; for each destination address translation request, the dst reqcnt of free entry 2 is incremented by 1. Upon receiving a response, for each source response corresponding to a source address translation request received, the srcreq cnt of free entry 2 is decremented by 1, and the src rtn cnt of free entry 2 is incremented by 1. For each destination response corresponding to a destination address translation request received, the dst req cnt of free entry 2 is decremented by 1, and the dst rtn cnt of free entry 2 is incremented by 1. At this point, all address translation requests for this task have been issued. The ready signal of the prefetch buffer is then set to valid, and the dst req cnt is checked. The sum of the values ​​of cnt and src / req cnt is used to determine the end of the current prefetch task when the ready signal of the prefetch buffer is valid and the sum is 0. This sets the valid, ready, and busy values ​​of idle entry 2 to invalid. The entire data transfer process ends when all tasks in cmd_buffer have been parsed and executed.

[0058] In one embodiment, the difference in benefits to the data moving task between performing a prefetch operation and not performing a prefetch operation is described in [reference needed]. Figure 6Specifically, without prefetching, each task is executed sequentially (Taking Task0 to Task3 as an example). Task0 is executed first, with MMU transpilation during its execution; then Task1 is executed, with its corresponding MMU transpilation; then Task2 is executed, with its corresponding MMU transpilation; and finally Task3 is executed. During this sequential execution, the system benefits accumulate gradually over time as each task progresses. With prefetching, Task0, Task1, and Task2 start simultaneously, each performing MMU transpilation in parallel, using a first-to-return, first-execution strategy. That is, the task whose physical address is translated first is prioritized for data transfer. After address translation is complete, subsequent tasks (such as Task3) can be executed sequentially or according to a scheduling strategy. This parallel mechanism effectively overlaps the time for address translation and data transfer, significantly reducing overall processing latency, thereby increasing the number of tasks completed per unit time and achieving higher system benefits.

[0059] Based on the high-efficiency DMA data transfer method provided in the foregoing embodiments, the present invention also provides an apparatus for implementing the high-efficiency DMA data transfer method described above, such as... Figure 7 The diagram shown is a schematic representation of the device architecture according to an embodiment of the present invention. The high-efficiency DMA data transfer device of this embodiment includes one or more processors 21 and a memory 22. Wherein, Figure 7 Take a processor 21 as an example.

[0060] Processor 21 and memory 22 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0061] The memory 22, as a non-volatile computer-readable storage medium for efficient DMA data transfer, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the efficient DMA data transfer method in the foregoing embodiments. The processor 21 executes various functional applications and data processing of the efficient DMA data transfer device by running the non-volatile software programs, instructions, and modules stored in the memory 22, thereby realizing the efficient DMA data transfer method of the foregoing embodiments.

[0062] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0063] The program instructions / modules are stored in memory 22. When executed by one or more processors 21, they perform the high-efficiency DMA data transfer method described in the foregoing embodiments, for example, the method described above. Figure 2 and Figure 5 The steps shown.

[0064] This invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, for example... Figure 7 One of the processors 21 can enable the one or more processors to execute the high-efficiency DMA data transfer method described above, for example, to perform the above-described... Figure 2 and Figure 5 The steps shown.

[0065] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0066] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-efficiency DMA data transfer method, characterized in that, include: Multiple data transfer requests are parsed to obtain the virtual address group for each data transfer request; Write multiple virtual address groups into a cache space, obtain the physical address of each virtual address in the virtual address group, and replace the virtual address in the cache space with the physical address; Prioritize data transfer requests that have returned a sufficient number of physical addresses to write data obtained from the source to the destination.

2. The high-efficiency DMA data transfer method according to claim 1, characterized in that, The cache space includes a page cache, a transfer cache, and a prefetch cache; the method further includes: The page cache stores the location of address translation requests and their responses; The prefetch buffer stores the status information of the prefetch task to which the current address translation request belongs; Page indexes and prefetch indexes are stored in the transport buffer to establish an association between address translation requests and prefetch tasks; and based on the association, the correct matching and distribution of address translation requests and prefetch tasks are achieved.

3. The high-efficiency DMA data transfer method according to claim 2, characterized in that, The method further includes: In response to a data transfer request, a virtual address is obtained based on the page index, and a prefetch index corresponding to the page index is obtained based on the association relationship; An address translation request is initiated based on the virtual address to obtain the physical address corresponding to the virtual address; The physical address is stored in the page table entry corresponding to the page index, and the prefetch task to which the address translation request belongs is identified based on the prefetch index, and the status information of the prefetch task is modified.

4. The high-efficiency DMA data transfer method according to claim 2, characterized in that, The step of storing page indexes and prefetch indexes in the transport buffer to establish the association between address translation requests and prefetch tasks includes: A valid signal in response to an entry in the transmission buffer; Allocate a first free entry in the page cache for the entry, and record the page index of the first free entry in the entry; Allocate a second free entry in the prefetch buffer for the entry, and record the prefetch index of the second free entry in the entry.

5. The high-efficiency DMA data transfer method according to claim 2, characterized in that, The method further includes: In response to a received data transfer request, allocate a free entry in the page cache. Set the allocation status signal of the free entry to the allocated status, and set the access attribute signal of the free entry to the private attribute; Parse the data transfer request to obtain the virtual address group of the data transfer request; Write the virtual address group into the page storage field of the free entry; The valid signal for the free entry is set to valid, and the ready signal is set to invalid, to indicate that the free entry has been occupied and the corresponding data is not yet ready.

6. The high-efficiency DMA data transfer method according to claim 3, characterized in that, The method further includes: The virtual address is obtained based on the page index, and the prefetch index corresponding to the page index is obtained based on the association relationship; For each address translation request initiated based on a virtual address, the number of in-transit requests for the entry corresponding to the prefetch index is incremented by 1; Upon receiving the physical address corresponding to the virtual address, the number of pending requests for the entry corresponding to the prefetch index is decremented by 1.

7. The high-efficiency DMA data transfer method according to claim 6, characterized in that, The pending requests include source pending requests and destination pending requests, and the method further includes: Based on the aforementioned relationship, obtain the prefetch index corresponding to the page index; Obtain the number of source requests and the number of destination requests for the entry corresponding to the prefetch index; When the number of pending requests from the source is 0 and the number of pending requests from the destination is 0, the entry corresponding to the prefetch index is marked as invalid, indicating that all address translation requests for the prefetch task have been sent.

8. The high-efficiency DMA data transfer method according to claim 3, characterized in that, The method further includes: Before initiating an address translation request based on a virtual address, obtain the value of the address type in the transport buffer; If the value of the address type is 0, then the source virtual address in the page cache is obtained, and an address translation request is issued based on the source virtual address; If the value of the address type is 1, then obtain the destination virtual address in the page cache and issue an address translation request according to the destination virtual address.

9. A high-efficiency DMA data transfer device, characterized in that, The device includes: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the high-efficiency DMA data transfer method according to any one of claims 1-8.

10. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions that are executed by one or more processors to perform the high-efficiency DMA data transfer method as described in any one of claims 1-8.

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