Wide dynamic range signal acquisition method and circuit

Abstract

The embodiment of the invention provides a wide dynamic range signal acquisition method and circuit, and the method comprises the steps: a quadrupole is connected with an ion receiving electrode, the ion receiving electrode is connected with a transimpedance amplifier circuit, the transimpedance amplifier circuit is connected with a threshold comparison circuit, the threshold comparison circuit is connected with a D trigger circuit, and the D trigger circuit is connected with a dead time correction circuit. The lower computer FPGA is connected with the D flip-flop circuit; the quadrupole is used for screening ion signal output; the ion receiving electrode is used for converting the ion signal into a current signal; the transimpedance amplifier is used for converting the current signal into a voltage signal; the threshold comparison circuit is used for turning the voltage signal into a logic level; the D flip-flop circuit is used for outputting a target signal level matched with the lower computer FPGA; and the lower computer FPGA is used for receiving the target signal level and counting the signals acquired by the plurality of pulses through the dead time correction circuit. In this way, the phenomenon of counting omission under high-frequency signals is reduced, and the counting accuracy is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, specifically to a wide dynamic range signal acquisition method and circuit in the field of circuit technology. Background Technology

[0002] The principle of a triple quadrupole LC-MS / MS is that the sample is separated into single components by liquid chromatography and then enters the mass spectrometry system. The ion source converts the molecules into gaseous ions. By applying different radio frequency and DC voltages to the pre-bars, different ions are selected. The Q1 pre-bar selects the precursor ion with a specific mass-to-charge ratio (m / z); in the Q2 collision chamber, the precursor ion collides and breaks up with an inert gas to generate daughter ions; the Q3 pre-bar selects the target daughter ions for detection. The ion detection device at the acquisition end converts the charge into a pulsed current, which is then converted into a voltage signal by a transimpedance amplifier circuit. The signal is then converted into a standard level by a level conversion circuit and provided to the FPGA for counting. Finally, the processed signals are aggregated into a mass spectrum. This process is not only complex, but the counting accuracy cannot be effectively guaranteed. Summary of the Invention

[0003] The purpose of this invention is to provide a wide dynamic range signal acquisition circuit, the circuit comprising: a quadrupole, an ion receiving electrode, a transimpedance amplifier circuit, a threshold comparator circuit, a D flip-flop circuit, a dead-time correction circuit, and a lower-level FPGA; wherein: The quadrupole is connected to the ion receiving electrode, the ion receiving electrode is connected to the transimpedance amplifier circuit, the transimpedance amplifier circuit is connected to the threshold comparator circuit, the threshold comparator circuit is connected to the D flip-flop circuit, the D flip-flop circuit is connected to the dead-time correction circuit, and the lower-level FPGA is connected to the D flip-flop circuit; wherein... The quadrupole is used to filter ion signal output; The ion receiving electrode is used to convert the ion signal output by the quadrupole into a current signal; The transimpedance amplifier is used to convert the current signal into a voltage signal; The threshold comparison circuit is used to flip the voltage signal into a logic level and output it to the D flip-flop; The D flip-flop circuit is used to output a target signal level that matches the level received by the lower-level FPGA. The lower-level FPGA is used to receive the target signal level and count the signals after multiple pulse acquisitions through the dead time correction circuit.

[0004] In some possible implementations, the ion receiving electrode includes: an electrode sheet and a high-voltage module, wherein: The high-voltage module is used to draw ions to the electrode plate by applying high voltage, so that the ion signal is transmitted to the detection end.

[0005] In some possible implementations, the transimpedance amplifier circuit includes: a high-voltage capacitor, a transimpedance amplifier, an impedance matching circuit, and a balun, wherein: the high-voltage capacitor is connected to the electrode plate, the transimpedance amplifier is connected to the high-voltage capacitor, the impedance matching circuit is connected to the transimpedance amplifier, and the balun is connected to the impedance matching circuit.

[0006] In some possible implementations, the threshold comparison circuit includes: a threshold comparator, a reference power supply, and a voltage divider circuit, wherein: the threshold comparator is connected to the balun, the voltage divider circuit is connected to the threshold comparator, and the reference power supply is connected to the voltage divider circuit.

[0007] In some possible implementations, the D flip-flop circuit includes: a D flip-flop, an impedance matching circuit, and a level shifting circuit, wherein the D flip-flop is connected to the threshold comparator, the impedance matching circuit is connected to the D flip-flop, and the level shifting circuit is connected to the impedance matching circuit.

[0008] In some possible implementations, the dead time correction circuit includes: a dead time extension line and a dead time logic chip, wherein the dead time extension line and the dead time logic chip are respectively connected to the D flip-flop.

[0009] In some possible implementations, the lower-level FPGA includes: an FPGA chip and a dead-time correction algorithm. The FPGA chip is connected to the level conversion circuit, and the dead-time correction algorithm is used to fit and correct the pulse corresponding to the target signal level to obtain the target count rate.

[0010] This invention provides a wide dynamic range signal acquisition method, applied to the aforementioned wide dynamic range signal acquisition circuit, the method comprising: An ion receiving electrode is used to convert the ion signal output from the quadrupole into a current signal; wherein, the ion receiving electrode is connected to the quadrupole; The current signal is converted into a voltage signal using a transimpedance amplifier; A threshold comparison circuit is used to flip the voltage signal into a logic level and output it to a D flip-flop; The D flip-flop circuit is used to output a signal level that matches the target signal level received by the lower-level FPGA. The target signal level is received by the lower-level FPGA, and the signals after multiple pulse acquisitions are counted based on the target signal level to obtain the target count rate.

[0011] This invention provides a computer program product comprising: computer program code, which, when run on a computer, causes the computer to execute the method in any of the possible implementations described above.

[0012] This invention provides a computer-readable storage medium storing computer program code that, when executed on a computer, causes the computer to perform the method in any of the possible implementations described above.

[0013] The present invention has the following beneficial effects: In the wide dynamic range signal acquisition circuit, the quadrupole is connected to the ion receiving electrode, the ion receiving electrode is connected to the transimpedance amplifier circuit, the transimpedance amplifier circuit is connected to the threshold comparison circuit, the threshold comparison circuit is connected to the D flip-flop circuit, the D flip-flop circuit is connected to the dead time correction circuit, and the lower-level FPGA is connected to the D flip-flop circuit; the quadrupole filters the ion signal output; the ion receiving electrode converts the ion signal output by the quadrupole into a current signal, thereby improving the accuracy of the current signal; then, the transimpedance amplifier converts the current signal into a voltage signal; the threshold comparison circuit flips the voltage signal into a logic level and outputs it to the D flip-flop; the output of the D flip-flop circuit matches the target signal level received by the lower-level FPGA; the lower-level FPGA receives the target signal level and determines the target count rate corresponding to the target signal level through the dead time correction circuit. Thus, under high signal strength, uncorrected systems are prone to signal accumulation, causing multiple pulses to be misjudged as a single event. Dead-time correction circuits can accurately resolve time and reduce such errors, ensuring more reliable quantitative results for high-concentration samples, significantly reducing undercounting under high-frequency signals, and improving the accuracy of the target count rate. Attached Figure Description

[0014] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the composition structure of the wide dynamic range signal acquisition circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another component structure of the wide dynamic range signal acquisition circuit provided in the embodiment of the present invention; Figure 3This is a schematic diagram illustrating the implementation process of the wide dynamic range signal acquisition method provided in this embodiment of the invention; Figure 4 This is a schematic diagram of another implementation process of the wide dynamic range signal acquisition method provided in this embodiment of the invention; Figure 5 This is a schematic diagram of the structure of a computer block device provided in an embodiment of the present invention. Detailed Implementation

[0016] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation, structure, features, and effects of the wide dynamic range signal acquisition circuit proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments may be combined by any suitable form.

[0017] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" means two or more.

[0018] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0020] This invention provides a wide dynamic range signal acquisition circuit; please refer to [link / reference]. Figure 1The diagram illustrates the structural composition of a wide dynamic range signal acquisition circuit 100 according to an embodiment of the present invention. The wide dynamic range signal acquisition circuit 100 includes: a quadrupole 101, an ion receiving electrode 102, a transimpedance amplifier circuit 103, a threshold comparison circuit 104, a D flip-flop circuit 105, a dead-time correction circuit 106, and a lower-level FPGA 107. The quadrupole is connected to the ion receiving electrode, the ion receiving electrode is connected to the transimpedance amplifier circuit, the transimpedance amplifier circuit is connected to the threshold comparison circuit, the threshold comparison circuit is connected to the D flip-flop circuit, the D flip-flop circuit is connected to the dead-time correction circuit, and the lower-level FPGA is connected to the D flip-flop circuit.

[0021] The quadrupole 101 is used for ion screening signal output.

[0022] Here, the quadrupole filters ion signals. The quadrupole 101 filters ions through the influence of the electric field.

[0023] The ion receiving electrode 102 is used to convert the ion signal output by the quadrupole into a current signal.

[0024] Here, the ion receiving electrode includes: an electrode sheet and a high-voltage module, wherein the high-voltage module is used to draw ions to the electrode sheet by applying high voltage, so that the ion signal is transmitted to the detection end. Figure 2 As shown, the ion receiving electrode 102 includes an electrode plate 108 and a high-voltage module 109. The quadrupole 101 transmits ion signals to the electrode plate 108. The high-voltage module applies high voltage to draw ions to the electrode plate, allowing the ion signal to be transmitted to the detection end. The high-voltage module is a high-voltage power supply that provides power to the ion receiving circuit electrodes. It can provide a maximum voltage of 8000 volts (V). The high-voltage module is a low-voltage control high-voltage output device, for example, using 0-5V to control a 0-8000V output.

[0025] The transimpedance amplifier 103 is used to convert the current signal into a voltage signal.

[0026] Here, the transimpedance amplifier circuit includes: a high-voltage capacitor, a transimpedance amplifier, an impedance matching circuit, and a balun, wherein: the high-voltage capacitor is connected to the electrode plate, the transimpedance amplifier is connected to the high-voltage capacitor, the impedance matching circuit is connected to the transimpedance amplifier, and the balun is connected to the impedance matching circuit. Figure 2As shown, the transimpedance amplifier circuit 103 includes a high-voltage capacitor 110, a transimpedance amplifier 111, an impedance matching circuit 112, and a balun 113. The high-voltage capacitor 110 is connected to the electrode plate 108, the transimpedance amplifier 111 is connected to the high-voltage capacitor, the impedance matching circuit 112 is connected to the transimpedance amplifier 111, and the balun 113 is connected to the impedance matching circuit 112.

[0027] The quadrupole 101 filters ions through the influence of the electric field. The electrode plate 108 controls the high-voltage module 109 via the lower-level FPGA 107 to adjust the output of a controllable high voltage. After applying the high voltage, the electrode plate 108 generates a potential gradient by applying an electrostatic field to manipulate the ions, thereby applying a Coulomb force to the ions output by the quadrupole 101 to achieve traction, focusing, or deflection, and then outputting the ion charge as a current to the transimpedance amplifier circuit 103. When the transimpedance amplifier circuit 103 processes the current signal, the high-voltage capacitor 110 isolates the DC signal from the high-voltage signal. Because there is excessively high voltage on the front-end electrode plate 108, it would break down if the signal were directly output to the transimpedance amplifier 111. The high-voltage capacitor 110 is used to isolate the high-voltage signal, while filtering out the DC component in the input signal to prevent DC offset from interfering with the saturation of the transimpedance amplifier 111, and can also effectively transmit AC signals. The transimpedance amplifier 111 converts the transmitted current signal into a differential voltage signal through its built-in resistor. The impedance matching circuit 112 maintains the output differential voltage signal at a transmission impedance of 100 ohms (Ω). The balun 113 converts the differential voltage output by the impedance matching circuit 112 into a single-ended voltage, suppressing common-mode noise in the signal path and facilitating processing in subsequent circuits.

[0028] Impedance matching circuits are used to maximize energy absorption and minimize reflection during signal transmission from the source to the load, thereby reducing reflection, ringing, and oscillation. By routing traces with specific widths and reference layers on the PCB, a unique characteristic impedance is created. Then, depending on requirements, a series resistor is connected at the source for matching, a parallel resistor is connected at the termination for matching, or a Thevenin equivalent matching circuit is connected at the termination to improve signal integrity.

[0029] The threshold comparison circuit 104 is used to flip the voltage signal into a logic level and output it to a D flip-flop.

[0030] Here, the threshold comparison circuit includes: a threshold comparator, a reference power supply, and a voltage divider circuit, wherein: the threshold comparator is connected to the balun, the voltage divider circuit is connected to the threshold comparator, and the reference power supply is connected to the voltage divider circuit. Figure 2As shown, the threshold comparison circuit 104 includes a threshold comparator 114, a voltage divider circuit 115, and a reference power supply 116. The threshold comparator 114 is connected to the balun 113, the voltage divider circuit 115 is connected to the threshold comparator 114, and the reference power supply 116 is connected to the voltage divider circuit 115. The voltage divider circuit is a resistor series voltage divider structure; for example, it divides a 5V voltage into a 2.5V voltage by connecting two 1K resistors in series.

[0031] In some possible implementations, the threshold comparator circuit 104 compares the input signal with a reference voltage and outputs a corresponding logic level (high or low) to achieve threshold detection, trigger control, or protection functions. When the voltage obtained by the standard reference power supply provided by the reference power supply 116 and divided by the voltage divider circuit 115 is simultaneously compared with the single-ended signal output from the balun 113, both input to the non-inverting and inverting inputs of the threshold comparator 114, a high or low logic level is output if the threshold condition is met.

[0032] The D flip-flop circuit 105 is used to output a target signal level that matches the level received by the lower-level FPGA.

[0033] Here, the D flip-flop circuit includes: a D flip-flop, an impedance matching circuit, and a level shifting circuit. The D flip-flop is connected to the threshold comparator, the impedance matching circuit is connected to the D flip-flop, and the level shifting circuit is connected to the impedance matching circuit. Figure 2 As shown, the D flip-flop circuit 105 includes a D flip-flop 117, an impedance matching circuit 118, and a level shifting circuit 119. The D flip-flop 117 is connected to the threshold comparator 114, the impedance matching circuit 118 is connected to the D flip-flop, and the level shifting circuit 119 is connected to the impedance matching circuit 118. The level shifting circuit can be configured in two ways: one is through a dedicated chip to convert the level, such as converting a Low-Voltage Differential Signaling (LVDS) level to a Low-Voltage Transistor-Transistor Logic (LVTTL) level; the other is through a resistor network to convert the level, such as converting a 5V level to a 3.3V level.

[0034] The lower-level FPGA 107 is used to receive the target signal level and count the signals after multiple pulse acquisitions through the dead time correction circuit 106.

[0035] Here, the lower-level FPGA includes: an FPGA chip and a dead-time correction algorithm. The FPGA chip is connected to the level conversion circuit, and the dead-time correction algorithm is used to fit and correct the pulse corresponding to the target signal level to obtain the target count rate. The dead-time correction circuit includes: a dead-time extension line and a dead-time logic chip, which are respectively connected to the D flip-flop. Figure 2 As shown, the dead time correction circuit 106 includes a dead time extension line 120 and a dead time logic chip 121. The dead time extension line 120 and the dead time logic chip 121 are respectively connected to the D flip-flop 117. The lower-level FPGA chip includes an FPGA chip 122 and a dead time correction algorithm 123. The FPGA chip 122 is respectively connected to the high-voltage module 109, the level conversion circuit 119, and the dead time logic chip 121.

[0036] In some possible implementations, the D flip-flop 117 functions as a synchronous sequential logic element, primarily used to store one bit of binary data (0 or 1), and updates the data on the rising or falling edge of the clock signal. The signal output from the threshold comparator 114 enters the D flip-flop 117 and is latched. The signal output from the D flip-flop 117 then passes through the dead-time extension line 120 or the dead-time logic chip 121, subsequently controlling the reset or output of the D flip-flop 117. The FPGA chip 122 controls the selection of the dead-time extension line 120 or the dead-time logic chip 121.

[0037] The control time of the dead time extension line is shown in formula (1): (1); in, For the corresponding trace length, For the speed of light ( ), is the relative permittivity of the PCB substrate.

[0038] The principle of dead-time control is that when a valid pulse is detected, the output Q is set to 1, and a counter is started to set the dead time. During this period, new pulses are ignored until the counter returns to zero. Therefore, the peak width of the output signal of the D flip-flop 117 can be controlled, thereby achieving the purpose of dead-time adjustment.

[0039] In signal detection using a triple quadrupole liquid chromatography-mass spectrometry (LC-MS) system, the FPGA port can only recognize digital levels, requiring basic analog level conversion at the circuit level. The output signal of the D flip-flop 117 passes through the impedance matching circuit 118 to output a signal conforming to the PECL level standard. Then, the level conversion circuit 119 converts the PECL level to the LVPECL level standard that can be recognized by the FPGA chip 122 for signal detection and counting.

[0040] The lower-level FPGA 107 includes an FPGA chip 122 and a dead-time correction algorithm 123. The FPGA chip 122 is mainly used to control the output of high voltage from the high-voltage module 109 and to control the activation and dead-time setting of the dead-time logic chip. At the same time, it collects the logic level signal output from the level conversion circuit 119 to complete the counting of signals.

[0041] The dead-time correction algorithm 123 is implemented in conjunction with the dead-time correction circuit 106. Its basic implementation correction model is shown in formula (2): (2); in, This represents the count rate of the actual signal. Indicates peak width, This represents the counting rate of the input signal. Therefore, when multiple pulse signals occur, the peak width of the signal... The value increases, causing the threshold comparator 114 to recognize only one pulse. The dead time correction circuit 106 corrects the dead time of different pulse signals and outputs different peak widths. Combined with dead-time correction algorithm 123, the fitting correction is completed, thereby improving the count rate of the actual signal. Count rate approaching the input signal .

[0042] In the wide dynamic range signal acquisition circuit of the triple quadrupole LC-MS / MS provided in this embodiment of the invention, the triple quadrupole LC-MS / MS can effectively address the signal accumulation problem caused by high pulse frequencies through the synchronization, shaping, and active dead-time control of the D flip-flop, significantly improving the linearity, dynamic range, and signal-to-noise ratio of the detection. This hardware-level solution, combined with subsequent algorithm correction, provides a reliable technical guarantee for high-throughput analysis of complex samples.

[0043] In this embodiment of the invention, an ion signal is output through a quadrupole filter; the ion receiving electrode converts the ion signal output by the quadrupole into a current signal, thereby improving the accuracy of the current signal; then, a transimpedance amplifier converts the current signal into a voltage signal; the voltage signal is flipped into a logic level by a threshold comparison circuit and output to a D flip-flop; the output of the D flip-flop circuit matches the target signal level received by the lower-level FPGA; the lower-level FPGA receives the target signal level, and the target count rate corresponding to the target signal level is determined by the dead-time correction circuit. Thus, under high signal strength, an uncorrected system is prone to signal accumulation, causing multiple pulses to be misjudged as a single event. The dead-time correction circuit can accurately resolve time and reduce such errors, ensuring more reliable quantitative results for high-concentration samples, significantly reducing missed counts under high-frequency signals, and improving the accuracy of the target count rate.

[0044] This invention provides a wide dynamic range signal acquisition method, applied to the aforementioned wide dynamic range signal acquisition circuit. This method can... Figure 3 The steps shown are to be implemented as follows: 301, uses an ion receiving electrode to convert the ion signal output by the quadrupole into a current signal; The ion receiving electrode is connected to a quadrupole. 302, A transimpedance amplifier is used to convert the current signal into a voltage signal; 303, A threshold comparison circuit is used to flip the voltage signal into a logic level and output it to a D flip-flop; 304, the D flip-flop circuit is used to output a signal level that matches the target signal level received by the lower-level FPGA; 305. The lower-level FPGA receives the target signal level and counts the signals after multiple pulse acquisitions based on the target signal level to obtain the target count rate.

[0045] Here, the target signal level is received by the FPGA chip in the lower-level FPGA; and based on the target signal level, the dead-time correction algorithm in the lower-level FPGA is used to distinguish and count the signals after multiple pulse acquisitions to obtain the target count rate.

[0046] In some possible implementations, firstly, a lower-level FPGA controls a dead-time logic chip or dead-time extension line to adjust the dead time of the logic level, so as to output a dead-time adjusted PECL level; secondly, the adjusted PECL level is level-converted to obtain and output a candidate level compatible with the lower-level FPGA; finally, based on the dead-time correction algorithm, the accumulated signal of the preset pulse frequency in the candidate level is counted and distinguished to obtain the target count rate. In some possible implementations, it can be achieved by... Figure 4 The steps shown demonstrate pulse acquisition: 401, The lower-level FPGA sends a start command.

[0047] 402 controls the selection of dead-time logic chips or extension lines, and simultaneously controls the reset time of D flip-flops.

[0048] 403, FPGA sets the high-voltage module voltage.

[0049] 404, the ion receiving electrode converts charge into an electric current signal. 405, the transimpedance amplifier circuit converts current signals into voltage signals.

[0050] 406, the threshold comparison circuit flips the voltage signal into a logic level by setting a threshold.

[0051] The 407 D flip-flop circuit outputs logic levels that conform to those received by the FPGA.

[0052] 408, the lower-level FPGA receives the signal level, and the dead-time correction algorithm is used to obtain the true count rate.

[0053] In this embodiment of the invention, the wide dynamic range signal acquisition circuit effectively addresses the signal buildup problem caused by high pulse frequencies, significantly improving the linearity, dynamic range, and signal-to-noise ratio of the detection. The hardware-level solution employing D flip-flop dead-time control, combined with subsequent algorithmic correction, provides reliable technical support for high-throughput analysis of complex samples. The use of a hardware-based dead-time correction extension line and an FPGA-controlled dead-time correction logic chip for dual switching allows for adjustable dead-time for convenient debugging.

[0054] Optionally, the transmission medium can be a wired link (e.g., but not limited to, coaxial cable, optical fiber, and Digital Subscriber Line (DSL)) or a wireless link (e.g., but not limited to, Wireless Fidelity (WIFI), Bluetooth, and mobile block device networks). It should be noted that the control block device provided in the above embodiments is only an example illustrating the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer block device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, and will not be repeated here.

[0055] Figure 5 This is a schematic diagram of the structure of a computer block device provided in an embodiment of the present invention. For example, as shown... Figure 5 As shown, the computer block device 500 includes: a memory 501, a processor 502, and a computer program 503 stored in the memory 501 and running on the processor 502, wherein when the processor 502 executes the computer program 503, the computer block device can execute the arbitrary wide dynamic range signal acquisition circuit described above.

[0056] Furthermore, embodiments of the present invention also protect a control block device, which may include a memory and a processor. The memory stores executable program code, and the processor is used to call and execute the executable program code to execute the wide dynamic range signal acquisition circuit provided in the embodiments of the present invention. Embodiments of the present invention can divide the control block device into functional modules according to the above method examples. For example, each module may correspond to a specific function, or two or more functions may be integrated into a processing module. The integrated module can be implemented in hardware. It should be noted that the module division in the embodiments of the present invention is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. It should be noted that all relevant content of each step involved in the above method embodiments can be referenced to the functional description of the corresponding functional module, and will not be repeated here. It should be understood that the control block device provided in the embodiments of the present invention is used to execute the above-mentioned wide dynamic range signal acquisition circuit, and therefore can achieve the same effect as the above implementation method. When using integrated units, the control block device may include a processing module and a storage module. When the control block device is applied to a block device, the processing module can be used to control and manage the actions of the block device. The storage module can be used to support block devices in executing mutual program code, etc. The processing module can be a processor or controller, which can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. The processor can also be a combination of functions that implement computing capabilities, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and microprocessors, etc., and the storage module can be a memory.

[0057] Furthermore, the control block device provided in the embodiments of the present invention may specifically be a chip, component, or module. The chip may include a connected processor and a memory; wherein, the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute the wide dynamic range signal acquisition circuit provided in the above embodiments. The embodiments of the present invention also provide a computer-readable storage medium storing computer program code. When the computer program code is run on a computer, the computer executes the aforementioned method steps to implement the wide dynamic range signal acquisition circuit provided in the above embodiments.

[0058] This invention also provides a computer program product. When the computer program product is run on a computer, it causes the computer to execute the aforementioned related steps to realize the wide dynamic range signal acquisition circuit provided in the above embodiments. The control block device, computer-readable storage medium, computer program product, or chip provided in this invention are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they achieve can be referred to in the beneficial effects of the corresponding methods provided above, and will not be repeated here. Through the description of the above embodiments, those skilled in the art can understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the control block device can be divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by this invention, it should be understood that the disclosed control block device and method can be implemented in other ways. For example, the control block device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another control block device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, control block device or unit, and can be electrical, mechanical or other forms.

[0059] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multiple task processing and parallel processing are possible or may be advantageous. The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. The above content is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A wide dynamic range signal acquisition circuit, characterized in that, include: The circuit consists of a quadrupole, ion receiving electrode, transimpedance amplifier circuit, threshold comparator circuit, D flip-flop circuit, dead-time correction circuit, and lower-level FPGA; among which: The quadrupole is connected to the ion receiving electrode, the ion receiving electrode is connected to the transimpedance amplifier circuit, the transimpedance amplifier circuit is connected to the threshold comparator circuit, the threshold comparator circuit is connected to the D flip-flop circuit, the D flip-flop circuit is connected to the dead-time correction circuit, and the lower-level FPGA is connected to the D flip-flop circuit; wherein... The quadrupole is used to filter ion signal output; The ion receiving electrode is used to convert the ion signal output by the quadrupole into a current signal; The transimpedance amplifier is used to convert the current signal into a voltage signal; The threshold comparison circuit is used to flip the voltage signal into a logic level and output it to the D flip-flop; The D flip-flop circuit is used to output a target signal level that matches the level received by the lower-level FPGA. The lower-level FPGA is used to receive the target signal level and count the signals after multiple pulse acquisitions through the dead time correction circuit.

2. The circuit according to claim 1, characterized in that, The ion receiving electrode includes: an electrode sheet and a high-voltage module, wherein: The high-voltage module is used to draw ions to the electrode plate by applying high voltage, so that the ion signal is transmitted to the detection end.

3. The circuit according to claim 2, characterized in that, The transimpedance amplifier circuit includes: a high-voltage capacitor, a transimpedance amplifier, an impedance matching circuit, and a balun, wherein: the high-voltage capacitor is connected to the electrode plate, the transimpedance amplifier is connected to the high-voltage capacitor, the impedance matching circuit is connected to the transimpedance amplifier, and the balun is connected to the impedance matching circuit.

4. The circuit according to claim 3, characterized in that, The threshold comparison circuit includes: a threshold comparator, a reference power supply, and a voltage divider circuit, wherein: the threshold comparator is connected to the balun, the voltage divider circuit is connected to the threshold comparator, and the reference power supply is connected to the voltage divider circuit.

5. The circuit according to claim 4, characterized in that, The D flip-flop circuit includes: a D flip-flop, an impedance matching circuit, and a level shifting circuit. The D flip-flop is connected to the threshold comparator, the impedance matching circuit is connected to the D flip-flop, and the level shifting circuit is connected to the impedance matching circuit.

6. The circuit according to claim 5, characterized in that, The dead time correction circuit includes a dead time extension line and a dead time logic chip, wherein the dead time extension line and the dead time logic chip are respectively connected to the D flip-flop.

7. The circuit according to claim 6, characterized in that, The lower-level FPGA includes an FPGA chip and a dead-time correction algorithm. The FPGA chip is connected to the level conversion circuit, and the dead-time correction algorithm is used to fit and correct the pulse corresponding to the target signal level to obtain the target count rate.

8. A wide dynamic range signal acquisition method, characterized in that, The method, applied to the wide dynamic range signal acquisition circuit according to any one of claims 1 to 7, comprises: An ion receiving electrode is used to convert the ion signal output from the quadrupole into a current signal; wherein, the ion receiving electrode is connected to the quadrupole; The current signal is converted into a voltage signal using a transimpedance amplifier; A threshold comparison circuit is used to flip the voltage signal into a logic level and output it to a D flip-flop; The D flip-flop circuit is used to output a signal level that matches the target signal level received by the lower-level FPGA. The target signal level is received by the lower-level FPGA, and the signals after multiple pulse acquisitions are counted based on the target signal level to obtain the target count rate.

9. The method according to claim 1, characterized in that, The step of using the lower-level FPGA to receive the target signal level and counting the signals after multiple pulse acquisitions based on the target signal level to obtain the target count rate includes: The target signal level is received by the FPGA chip in the lower-level FPGA. Based on the target signal level, the dead-time correction algorithm in the lower-level FPGA is used to distinguish and count the signals after multiple pulse acquisitions to obtain the target count rate.

10. The method according to claim 9, characterized in that, Based on the target signal level, the dead-time correction algorithm in the lower-level FPGA is used to distinguish and count the signals after multiple pulse acquisitions to obtain the target count rate, including: The dead time of the logic level is adjusted by using the lower-level FPGA to control the dead time logic chip or dead time extension line, so as to output the dead time adjusted PECL level. The adjusted PECL level is level-converted to obtain and output a candidate level compatible with the lower-level FPGA; The target count rate is obtained by counting and resolving the accumulated signal of the preset pulse frequency in the candidate level based on the dead time correction algorithm.

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