Switching circuit, quick switching-on method of switching circuit and electronic equipment

Abstract

The embodiment of the invention discloses a switching circuit, a quick opening method of the switching circuit and a chip. The switching circuit comprises: a switching unit having a first switching tube and a second switching tube; a driving unit having a first driving circuit and a second driving circuit; the control unit is connected between the driving unit and the switch unit and is used for controlling the first driving circuit and the second switch tube to be conducted in a pre-charging stage so as to pre-charge the second switch tube, so that the second switch tube is conducted and charges are stored; and in a switch starting stage, the first switch tube and the second switch tube are controlled to be switched on, so that the first switch tube is switched on by utilizing the stored charge of the second switch tube, and the first driving circuit and the second driving circuit are controlled to be switched on with the first switch tube and the second switch tube, so that the first switch tube and the second switch tube are kept in a switched-on state. Therefore, according to the invention, the pre-charging and charge sharing strategies are introduced, so that the switching circuit can be quickly turned on under a low-current driving condition.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a switching circuit, a method for quickly turning on the switching circuit, and an electronic device. Background Technology

[0002] Fast Role Swap (FRS) is a key feature defined in the USB PD (USB Power Delivery) 3.0 protocol. It aims to enable devices to quickly switch between power supply and receiving roles in the event of an unexpected power outage, ensuring continuous system power. According to the protocol requirements, power switching chips supporting FRS must complete turn-on within 150 microseconds.

[0003] In traditional technical solutions, achieving rapid turn-on of power switches typically faces significant challenges. Due to the large gate capacitance of high-power MOSFETs and the need to control the on-resistance (Ron) to the tens of milliohms, turning on within 150 microseconds requires a charge pump to provide a large current for gate charging in a short period of time. This leads to problems such as complex chip design, increased area, and increased cost, and the high-current charging may also cause gate overshoot risk.

[0004] Therefore, there is an urgent need for an innovative solution that can achieve rapid start-up under low current driving conditions. Summary of the Invention

[0005] In view of this, this disclosure provides a switching circuit, a method for quickly turning on the switching circuit, and a chip, which utilizes a charge pre-charging strategy to achieve rapid turn-on of a high-power switching circuit under low drive current conditions.

[0006] According to a first aspect of this disclosure, a switching circuit is provided, comprising: A switching unit, comprising a first switching transistor and a second switching transistor connected in series; A driving unit, which includes a first driving circuit and a second driving circuit; A control unit, connected between the drive unit and the switch unit, is configured to: During the pre-charging phase, the first driving circuit is controlled to be turned on and the second switching transistor is turned on to pre-charge the second switching transistor, so that the second switching transistor is turned on and stores charge. During the switch-on phase, the first switch and the second switch are controlled to conduct, so that the stored charge of the second switch is used to conduct the first switch, thereby turning on the switch unit. The first drive circuit and the second drive circuit are also controlled to conduct with the first switch and the second switch, so that the first switch and the second switch remain in the conducting state.

[0007] According to a second aspect of this disclosure, a method for rapidly turning on a switching circuit is provided, applied to the switching circuit as described in the first aspect. The method includes: in response to the triggering of a precharge signal, precharging a second switching transistor via a first driving circuit; in response to the triggering of a switch-on signal, turning on the first switching transistor using the stored charge of the second switching transistor, thereby rapidly turning on the switching unit, and continuously charging the first and second switching transistors via the first and second driving circuits to maintain the conducting state of the switching unit.

[0008] According to a third aspect of this disclosure, a chip is provided that includes a switching circuit as described in the first aspect.

[0009] According to the switching circuit and its fast turn-on method provided in various aspects of this disclosure, by pre-charging the second switching transistor in the switching unit and using the stored charge of the second switching transistor to quickly turn on the first switching transistor during the switching turn-on phase, the switching circuit can be quickly turned on under low drive current conditions, without the need for additional charge storage devices or external capacitors, thus saving chip area and reducing the number of pins. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0011] Figure 1 A simplified structural diagram of a switching circuit according to an exemplary embodiment of this disclosure.

[0012] Figure 2 According to Figure 1 An exemplary circuit structure diagram of the switching circuit shown.

[0013] Figures 3 to 4 This is a timing diagram of the control of the switching circuit at different stages.

[0014] Figure 5 This is a flowchart illustrating a fast-start method for a switching circuit, which is an exemplary embodiment of this disclosure.

[0015] List of reference numerals in the attached diagram: 100. Switching circuit 110. Switching Unit 112. First switching transistor 114. Second switching transistor 120. Drive Unit 122. First driving circuit 124. Second driving circuit 130. Control Unit 212. First NMOS transistor 213. Parasitic diode of the first NMOS transistor 214. Second NMOS transistor 215. Parasitic diode of the second NMOS transistor I1~I2, current source T1~T5, Switches Detailed Implementation To enable those skilled in the art to better understand the technical solutions in the embodiments of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art should fall within the protection scope of this disclosure.

[0016] Reference is made to the accompanying drawings, which form part of the detailed description and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that orientations and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0017] Numerous details are set forth in the following description. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without these specific details. In some instances, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the embodiments described herein. Throughout this specification, references to “embodiment,” “one embodiment,” or “some embodiments” mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment herein. Therefore, the phrases “in an embodiment,” “in one embodiment,” or “some embodiments” appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, functions, or characteristics can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment in any way that does not mutually exclude particular features, structures, functions, or characteristics associated with two embodiments.

[0018] As used in the description and appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0019] The terms “coupling” and “connection”, along with their derivatives, are used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” can be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupling” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship).

[0020] As used herein, the terms “above,” “below,” “between,” and “on” refer to the relative position of a component or material with respect to other components or materials, where such physical relationships are noteworthy. For example, in the context of materials, a material positioned above or below another material may be in direct contact with it, or may have one or more intermediate materials. Furthermore, a material positioned between two materials may be in direct contact with both layers, or may have one or more intermediate layers. In contrast, a first material or material “on” a second material or material is in direct contact with that second material / material. Similar distinctions are made in the context of component assembly.

[0021] As described throughout this document and in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the listed items. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0022] The terms "circuit" or "module" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially," "close to," "approximately," "near," and "about" generally refer to a value + / - of the target value. Within 10%.

[0023] With the widespread adoption of the USB Power Delivery (USB PD) protocol, especially the Fast Role Switching (FRS) feature introduced in the USB PD 3.0 specification, higher demands have been placed on power path switching speed. The FRS function aims to ensure continuous system power supply by enabling devices to quickly switch from being a provider to a consumer when the mains power is disconnected. According to the USB PD 3.0 protocol, power switching chips supporting FRS must complete turn-on within 150 microseconds.

[0024] Achieving rapid turn-on of power switches in traditional technologies typically presents significant challenges. High-power MOSFETs have large gate capacitances and their on-resistance (Ron) needs to be controlled within the tens of milliohms range. To achieve turn-on within 150 microseconds, a charge pump needs to provide a large current to charge the gate in a short time, leading to increased chip area and design complexity. Furthermore, some products enhance the charge pump's load-carrying capacity by adding extra pins to connect external capacitors, but this approach increases system cost and PCB space requirements.

[0025] Based on the above-mentioned technical problems, the embodiments of this disclosure provide a switching circuit solution that can meet the requirements of rapid start-up, reduce the performance requirements of the charge pump, and eliminate the need for external components.

[0026] The specific implementations of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings: Switching circuit Figure 1 A simplified structural diagram of a switching circuit according to an exemplary embodiment of this disclosure.

[0027] like Figure 1 As shown, the switching circuit 100 in this embodiment mainly includes: a switching unit 110, a driving unit 120, and a control unit 130.

[0028] The switching unit 110 includes a first switching transistor 112 and a second switching transistor 114.

[0029] In some embodiments, the switching unit 110 includes an input terminal A and an output terminal B. The first switching transistor 112 and the second switching transistor 114 are two field-effect transistors connected in series between the input terminal A and the output terminal B.

[0030] For example, both the first switch 112 and the second switch 114 can be designed as NMOS transistors; alternatively, both the first switch 112 and the second switch 114 can be designed as PMOS transistors; still alternatively, one of the first switch 112 and the second switch 114 can be designed as an NMOS transistor, and the other of the first switch 112 and the second switch 114 can be designed as a PMOS transistor. Those skilled in the art can make adjustments according to actual design requirements, and this embodiment does not impose any limitations on this.

[0031] In this embodiment, when both the first NMOS transistor 212 and the second NMOS transistor 214 are in the ON state, the input terminal A and the output terminal B of the switching unit 110 are connected. When at least one of the first NMOS transistor 212 and the second NMOS transistor 214 is in the OFF state, the input terminal A and the output terminal B of the switching unit 110 are not connected.

[0032] The driving unit 120 includes a first driving circuit 122 and a second driving circuit 124.

[0033] In some embodiments, the driving unit 120 is used to generate a driving voltage higher than the input voltage VIN at the input terminal A, and provides current source I1 and current source I2 to the switching unit 110 through the first driving circuit 122 and the second driving circuit 124.

[0034] The control unit 130 is connected between the drive unit 120 and the switch unit 110, and is configured to: During the pre-charging phase, the first drive circuit 122 in the control drive unit 120 is connected to the second switch tube 114 in the switch unit 110 so as to pre-charge the second switch tube 114 using the first drive circuit 122, so that the second switch tube 114 is turned on and stores charge.

[0035] During the switching-on phase, the first switch transistor 112 and the second switch transistor 114 are controlled to conduct to each other, so that the stored charge of the second switch transistor 114 can conduct the first switch transistor 112, so that the input terminal A and the output terminal B of the switching unit 110 are quickly connected. The first driving circuit 122 and the second driving circuit 124 are controlled to conduct with the first switch transistor 112 and the second switch transistor 114. The first driving circuit 122 and the second driving circuit 124 continuously charge the first switch transistor 112 and the second switch transistor 114, so that the first switch transistor 112 and the second switch transistor 114 are kept in the conducting state.

[0036] In summary, the switching circuit of this embodiment uses the first driving circuit to precharge the second switching transistor, thereby quickly turning on the first switching transistor during the switching on phase by utilizing the stored charge in the second switching transistor. This enables the switching circuit to turn on quickly under low driving current (only about 10μA of driving current is required to achieve FRS fast start-up), and there is no need to add additional charge storage devices or external pins. This not only saves chip area but also reduces chip design complexity and manufacturing costs.

[0037] Figure 2 for Figure 1 The exemplary circuit structure diagram of the switching circuit 100 shown illustrates a specific implementation of the switching circuit 100 when both the first switching transistor 112 and the second switching transistor 114 are NMOS transistors.

[0038] like Figure 2 As shown, the switching circuit 100 in this embodiment mainly includes a switching unit 110, a driving unit 120, and a control unit 130.

[0039] The switching unit 110 includes a first NMOS transistor 212 and a second NMOS transistor 214. The drain of the first NMOS transistor 212 is connected to the input terminal A, and the drain of the second NMOS transistor 214 is connected to the output terminal B. The sources of the first NMOS transistor 212 and the second NMOS transistor 214 are connected through a shared node PMID. The gates of the first NMOS transistor 212 and the second NMOS transistor 214 are connected to the driving unit 120 via the control unit 130.

[0040] Specifically, when both the first NMOS transistor 212 and the second NMOS transistor 214 are in the on state, the input terminal A and the output terminal B of the switching unit 110 are connected; when at least one of the first NMOS transistor 212 and the second NMOS transistor 214 is in the off state, the input terminal A and the output terminal B of the switching unit 110 are in the off state.

[0041] The driving unit 120 includes a charge pump 220, which is connected to a first driving circuit 122 and a second driving circuit 124. The first driving circuit 122 includes a first current source I1, and the second driving circuit 124 includes a second current source I2. The charge pump 220 generates a driving voltage higher than the input voltage VIN at input terminal A, and provides current sources I1 and I2 to the first NMOS transistor 212 and the second NMOS transistor 214 in the switching unit 110, respectively, through the first driving circuit 122 and the second driving circuit 124. This current source driving method effectively limits inrush current and avoids gate overshoot, thereby improving the reliability and stability of the operation of the first NMOS transistor 212 and the second NMOS transistor 214.

[0042] The control unit 130 is connected between the drive unit 120 and the switch unit 110, and is configured to: During the pre-charging phase, the control unit 130 short-circuit the gate and source of the first NMOS transistor 212, causing the first NMOS transistor 212 to be in an off state. The control unit 130 then controls the first driving circuit 122 to conduct through the gate of the second NMOS transistor 214, enabling the charge pump 220 to provide a current source I1 to the gate of the second NMOS transistor 214 through the first driving circuit 122, thus pre-charging the gate-source capacitance of the second NMOS transistor 214.

[0043] During the switching-on phase, the control unit 130 controls the gate of the first NMOS transistor 212 to connect with the gate of the second NMOS transistor 214. By sharing the stored charge of the second NMOS transistor 214 with the first NMOS transistor 212, the gate-source voltage of the first NMOS transistor 212 can rise rapidly, thereby enabling the first NMOS transistor 212 to conduct quickly. This, in turn, enables rapid conduction between the input terminal A and the output terminal B of the switching unit 110. The control unit 130 also controls the first driving circuit 122 and the second driving circuit 124 to conduct with the gates of the first NMOS transistor 212 and the second NMOS transistor 214 respectively, so as to continuously charge the first NMOS transistor 212 and the second NMOS transistor 214 using a constant current source I1+I2, thereby maintaining the conduction state between the input terminal A and the output terminal B.

[0044] In some embodiments, the control unit 130 includes a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, and a fifth switch T5.

[0045] The first switch T1 is connected between the gate of the first NMOS transistor 212 and the gate of the second NMOS transistor 214; the second switch T2 is connected between the gate and source of the first NMOS transistor 212; the third switch T3 is connected between the gate and source of the second NMOS transistor 214; the fourth switch T4 is connected between the gate of the first driving circuit 122 and the second NMOS transistor 214; and the fifth switch T5 is connected between the second driving circuit 124 and the gate of the first NMOS transistor 212.

[0046] Reference Figure 2 and 3 The control unit 130 can control switches T1 to T5 to switch the switching unit 110 between the switch-off phase, the pre-charging phase, and the switch-on phase, as follows: During the switch-off phase, the first switch T1, the fourth switch T4, and the fifth switch T5 are opened, while the second switch T2 and the third switch T3 are closed.

[0047] Specifically, closing the second switch T2 short-circuites the gate and source of the first NMOS transistor 212, putting it in an off state. Closing the third switch T3 short-circuites the gate and source of the second NMOS transistor 214, putting it in an off state. Opening the first switch T1 keeps the gates of the first NMOS transistor 212 and the second NMOS transistor 214 in an off state; opening the fourth switch T4 and the fifth switch T5 disconnects the connection between the first driving circuit 122 and the second driving circuit 124 and the switching unit 110. Figure 3 It can be seen that during the switch-off phase, the gates of the first NMOS transistor 212 and the second NMOS transistor 214 are both kept at a low voltage.

[0048] During the pre-charging phase, the first switch T1, the third switch T3, and the fifth switch T5 are opened, while the second switch T2 and the fourth switch T4 are closed.

[0049] Specifically, by closing the second switch T2, the gate and source of the first NMOS transistor 212 are short-circuited, putting the first NMOS transistor 212 in the off state. By closing the fourth switch T4, the first driving circuit 122 is turned on by the gate of the second NMOS transistor 214, so that the gate-source capacitance of the second NMOS transistor 214 is charged using the current source I1. When the gate-source voltage of the second NMOS transistor 214 is higher than a preset voltage threshold, the second NMOS transistor 214 switches to the on state. Figure 3 It can be seen that during the pre-charging phase, the gate of the first NMOS transistor 212 remains at a low voltage, while the gate-source voltage of the second NMOS transistor 214 gradually increases.

[0050] Furthermore, during the pre-charging phase, since the second NMOS transistor 214 is in the on state and its source is connected to the source of the first NMOS transistor 212, the parasitic diode 213 connected to the source and drain of the first NMOS transistor 212 can be shorted to prevent current from flowing from the source to the drain of the first NMOS transistor 212, thus ensuring that the first NMOS transistor 212 is in a completely off state.

[0051] During the switch-on phase, the second switch T2 and the third switch T3 are opened, while the first switch T1, the fourth switch T4, and the fifth switch T5 are closed. Specifically, by closing the first switch T1, the gate of the first NMOS transistor 212 is connected to the gate of the second NMOS transistor 214. Since the source of the first NMOS transistor 212 and the source of the second NMOS transistor 214 are connected through a shared node PMID, in this state, the stored charge in the gate-source capacitance of the second NMOS transistor 214 can be quickly shared to the gate of the first NMOS transistor 212, causing the gate-source voltage of the first NMOS transistor 212 to rise rapidly and exceed the threshold voltage, thereby realizing the rapid turn-on of the first NMOS transistor 212, and thus realizing the rapid turn-on of the switch unit 110 under low drive current. Simultaneously, by closing the fourth switch T4 and the fifth switch T5, the gate channels of the first driving circuit 122 and the second NMOS transistor 214, and the gate of the second driving circuit 124 and the first NMOS transistor 212 are connected. This allows for constant current charging of the gates of the first NMOS transistor 212 and the second NMOS transistor 214 using current sources I1+I2. This causes the gate-source voltages of the first NMOS transistor 212 and the second NMOS transistor 214 to gradually increase to their stable operating points. This achieves both rapid turn-on of the switching unit 110 and control of the turn-on current of the switching unit through constant current charging, thereby improving the system reliability of the switching circuit. Figure 3 It can be seen that during the switching-on phase, the gate-source voltage of the first NMOS transistor 212 and the gate-source voltage of the second NMOS transistor 214 gradually increase to achieve complete conduction between the input terminal A and the output terminal B.

[0052] In some embodiments, the control unit 130 may control the switching unit 110 to switch between the switch-off phase, the pre-charging phase, and the switch-on phase based on control commands input by the user or control commands automatically triggered by the system.

[0053] In some embodiments, the control unit 130 is further configured to: during the switch-on phase, in response to detecting that the output voltage VOUT of the output terminal B is higher than the input voltage VIN of the input terminal A (i.e., VOUT > VIN), control the gate and source of the second NMOS transistor 214 to be short-circuited, and the second drive circuit 124 is turned on with the gate of the first NMOS transistor 212.

[0054] Reference Figure 2 and Figure 4The control unit 130 can automatically switch from the switch-on phase to the switch protection phase when it detects that the output voltage VOUT of output terminal B is higher than the input voltage VIN of input terminal A during the switch-on phase. This control unit opens the first switch T1, the second switch T2, and the fourth switch T4, while closing the third switch T3 and the fifth switch T5. Specifically, closing the third switch T3 short-circuits the gate and source of the second NMOS transistor 214, putting it in an off state. Closing the fifth switch T5 keeps the second drive circuit 124 connected to the gate of the first NMOS transistor 212, continuously charging the gate of the first NMOS transistor 212 using the current source I2, causing the input voltage VIN of input terminal A to exceed the output voltage VOUT of output terminal B. Figure 4 It can be seen that during the switching protection phase, the gate-source voltage of the first NMOS transistor 212 remains at a high level, while the gate-source voltage of the second NMOS transistor 214 is at a low level.

[0055] Furthermore, during the switching protection phase, since the first NMOS transistor 212 is in the conducting state and the source of the first NMOS transistor 212 is connected to the source of the second NMOS transistor 214, the parasitic diode 215 connected to the source and drain of the second NMOS transistor 214 can be shorted to prevent current from flowing from the source to the drain of the second NMOS transistor 214, thus ensuring that the second NMOS transistor 214 is in a completely off state.

[0056] In some embodiments, the control unit 130 is further configured to: during the switch protection phase, in response to detecting that the output voltage VOUT of the output terminal B is lower than the input voltage VIN of the input terminal A (i.e., VOUT < VIN), automatically return from the switch protection phase to the switch opening phase, so as to control the second switch T2 and the third switch T3 to be open, and the first switch T1, the fourth switch T4 and the fifth switch T5 to be closed.

[0057] In summary, this embodiment uses only five switches T1 to T5 to achieve seamless switching between the pre-charging stage, the turn-on stage, and the turn-off stage of the switching unit. It does not require the introduction of additional charge storage devices, control chips, or pins, thereby saving chip area and reducing chip manufacturing costs.

[0058] In addition, this embodiment can automatically trigger a switch protection mechanism when the output voltage is detected to be higher than the input voltage, so as to avoid reverse current damage to the system and improve the operational reliability of the switch circuit.

[0059] It should also be noted that the switching circuits of the embodiments of this disclosure are not limited to FRS applications, but can be applied in any application scenario that requires rapid power transistor switching or rapid power transistor current recovery. In particular, a small current can be used during the pre-charging phase of the switching circuit to reduce the load-carrying capacity requirements of the drive unit (charge pump).

[0060] Quick turn-on method for switching circuits Figure 5 This is a fast-start method for a switching circuit, which is an exemplary embodiment of the present disclosure. The method of this embodiment is applied to the switching circuit 100 described in any of the above embodiments.

[0061] like Figure 5 As shown, this embodiment mainly includes: Step 502: In response to the triggering of the pre-charge signal, the second switching transistor is pre-charged through the first driving circuit.

[0062] For example, refer to Figure 2 The gate and source of the first NMOS transistor 212 can be short-circuited to remain in an open state by controlling the first switch T1, the third switch T3 and the fifth switch T5 to be open, and the second switch T2 and the fourth switch T4 to be closed, thereby enabling the first driving circuit 122 to be connected to the gate of the second NMOS transistor 214, so as to charge the gate-source capacitance of the second NMOS transistor 214 using the current source I1.

[0063] Step 504: In response to the triggering of the switch-on signal, the first switch is turned on by the stored charge of the second switch, so that the switch unit is turned on quickly, and the first and second switch are continuously charged by the first and second drive circuits to maintain the conduction state of the switch unit.

[0064] For example, refer to Figure 2 The system can control the second switch T2 and the third switch T3 to be open, and the first switch T1, the fourth switch T4, and the fifth switch T5 to be closed, so that the gate of the first NMOS transistor 212 is connected to the gate of the second NMOS transistor 214. This allows the first NMOS transistor 212 to be quickly turned on using the stored charge of the second NMOS transistor 214, thereby achieving rapid turn-on of the switching unit 110 under low drive current. The first NMOS transistor 212 and the second NMOS transistor 214 are then charged with a constant current through the current source I1 of the first drive circuit 122 and the current source I2 of the second drive circuit 124 to maintain the conduction state of the switching unit 110.

[0065] In some embodiments, the method of this embodiment further includes: during the switch-on phase, in response to detecting that the output voltage of the output terminal is higher than the input voltage of the input terminal, automatically switching from the switch-on phase to the switch protection phase, so as to control the first switch, the second switch and the fourth switch to be disconnected, and the third switch and the fifth switch to be closed, so that the gate and source of the second NMOS transistor are short-circuited, and the second driving circuit is connected to the gate of the first NMOS transistor.

[0066] In some embodiments, the method of this embodiment further includes: during the switch protection phase, in response to detecting that the output voltage of the output terminal is lower than the input voltage of the input terminal, automatically reverting from the switch protection phase to the switch-on phase.

[0067] In summary, this embodiment, by clearly defining the pre-charging and switching-on phases and optimizing the control timing of the switching circuit, can ensure that the switching circuit can achieve rapid switching-on under low drive current conditions.

[0068] chip Another embodiment of this disclosure provides a chip including the switching circuit described in the above embodiments to achieve rapid switching.

[0069] In some embodiments, the chip is a power switch chip that supports the USB PD 3.0 protocol.

[0070] Specific embodiments of the subject matter have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0071] It should also be noted that improvements to a technology can be hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology), or even direct improvements to the hardware circuit structure. Therefore, it cannot be said that an improvement to a methodology cannot be implemented using hardware modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and fabricate dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must also be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0072] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0073] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A switching circuit, comprising: A switching unit, comprising a first switching transistor and a second switching transistor connected in series; A driving unit, which includes a first driving circuit and a second driving circuit; A control unit, connected between the drive unit and the switch unit, is configured to: During the pre-charging phase, the first driving circuit is controlled to be turned on and the second switching transistor is turned on to pre-charge the second switching transistor, so that the second switching transistor is turned on and stores charge. During the switch-on phase, the first switch and the second switch are controlled to conduct, so that the stored charge of the second switch is used to conduct the first switch, thereby turning on the switch unit. The first drive circuit and the second drive circuit are also controlled to conduct with the first switch and the second switch, so that the first switch and the second switch remain in the conducting state.

2. The switching circuit according to claim 1, wherein, The switching unit includes an input terminal and an output terminal; The first switch and the second switch are a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor and the source of the second NMOS transistor are connected through a shared node. The drain of the first NMOS transistor is connected to the input terminal and the drain of the second NMOS transistor is connected to the output terminal. When both the first NMOS transistor and the second NMOS transistor are in the on state, the input and output terminals of the switching unit are connected; When at least one of the first NMOS transistor and the second NMOS transistor is in an off state, the input and output terminals of the switching unit are disconnected.

3. The switching circuit according to claim 2, wherein, The gates of the first NMOS transistor and the second NMOS transistor are connected to the driving unit via the control unit; The control unit is configured to: During the pre-charging phase, the gate and source of the first NMOS transistor are short-circuited, and the first driving circuit is turned on with the gate of the second NMOS transistor to pre-charge the gate-source capacitance of the second NMOS transistor. During the switch-on phase, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. By sharing the stored charge of the second NMOS transistor with the first NMOS transistor, the first NMOS transistor is turned on. The first driving circuit and the second driving circuit are respectively turned on with the gates of the first NMOS transistor and the second NMOS transistor to continuously charge the first NMOS transistor and the second NMOS transistor.

4. The switching circuit according to claim 3, wherein, The control unit includes: The first switch is connected between the gate of the first NMOS transistor and the gate of the second NMOS transistor; The second switch is connected between the gate and source of the first NMOS transistor; The third switch is connected between the gate and source of the second NMOS transistor; The fourth switch is connected between the gate of the first driving circuit and the gate of the second NMOS transistor; The fifth switch is connected between the second driving circuit and the gate of the first NMOS transistor; The control unit is configured as follows: During the pre-charging phase, the first switch, the third switch, and the fifth switch are disconnected, while the second switch and the fourth switch are closed. During the switch-on phase, the second switch and the third switch are controlled to open, while the first switch, the fourth switch, and the fifth switch are closed.

5. The switching circuit according to claim 4, wherein, The control unit is also configured to: During the switch-off phase, the first switch, the fourth switch, and the fifth switch are controlled to open, while the second switch and the third switch are closed, so that the gate and source of the first NMOS transistor and the second NMOS transistor are short-circuited respectively.

6. The switching circuit according to claim 4, wherein, The control unit is also configured to: During the switch-on phase, in response to detecting that the output voltage at the output terminal is higher than the input voltage at the input terminal, the switch-on phase is automatically switched to the switch protection phase to control the first switch, the second switch, and the fourth switch to be disconnected, and the third switch and the fifth switch to be closed, so that the gate and source of the second NMOS transistor are short-circuited, and the second driving circuit is connected to the gate of the first NMOS transistor.

7. The switching circuit according to claim 6, wherein, The control unit is also configured to: During the switch protection phase, in response to detecting that the output voltage at the output terminal is lower than the input voltage at the input terminal, the switch protection phase automatically returns to the switch-on phase.

8. The switching circuit according to claim 1, wherein, The driving unit includes a charge pump, which is connected to the first driving circuit and the second driving circuit. The first driving circuit includes a first current source, and the second driving circuit includes a second current source.

9. A method for quickly turning on a switching circuit, applied to the switching circuit as described in any one of claims 1 to 8, the method comprising: In response to the triggering of the pre-charge signal, the second switching transistor is pre-charged through the first driving circuit; In response to the triggering of the switch-on signal, the first switch is turned on using the stored charge of the second switch, so that the switch unit is turned on quickly, and the first and second switch are continuously charged through the first and second drive circuits to maintain the conduction state of the switch unit.

10. A chip comprising a switching circuit as claimed in any one of claims 1 to 8.

Images