Programmable erasable non-volatile memory cell

Abstract

The invention discloses a nonvolatile memory cell capable of programming and erasing. The nonvolatile memory cell comprises an isolation structure, a first well region, a second well region, a first gate structure, a first gap wall and a metal layer. The isolation structure divides the surface of the semiconductor substrate into a first region and a second region. The first well region is formed in the first region. The second well region is formed in the second region. A first gate structure is formed over the first region surface and over the second region surface. The first gap wall is in contact with the side wall of the first gate structure. The first merged doped region and the second merged doped region are formed below the surface of the first region. The third merged doped region is formed below the surface of the second region. The metal layer is over the first gate structure.

Description

Technical Field

[0001] This invention relates to a non-volatile memory cell, and more particularly to a programmable and erasable non-volatile memory cell. Background Technology

[0002] As is well known, non-volatile memory (MVM) is widely used in various electronic products, such as SD cards and solid-state drives (SSDs). Essentially, a programmable and erasable non-volatile memory includes a memory array, which in turn includes multiple programmable and erasable non-volatile memory cells.

[0003] For example, each programmable and erasable memory cell contains a floating-gate transistor. The floating gate of the floating-gate transistor stores hot carriers, and the storage state of the floating-gate transistor is determined by the amount of hot carriers stored. For example, hot carriers can be electrons or holes.

[0004] Furthermore, current CMOS fabrication processes can create both high-voltage input / output (IO) devices and low-voltage core devices on a single semiconductor substrate. Core devices are called low-voltage devices (LV devices), such as low-voltage P-type transistors (LV P-type transistors) and low-voltage N-type transistors (LV N-type transistors). Input / output devices are called medium-voltage devices (MV devices), such as medium-voltage P-type transistors (MV P-type transistors) and medium-voltage N-type transistors (MV N-type transistors). Low-voltage devices have thinner gate dielectric layers, resulting in faster operation speeds, but they can withstand lower voltage stress. Medium-voltage devices have thicker gate dielectric layers, allowing them to withstand higher voltage stresses, but their operation speeds are slower.

[0005] Generally, programming and erasing programmable and erasable memory cells require relatively high programming or erasing voltages. For example, the erasing voltage is typically between 14V and 19V, while the programming voltage is between 7.5V and 9V. This means that all transistors in existing programmable and erasable memory cells, such as floating-gate transistors, are medium-voltage devices. Therefore, the design of programmable and erasable memory cells must adhere to medium-voltage device design rules. For instance, medium-voltage transistors have a gate channel length of at least 0.45μm.

[0006] Due to the design specifications of medium-voltage components, the size of existing programmable and erasable memory cells will be too large. Summary of the Invention

[0007] This invention relates to a non-volatile memory cell, comprising: an isolation structure formed on a semiconductor substrate, the isolation structure dividing the surface of the semiconductor substrate into a first region and a second region; a first well region formed below the surface of the first region of the semiconductor substrate; a second well region formed below the surface of the second region of the semiconductor substrate; a first gate structure formed above the surface of the first region and above the surface of the second region; a first spacer wall contacting a sidewall of the first gate structure; a first merged doped region formed below the surface of the first region, wherein the first merged doped region is located on a first side of the first gate structure; a second merged doped region formed below the surface of the first region, wherein the second merged doped region is located on a second side of the first gate structure; a third merged doped region formed below the surface of the second region; a metal layer located above the first gate structure, and a vertical projection of the metal layer covering the first gate structure; a bit line electrically connected to the second merged doped region; a control line electrically connected to the third merged doped region; and an auxiliary line electrically connected to the metal layer. A metal-oxide-semiconductor capacitor, wherein a first terminal of the metal-oxide-semiconductor capacitor is electrically connected to the control line and a second terminal of the metal-oxide-semiconductor capacitor is electrically connected to the first gate structure; and a parallel plate capacitor, wherein a first terminal of the parallel plate capacitor is electrically connected to the metal layer and a second terminal of the parallel plate capacitor is electrically connected to the first gate structure; wherein the first merged doped region, the first gate structure and the second merged doped region form a floating gate transistor.

[0008] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0009] Figures 1A to 1I This is a flowchart illustrating the fabrication process of the storage unit according to the first embodiment of the present invention;

[0010] Figure 1J Equivalent circuit diagram for a programmable and erasable non-volatile memory cell;

[0011] Figures 2A to 2F This is a flowchart illustrating the fabrication process of the storage unit according to the second embodiment of the present invention;

[0012] Figure 3A A schematic diagram of a bias gauge used for programming, erasing, and reading operations of the storage unit in the first embodiment;

[0013] Figures 3B to 3D A schematic diagram illustrating the operation of programming, erasing, and reading actions of the storage unit in the first embodiment;

[0014] Figure 4A A schematic diagram of a first example of the control line, source line, and N-type well region receiving voltage during programming operations;

[0015] Figure 4B A schematic diagram of a second example of the control line, source line, and N-type well region receiving voltage during programming operations;

[0016] Figure 4C A schematic diagram of the third example of the control line, source line, and N-type well region received voltage during programming operations;

[0017] Figure 4D A schematic diagram of the fourth example of the control line, source line, and N-type well region received voltage during programming operations;

[0018] Figure 4E A schematic diagram of the fifth example of the control line, source line, and N-type well region received voltage during programming operations;

[0019] Figure 4F A schematic diagram of the sixth example of the control line, source line, and N-type well region received voltage during programming operations;

[0020] Figure 5 This is a schematic diagram of a storage unit according to a third embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of a storage unit according to the fourth embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of a storage unit according to the fifth embodiment of the present invention;

[0023] Figure 8This is a schematic diagram of a storage unit according to the sixth embodiment of the present invention;

[0024] Figure 9A This is a schematic diagram of a storage unit according to the seventh embodiment of the present invention;

[0025] Figure 9B A schematic diagram of the equivalent circuit of the storage cell in the seventh embodiment; and

[0026] Figure 10 This is a schematic diagram of a storage unit according to the eighth embodiment of the present invention.

[0027] Symbol explanation:

[0028] 502, 602: Isolation structure

[0029] 503, 505: Gate dielectric layers

[0030] 513, 515, 613, 615: Polysilicon gate layers

[0031] 523, 525: Gate structure

[0032] 540, 550: Mask

[0033] 541, 542, 543, 551, 552: p-type lightly doped drain regions

[0034] 548, 558: Spacer wall

[0035] 561, 562, 563, 564: p-type ion implantation regions

[0036] 571, 572, 573, 574, 671, 672, 673, 674, 771, 772: Merged p-type doped regions

[0037] 580, 680: Metal layer

[0038] 702: Barrier Layer

[0039] 704: Polycrystalline silicon layer

[0040] 706: Wire

[0041] 774, 874: Merging n-type doped regions Detailed Implementation

[0042] Because current CMOS fabrication processes can fabricate both medium-voltage and low-voltage devices on a single semiconductor substrate, the programmable and erasable non-volatile memory cell of this invention utilizes fabrication steps from both the medium-voltage (MV) and low-voltage (LV) production procedures. That is, in designing the programmable and erasable non-volatile memory cell of this invention, a portion of the structure utilizes the design rules for medium-voltage devices, while another portion utilizes the design rules for low-voltage devices. Therefore, the size of the programmable and erasable non-volatile memory cell of this invention is effectively reduced, and the programming and erasing voltages can be lowered. Various embodiments of this invention are described below.

[0043] Please refer to Figures 1A to 1I The diagram shown is a flowchart illustrating the fabrication process of a programmable, erasable, non-volatile memory cell according to a first embodiment of the present invention. Figure 1J This is an equivalent circuit diagram of a programmable and erasable non-volatile memory cell. In the following description, the programmable and erasable non-volatile memory cell will be simply referred to as a memory cell.

[0044] like Figure 1A As shown, an isolation structure 502 is formed on the semiconductor substrate Sub, defining regions A and B. That is, the semiconductor substrate Sub is covered by the isolation structure 502, with only regions A and B exposing the surface of the semiconductor substrate Sub. For example, the isolation structure 502 is a shallow trench isolation structure (STI). Essentially, a memory cell of the present invention is formed in regions A and B.

[0045] Next, the well region formation step is performed. A first well region is formed below region A on the surface of the semiconductor substrate Sub, and a second well region is formed below region B on the surface of the semiconductor substrate Sub. For example, the first well region is an N-type well region NW, the second well region is a P-type well region PW, and the semiconductor substrate Sub is a P-type semiconductor substrate P_sub.

[0046] Next, the gate structure formation step is performed. For example... Figure 1BAs shown, two gate structures 523 and 525 are formed. Gate structure 523 includes a gate dielectric layer 503 and a polysilicon gate layer 513. Gate structure 525 includes a gate dielectric layer 505 and a polysilicon gate layer 515. The gate dielectric layer 503 contacts the surface of the N-type well region NW and the isolation structure 502, while the gate dielectric layer 505 contacts the surface of the N-type well region NW, the isolation structure 502, and the P-type well region PW. The polysilicon gate layer 513 is formed on the gate dielectric layer 503, and the polysilicon gate layer 515 is formed on the gate dielectric layer 505.

[0047] A gate structure 525 is formed above the surface of region A. Furthermore, the gate structure 525 extends above the surface of region B via an isolation structure 502. A gate structure 523 is formed above the surface of region A, and the gate structure 523 extends to other memory cells (not shown) via the isolation structure 502. In other words, multiple memory cells share the gate structure 523.

[0048] Gate structures 523 and 525 divide the surface of region A into three sub-regions. Specifically, the polysilicon gate layer 515 of gate structure 525 serves as the floating gate of the floating gate transistor. The polysilicon gate layer 513 of gate structure 523 serves as the select gate of the select transistor.

[0049] In this embodiment, the channel length L of the floating gate transistor is... F Less than the channel length L of the selected transistor S That is, L F <L S For example, choosing the channel length L of a transistor. S The channel length L of the floating gate transistor is approximately 0.55 μm. F It is approximately 0.35 μm.

[0050] Next, the subsequent manufacturing process of this invention will be described. Figure 1C , Figure 1D , Figure 1E , Figure 1F , plotted Figure 1B The cross-sectional view of the storage cell along the direction of the cd dotted line is used to further describe the subsequent manufacturing process of the storage cell of the present invention.

[0051] like Figure 1CAs shown, in region A, mask 540, indicated by dashed lines, covers gate structure 525 and its two side regions, exposing gate structure 523 and its two side regions. Furthermore, mask 540 does not cover region B, thus exposing gate structure 525 and its surrounding region in region B. For example, mask 540 is formed of a photoresist layer. Additionally, by… Figure 1B It can be seen that there is only a single polysilicon gate layer 515. Therefore, in Figure 1C The solid line connecting the two polysilicon gate layers 515 indicates that the two polysilicon gate layers 515 are the same polysilicon gate layer 515.

[0052] Next, a lightly doped drain process (LDD process) is performed in the medium-voltage component fabrication process. Therefore, p-type lightly doped drain regions (p-LDD regions) 541 and 542 are formed below the surface of the semiconductor substrate Sub, which is not covered by mask 540 and gate structure 523. Additionally, a p-type lightly doped drain region 543 is formed below the surface of the semiconductor substrate Sub, which is not covered by gate structure 525. The p-type lightly doped drain regions 541 and 542 are located below the surface of region A, on either side of gate structure 523. Furthermore, the p-type lightly doped drain region 543 is located below the surface of region B, surrounding gate structure 525. The doping concentrations and doping depths of the p-type lightly doped drain regions 541, 542, and 543 are equal.

[0053] like Figure 1D As shown, after removing mask 540, mask 550 (shown as dashed lines) covers the gate structure 523 and the areas on both sides of it in region A, and also covers the gate structure 525 in region B. That is, the area previously covered by mask 540 is exposed. Mask 550 is formed of a photoresist layer. Next, using a lightly doped drain fabrication process in the low-voltage device fabrication procedure, p-type lightly doped drain regions 551 and 552 are formed on the surface of the semiconductor substrate Sub that is not covered by mask 550 and gate structure 525. The p-type lightly doped drain regions 551 and 552 are located below the surface of region A, on both sides of gate structure 525, with equal doping concentrations and depths.

[0054] Furthermore, the distance between the p-type lightly doped drain region 541 and the p-type second lightly doped drain region 542 is L. S This is used as a channel for selecting the transistor. The distance between the p-type lightly doped drain region 551 and the p-type lightly doped drain region 552 is L.F This is used as a channel for selecting the transistor. And L F <L S .

[0055] The first lightly doped drain fabrication process is part of the medium-voltage device fabrication process, and the second lightly doped drain fabrication process is part of the low-voltage device fabrication process. Therefore, the doping concentration of the p-type lightly doped drain regions 541, 542, and 543 is less than that of the p-type lightly doped drain regions 551 and 552, and the doping depth of the p-type lightly doped drain regions 551 and 552 is shallower than that of the p-type lightly doped drain regions 541, 542, and 543.

[0056] like Figure 1E As shown, after removing the mask 550, a gap wall 548 is formed on the sidewall of the gate structure 523, and a gap wall 558 is formed on the sidewall of the gate structure 525. The gap wall 548 contacts the sidewall of the gate structure 523, and the gap wall 558 contacts the sidewall of the gate structure 525.

[0057] Next, as Figure 1F As shown, a p-type ion implantation process is performed on the Sub surface of the semiconductor substrate using two gate structures 523 and 525 and spacers 548 and 558 as masks. Therefore, the three sub-regions in region A not covered by the two gate structures 523 and 525 and spacers 548 and 558 form p-type ion implantation regions 561, 562, and 563, as shown by the diagonal lines. The region in region B not covered by the gate structure 525 and spacer 558 forms p-type ion implantation region 564, as shown by the diagonal lines. Essentially, the p-type ion implantation regions 561, 562, 563, and 564 have the highest doping concentration, which is greater than the doping concentration of all lightly doped drain regions 541, 542, 543, 551, and 552.

[0058] like Figure 1FAs shown, in region A, the lightly doped p-type drain region 541 and the p-type ion implantation region 561 form a merged p-doped region 571, located below the Sub surface of the conductor substrate on the first side of the gate structure 523. The lightly doped p-type drain regions 542 and 551 and the p-type ion implantation region 562 form a merged p-doped region 572, located below the Sub surface of the conductor substrate between the second side of the gate structure 523 and the first side of the gate structure 525. The lightly doped p-type drain region 552 and the p-type ion implantation region 563 form a merged p-doped region 573, located below the Sub surface of the conductor substrate on the second side of the gate structure 525. In region B, the lightly doped p-type drain region 543 and the p-type ion implantation region 564 form a merged p-doped region 574, located below the Sub surface of the conductor substrate next to the gate structure 525. Additionally, in region A, the p-type lightly doped drain region 541 is located below the spacer wall 548 on the first side of the gate structure 523, the p-type lightly doped drain region 542 is located below the spacer wall 548 on the second side of the gate structure 523, the p-type lightly doped drain region 551 is located below the spacer wall 558 on the first side of the gate structure 525, and the p-type lightly doped drain region 552 is located below the spacer wall 558 on the second side of the gate structure 525.

[0059] in addition, Figure 1G for Figure 1F A 3D view. In region A, the gate structure 523 and the merged p-type doped regions 571 and 572 on both sides form the selection transistor M. S1 The gate structure 525 and the merged p-type doped regions 572 and 573 on both sides form a floating gate transistor M. F1 In region B, the gate structure 525, together with the P-type well region PW and the merged p-type doped region 574, forms a metal-oxide-semiconductor capacitor (MOS capacitor, C). C1 Among them, metal oxide semiconductor capacitor C C1 This is a p-type metal-oxide-semiconductor capacitor (PMOS capacitor). In this embodiment, the floating gate transistor M... F1 With selection transistor M S1 It is a p-type transistor, fabricated within the N-type well region NW. That is, a floating gate transistor M. F1 With selection transistor M S1 The body terminal is connected to the N-type well region NW.

[0060] Next, as Figure 1H and Figure 1I As shown, where Figure 1I for Figure 1HA cross-sectional view is shown. A metal layer 580 is also formed above the polysilicon gate layer 515 of the gate structure 525. The size of the metal layer 580 is larger than that of the polysilicon gate layer 515, so that the vertical projection of the metal layer 580 can completely cover the polysilicon gate layer 515 of the gate structure 525. Therefore, the polysilicon gate layer 515 and the metal layer 580 form a metal / polysilicon parallel plate capacitor (C). C2 Furthermore, the connection line step is performed, and the storage unit C of the first embodiment of the present invention is completed. ELL .

[0061] like Figure 1H and Figure 1I As shown, the merged p-type doped region 571 is connected to the source line SL, the merged p-type doped region 573 is connected to the bit line BL, the polysilicon gate layer 513 is connected to the word line WL, the metal layer 580 is connected to the assistant line (AG), and the merged p-type doped region 574 is connected to the control line (CG).

[0062] like Figure 1J As shown, storage unit C ELL Includes a selection transistor M S1 A floating gate transistor M F1 A metal oxide semiconductor capacitor C C1 With a metal / polycrystalline silicon parallel plate capacitor C C2 Select transistor M S1 The gate terminal is connected to a word line WL, selecting transistor M. S1 The first drain / source terminal is connected to the source line SL. Floating gate transistor M F1 The first drain / source terminal is connected to the select transistor M. S1 The second drain / source terminal, floating gate transistor M F1 The second drain / source terminal is connected to the bit source line BL. Furthermore, the metal-oxide-semiconductor capacitor C... C1 The first terminal is connected to the floating gate transistor M F1 Floating gate 515, metal-oxide-semiconductor capacitor C C1 The second terminal is connected to the control line CG. Metal / polysilicon parallel plate capacitor C C2 The first terminal is connected to the floating gate transistor M F1 Floating gate 515, metal / polysilicon parallel plate capacitor C C2 The second end is connected to the auxiliary line AG. That is, the storage unit C of the first embodiment of the present invention... ELL Composed of two transistors M F1 MS1 With two capacitors C C1 C C2 This configuration can be termed a 2T2C memory cell. The metal-oxide-semiconductor capacitor C is one of these components. C1 With a metal / polycrystalline silicon parallel plate capacitor C C2 As coupling capacitors, hot carriers will not penetrate these two coupling capacitors C during the erase operation. C1 C C2 .

[0063] In region A, a shallow, lightly doped drain region is fabricated using a low-voltage device fabrication process, forming merged p-type doped regions 572 and 573. Therefore, the channel length L can be designed. F Shorter floating gate transistor M F1 For example, a channel length L of 0.35 μm F Therefore, the number of storage units C can be reduced. ELL The layout area.

[0064] Furthermore, the present invention can also control the selection transistor M by modifying the shape of region A and the shape of the polysilicon gate layers 513 and 515. S1 With floating gate transistor M F1 The aspect ratio was adjusted, and the selection transistor M was selected. S1 Floating gate transistor M F1 and metal oxide semiconductor capacitor C C1 The characteristics of this are briefly explained below.

[0065] Please refer to Figures 2A to 2F The diagram illustrates the manufacturing process of the storage unit according to the second embodiment of the present invention. The manufacturing process of the storage unit in the second embodiment is presented in a top view.

[0066] like Figure 2A As shown, regions A and B are defined on the semiconductor substrate Sub using an isolation structure 602. Region B is square, and region A is an inverted L-shape. The width of region A at its top is W. S The width at the bottom is W F And W S >W F In other words, once the memory cell is completed, the channel width W of the floating gate transistor... F Smaller than the channel width W of the selected transistor S .

[0067] Next, the trap formation step is performed. For example... Figure 2BAs shown, a first well region is formed below the surface of region A and below the isolation structure 602 near region A. A second well region is formed below the surface of region B and below the isolation structure 602 near region B. For example, the first well region is an N-type well region NW, the second well region is a P-type well region PW, and the semiconductor substrate Sub is a P-type semiconductor substrate P_sub.

[0068] As shown in Figure 2C, two gate structures are formed. The first gate structure includes a polysilicon gate layer 613. The second gate structure includes a polysilicon gate layer 615. Similarly, the first gate structure is formed above the surface of region A and extends to another memory cell (not shown). The second gate structure is formed above the surface of region A and extends above the surface of region B.

[0069] In region A, the length L of the second gate structure is designed. F The length L of the first gate structure is less than S In other words, once the memory cell is completed, the channel length L of the floating gate transistor... F Less than the channel length L of the selected transistor S That is, L F <L S Furthermore, the aspect ratio of the selected transistor is (W). S / L S The aspect ratio of the floating gate transistor is (W) F / L F For example, the channel length L S The channel length L of the floating gate transistor is approximately 0.55 μm. F It is approximately 0.35 μm.

[0070] Additionally, in region B, the width W of the second gate structure C And the length is L C And L C >L F The overlap area A between the second gate structure and the diagonal line of region A is... F For (W) F ×L F The overlapping area A between the second gate structure and the oblique line of region B. C For (W) C ×L C Basically, to improve the coupling ratio of a metal-oxide-semiconductor capacitor, the overlap area A... C At least greater than the overlapping area A F More than three times, for example, the design overlap area A C Let the overlapping area be A F Five times.

[0071] Next, the same steps as in the first embodiment are performed, and a process similar to that in the first embodiment is completed. Figure 1G The structure is as follows: That is, the lightly doped drain fabrication process (LDD process) in the medium-voltage device fabrication process, the lightly doped drain fabrication process, the spacer wall fabrication process, and the ion implantation process are performed sequentially. For example... Figure 2D As shown, three merged p-type doped regions 671, 672, and 673 are formed in region A, and one merged p-type doped region 674 is formed in region B. The merged p-type doped regions 671 and 672 on both sides of the polysilicon gate layer 613 include lightly doped p-type drain regions fabricated using a medium-voltage device fabrication process. Additionally, the merged p-type doped regions 672 and 673 on both sides of the polysilicon gate layer 615 include lightly doped p-type drain regions fabricated using a low-voltage device fabrication process.

[0072] Next, as Figure 2E As shown, a metal layer 680 is formed above the polysilicon gate layer 615 of the second gate structure. The size of the metal layer 680 is larger than that of the polysilicon gate layer 615, such that the vertical projection of the metal layer 680 can completely cover the polysilicon gate layer 615. Therefore, the polysilicon gate layer 615 and the metal layer 680 form a metal / polysilicon parallel plate capacitor.

[0073] like Figure 2F As shown, a connection line step is performed to complete the memory cell of the second embodiment. That is, the merged p-type doped region 671 is connected to the source line SL, the merged p-type doped region 673 is connected to the bit line BL, the polysilicon gate layer 613 is connected to the word line WL, the metal layer 680 is connected to the auxiliary line AG, and the merged p-type doped region 674 is connected to the control line CG.

[0074] Both the first and second embodiments use 2T2C memory cells and have the same equivalent circuitry, which will not be described in detail here. Furthermore, the present invention also designs various bias voltages applicable to the memory cells of the first and second embodiments, enabling the memory cells to perform programming, erasing, and reading operations.

[0075] Please refer to Figure 3A The diagram shows the bias table for the first embodiment's storage unit to perform programming (PGM), erasure (ERS) and read operations. Figures 3B to 3D This is a schematic diagram illustrating the operation of programming (PGM), erasing (ERS), and reading operations in the memory cell of the first embodiment. The N-type well region NW and the source line SL receive the same voltage. Essentially, Figure 3A The bias gauge is also applicable to the storage unit of the second embodiment.

[0076] like Figure 3A and Figure 3B As shown, during the programming operation, the source line SL receives the programming voltage V. PP The word line WL receives the first turn-on voltage V. ON1 The bit line BL receives the ground voltage (0V), and the control line CG receives a voltage that can be set between the ground voltage (0V) and the programming voltage V. PP Between these points, the voltage received by the auxiliary line AG can be set to half of the programming voltage (0.5V). PP ) and twice the programming voltage (2V) PP Between ) . For example, the programming voltage V PP Between 6V and 6.5V, the first turn-on voltage V ON1 It can be set between ground voltage (0V) and 7 / 8 times the programming voltage (7V). PP Between / 8).

[0077] When programming, select transistor M. S1 When the circuit is turned on, a programming current I is generated between the source line SL and the bit line BL. P When the programming current I P Hot carriers (e.g., holes) pass through the floating gate transistor M F1 When the channel is activated, the generation of channel hot holes triggers the hot electron injection effect (CHHIHE effect), producing electron-hole pairs. The generated electrons are then attracted by the voltage applied by the auxiliary line AG and the control line CG and injected into the floating gate 515. Therefore, the memory cell C... ELL The storage state is changed to the programming state.

[0078] In storage unit C ELL In this process, merging the differences between p-type doped regions 571, 572, and 573 can reduce the programming voltage V. PP And improve programming efficiency.

[0079] by Figure 1F Let's take the structure of the floating gate transistor M as an example to illustrate. F1 In the middle, the p-type lightly doped drain regions 551 and 552 near the two sides of the floating gate layer 515 have a high concentration and shallow depth, and the floating gate transistor M F1 It has a short channel. Therefore, in storage cell C ELL When performing programming operations, a lower programming voltage V is provided. PPThis allows a high electric field to be generated at the pinch-off point of the channel, thereby improving programming efficiency. Simultaneously, due to the programming voltage V... PP The programming current I is low. P It will also be smaller, reducing power consumption during programming operations.

[0080] like Figure 3A and Figure 3C As shown, during the erase operation, the source line SL receives the erase voltage V. EE The word line WL receives the second turn-on voltage V. ON2 Bit line BL receives erase voltage V EE Alternatively, it can be floated, with the control line CG receiving the ground voltage (0V), and the auxiliary line AG receiving a voltage that can be set to be less than or equal to the ground voltage (0V). The erase voltage V... EE Between 9V and 12V, the second turn-on voltage V ON2 It can be set to be less than or equal to the erase voltage V EE .

[0081] During the erase operation, select transistor M. S1 Turn on, erase voltage V EE The signal is transferred from the source line SL to the floating gate transistor M. F1 And floating gate transistor M F1 The N-type well region NW receives the erase voltage V EE Therefore, the floating gate transistor M F1 An internal FN tunneling effect is generated, allowing electrons to pass through the gate dielectric layer from the floating gate 515 to the N-type well region NW to complete the erase operation. In other words, during the erase operation, electrons are ejected from the floating gate 515 to the floating gate transistor M. F1 The body terminal. Therefore, storage unit C ELL The storage state is changed to the erase state.

[0082] Therefore, in storage unit C ELL During the erasure operation, the coupling ratio of the metal-oxide-semiconductor capacitor is increased, and the overlap area A... C At least greater than the overlapping area A F More than three times, for example, the design overlap area A C Let the overlapping area be A F Five times that of the standard, providing a lower erase voltage V EE The erasure process can then be completed.

[0083] like Figure 3A and Figure 3D As shown, during the read operation, the source line SL receives the read voltage V. R The word line WL receives the third turn-on voltage V. ON3 The bit line BL receives the ground voltage (0V), and the voltage received by the control line CG can be set between the ground voltage (0V) and the read voltage V. R Between these two voltages, the voltage received by the auxiliary line AG can be set between the ground voltage (0V) and the reading voltage V. R Between. Among them, the third turn-on voltage V ON3 Less than or equal to half the reading voltage (0.5V) R For example, reading the voltage V R It is 2.5V.

[0084] During the read operation, transistor M is selected. S1 When the signal is turned on, a read current I is generated between the source line SL and the bit line BL. R And according to the reading current I R The size of the current determines the storage state of the memory cell. For example, when there are no stored electrons in the floating gate 515, the read current I... R Very small, almost zero, visual memory unit C ELL In erase state. When electrons are stored in the floating gate 515, the read current I... R Larger, visual storage unit C ELL In programming mode.

[0085] In addition, in this embodiment, the erasure voltage V EE Greater than the programming voltage V PP Programming voltage V PP Greater than the reading voltage V R Read voltage V R It is greater than the ground voltage (0V).

[0086] In addition to providing a fixed voltage to the control line CG and the auxiliary line AG during the programming process, a gradually increasing voltage waveform can also be provided. For example, a step waveform, a triangle waveform, or a quarter ellipse waveform. These will be explained below.

[0087] Please refer to Figure 4AThe diagram illustrates a first example of the received voltages of the control line CG, source line SL, and N-type well region NW during programming. In this first example, the programming operation can be divided into a programming phase (P1) and a verification phase (V1).

[0088] Time points t1 to t6 constitute programming phase P1. During programming phase P1, the source line and the N-type well region NW receive the programming voltage V. PP The voltage received by the control line CG is determined by the initial voltage V. P1 Gradually rise to the programming voltage V PP For example, from time point t1 to time point t2, the voltage received by the control line CG is equal to the initial voltage V. P1 From time point t2 to time point t3, the voltage received by the control line CG is the initial voltage V. P1 Add voltage increment ΔV(V) P1 +ΔV); From time point t3 to time point t4, the voltage received by the control line CG is the initial voltage V. P1 Add twice the voltage increment ΔV(V) P1 +2ΔV); and so on; from time point t5 to time point t6, the voltage received by the control line CG is the programming voltage V. PP Additionally, during programming phase P1, the voltage received by the auxiliary line AG can also be a stepped waveform, gradually rising to twice the programming voltage of 2V. PP This will not be elaborated upon here.

[0089] The period from time point t6 to time point t7 is the verification phase V1. Verification phase V1 is similar to a read operation and is used to determine the memory cell C. ELL The storage state. During phase V1 verification, the source line and the N-type well region NW receive the read voltage V. R The control line CG receives the ground voltage (0V). Therefore, according to the storage cell C... ELL Reading current I R The size of the storage unit C is used to determine the size of the storage unit C. ELL The storage status. Upon confirming storage unit C... ELL When in programming state, the programming action is completed. This is done after confirming storage unit C. ELL If the program is not in a programming state, it indicates a programming failure (program fail), and it may be possible to target that memory location C. ELL Perform another programming action or determine that the storage unit is a fail cell.

[0090] Please refer to Figure 4BThe diagram illustrates a second example of the control line CG, source line SL, and N-type well region NW receiving voltage during programming. The programming operation can be divided into multiple programming phases P1~Pn and multiple verification phases V1~Vn.

[0091] The time points from t1 to t2 constitute the programming phase P1. During programming phase P1, the source line and the N-type well region NW receive the programming voltage V. PP The voltage received by the control line CG is determined by the initial voltage V. P1 Gradually rise to (V) P1 +2ΔV). For example, from time point t1 to time point t2, the control line CG receives three pulses sequentially, and the pulse heights of the three pulses are respectively the initial voltage V. P1 、(V P1 +ΔV), (V P1 +2ΔV).

[0092] Time points t2 to t3 constitute the verification phase V1. For example, during the verification phase V1, the source line and the N-type well region NW receive the read voltage V. R The control line CG receives the ground voltage (0V). This is confirmed in memory cell C. ELL When in the programming state, the programming action is complete, and subsequent programming phases P2~Pn and verification phases V2~Vn are no longer performed. This is confirmed in memory cell C. ELL If not in a programming state, proceed to the next programming phase P2 and verification phase V2.

[0093] The time points from t3 to t4 constitute the programming phase P2. During programming phase P2, the source line and the N-type well region NW receive the programming voltage V. PP The voltage received by the control line CG rises to (V) P1 +3ΔV). That is, a pulse received by the control line CG, the pulse height of which is (V P1 +3ΔV). Of course, multiple pulses can also be received in the programmed phase P2, and the pulse height gradually increases.

[0094] Time points t4 to t5 represent verification phase V2. During verification phase V2, the source line and the N-type well region NW receive the read voltage V. R The control line CG receives the ground voltage (0V). This is confirmed in memory cell C. ELL When in the programming state, the programming action is complete, and subsequent programming phases P3~Pn and verification phases V3~Vn are no longer performed. This is confirmed in memory cell C. ELL If not in a programming state, proceed to the next programming phase and verification phase.

[0095] Similarly, time points t5 to t6 constitute programming phase P3, and so on. Time points t7 to t8 constitute programming phase Pn. During programming phase Pn, the source line and the N-type well region NW receive the programming voltage V. PP The voltage received by the control line CG rises to the programming voltage V. PP That is, the control line CG receives a pulse wave, the pulse height of which is the programming voltage V. PP .

[0096] Time points t8 to t9 represent the verification phase Vn. During the verification of phase Vn, the source line and the N-type well region NW receive the read voltage V. R The control line CG receives the ground voltage (0V). This is confirmed in memory cell C. ELL When in programming state, the programming action is completed. This is done after confirming storage unit C. ELL If the program is not in a programming state, it indicates a programming failure (program fail), and it may be possible to target that memory location C. ELL Perform another programming action or determine that the storage unit is a fail cell.

[0097] Similarly, during the programming phases P1~Pn and the verification phases V1~Vn, the voltage received by the auxiliary line AG can be gradually increased to twice the programming voltage, 2V. PP This will not be elaborated upon here.

[0098] Please refer to Figure 4C The diagram illustrates a third example of the control line CG, source line SL, and N-type well region NW receiving voltage during programming operations. Figure 4D The fourth example of receiving voltages for the control line CG, source line SL, and N-type well region NW during programming operations.

[0099] Similar to Figure 4A and Figure 4B ,exist Figure 4C The voltage received by the control line CG is a triangular waveform. Additionally, Figure 4D The triangular waveform is further divided into multiple programming phases P1~Pn and multiple verification phases V1~Vn.

[0100] Please refer to Figure 4E The diagram illustrates the fifth example of the control line CG, source line SL, and N-type well region NW receiving voltage during programming operations. Figure 4F The sixth example of receiving voltages for the control line CG, source line SL, and N-type well region NW during programming operations.

[0101] Similar to Figure 4A and Figure 4B ,exist Figure 4EThe voltage received by the control line CG is a 1 / 4 elliptical waveform. Additionally, Figure 4F The 1 / 4 elliptical waveform is further divided into multiple programming phases P1~Pn and multiple verification phases V1~Vn.

[0102] Of course, those skilled in the art can modify the storage unit of the first or second embodiment of the present invention. In other embodiments, the coupling capacitor C can be modified. C2 The structure is designed to improve the voltage coupling ratio.

[0103] Please refer to Figure 5 The illustration depicts a storage unit according to a third embodiment of the present invention. Compared to the storage unit C of the first embodiment... ELL Storage unit C in the third embodiment ELLA It also adds a block layer 702, a polysilicon layer 704, and a conductive line 706. The following only describes the memory cell C of the first embodiment. ELL Storage unit C in the third embodiment ELLA The dissimilar structures between them will not be elaborated further.

[0104] like Figure 5 As shown, in storage unit C ELLA In this structure, the gate structure 525 and the spacer 558 are covered by a barrier layer 702. For example, the barrier layer 702 is a salicide block layer (SAB), which is an insulator. Furthermore, a polysilicon layer 704 is formed on the upper surface of the barrier layer 702. That is, the memory cell C... ELLA A polysilicon layer 704 is also formed between the metal layer 580 and the polysilicon gate layer 515. Additionally, a wire 706 is formed between the metal layer 580 and the polysilicon layer 704, and the wire 706 is electrically connected to the metal layer 580 and the polysilicon layer 704. Therefore, the polysilicon layer 704 and the polysilicon gate layer (floating gate) 515 form a polysilicon / polysilicon plate capacitor (C). C2 Because the distance between the two polysilicon layers 704 and 515 is relatively short, the voltage coupling efficiency of the coupling capacitor can be effectively improved.

[0105] Basically, the storage unit C in the first embodiment ELL Storage unit C of the third embodiment ELLA They have the same equivalent circuit. The memory cell C in the third embodiment... ELLA Can be used Figure 3A The bias gauge is used to perform programming, erasing, and reading operations, which will not be elaborated here.

[0106] Furthermore, those skilled in the art can further modify the structure of the merged p-type doped regions 571, 572, and 573 of the memory cell in the first embodiment of the present invention to create memory cells in other embodiments. Please refer to... Figure 6 The illustration depicts a storage unit according to a fourth embodiment of the present invention. Compared to the storage unit C of the first embodiment... ELL Fourth embodiment storage unit C ELLB The difference lies in the gate structure 723 and the combined p-type doped regions 771 and 772. The gate structure 723 includes a gate dielectric layer 703 and a polysilicon gate layer 713, with spacer walls 748 formed on the sidewalls of the gate structure 723. Only two memory cells C are described below. ELL C ELLB The structural differences between them are not discussed further.

[0107] According to a fourth embodiment of the present invention, the p-type lightly doped drain regions in region A are all fabricated using a lightly doped drain fabrication process in a low-voltage device fabrication process, while the p-type lightly doped drain regions in region B are fabricated using a lightly doped drain fabrication process in a medium-voltage device fabrication process. Therefore, in memory cell C... ELLB In the combined p-type doped regions 771, 772, and 573, the lightly doped p-type drain regions have the same doping depth and concentration. However, the doping depth of the lightly doped p-type drain regions in combined p-type doped regions 771, 772, and 573 is shallower than that in combined p-type doped region 574. Furthermore, the doping concentration of the lightly doped p-type drain regions in combined p-type doped regions 771, 772, and 573 is greater than that in combined p-type doped region 574.

[0108] Furthermore, since the lightly doped p-type drains of the merged p-type doped regions 771 and 772 are fabricated using the lightly doped drain fabrication process in the low-voltage device fabrication process, the length of the gate structure 723 can be shortened, thus enabling the selection transistor M to... S1 It also features a short channel to reduce the size of the storage unit C. ELLB The size.

[0109] Basically, the storage unit C in the first embodiment ELL Storage unit C in the fourth embodiment ELLB They have the same equivalent circuit. The memory cell C in the fourth embodiment... ELLB Can be used Figure 3A The bias gauge is used to perform programming, erasing, and reading operations, which will not be elaborated here.

[0110] Please refer to Figure 7The illustration depicts a storage unit according to a fifth embodiment of the present invention. Compared to the storage unit C of the first embodiment... ELL Fifth embodiment storage unit C ELLC Metal-oxide-semiconductor capacitor C C1 This is an n-type metal-oxide-semiconductor capacitor. Only two memory cells C are described below. ELL C ELLC The structural differences between them are not discussed further.

[0111] According to a fifth embodiment of the present invention, the second well region in region B is an N-type well region NW. For example... Figure 7 As shown, since the first well region in region A and the second well region in region B are both N-type well regions NW, the two N-type well regions NW below the isolation structure 502 do not contact each other.

[0112] In this embodiment, the lightly doped drain region in region B is fabricated using a lightly doped drain fabrication process in the medium-voltage component fabrication procedure, and an n-type ion implantation region is formed using an n-type ion implantation process. The lightly doped drain region and the n-type ion implantation region together form a merged n-type doped region 774. Therefore, the gate structure 525, the N-type well region NW, and the merged n-type doped region 774 together form an n-type metal-oxide-semiconductor capacitor C. C1 .

[0113] Basically, the storage unit C in the first embodiment ELL Storage unit C of the fifth embodiment ELLC They have the same equivalent circuit. Furthermore, due to the storage cell C... ELLC Metal-oxide-semiconductor capacitor C C1 For n-type metal-oxide-semiconductor capacitors C C1 Therefore, when performing programming operations, the voltage range received by the control line CG can be modified from the ground voltage (0V) to 1.4 times the programming voltage V. PP (1.4V PP Between ), and the bias voltage for the erase and read operations is similar to that of memory cell C in the first embodiment. ELL This will not be elaborated upon here.

[0114] Please refer to Figure 8 The illustration depicts a storage unit according to a sixth embodiment of the present invention. Compared to the storage unit C of the first embodiment... ELL In region B, there are P-type well regions PW and merged p-type doped regions 574 of the same type. In the memory cell C of the sixth embodiment... ELLDIn region B, there are P-type well regions PW of different types and a combined n-type doped region 874, and the gate structure 525 and the combined n-type doped region 874 form an n-type metal-oxide-semiconductor capacitor C. C1 .

[0115] First embodiment storage unit C ELL Storage unit C of the sixth embodiment ELLD They have the same equivalent circuit. Furthermore, since the P-type well region PW and the merged n-type doped region 874 are of different types, the memory cell C... ELLD During programming, erasing, and reading operations, the voltage received by the control line CG must be greater than or equal to the voltage received by the P-type well region PW, while the bias voltages of other terminals are similar to those in the first embodiment. For example, during programming, the voltage received by the control line CG is greater than or equal to the programming voltage V. PP The voltage received by the P-type well region PW is less than or equal to the programming voltage V. PP During the erase operation, the control line CG receives a ground voltage (0V), and the P-type well region PW also receives a ground voltage (0V). During the read operation, the voltage received by the control line CG is between the ground voltage (0V) and the read voltage V. R Between these points, the P-type well region PW receives the ground voltage (0V).

[0116] Please refer to Figure 9A The diagram shown is a storage unit according to the seventh embodiment of the present invention. Figure 9B This is the equivalent circuit of the memory cell in the seventh embodiment. Compared to the memory cell C in the first embodiment... ELL The difference lies in the storage unit C of the seventh embodiment. ELLE No transistor was designed for selection. Therefore, the source line SL is connected to the merged p-type doped region 572.

[0117] like Figure 9B As shown, storage unit C ELLE Includes a floating gate transistor M F1 A metal oxide semiconductor capacitor C C1 With a metal / polycrystalline silicon parallel plate capacitor C C2 Floating gate transistor M F1 The first drain / source terminal is connected to the source line SL, and the floating gate transistor M F1 The second drain / source terminal is connected to the bit line BL. Furthermore, the metal-oxide-semiconductor capacitor C... C1 The first terminal is connected to the floating gate transistor M F1 Floating gate 515, metal-oxide-semiconductor capacitor C C1 The second terminal is connected to the control line CG. Metal / polysilicon parallel plate capacitor C C2The first terminal is connected to the floating gate transistor M F1 Floating gate 515, metal / polysilicon parallel plate capacitor C C2 The second end is connected to the auxiliary line AG.

[0118] Furthermore, due to the seventh embodiment storage unit C ELLE No transistor was selected. Therefore, Figure 3A In the bias table, after removing the bias of word line WL, it can be applied to memory cell C. ELLE Programming actions, erasing actions, and reading actions.

[0119] Furthermore, those skilled in the art can further modify the structure of the storage unit in the first embodiment. Please refer to... Figure 10 The diagram illustrates a storage unit according to the eighth embodiment of the present invention. Figure 10 As shown, in storage unit C ELLF In this embodiment, a deep N-well (DNW) is designed between the semiconductor substrate Sub and the N-well region NW. The lower part of the deep N-well region DNW contacts the semiconductor substrate Sub, and the upper part of the deep N-well region DNW contacts both the N-well region NW and the P-well region PW. Similarly, a deep N-well region DNW can also be added to the memory cell in the second to seventh embodiments, which will not be described in detail here.

[0120] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A non-volatile storage unit, comprising: An isolation structure is formed on a semiconductor substrate, and the isolation structure divides the surface of the semiconductor substrate into a first region and a second region; A first well region is formed below the surface of the first region of the semiconductor substrate; A second well region is formed below the surface of the second region of the semiconductor substrate; A first gate structure is formed above the surface of the first region and above the surface of the second region; A first gap wall, which contacts the sidewall of the first gate structure; A first merged doped region is formed below the surface of the first region; wherein the first merged doped region is located on the first side of the first gate structure; A second merged doped region is formed below the surface of the first region; wherein the second merged doped region is located on the second side of the first gate structure; A third merged doped region is formed below the surface of the second region; A metal layer is located above the first gate structure, and the vertical projection of the metal layer covers the first gate structure; The bit line is electrically connected to the second merged doped region; The control line is electrically connected to the third merged doped region; Auxiliary lines are electrically connected to the metal layer; A metal-oxide-semiconductor (MOS) capacitor, wherein a first terminal of the MOS capacitor is electrically connected to the control line, and a second terminal of the MOS capacitor is electrically connected to the first gate structure; and A parallel plate capacitor, wherein a first end of the parallel plate capacitor is electrically connected to the metal layer, and a second end of the parallel plate capacitor is electrically connected to the first gate structure; The first merged doped region, the first gate structure, and the second merged doped region form a floating gate transistor.

2. The non-volatile memory cell as described in claim 1, further comprising: A second gate structure is formed above the surface of the first region; A second gap wall, which contacts the sidewall of the second gate structure; A fourth merged doped region is formed below the surface of the first region; wherein the fourth merged doped region is located on the first side of the second gate structure, and the first merged doped region is located between the second side of the second gate structure and the first side of the first gate structure; The source line is electrically connected to the fourth merged doped region; and The word line is electrically connected to the second gate structure; The fourth merged doped region, the second gate structure, and the first merged doped region together form a selection transistor.

3. The non-volatile memory cell of claim 2, wherein the channel length of the floating gate transistor is less than the channel length of the select transistor.

4. The non-volatile memory cell of claim 2, wherein the channel width of the floating gate transistor is smaller than the channel width of the select transistor.

5. The non-volatile memory cell of claim 2, wherein the first gate structure and the first region have a first overlap area, the first gate structure and the second region have a second overlap area, and the second overlap area is at least three times the first overlap area.

6. The non-volatile memory cell of claim 2, wherein the first gate structure includes a first gate dielectric layer and a first polysilicon gate layer, the second gate structure includes a second gate dielectric layer and a second polysilicon gate layer; the first gate dielectric layer is in contact with the surface of the first region and the surface of the second region, and the first polysilicon gate layer is in contact with the first gate dielectric layer; and the second gate dielectric layer is in contact with the surface of the first region, and the second polysilicon gate layer is in contact with the second gate dielectric layer.

7. The non-volatile memory cell of claim 6, further comprising: A barrier layer that covers the first gate structure and the first gap wall; A first polycrystalline silicon layer is formed on the upper surface of the barrier layer; as well as A wire electrically connects the first polysilicon layer to the metal layer; The first polysilicon gate layer and the first polysilicon layer form the parallel plate capacitor, and the parallel plate capacitor is a polysilicon / polysilicon parallel plate capacitor.

8. The non-volatile memory cell of claim 6, wherein the metal layer and the first polysilicon gate layer form the parallel plate capacitor, and the parallel plate capacitor is a metal / polysilicon parallel plate capacitor.

9. The non-volatile memory cell of claim 6, wherein during programming, the source line receives a programming voltage, the word line receives an enable voltage, the bit line receives a ground voltage, the voltage received by the control line is set between the ground voltage and the programming voltage, and the voltage received by the auxiliary line is set between half and twice the programming voltage; wherein, During the programming operation, hot holes in the channel induce a hot electron injection effect, and the generated electrons are attracted by the voltage received by the auxiliary line and the control line and injected into the first polysilicon gate layer of the first gate structure.

10. The non-volatile memory cell of claim 9, wherein during the programming operation, the waveform received by the control line is a stepped waveform, a triangular waveform, or a quarter elliptical waveform, and the waveform rises from the initial voltage to the programming voltage.

11. The non-volatile memory cell of claim 6, wherein during an erase operation, the source line receives an erase voltage, the word line receives an enable voltage, the bit line receives the erase voltage or is floating, the control line receives a ground voltage, and the voltage received by the auxiliary line is less than or equal to the ground voltage; wherein, During the erasure operation, the FN tunneling effect occurs, and multiple electrons pass through the first polysilicon gate layer, the first gate dielectric layer, and the first well region.

12. The non-volatile memory cell of claim 2, wherein the first merged doped region, the second merged doped region, the third merged doped region and the fourth merged doped region are merged p-type doped regions; the first well region is an N-type well region; and the second well region is a P-type well region.

13. The non-volatile memory cell of claim 2, wherein the first merged doped region, the second merged doped region and the fourth merged doped region are merged p-type doped regions; the third merged doped region is a merged n-type doped region; and the first well region and the second well region are N-type well regions.

14. The non-volatile memory cell of claim 2, wherein the first merged doped region, the second merged doped region and the fourth merged doped region are merged p-type doped regions; the third merged doped region is a merged n-type doped region; the first well region is an N-type well region; and the second well region is a P-type well region.

15. The non-volatile memory cell as claimed in claim 2, wherein, The first merged doped region includes a first ion implantation region, a first lightly doped drain region, and a second lightly doped drain region. The second merged doped region includes a second ion implantation region and a third lightly doped drain region. The third merged doped region includes a third ion implantation region and a fourth lightly doped drain region. The fourth merged doped region includes a fourth ion implantation region and a fifth lightly doped drain region. The second lightly doped drain region is located below the first gap wall on the first side of the first gate structure. The third lightly doped drain region is located below the first gap wall on the second side of the first gate structure. The fifth lightly doped drain region is located below the second gap wall on the first side of the second gate structure. The first lightly doped drain region is located below the second gap wall on the second side of the second gate structure.

16. The non-volatile memory cell of claim 15, wherein the first distance between the fifth lightly doped drain region and the first lightly doped drain region is greater than the second distance between the second lightly doped drain region and the third lightly doped drain region.

17. The non-volatile memory cell of claim 15, wherein the doping depth of the second lightly doped drain region is equal to the doping depth of the third lightly doped drain region, the doping depth of the third lightly doped drain region is shallower than the doping depth of the fifth lightly doped drain region, the doping depth of the fifth lightly doped drain region is equal to the doping depth of the first lightly doped drain region, and the doping depth of the second lightly doped drain region is shallower than the doping depth of the fourth lightly doped drain region.

18. The non-volatile memory cell of claim 15, wherein the doping depth of the second lightly doped drain region is equal to the doping depth of the third lightly doped drain region, the doping depth of the third lightly doped drain region is equal to the doping depth of the fifth lightly doped drain region, the doping depth of the fifth lightly doped drain region is equal to the doping depth of the first lightly doped drain region, and the doping depth of the second lightly doped drain region is shallower than the doping depth of the fourth lightly doped drain region.

19. The non-volatile memory cell of claim 15, wherein the doping concentration of the second lightly doped drain region is equal to the doping concentration of the third lightly doped drain region, the doping concentration of the third lightly doped drain region is greater than the doping concentration of the fifth lightly doped drain region, the doping concentration of the fifth lightly doped drain region is equal to the doping concentration of the first lightly doped drain region, and the doping concentration of the first lightly doped drain region is equal to the doping concentration of the fourth lightly doped drain region.

20. The non-volatile memory cell of claim 15, wherein the doping concentration of the second lightly doped drain region is equal to the doping concentration of the third lightly doped drain region, the doping concentration of the third lightly doped drain region is equal to the doping concentration of the fifth lightly doped drain region, the doping concentration of the fifth lightly doped drain region is equal to the doping concentration of the first lightly doped drain region, and the doping concentration of the first lightly doped drain region is greater than the doping concentration of the fourth lightly doped drain region.

21. The non-volatile memory cell of claim 1 further includes a deep well region, the lower part of which contacts the semiconductor substrate, and the upper part of which contacts the first well region and the second well region.

Images