Preparation method of gate oxide layer of SiC-based groove type transistor based on low-temperature oxidation and device
By employing low-temperature oxidation processes and barium ion implantation technology, the problems of uneven oxide layer thickness and interface defects in SiC MOSFETs were solved, enabling the fabrication of high-quality gate oxide layers, improving device performance, and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHU RES INST OF XIAN UNIV OF ELECTRONIC SCI & TECH
- Filing Date
- 2025-12-08
- Publication Date
- 2026-04-14
AI Technical Summary
The slow oxidation rate of SiC materials and the uneven oxide layer thickness and interface defects caused by high-temperature oxidation affect device performance and increase costs, thus limiting the performance improvement and industrial application of SiC MOSFETs.
A low-temperature oxidation process is used to form a mask layer through barium ion implantation and ICP etching. The barium ion implantation concentration and oxidation rate are controlled, and combined with annealing, a uniform gate oxide layer is formed.
Growing high-quality gate oxide layers at low temperatures reduces process costs, improves device performance and reliability, and solves the problems of uneven oxide layer thickness and interface defects.
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Figure CN121865672A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method and device for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation. Background Technology
[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor material with advantages such as high critical breakdown electric field strength, high saturated electron mobility, and high thermal conductivity, making it particularly suitable for applications in high-power power transmission and energy conversion technologies. Power electronic devices made from SiC can carry high voltage and high current and operate stably in harsh environments such as high radiation and high temperature.
[0003] SiC materials can be used to fabricate rectifier devices such as Schottky diodes and PIN diodes, as well as switching devices such as MOSFETs, JFETs, and IGBTs. Oxidation is a commonly used process in semiconductor device fabrication. However, SiC itself is chemically very stable, its oxidation rate is very slow, and it requires very high oxidation temperatures and a large thermal budget. Furthermore, the high density of the oxide layer grown by thermal oxidation severely hinders subsequent oxidation processes, resulting in a much slower process and requiring significantly more time and temperature than common Si oxidation. For silicon carbide trench MOSFETs, the different crystal orientations of the trench sidewalls and bottom lead to a significant difference in oxidation rates, resulting in uneven gate oxide layer thickness and severely affecting device electrical performance. In addition, the presence of carbon-related defects during oxidation leads to a higher density of interface defects at the gate oxide interface of the thermally oxidized layer, making the growth of thicker oxide layers for isolation or shielding applications extremely difficult. How to grow a high-quality gate oxide layer on a silicon carbide trench MOSFET substrate has become a pressing technical challenge for those skilled in the art.
[0004] To address the aforementioned problems, existing technologies involve increasing the oxidation temperature of SiC. However, increasing the SiC oxidation temperature necessitates expensive equipment for SiC device fabrication, resulting in extremely low production capacity. Furthermore, the fabricated oxide layer and the interface between the oxide layer and the silicon carbide substrate exhibit numerous functional issues. Extensive research shows that the high interface state density of the SiO2 / SiC structure leads to lower inversion layer mobility and specific on-resistance in SiC MOSFETs, and causes gate oxide-related reliability problems under harsh operating conditions. This severely limits device performance improvement and cost reduction, becoming one of the biggest bottlenecks restricting the technological upgrade and large-scale industrial application of SiC MOSFETs.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a method and device for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation, comprising the following steps: S10. Obtain a silicon carbide substrate, wherein the silicon carbide substrate includes a planar region and a trench region having trenches; S20. A first silicon dioxide mask layer is formed, the first silicon dioxide mask layer covering the sidewall of the trench; S30. Barium ions are implanted using an ion implanter to form an ion implantation layer; The barium ion implantation concentration at the bottom of the trench is higher than that at the sidewall of the trench. S40. Remove the first silicon dioxide mask layer from the sidewall of the trench to expose the sidewall of the trench after barium ion treatment. S50. A second silicon dioxide mask layer is formed, the second silicon dioxide mask layer covering the surface of the planar region, the bottom of the trench and the sidewalls of the trench; S60. Oxidize the ion implantation layer at a temperature of 700-900℃ for 10-120 minutes to form a prefabricated gate oxide layer, and then perform annealing to obtain the gate oxide layer.
[0007] In one embodiment of the present invention, in step S30, the barium ion implantation concentration at the bottom of the trench is C1, and the barium ion implantation concentration on the sidewall of the trench is C2, where C1 = (4~6) × C2.
[0008] In one embodiment of the present invention, in step S30, during the barium ion implantation process using an ion implanter, the barium ion implantation concentration is 1×10⁻⁶. 14 ~1×10 16 cm -2 .
[0009] In one embodiment of the present invention, step S20, forming the first silicon dioxide mask layer includes: A silicon dioxide layer is formed; the silicon dioxide layer covers the surface of the planar region, the bottom of the trench, and the sidewalls of the trench; The silicon dioxide layer is etched to retain the silicon dioxide layer covering the sidewalls of the trench, forming a first silicon dioxide mask layer.
[0010] In one embodiment of the present invention, the etching of the silicon dioxide layer includes: using ICP dry etching, wherein the etching gas is CHF3 and Ar.
[0011] In one embodiment of the present invention, the silicon dioxide in the second silicon dioxide mask layer is amorphous silicon dioxide, and the thickness of the second silicon dioxide mask layer is 20-40 nm.
[0012] In one embodiment of the present invention, the annealing treatment uses supercritical nitric oxide fluid, the annealing temperature is 100-150°C, and the annealing time is 30-90 min.
[0013] In one embodiment of the present invention, in step S10, the silicon carbide substrate includes a silicon carbide substrate and a silicon carbide epitaxial layer located on one side of the silicon carbide substrate, and the trench is located in the silicon carbide epitaxial layer; the depth of the trench is less than the thickness of the silicon carbide epitaxial layer.
[0014] In one embodiment of the present invention, step S40, removing the first silicon dioxide mask layer from the sidewall of the trench, includes using hydrofluoric acid as an etching solution to wet-etch and remove the first silicon dioxide mask layer.
[0015] Secondly, the present invention provides a SiC-based trench transistor device, comprising a gate oxide layer prepared by the above-described preparation method.
[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided by this invention involves performing Ba oxidation on a silicon carbide substrate. 2+ Ion implantation forms an ion implantation layer, which can achieve local amorphization of silicon carbide crystals. The synergistic activation of the oxidation enhancement effect of barium ions can reduce the oxidation temperature in subsequent processes, avoid damage to the material caused by high-temperature treatment, and reduce process costs.
[0017] 2. In the method provided by this invention, a silicon dioxide layer is formed on a silicon carbide substrate. Utilizing the anisotropy of ICP etching, the silicon dioxide layer on the sidewalls of the silicon carbide trench is retained as a first silicon dioxide mask layer. The first silicon dioxide mask layer serves as a barium ion implantation barrier layer, used to control the barium ion implantation dose on the sidewalls and bottom (the greater the thickness, the more obvious the barrier effect; the smaller the barium ion dose on the sidewalls), thereby improving the thickness uniformity of the gate oxide layer formed by subsequent oxidation processing.
[0018] 3. This invention combines the oxidation enhancement effect of barium ions, the amorphization of the silicon carbide surface caused by barium ion implantation bombardment, and the regulation of the oxygen diffusion rate of the amorphous second silicon dioxide mask layer to jointly control the oxidation rate of different regions of the silicon carbide trench. This balances the phenomenon of different gate oxide layer thicknesses on the sidewalls and bottom of the trench in trench transistor devices caused by crystal orientation. It can grow a thick gate oxide layer at low oxidation temperature, while reducing the cost of high-temperature equipment and process thermal budget.
[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the structure of the silicon carbide substrate obtained in step S10 of the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure prepared in step S21 of the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in the embodiments of the present invention. Figure 3 This is a schematic diagram of the structure prepared in step S22 of the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of the structure obtained in step S30 of the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure obtained in step S40 of the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in this embodiment of the invention. Figure 6 This is a schematic diagram of the structure obtained in step S50 of the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in this embodiment of the invention. Figure 7 This is a schematic diagram of the structure after oxidation treatment in step S60 of the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of step S60 annealing in the method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation provided in an embodiment of the present invention.
[0021] Explanation of reference numerals in the attached figures: 1-Silicon carbide substrate; 2-Silicon carbide epitaxial layer; 3-Silicon dioxide layer; 4-First silicon dioxide mask layer; 5-Ion implantation layer; 6-Second silicon dioxide mask layer; 7-Pre-fabricated gate oxide layer; 8-Gate oxide layer. Detailed Implementation
[0022] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a method for preparing the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation and the device proposed in accordance with the present invention.
[0023] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0024] It should be noted that, in this document, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element.
[0025] In the description of this invention, it should be understood that the terms "thickness", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0026] Example 1 This invention provides a method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation, comprising the following steps S10 to S60.
[0027] S10, such as Figure 1 As shown, a silicon carbide substrate is obtained, which includes a planar region and a trench region with trenches.
[0028] For example, a silicon carbide substrate may include a silicon carbide substrate 1 and a silicon carbide epitaxial layer 2 located on one side of the silicon carbide substrate 1, with trenches located in the silicon carbide epitaxial layer 2; the depth of the trenches is less than the thickness of the silicon carbide epitaxial layer 2.
[0029] S20, such as Figure 2 and Figure 3 As shown, a first silicon dioxide mask layer 4 is formed, which covers the sidewalls of the trench.
[0030] For example, in step S20, forming the first silicon dioxide mask layer 4 specifically includes: S21, see also Figure 2 First, silicon dioxide 3 is formed; the silicon dioxide layer 3 covers the surface of the planar area, the bottom of the trench, and the sidewalls of the trench.
[0031] S22, see also Figure 3 The silicon dioxide layer 3 is etched to retain the silicon dioxide layer 3 covering the sidewalls of the trench, forming the first silicon dioxide mask layer 4.
[0032] For example, the silicon dioxide layer 3 can be etched using ICP dry etching, and the etching gas used can be CHF3 and Ar.
[0033] S30, such as Figure 4 As shown, Ba was implanted using an ion implanter. 2+ Ion implantation is performed to form an ion implantation layer 5; wherein, the Ba at the bottom of the trench... 2+ The ion implantation concentration is higher than that of Ba on the sidewall of the trench. 2+ Ion implantation concentration, Ba at the bottom of the trench 2+ Ion implantation concentration equal to the surface Ba of the planar region 2+ Ion implantation concentration. In this step, the silicon carbide substrate is subjected to Ba... 2+ Ion implantation forms an ion implantation layer 5, which can achieve local amorphization of silicon carbide crystals. The introduced barium metal ions work together to enhance the oxidation process in subsequent processes, reduce the temperature in the oxidation process, avoid damage to the material from high-temperature treatment, and reduce process costs.
[0034] Furthermore, a key challenge in oxidizing silicon carbide-based trench structures lies in the different crystal orientations of the trench bottom and sidewalls, meaning different atomic densities and bonding states. The trench sidewalls and bottom are cut along different directions of the SiC crystal (e.g., sidewalls are typically (11-20) or (1-100) planes, and the bottom is typically (0001) plane). The oxidation rate of the trench sidewalls is usually much higher than that of the trench bottom. Thus, under the same oxidation conditions, a thicker oxide layer has grown on the trench sidewalls, while the oxide layer at the bottom is still relatively thin, leading to uneven gate oxide layer thickness and affecting the overall performance of the semiconductor device. In the embodiments provided by this invention, a silicon dioxide layer is first formed on the silicon carbide substrate. Utilizing the anisotropy of ICP etching, only the silicon dioxide layer on the sidewalls of the silicon carbide trench is retained as the first silicon dioxide mask layer 4. The first silicon dioxide mask layer 4 serves as a barium ion implantation barrier layer, used to regulate the barium ion implantation dose on the sidewalls and bottom (the greater the thickness, the more obvious the blocking effect, and the smaller the barium ion dose on the sidewalls). This ensures that the barium ion implantation concentration at the bottom of the trench and on the upper surface of the planar region is greater than that on the trench sidewalls, thereby improving the uniformity of the gate oxide layer thickness formed by subsequent oxidation processing.
[0035] In some examples, depending on the specific application, the anisotropy of ICP etching can be utilized to retain the silicon dioxide layer at the bottom and sidewalls of the silicon carbide trench and make the silicon dioxide layer thickness at the bottom and sidewalls of the silicon carbide trench different (the sidewall thickness is greater than the bottom) to serve as a first silicon dioxide mask layer to adjust the barium ion implantation concentration.
[0036] In some embodiments, the Ba at the bottom of the trench 2+ The ion implantation concentration is C1, and the Ba content on the sidewalls of the trench is... 2+ The ion implantation concentration is C2, where C1 = (4~6) × C2. That is, the bottom of the trench contains Ba. 2+ Ion implantation concentration is Ba on the sidewall of the trench. 2+ Four to six times the ion implantation concentration.
[0037] In some examples, the use of an ion implanter for Ba 2+ During ion implantation, Ba 2+ The ion implantation dose is 1×10 14 ~1×10 16 cm -2 .
[0038] S40, such as Figure 5 As shown, the first silica mask layer 4 is removed from the sidewalls of the trench to expose Ba. 2+ The sidewall of the trench after ion treatment.
[0039] For example, in step S40, hydrofluoric acid can be used as the etching solution to remove the first silicon dioxide mask layer 4 of the trench sidewall. That is, the first silicon dioxide mask layer 4 is removed by wet etching.
[0040] S50, such as Figure 6 As shown, a second silicon dioxide mask layer 6 is formed, which covers the surface of the planar area, the bottom of the trench, and the sidewalls of the trench.
[0041] In one example, the silicon dioxide in the second silicon dioxide mask layer 6 is amorphous silicon dioxide, and the thickness of the second silicon dioxide mask layer 6 is 20–40 nm. First, the amorphous second silicon dioxide mask layer 6, covering the silicon carbide surface, can control problems such as gate oxide surface roughening and oxidation voids caused by the oxidation rate (thickness is inversely proportional to the oxidation rate). Second, compared to silicon dioxide layers produced by conventional oxidation processes, the lower density and better oxygen diffusion rate of the amorphous second silicon dioxide mask layer 6 are beneficial for promoting the oxidation process. Finally, as the oxidation process increases, the film density and quality of the second silicon dioxide mask layer 6 improve, which can also synergistically enhance the performance of the gate oxide layer.
[0042] S60, such as Figure 7 and Figure 8 As shown, oxidation treatment at 700–900℃ for 10–120 min oxidizes the ion-implanted layer 5 to form the prefabricated gate oxide layer 7, followed by annealing to obtain the gate oxide layer 8. At 700–900℃, barium ion activation can be achieved simultaneously with silicon carbide oxidation. The incorporated barium element has strong electropositivity and can vigorously adsorb oxygen molecules, accelerating the oxidation reaction at the silicon carbide interface while also polarizing the Si-C bonds in the silicon carbide crystal. This reduces the energy required for Si-C bond breaking and Si-O formation during the oxidation process, further increasing the oxidation rate.
[0043] In one example, the annealing process can be performed using supercritical nitric oxide fluid, with an annealing temperature of 100–150°C and an annealing time of 30–90 minutes. Annealing can repair interface defects in the gate oxide layer, reduce the interface state density, and improve the pressure resistance of the gate oxide layer.
[0044] Example 2 This invention also provides a SiC-based trench transistor device, which includes a gate oxide layer fabricated using the method described in the above embodiments. For example, the device can be a SiC-based trench MOSFET device, a SiC-based trench JFET device, or a SiC-based trench IGBT device, etc. Because this SiC-based trench transistor device possesses the gate oxide layer obtained by the above fabrication method, it also exhibits corresponding excellent effects, which will not be elaborated further here.
[0045] Example 3 This invention provides a specific method for preparing the gate oxide layer of a SiC-based trench MOSFET based on low-temperature oxidation.
[0046] 1. For example Figure 1 As shown, a silicon carbide MOSFET substrate with etched trenches is obtained. The silicon carbide MOSFET substrate includes a silicon carbide substrate 1 and a silicon carbide epitaxial layer 2 located on one side of the silicon carbide substrate 1. The trenches are located in the silicon carbide epitaxial layer 2; the depth of the trenches is less than the thickness of the silicon carbide epitaxial layer 2. The side of the silicon carbide MOSFET substrate with trenches can be divided into a planar region and a trench region with trenches.
[0047] 2. For example Figure 2 As shown, a silicon dioxide layer 3 is grown on the surface of a silicon carbide substrate using LPCVD (low-pressure chemical vapor deposition). The silicon dioxide layer 3 is a mask layer covering the surface of the planar area, the bottom of the trench, and the sidewalls of the trench.
[0048] 3. For example Figure 3 As shown, the silicon dioxide layer 3 on the surface of the anisotropic removal or reduction planar region and the bottom of the trench is etched using ICP (inductively coupled plasma etching) dry etching. Part of the silicon dioxide is retained on the sidewalls of the trench. CHF3 and Ar are selected as the etching gases to form a first silicon dioxide mask layer 4 that only covers the sidewalls of the trench.
[0049] 4. For example Figure 4 As shown, using the first silica mask layer 4 covering the sidewalls of the trench as a mask, Ba was implanted using an ion implanter. 2+ Ion implantation was performed to form ion implantation layer 5. The implantation concentration of barium ions was 1 × 10⁻⁶. 14 ~1×10 16 cm -2 And satisfy the bottom Ba of the trench 2+ Ion implantation concentration is Ba on the sidewall of the trench. 2+ Five times the ion implantation concentration.
[0050] 5. For example Figure 5 As shown, the first silicon dioxide mask layer 4 is removed by wet etching using hydrofluoric acid as the etchant.
[0051] 6. For example Figure 6 As shown, PECVD is used in Ba... 2+ An amorphous second silicon dioxide mask layer 6 is deposited on the surface of the processed silicon carbide substrate. The second silicon dioxide mask layer 6 covers the surface of the planar region, the bottom of the trench, and the sidewalls of the trench. The thickness of the second silicon dioxide mask layer 6 is 30 nm.
[0052] 7. For example Figure 7As shown, silicon carbide at the interface near the second silicon dioxide mask layer 6 is oxidized to SiO2 using a low-temperature thermal oxidation process at an oxidation temperature of 900℃ and an oxidation time of 60min.
[0053] 8. For example Figure 8 As shown, a gate oxide layer 8 was prepared by supercritical nitric oxide fluid annealing at a temperature of 120°C for 30 minutes.
[0054] The second silicon dioxide mask layer 6 can then be removed to prepare the gate and other functional layers, thereby obtaining a silicon carbide-based trench MOSFET device.
[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0056] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation, characterized in that, Includes the following steps: S10. Obtain a silicon carbide substrate, wherein the silicon carbide substrate includes a planar region and a trench region having trenches; S20. A first silicon dioxide mask layer is formed, the first silicon dioxide mask layer covering the sidewall of the trench; S30. Barium ions are implanted using an ion implanter to form an ion implantation layer; The barium ion implantation concentration at the bottom of the trench is higher than that at the sidewall of the trench. S40. Remove the first silicon dioxide mask layer from the sidewall of the trench to expose the sidewall of the trench after barium ion treatment. S50. A second silicon dioxide mask layer is formed, the second silicon dioxide mask layer covering the surface of the planar region, the bottom of the trench and the sidewalls of the trench; S60. Oxidize the ion implantation layer at a temperature of 700-900℃ for 10-120 minutes to form a prefabricated gate oxide layer, and then perform annealing to obtain the gate oxide layer.
2. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to claim 1, characterized in that, In step S30, the barium ion implantation concentration at the bottom of the trench is C1, and the barium ion implantation concentration on the sidewall of the trench is C2, where C1 = (4~6) × C2.
3. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to claim 2, characterized in that, In step S30, during the barium ion implantation process using an ion implanter, the barium ion implantation concentration is 1×10⁻⁶. 14 ~1×10 16 cm -2 .
4. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to claim 1, characterized in that, In step S20, forming the first silicon dioxide mask layer includes: A silicon dioxide layer is formed; the silicon dioxide layer covers the surface of the planar region, the bottom of the trench, and the sidewalls of the trench; The silicon dioxide layer is etched to retain the silicon dioxide layer covering the sidewalls of the trench, forming a first silicon dioxide mask layer.
5. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to claim 4, characterized in that, The etching of the silicon dioxide layer includes: using ICP dry etching, with CHF3 and Ar as the etching gases.
6. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to any one of claims 1-5, characterized in that, The silicon dioxide in the second silicon dioxide mask layer is amorphous silicon dioxide, and the thickness of the second silicon dioxide mask layer is 20-40 nm.
7. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to claim 6, characterized in that, The annealing process uses supercritical nitric oxide fluid, with an annealing temperature of 100–150°C and an annealing time of 30–90 min.
8. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to claim 7, characterized in that, In step S10, the silicon carbide substrate includes a silicon carbide substrate and a silicon carbide epitaxial layer located on one side of the silicon carbide substrate, and the trench is located in the silicon carbide epitaxial layer; the depth of the trench is less than the thickness of the silicon carbide epitaxial layer.
9. The method for fabricating the gate oxide layer of a SiC-based trench transistor based on low-temperature oxidation according to claim 8, characterized in that, In step S40, removing the first silicon dioxide mask layer from the sidewall of the trench includes using hydrofluoric acid as an etching solution to wet-etch and remove the first silicon dioxide mask layer.
10. A SiC-based trench transistor device, characterized in that, This includes the gate oxide layer prepared by the preparation method according to any one of claims 1-9.