Display substrate

Abstract

The display substrate is provided with a display area and a peripheral area at least partially surrounding the display area, and comprises a substrate, a first barrier dam, a first power signal line and a crack detection circuit, the first barrier dam is arranged on the substrate and in the peripheral area, and at least partially surrounds the display area; the first power signal line is arranged between the substrate and the first barrier dam and at least extends in the peripheral area; the crack detection circuit is arranged between the substrate and the first barrier dam, is arranged in the peripheral area and at least partially surrounds the display area, and the orthographic projection of the crack detection circuit on the substrate and the orthographic projection of the first barrier dam on the substrate are at least partially overlapped. The display substrate can realize a narrow frame design and has relatively high packaging reliability.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202210307455.2, entitled "Display Substrate", filed on March 25, 2022. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate. Background Technology

[0003] OLED (Organic Light Emitting Diode) displays offer a range of advantages, including self-illumination, high contrast, high definition, wide viewing angles, low power consumption, fast response times, and low manufacturing costs. As a result, they have become a key development direction for next-generation display devices and are attracting increasing attention. Currently, OLED displays are evolving towards narrower bezels and larger screen sizes to meet user demands. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate having a display area and a peripheral area at least partially surrounding the display area, and including a substrate, a first barrier dam, a first power signal line, and a crack detection circuit. The first barrier dam is disposed on the substrate and in the peripheral area, and at least partially surrounds the display area. The first power signal line is disposed between the substrate and the first barrier dam, and extends at least in the peripheral area, wherein at least a portion of the boundary of the first power signal line away from the display area is projected onto the substrate in an orthographic projection within the orthographic projection of the first barrier dam on the substrate. The crack detection circuit is disposed between the substrate and the first barrier dam, and in the peripheral area, and at least partially surrounds the display area, wherein the orthographic projection of the crack detection circuit on the substrate at least partially overlaps with the orthographic projection of the first barrier dam on the substrate.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, the crack detection circuit includes a first trace portion disposed on the substrate and a second trace portion disposed on the side of the first trace portion away from the substrate. The second trace portion is electrically connected to the first trace portion through a via, and the orthographic projection of the second trace portion on the substrate is located inside the orthographic projection of the first barrier dam on the substrate.

[0006] For example, in at least one embodiment of the display substrate provided in this disclosure, the second trace portion is disposed on the same layer as the first power signal line.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the second trace portion is disposed on the side of the first power signal line away from the display area, and the first trace portion is disposed on the side of the second trace portion away from the display area.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the first trace portion includes a plurality of first traces, the orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is located inside the orthographic projection of the plurality of first traces on the substrate, or the orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is located inside the orthographic projection of the interval between two adjacent first traces among the plurality of first traces on the substrate.

[0009] For example, in at least one embodiment of the display substrate provided in this disclosure, the orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is located at the middle of the orthographic projection of one of the plurality of first traces on the substrate, or the orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is within the orthographic projection of two adjacent first traces among the plurality of first traces, and the distance between the orthographic projection of the first trace away from the display area among the two adjacent first traces on the substrate is greater than or equal to 3 micrometers.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the display area includes a plurality of sub-pixels, each of the plurality of sub-pixels including a light-emitting device and a pixel driving circuit for driving the light-emitting device, the pixel driving circuit including a thin-film transistor and a storage capacitor, the thin-film transistor including a gate disposed on the substrate and a source / drain electrode disposed on the side of the gate away from the substrate, the storage capacitor including a first capacitor electrode disposed on the substrate and a second capacitor electrode disposed on the side of the first capacitor electrode away from the substrate, the gate and the first capacitor electrode being disposed in the same layer, the second capacitor electrode being disposed in the same layer as the first trace portion, and the source / drain electrode being disposed in the same layer as the second trace portion.

[0011] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a crack barrier dam, wherein the crack barrier dam is disposed on the side of the crack detection circuit away from the display area.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the peripheral region includes an inorganic layer, and the crack barrier dam includes a groove disposed in the inorganic layer.

[0013] For example, in at least one embodiment of the present disclosure, the display area further includes a planarization layer disposed on the side of the pixel driving circuit away from the substrate, a pixel defining layer disposed on the side of the planarization layer away from the substrate, and a spacer disposed on the side of the pixel defining layer away from the substrate, wherein the first barrier dam is disposed in the same layer as at least one of the planarization layer, the pixel defining layer, and the spacer.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of at least a portion of the boundary of the crack detection circuit away from the display area on the substrate is located inside the orthographic projection of the first barrier dam on the substrate.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the crack detection circuit on the substrate at least partially overlaps with the orthographic projection of the first power signal line on the substrate.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the first power signal line is disposed on the side of the crack detection circuit away from the substrate.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the peripheral area further includes at least one auxiliary trace, and the first power signal line is electrically connected to the at least one auxiliary trace through a via, so as to be connected in parallel with the at least one auxiliary trace.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the display area includes a plurality of sub-pixels, each of the plurality of sub-pixels including a light-emitting device and a pixel driving circuit for driving the light-emitting device, the pixel driving circuit including a thin-film transistor and a storage capacitor, the thin-film transistor including a gate disposed on the substrate and a source / drain electrode disposed on the side of the gate away from the substrate, the storage capacitor including a first capacitor electrode disposed on the substrate and a second capacitor electrode disposed on the side of the first capacitor electrode away from the substrate, the gate and the first capacitor electrode being disposed on the same layer, the second capacitor electrode being disposed on the same layer as the at least one auxiliary trace, and the source / drain electrode being disposed on the same layer as the first power signal line.

[0019] For example, in at least one embodiment of the display substrate provided in this disclosure, the crack detection circuit is disposed on the same layer as the at least one auxiliary trace.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the thin-film transistor further includes an active layer disposed on the side of the gate near the substrate, and the display area further includes a light-shielding pattern disposed between the active layer and the substrate, wherein the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the light-shielding pattern on the substrate.

[0021] For example, in at least one embodiment of the display substrate provided in this disclosure, the crack detection circuit is disposed on the same layer as the light-shielding pattern.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the crack detection circuit on the substrate at least partially overlaps with the orthographic projection of the at least one auxiliary trace on the substrate.

[0023] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a crack barrier dam disposed in the peripheral region and on the side of the first barrier dam near the display region, at least partially surrounding the display region, wherein the orthographic projection of the crack barrier dam on the substrate at least partially overlaps with the orthographic projection of the first power signal line on the substrate.

[0024] For example, in a display substrate provided in at least one embodiment of this disclosure, the crack barrier dam is disposed in the same layer as at least one of the gate and the second capacitor electrode.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, the crack barrier dam includes a plurality of sub-crack barrier dams spaced apart in the extension direction of the crack barrier dam.

[0026] For example, in a display substrate provided in at least one embodiment of this disclosure, the length of each of the plurality of sub-crack barrier dams is less than 50 mm in the extension direction of the crack barrier dam.

[0027] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a second barrier dam disposed on the side of the first barrier dam near the display area and on the side of the crack barrier dam away from the substrate, wherein the orthographic projection of the crack barrier dam on the substrate at least partially overlaps with the orthographic projection of the second barrier dam on the substrate.

[0028] For example, in a display substrate provided in at least one embodiment of this disclosure, the first power signal line is configured to provide a first power signal to the display area, and the display substrate further includes a second power signal line, which is configured to provide a second power signal to the display area, wherein the potential of the second power signal is higher than the potential of the first power signal. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0030] Figure 1 This is a schematic diagram showing the circuit and structural layout of the peripheral area of ​​a display substrate.

[0031] Figure 2 This is a plan view of a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 3 for Figure 2 An enlarged schematic diagram of the display substrate in the area within the dashed box;

[0033] Figure 4 for Figure 3 A schematic diagram of the cross-section of the display substrate along line AA;

[0034] Figure 5A A partial cross-sectional schematic diagram of a sub-pixel of the display area of ​​a display substrate provided in at least one embodiment of the present disclosure;

[0035] Figure 5B A schematic cross-sectional view of another portion of a sub-pixel of the display area of ​​a display substrate provided in at least one embodiment of the present disclosure;

[0036] Figure 6A for Figure 2 Another enlarged schematic diagram of the display substrate in the area within the dashed frame;

[0037] Figure 6B for Figure 6A A schematic diagram of the cross-section of the display substrate along the BB line;

[0038] Figure 7A for Figure 2 A further enlarged schematic diagram of the display substrate in the area within the dashed frame;

[0039] Figure 7B for Figure 7A A schematic diagram of the cross-section of the display substrate along the DD line;

[0040] Figure 8A for Figure 2 Another enlarged schematic diagram of the display substrate in the area within the dashed frame;

[0041] Figure 8B for Figure 8A A schematic diagram of the cross-section of the display substrate along the EE line;

[0042] Figure 9 This is a scanning electron microscope (SEM) schematic diagram of a broken encapsulation layer next to a first trace in a display substrate.

[0043] Figure 10 A plan view of another display substrate provided for at least one embodiment of this disclosure;

[0044] Figure 11 for Figure 10 A schematic cross-sectional view of the display substrate along the CC line;

[0045] Figure 12 for Figure 10 Another cross-sectional view of the display substrate along the CC line;

[0046] Figure 13 A schematic cross-sectional view of another portion of a sub-pixel of the display area of ​​a display substrate provided in at least one embodiment of the present disclosure;

[0047] Figure 14 for Figure 10 Another cross-sectional view of the display substrate along the CC line;

[0048] Figure 15 for Figure 10 An enlarged schematic diagram of the display substrate in the area within the dashed box;

[0049] Figure 16 for Figure 10 Another cross-sectional view of the display substrate along the CC line; and

[0050] Figure 17 This is a schematic diagram showing the circuit and structure layout of the peripheral area of ​​a display substrate provided in at least one embodiment of the present disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0053] In display panels, how to further narrow the bezels while ensuring the reliability of the display panel's packaging under narrow bezels is a common goal for those skilled in the art.

[0054] In display panels, a panel crack detection (PCD) circuit is typically included to detect cracks. The circuit pattern in the PCD circuit requires a protective layer, commonly of two types: organic and inorganic. When using an organic protective layer, an inorganic layer is usually placed on top to prevent the organic layer from absorbing water and swelling. However, in actual manufacturing processes, due to variations in process parameters, the inorganic layer thickness is often insufficient. At locations with slits, the inorganic layer is prone to breakage, exposing the organic protective layer and leading to water absorption, swelling, and encapsulation failure. Using an inorganic protective layer requires an additional step in its fabrication process, which reduces production capacity.

[0055] Additionally, when designing narrow bezels, for example, Figure 1 This diagram illustrates the structural arrangement of the bezel of a display substrate, specifically the non-display area surrounding the display area. Figure 1 As shown, in some narrow bezel display substrates, the non-display area is provided with an edge cutting area A, a crack blocking area B, a power supply trace area C, a circuit setting area D, and a connection area E.

[0056] Edge cutting area A is a reserved area for the cutting operation of forming a single display substrate by cutting the master plate. The width of this area is typically about 110 micrometers. Crack blocking area B is provided with crack blocking structure and crack inspection circuit to deal with cracks that may be formed in the display substrate during the cutting operation when forming a single display substrate. The width of this area is typically about 100 micrometers. Power trace area C is, for example, a setting area for a power bus that transmits low-level voltage signals to multiple sub-pixels in the display area. The width of this area is typically about 150 micrometers. Circuit setting area D is a setting area for GOA (Gate on Array) driving circuit that provides driving signals to the pixel driving circuits of multiple sub-pixels in the display area. The width of this area is typically about 350 micrometers. Connection area E is an area where the structure (e.g., traces and circuits) of the peripheral area is connected to the structure (e.g., traces and circuits) of the display area. The width of this area is typically about 90 micrometers.

[0057] The sum of the widths of the aforementioned regions is the bezel width of the display substrate, which is approximately 850 micrometers. This width is the narrowest width achievable through precise design based on the basic functions of the circuitry and functional structures in each region. This width is difficult to reduce further, thus posing a greater challenge to engineers to further narrow the bezel.

[0058] At least one embodiment of this disclosure provides a display substrate having a display area and a peripheral area at least partially surrounding the display area, and including a substrate, a first barrier dam, a first power signal line, and a crack detection circuit. The first barrier dam is disposed on the substrate and in the peripheral area, and at least partially surrounds the display area. The first power signal line is disposed between the substrate and the first barrier dam, and extends at least in the peripheral area. The orthographic projection of at least a portion of the boundary of the first power signal line away from the display area on the substrate is located inside the orthographic projection of the first barrier dam on the substrate. The crack detection circuit is disposed between the substrate and the first barrier dam, and in the peripheral area, and at least partially surrounds the display area. The orthographic projection of the crack detection circuit on the substrate at least partially overlaps with the orthographic projection of the first barrier dam on the substrate.

[0059] In the display substrate provided in the embodiments of this disclosure, by designing the positional relationship between the crack inspection circuit and its nearby first power signal line and first barrier dam, the bezel of the display substrate can be further narrowed, for example, the bezel can be reduced to below 720 micrometers, such as achieving an extremely narrow bezel design of 600 micrometers or 650 micrometers; and, while achieving the barrier function, the first barrier dam can also achieve the protection function of the crack inspection circuit, and facilitate the subsequent packaging process, thereby improving the packaging reliability.

[0060] The display substrate of this disclosure will be described below through several specific embodiments.

[0061] This disclosure provides a display substrate in at least one embodiment. Figure 2 A planar schematic diagram of the display substrate is shown. Figure 3 It shows Figure 2 An enlarged schematic diagram of the display substrate in the area within the dashed box. Figure 4 It shows Figure 3 A schematic cross-sectional view of the display substrate along line AA. (See diagram below.) Figures 2-4 As shown, the display substrate has a display area AA and a peripheral area NA that at least partially surrounds the display area AA, and includes a substrate 110, a first barrier dam D1, a first power signal line VSS, and a crack detection circuit PCD.

[0062] A first barrier dam D1 is disposed on the substrate 110 and in the peripheral region NA, at least partially surrounding the display region AA, for example, surrounding the display region AA around its perimeter, to prevent material formed in the display region AA (e.g., inkjet printing) from flowing into the peripheral region NA. A first power signal line VSS is disposed between the substrate 110 and the first barrier dam D1, and extends at least in the peripheral region NA, for example, extending from the display region AA to the peripheral region NA in some embodiments. The orthographic projection of at least a partial boundary B2 of the first power signal line VSS away from the display region AA onto the substrate 110 lies within the orthographic projection of the first barrier dam D1 onto the substrate 110. Thus, the first barrier dam D1 covers at least a partial boundary B2 of the first power signal line VSS away from the display region AA to protect the first power signal line VSS.

[0063] The crack detection circuit PCD is disposed between the substrate 110 and the first barrier dam D1, and is disposed in the peripheral area NA, and at least partially surrounds the display area AA, for example, surrounding the display area AA on the left, upper and right sides. The crack detection circuit PCD can detect whether there are defects such as cracks caused by cutting on the display substrate.

[0064] The orthographic projection of the crack detection circuit PCD on the substrate 110 at least partially overlaps with the orthographic projection of the first barrier dam D1 on the substrate 110. Therefore, the first barrier dam D1 can also protect at least a portion of the crack detection circuit PCD, eliminating the need for an additional protective layer. This simplifies the fabrication process of the display substrate. Furthermore, this arrangement can shorten the distance from the first barrier dam D1 to the dicing line CL (see reference). Figure 6A , Figure 7A and Figure 8A The distance is increased to further narrow the border.

[0065] For example, in some embodiments, the crack detection circuit PCD includes a first trace portion P1 disposed on a substrate 110 and a second trace portion P2 disposed on the side of the first trace portion P1 away from the substrate 110. The second trace portion P2 is electrically connected to the first trace portion P1 through a via V. The orthographic projection of the second trace portion P2 on the substrate 110 is located inside the orthographic projection of the first barrier dam D1 on the substrate 110. For example, the first barrier dam D1 can be directly disposed above the second trace portion P2 to contact the second trace portion P2 and achieve a protective function.

[0066] In the embodiments of this disclosure, by setting the crack detection circuit PCD to include a first trace portion P1 and a second trace portion P2 that are electrically connected and located in different conductive layers, it is possible to prevent adverse phenomena such as electrostatic interference from long traces (long-distance traces), thereby achieving the technical effect of anti-static.

[0067] For example, in some embodiments, the second trace portion P2 is disposed on the same layer as the first power signal line VSS to simplify the fabrication process of the display substrate.

[0068] It should be noted that in the embodiments of this disclosure, "same-layer setting" means that two functional layers or structural layers are formed on the same layer and with the same material in the layer structure of the display substrate. That is, in the manufacturing process, the two functional layers or structural layers can be formed from the same material layer and can be formed with the same patterning process to form the required pattern and structure.

[0069] For example, in some embodiments, the second trace portion P2 is disposed on the side of the first power signal line VSS away from the display area AA, and the first trace portion P1 is disposed on the side of the second trace portion P2 away from the display area AA. That is, the first trace portion P1, the second trace portion P2, and the first power signal line VSS are arranged sequentially in the direction close to the display substrate AA.

[0070] For example, in some embodiments, the first trace portion P1 includes multiple first traces 111 (i.e., the number of first traces arranged side by side on one side of the display substrate), such as two to six first traces 111, and the second trace portion P2 includes at least one second trace 112 (i.e., the number of second traces arranged side by side on one side of the display substrate), such as one to three second traces 112. The embodiments of this disclosure do not specifically limit this.

[0071] For example, the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA on the substrate 110 lies inside the orthographic projection of the plurality of first traces 111 on the substrate, that is, the boundary B1 of the first barrier dam D1 away from the display area AA lies directly above any one of the plurality of first traces 111; or, in other embodiments, the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA on the substrate 110 lies inside the orthographic projection of the interval between two adjacent first traces 111 on the substrate 110, that is, the boundary B1 of the first barrier dam D1 away from the display area AA lies directly above the interval between the plurality of first traces 111.

[0072] For example, in some embodiments, the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA onto the substrate 110 is located at the middle of the orthographic projection of one of the multiple first traces 111 onto the substrate 110, such as... Figure 6A As shown, the boundary B1 of the first barrier dam D1, away from the display area AA, is located in the positive direction of the middle part of a first routing line 111; or, in other embodiments, such as Figure 3 As shown, the orthographic projection of the boundary B1 of the first barrier dam D1 away from the display area AA on the substrate 110 is within the orthographic projection of two adjacent first traces 111 on the substrate 110, and the distance L1 between the first trace 111 away from the display area AA and the orthographic projection of the first trace 111 on the substrate 110 is greater than or equal to 3 micrometers, so as to have sufficient spacing with the first trace 111.

[0073] For example, Figure 7A It also illustrates a case where the orthographic projection of the boundary B1 of the first barrier dam D1, which is far from the display area AA, onto the substrate 110 is such that the spacing between two adjacent first traces 111 is within the orthographic projection onto the substrate 110, and the distance L1 between this boundary B1 and the orthographic projection of the first trace 111 far from the display area AA onto the substrate 110 is greater than or equal to 3 micrometers. Figure 7B for Figure 7A A schematic cross-sectional view of the display substrate along the DD line.

[0074] With the above configuration, the inorganic encapsulation layer formed above the first barrier dam D1 can be prevented from breaking at the boundary of the first trace 111. For example, when the boundary B1 of the first barrier dam D1 away from the display area AA and its orthographic projection on the substrate 110 are within the orthographic projection of two adjacent first traces 111 on the substrate 110, and the distance L1 between the boundary B1 and the orthographic projection of the first trace 111 away from the display area AA on the substrate 110 is relatively close, for example, less than 3 micrometers, then... Figure 9 As shown, the first inorganic encapsulation layer 1051 (described in detail later) formed above the first barrier dam D1 is prone to breakage next to the first trace 111, thus affecting the encapsulation effect of the display substrate. Through the above-described configuration of this embodiment, the risk of breakage of the first inorganic encapsulation layer 1051 can be effectively avoided, improving the encapsulation effect of the display substrate.

[0075] For example, in some embodiments, such as Figure 2 As shown, the crack detection circuit PCD can include circuits that use two principles to detect whether the display substrate has broken: a bright line detection circuit PCD1 and a resistance detection circuit PCD2. The bright line detection circuit PCD1 can be connected to some sub-pixels via a bright line detection data line PD. It detects whether the bright line detection circuit PCD1 is open-circuited by detecting whether the sub-pixels can be lit, and thus infers whether the display substrate has broken. The resistance detection circuit PCD2, for example, includes two ends. A detection circuit detects the resistance of the resistance detection circuit PCD2 to determine whether the resistance detection circuit PCD2 is open-circuited, and thus infers whether the display substrate has broken. For example, the bright line detection circuit PCD1 and the resistance detection circuit PCD2 can be connected to a circuit board FPC, and the detection process can be controlled by the circuit board FPC.

[0076] For example, in some embodiments, such as Figure 2 As shown, the display area AA includes multiple sub-pixels S, each of which includes a light-emitting device EN and a pixel driving circuit for driving the light-emitting device EM. The pixel driving circuit may include multiple thin-film transistors and storage capacitors, and may be configured in various structures such as 2T1C (i.e., including two thin-film transistors and one storage capacitor), 7T1C (i.e., including seven thin-film transistors and one storage capacitor), 8T2C (i.e., including eight thin-film transistors and two storage capacitors), etc. The embodiments of this disclosure do not limit the specific form of the pixel driving circuit.

[0077] For example, Figure 5A A partial cross-sectional schematic diagram of a sub-pixel S is shown, as follows: Figure 5AAs shown, the pixel driving circuit includes a thin-film transistor (TFT) T and a storage capacitor C. The TFT C includes an active layer 1021, a gate 1022, and source / drain electrodes 1023 and 1024 disposed on the side of the gate 1022 away from the substrate 110. The storage capacitor C includes a first capacitor electrode 1031 disposed on the substrate 110 and a second capacitor electrode 1032 disposed on the side of the first capacitor electrode 1031 away from the substrate 110. The gate 1022 and the first capacitor electrode 1031 are disposed on the same layer, the second capacitor electrode 1032 is disposed on the same layer as the first trace portion P1, and the source / drain electrodes 1023 and 1024, the first power signal line VSS, and the second trace portion P2 are disposed on the same layer. This simplifies the fabrication process of the display substrate.

[0078] For example, a light-emitting device (EM) includes a first electrode layer 1041 (e.g., an anode layer), a light-emitting material layer 1042, and a second electrode layer 1043 (e.g., a cathode layer). For example, the first electrode layer 1041 is electrically connected to a pixel driving circuit (e.g., the source / drain electrodes 1023 of a thin-film transistor T), and the second electrode layer 1043 is electrically connected to a first power signal line VSS. Under the voltage applied to the first electrode layer 1041 and the second electrode layer 1043, the light-emitting material layer 1042 can emit light.

[0079] For example, Figure 6A It shows Figure 2 The diagram shows another plane view of the display substrate within the dashed box area. Figure 6B for Figure 6A A schematic cross-sectional view of the display substrate along the BB line. (See attached diagram.) Figure 6A and Figure 6B As shown, in some embodiments, the display substrate may further include crack-blocking dams D3, such as multiple crack-blocking dams D3. Figure 6A and Figure 6B The diagram shows five crack-blocking dams as an example. Crack-blocking dams D3 are positioned on the side of the crack detection circuit PCD away from the display area AA, and at least partially surround the display area AA. Crack-blocking dams D3 can prevent crack formation and propagation, for example, preventing cracks formed during the cutting of the display substrate or preventing existing cracks from propagating to the display area AA, thereby protecting the display substrate in the surrounding area NA.

[0080] For example, in some embodiments, the peripheral region NA includes an inorganic layer IN, and the crack barrier dam D3 includes a groove GV disposed in the inorganic layer IN. Since most cracks are generated in the inorganic layer under stress and propagate along the inorganic layer, etching part of the inorganic layer, for example, to form multiple inorganic grooves, can effectively prevent microcracks from propagating to the display area AA. For example, the inorganic layer IN can be disposed in the same layer as at least one (e.g., all) of the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015. For example, a partial planarization layer 1016 covers the crack barrier dam D3 to protect it.

[0081] It should be noted that, for the sake of brevity, Figure 4 , Figure 6B And afterwards Figure 7B and Figure 8B The structures of the first gate insulating layer 1014A, the second gate insulating layer 1014B, the interlayer insulating layer 1015, the barrier layer 1112, the buffer layer 1013, and the substrate 110 are not shown separately. The stacking relationship of these structures can be found in [reference needed]. Figure 5A and Figure 5B .

[0082] For example, in some embodiments, such as Figure 2 As shown, the display substrate may further include a second power supply line VDD, a first power signal line VSS configured to provide a first power signal to the display area AA, and a second power signal line VDD configured to provide a second power signal to the display area AA. The potential of the second power signal is higher than that of the first power signal, that is, the second power signal is a high-level signal and the first power signal is a low-level signal.

[0083] For example, in some embodiments, such as Figure 2 As shown, the peripheral area NA of the display substrate may also include trace fan-out areas F1 / F2, bending area B, and integrated circuit ICs. The trace fan-out areas F1 / F2 include multiple connecting traces to connect multiple leads (such as data lines) from the display area AA to the integrated circuit ICs. The bending area B has good flexibility to bend the integrated circuit ICs and circuit boards (FPCs) to the non-display side of the display substrate, thereby achieving a narrow bezel design.

[0084] For example, in some embodiments, such as Figure 5A and Figure 5BAs shown, the display area also includes a planarization layer 1016 disposed on the side of the pixel driving circuit away from the substrate 110, a pixel defining layer 1017 disposed on the side of the planarization layer 1016 away from the substrate 110, and a spacer 1018 disposed on the side of the pixel defining layer 1017 away from the substrate. The planarization layer 1016 can serve to planarize the pixel driving circuit. The pixel defining layer 1017 includes multiple sub-pixel openings PO, which expose the first electrode layer 1041 of multiple light-emitting devices EM to define the light-emitting area of ​​the sub-pixels. The spacer 1018 can serve as a spacer and support, for example, supporting devices such as photomasks that may be used during the fabrication process.

[0085] For example, the first barrier dam D1 may be disposed in the same layer as at least one of the planarization layer 1016, the pixel defining layer 1017, and the spacer 1018. For example, in some embodiments, such as Figure 4 As shown, the first barrier dam D1 may include three sub-layers D11 / D12 / D13, which are disposed in the same layer as the planarization layer 1016, the pixel defining layer 1017 and the spacer 1018, respectively, to simplify the manufacturing process of the display substrate.

[0086] For example, in other embodiments, such as Figure 5B As shown, the display substrate also includes a connection electrode CEL disposed on the side of the pixel driving circuit away from the substrate. This connection electrode CEL electrically connects the pixel driving circuit to the first electrode layer 1041. At this time, another planarization layer 1019 is also disposed on the side of the connection electrode CEL away from the substrate. For example, the first barrier dam D1 can be disposed in the same layer as at least one of the planarization layer 1016, the other planarization layer 1019, the pixel defining layer 1017, and the spacer 1018. For example, during the fabrication process, the pixel defining layer 1017 and the spacer 1018 can be formed using a grayscale mask through the same patterning process to simplify the fabrication process of the display substrate. For example, when the planarization layer 1016 or the other planarization layer needs to form portions of different thicknesses in the display substrate, portions of different thicknesses can also be formed using a grayscale mask through the same patterning process.

[0087] For example, in some embodiments, the display substrate further includes a second barrier dam D2, which is disposed on the side of the first barrier dam D1 near the display area AA and at least partially surrounds the display area AA. For example, the second barrier dam D2 may also be disposed in the same layer as at least one of the planarization layer 1016 / 1019, the pixel defining layer 1017, and the spacer 1018.

[0088] For example, the height of the first barrier dam D1 relative to the substrate 110 is greater than the height of the second barrier dam D2 relative to the substrate 110. For example, in some embodiments, such as Figure 4 As shown, the second barrier dam D2 may include two sub-layers, which are respectively disposed in the same layer as two of the planarization layers 1016 / 1019, the pixel defining layer 1017, and the spacer 1018, to simplify the fabrication process of the display substrate. For example, the second barrier dam D2 includes two sub-layers D21 and D22, where sub-layer D21 is disposed in the same layer as the planarization layer 1016 or the planarization layer 1019, and sub-layer D22 is disposed in the same layer as the pixel defining layer 1017 or the spacer 1018. The first barrier dam D1 and the second barrier dam D2 can provide multiple blocking functions to improve the blocking effect.

[0089] For example, in some embodiments, the crack detection circuit PCD may only have a first trace portion P1. In this case, the number (length) of the first traces 111 included in the first trace portion P1 can be appropriately reduced to avoid electrostatic interference. For example, Figure 8A This illustrates the case where the crack detection circuit PCD only includes the first trace portion P1. Figure 8B for Figure 8A A schematic cross-sectional view of the display substrate along line EE. (See diagram below.) Figure 8A and Figure 8B As shown, the crack detection circuit PCD only includes the first trace portion P1, excluding the second trace portion P2. The first trace portion P1 includes four first traces 111, which can also achieve crack detection using methods such as bright line detection and / or resistance detection. This technical solution can further shorten the distance between the first barrier dam D1 and the cutting line CL, narrowing the frame.

[0090] For example, such as Figure 5A and Figure 5B As shown, the display substrate may further include a barrier layer 1112 and a buffer layer 1013 disposed on the substrate 110. The barrier layer 1112 and the buffer layer 1013 can prevent impurities in the substrate 110 from entering the multiple functional layers on the display substrate 110, thereby playing a protective role. For example, the barrier layer 1112 and the buffer layer 1013 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0091] For example, such as Figure 5A and Figure 5BAs shown, the display substrate may further include a first gate insulating layer 1014A disposed on the side of the active layer 1021 away from the substrate 110, a second gate insulating layer 1014B disposed on the side of the gate electrode 1022 and the first capacitor electrode 1031 away from the substrate 110, and an interlayer insulating layer 1015 disposed on the side of the second capacitor electrode 1032 away from the substrate 110. For example, the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0092] For example, such as Figure 5A and Figure 5B As shown, the display substrate may further include an encapsulation layer EN disposed on the side of the light-emitting device EM away from the substrate 110. The encapsulation layer EN may be a composite encapsulation layer, including a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053. The first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The first organic encapsulation layer 1052 may be made of organic insulating materials such as resin or polyimide.

[0093] For example, in embodiments of this disclosure, the substrate 110 can be a flexible substrate such as polyimide, and the gate electrode 1022 can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), for example, forming a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The first source / drain electrode 1023 and the first source / drain electrode 1024 can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), for example, forming a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The materials of the first electrode 1031 and the second electrode 1032 include metal materials or alloy materials such as aluminum, titanium, cobalt, and copper. The active layer 1021 can be made of materials such as polysilicon and metal oxides.

[0094] For example, the planarization layer 1016, the pixel defining layer 1017, the spacer layer 1018, and the first organic encapsulation layer 1052 of the encapsulation layer EN can be made of organic insulating materials such as polyimide and resin.

[0095] For example, such as Figure 6B , Figure 7B and Figure 8BAs shown, in some embodiments, the second motor layer 1043 of the light-emitting device EM can be formed on the entire surface of the display substrate, thus extending from the display area to the peripheral area NA. The peripheral area NA may also have an electrode material layer 1041A and a light-emitting material 1042A, which are respectively disposed in the same layer as the first electrode layer 1041 and the light-emitting material layer 1042 of the light-emitting device EM.

[0096] For example, the peripheral area NA also includes a gate scan driving circuit GOA, which also includes structures such as thin-film transistors and storage capacitors. These structures can be arranged on the same layer as the thin-film transistors T and storage capacitors C of the pixel driving circuit in the display area AA. The peripheral area NA may also include some traces W, which can be arranged on the same layer as the connecting electrodes CEL.

[0097] For example, the display substrate may also include other structures besides those described above. For details, please refer to the relevant technologies, which will not be elaborated here.

[0098] Furthermore, it should be noted that the embodiments of this disclosure do not limit the materials of each functional layer, and the materials of each functional layer are not limited to the examples described above. In the embodiments of this disclosure, each thin-film transistor can be a P-type thin-film transistor or an N-type thin-film transistor, and the structure can be bottom-gate, top-gate, or dual-gate. The structures shown in the accompanying drawings are merely exemplary, and the embodiments of this disclosure do not limit the specific form of each thin-film transistor.

[0099] For example, Figure 10 A plan view of another display substrate provided in at least one embodiment of the present disclosure is shown, which mainly illustrates the arrangement of the crack detection circuit PCD. Figure 11 It shows Figure 10 A cross-sectional view of the display panel along the CC line.

[0100] like Figure 10 and Figure 11 As shown, the display substrate has a display area AA and a peripheral area NA that at least partially surrounds the display area AA, and includes a substrate 110, a first barrier dam D1, a first power signal line VSS, and a crack detection circuit PCD.

[0101] A first barrier dam D1 is disposed on the substrate 110 and in the peripheral region NA, at least partially surrounding the display region AA to prevent material, for example, formed in the display region AA, from flowing into the peripheral region NA. A first power signal line VSS is disposed between the substrate 110 and the first barrier dam D1 and extends at least in the peripheral region NA, for example, from the display region AA to the peripheral region NA in some embodiments. The orthographic projection of at least a partial boundary B2 of the first power signal line VSS away from the display region AA onto the substrate 110 lies within the orthographic projection of the first barrier dam D1 onto the substrate 110. Thus, the first barrier dam D1 covers at least a partial boundary B2 of the first power signal line VSS away from the display region AA.

[0102] A crack detection circuit PCD is disposed between the substrate 110 and the first barrier dam D1, and is located in the peripheral region NA, at least partially surrounding the display region AA. The crack detection circuit PCD can detect whether there are defects such as breakage in the display substrate. The orthographic projection of the crack detection circuit PCD on the substrate 110 at least partially overlaps with the orthographic projection of the first barrier dam D1 on the substrate 110.

[0103] For example, in some embodiments, the orthographic projection of at least a portion of the boundary B3 of the crack detection circuit PCD, which is away from the display area AA, onto the substrate 110 lies within the orthographic projection of the first barrier dam D1 onto the substrate 110. That is, the overall structure of the crack detection circuit PCD is located on the side of the boundary B1 of the first barrier dam D1, which is away from the display area AA, closer to the display area AA.

[0104] For example, in some embodiments, such as Figure 11 As shown, the crack detection circuit PCD includes a first part PCD3 and a second part PCD4. The first part PCD3 and the second part PCD4 can be connected end-to-end to form a detection circuit, or they can be two separate detection circuits. For example, the second part PCD4 is located on the side of the first part PCD3 closer to the display area AA. For example, the orthographic projection of the first part PCD3 on the substrate 110 lies within the orthographic projection of the first barrier dam D1 on the substrate 110. The second part PCD4 is located on the side of the first barrier dam D1 closer to the display area AA.

[0105] For example, in some embodiments, the orthographic projection of the crack detection circuit PCD on the substrate 110 at least partially overlaps with the orthographic projection of the first power signal line VSS on the substrate 110. Thus, the crack detection circuit PCD and the first power signal line VSS occupy substantially the same space on the substrate 110, achieving full utilization of the arrangement space and facilitating narrow bezel design.

[0106] For example, in some embodiments, the first power signal line VSS is disposed on the side of the crack detection circuit PCD away from the substrate 110.

[0107] For example, such as Figure 10 As shown, the display area AA includes multiple sub-pixels S, each of the multiple sub-pixels S including a light-emitting device EN and a pixel driving circuit for driving the light-emitting device EM, as shown in the reference. Figure 5A and Figure 5B The display area AA includes multiple sub-pixels S. Each sub-pixel S includes a light-emitting device EM and a pixel driving circuit for driving the light-emitting device EM. The pixel driving circuit includes a thin-film transistor T and a storage capacitor C. The thin-film transistor T includes a gate 1022 disposed on the substrate 110 and source / drain electrodes 1023 and 1024 disposed on the side of the gate 1022 away from the substrate 110. The storage capacitor C includes a first capacitor electrode 1031 disposed on the substrate 110 and a second capacitor electrode 1032 disposed on the side of the first capacitor electrode 1031 away from the substrate 110. The gate 1022 and the first capacitor electrode 1031 are disposed on the same layer. Other structures of the light-emitting device EM and the pixel driving circuit can be found in [reference needed]. Figure 5A , Figure 5B Its description will not be repeated here.

[0108] For example, the crack detection circuit PCD is disposed on the same layer as the second capacitor electrode 1032, and the first power signal line VSS is disposed on the same layer as the source and drain electrodes 1023 and 1024, so as to simplify the fabrication process of the display substrate.

[0109] For example, in some embodiments, such as Figure 5B As shown, the light-emitting device EM and the pixel driving circuit are electrically connected through the connecting electrode CEL, as follows. Figure 11 As shown, the display substrate also includes a trace SG disposed on the side of the first power signal line VSS away from the substrate 110 and an electrode material layer 1041A on the same layer as the first electrode layer 1041. The trace SG is disposed on the same layer as the connecting electrode CEL, and the electrode material layer 1041A is, for example, a material layer formed in the peripheral region NA at the same time as the first electrode layer 1041 is formed.

[0110] For example, in some embodiments, such as Figure 12As shown, the surrounding area NA also includes at least one auxiliary trace AL, such as multiple auxiliary traces AL (five auxiliary traces AL are shown in the figure as an example). The first power signal line VSS is electrically connected to at least one auxiliary trace AL through a via V2, so as to be connected in parallel with the at least one auxiliary trace AL. By connecting the auxiliary trace AL in parallel with the first power signal line VSS, the resistance of the first power signal line VSS and the voltage drop of the transmitted signal can be reduced, thereby reducing the signal difference provided to sub-pixels at different locations.

[0111] For example, in some embodiments, the auxiliary trace AL is disposed on the same layer as the crack detection circuit PCD and the second capacitor electrode 1032 to simplify the fabrication process of the display substrate.

[0112] For example, in other embodiments, such as Figure 13 As shown, the thin-film transistor T further includes an active layer 1021, which is disposed on the side of the gate 1022 near the substrate 110. The display area AA also includes a light-shielding pattern SH, which is disposed between the active layer 1021 and the substrate 110. The orthographic projection of the active layer 1021 onto the substrate 110 at least partially overlaps with the orthographic projection of the light-shielding pattern SH onto the substrate 110. Thus, the light-shielding pattern SH can shield the active layer 1021 from light, preventing light from shining on the active layer 1021 and affecting the normal operation of the thin-film transistor T.

[0113] For example, in the above embodiments, such as Figure 14 As shown, the crack detection circuit PCD can be set on the same layer as the light-shielding pattern SH to simplify the manufacturing process of the display substrate.

[0114] For example, Figure 14 The embodiments relative to Figure 12 In some embodiments, two additional auxiliary traces AL can be provided (seven auxiliary traces AL are shown in the figure as an example) to further reduce the resistance of the first power signal line VSS and the voltage drop of the transmitted signal. Figure 14 As shown, an auxiliary trace AL is respectively provided above the first part PCD3 and the second part PCD4 of the crack detection circuit PCD. The orthographic projection of the crack detection circuit PCD on the substrate 110 overlaps at least partially with the orthographic projection of the auxiliary trace AL on the substrate 110. Thus, the crack detection circuit PCD and the auxiliary trace AL occupy basically the same area on the display substrate, thereby making full use of the layout space of the display substrate and realizing a narrow bezel design.

[0115] For example, in some embodiments, such as Figure 11 and Figure 14As shown, the display substrate also includes crack barrier dams D3, such as multiple crack barrier dams D3. Five crack barrier dams D3 are shown in the figure as an example. The crack barrier dams D3 are disposed in the peripheral region NA and on the side of the first barrier dam D1 closest to the display region AA, at least partially surrounding the display region AA. The crack barrier dams D3 can prevent crack formation and propagation, for example, preventing cracks formed during the cutting of the display substrate or preventing existing cracks from propagating to the display region AA, thereby protecting the display substrate in the peripheral region NA.

[0116] For example, the orthographic projection of the crack barrier dam D3 on the substrate 110 at least partially overlaps with the orthographic projection of the first power signal line VSS on the substrate 110. For example, the orthographic projection of the crack barrier dam D3 on the substrate 110 lies within the orthographic projection of the first power signal line VSS on the substrate 110.

[0117] For example, the orthographic projection of the crack barrier dam D3 on the substrate 110 is located between the orthographic projections of the first part PCD3 and the second part PCD4 of the crack detection circuit PCD on the substrate 110, that is, the crack detection circuit PCD can at least partially surround the crack barrier dam D3.

[0118] For example, in some embodiments, such as Figure 11 As shown, the crack barrier dam D3 includes two metal layers D31 and D32, which are respectively disposed in the same layer as the gate electrode 1022 and the second capacitor electrode 1032 to simplify the fabrication process of the display substrate. For example, in other embodiments, such as Figure 14 As shown, the crack barrier dam D3 includes two metal layers D31 and D32, which are disposed in the same layer as the light-shielding pattern SH and the gate 1022, respectively, to simplify the fabrication process of the display substrate.

[0119] For example, Figure 15 It shows Figure 10 An enlarged schematic diagram of the display substrate in the area within the dashed box, as shown below. Figure 15 As shown, in some embodiments, in the extension direction of the crack barrier dam D3, i.e., the vertical direction in the figure, the crack barrier dam D3 includes a plurality of sub-crack barrier dams D3A spaced apart.

[0120] The inventors of this disclosure discovered that if the crack barrier dam D3 is too long, it easily accumulates charge, resulting in a large static charge that cannot be discharged. Therefore, tip-generating electricity is likely to occur at the end of the crack barrier dam D3, which can melt the metal and cause oxidation and corrosion. By configuring the crack barrier dam D3 as including multiple spaced sub-crack barrier dams D3A, the aforementioned adverse phenomena can be avoided.

[0121] For example, in some embodiments, in the extension direction of the crack barrier dam D3, the length L0 of each of the multiple sub-crack barrier dams D3A is less than 50 mm, such as 47 mm, 45 mm, or 40 mm. Experimental tests have shown that under the above conditions, the crack barrier dam D3 basically does not experience adverse phenomena such as oxidation and corrosion.

[0122] For example, in some embodiments, such as Figure 11 , 12 As shown in Figure 14, the display substrate further includes a second barrier dam D2, which is disposed on the side of the first barrier dam D1 near the display area AA and on the side of the crack barrier dam D3 away from the substrate 110. The orthographic projection of the crack barrier dam D3 on the substrate 110 at least partially overlaps with the orthographic projection of the second barrier dam D2 on the substrate 110.

[0123] For example, the height of the first barrier dam D1 relative to the substrate 110 is greater than the height of the second barrier dam D2 relative to the substrate 110, so the first barrier dam D1 and the second barrier dam D2 play a dual blocking role at different positions and to different degrees.

[0124] For example, such as Figure 11 As shown, a planarization layer 1016 is disposed below the first barrier dam D1, thereby having a higher height. For example, the first barrier dam D1 and the second barrier dam D2 may be disposed on the same layer as at least one of the pixel defining layer 1017, the spacer 1018, or other planarization layers (not shown) disposed on the planarization layer 1016.

[0125] For example, in some embodiments, such as Figure 16 As shown, the display substrate may also omit the second barrier dam D2. In this case, the number of crack barrier dams D3 can be appropriately reduced. Figure 16 The image shows three crack barrier dams D3 as examples, thereby reducing the area occupied by the crack barrier dams D3 to further narrow the border.

[0126] For example, in some embodiments, the display substrate further includes a second power signal line VDD, the first power signal line VSS is configured to provide a first power signal to the display area AA, and the second power signal line VDD is configured to provide a second power signal to the display area AA. The potential of the second power signal is higher than that of the first power signal, that is, the second power signal is configured to provide a high-level voltage. For example, the first power signal line VSS is electrically connected to the second electrode layer 1043 of the light-emitting device EM to provide a low-level voltage.

[0127] For example, Figure 9 The circuit / structure arrangement of the non-display area NA in a display substrate provided by an embodiment of this disclosure is illustrated. For example... Figure 9 As shown, in the direction near the display area AA, the non-display area NA includes an edge-cutting area A1, a crack-blocking and power trace area B0, a circuit setting area C1, and a connection area D1. For example, the length of the edge-cutting area A1 is approximately 110 micrometers; the width of the crack-blocking and power trace area B0 is approximately 100 micrometers; the width of the circuit setting area C1 is approximately 350 micrometers; and the width of the connection area D1 is typically approximately 90 micrometers. The total width of all the above areas is approximately 650 micrometers. It can be seen that through the above design of the embodiments of this disclosure, the bezel of the display substrate can be further narrowed, achieving an extremely narrow bezel design effect.

[0128] This disclosure provides at least one embodiment of a display device, which includes any of the display substrates described above. For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0129] The following points also need to be explained:

[0130] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0131] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0132] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0133] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising: Substrate; A first barrier dam is disposed on the substrate and in the peripheral region, and at least partially surrounds the display area; A first power signal line is disposed between the substrate and the first barrier dam, and extends at least in the peripheral region; as well as A crack detection circuit is disposed between the substrate and the first barrier dam, and is disposed in the peripheral area and at least partially surrounds the display area, wherein the orthographic projection of the crack detection circuit on the substrate at least partially overlaps with the orthographic projection of the first barrier dam on the substrate. The crack detection circuit includes a first trace portion disposed on the substrate and a second trace portion disposed on the side of the first trace portion away from the substrate. The second trace portion is electrically connected to the first trace portion through a via. The orthographic projection of the second trace portion on the substrate is located inside the orthographic projection of the first barrier dam on the substrate; The second trace portion is located on the side of the first power signal line away from the display area, and the first trace portion is located on the side of the second trace portion away from the display area.

2. The display substrate according to claim 1, wherein, At least a portion of the boundary of the first power signal line away from the display area is projected onto the substrate in a projection that is inside the projection of the first barrier dam onto the substrate.

3. The display substrate according to claim 1, wherein, The second trace is arranged on the same layer as the first power signal line.

4. The display substrate according to claim 1 or 2, wherein, The first routing section includes multiple first routing lines. The orthographic projection of the boundary of the first barrier dam away from the display area on the substrate lies within the orthographic projection of the plurality of first traces on the substrate, or The orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is located within the orthographic projection of the interval between two adjacent first traces on the substrate.

5. The display substrate according to claim 4, wherein, The orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is located at the middle of the orthographic projection of one of the plurality of first traces on the substrate, or The orthographic projection of the boundary of the first barrier dam away from the display area on the substrate is within the orthographic projection of the interval between two adjacent first traces in the plurality of first traces on the substrate, and the distance between the orthographic projection of the first trace away from the display area in the adjacent two first traces on the substrate is greater than or equal to 3 micrometers.

6. The display substrate according to claim 1 or 2, wherein, The display area includes a plurality of sub-pixels, each of the plurality of sub-pixels including a light-emitting device and a pixel driving circuit for driving the light-emitting device. The pixel driving circuit includes a thin-film transistor and a storage capacitor. The thin-film transistor includes a gate disposed on the substrate and a source / drain electrode disposed on the side of the gate away from the substrate. The storage capacitor includes a first capacitor electrode disposed on the substrate and a second capacitor electrode disposed on the side of the first capacitor electrode away from the substrate. The gate electrode and the first capacitor electrode are disposed on the same layer, the second capacitor electrode is disposed on the same layer as the first trace portion, and the source and drain electrodes are disposed on the same layer as the second trace portion.

7. The display substrate according to claim 6 further includes a crack barrier dam, wherein, The crack barrier dam is located on the side of the crack detection circuit away from the display area.

8. The display substrate according to claim 7, wherein, The surrounding area includes an inorganic layer, and the crack barrier dam includes a groove disposed in the inorganic layer.

9. The display substrate according to claim 6, wherein, The display area further includes a planarization layer disposed on the side of the pixel driving circuit away from the substrate, a pixel defining layer disposed on the side of the planarization layer away from the substrate, and a spacer disposed on the side of the pixel defining layer away from the substrate. The first barrier dam is disposed in the same layer as at least one of the planarization layer, pixel defining layer and spacer.

10. The display substrate according to claim 1, wherein, At least a portion of the boundary of the crack detection circuit, which is far from the display area, is projected onto the substrate in a projection that is inside the projection of the first barrier dam onto the substrate.

11. The display substrate according to claim 10, wherein, The orthographic projection of the crack detection circuit on the substrate at least partially overlaps with the orthographic projection of the first power signal line on the substrate.

12. The display substrate according to claim 11, wherein, The first power signal line is located on the side of the crack detection circuit away from the substrate.

13. The display substrate according to claim 12, wherein, The surrounding area also includes at least one auxiliary trace, and the first power signal line is electrically connected to the at least one auxiliary trace through a via, so as to be connected in parallel with the at least one auxiliary trace.

14. The display substrate according to claim 13, wherein, The display area includes a plurality of sub-pixels, each of the plurality of sub-pixels including a light-emitting device and a pixel driving circuit for driving the light-emitting device. The pixel driving circuit includes a thin-film transistor and a storage capacitor. The thin-film transistor includes a gate disposed on the substrate and a source / drain electrode disposed on the side of the gate away from the substrate. The storage capacitor includes a first capacitor electrode disposed on the substrate and a second capacitor electrode disposed on the side of the first capacitor electrode away from the substrate. The gate electrode and the first capacitor electrode are disposed on the same layer, the second capacitor electrode and the at least one auxiliary trace are disposed on the same layer, and the source and drain electrodes are disposed on the same layer as the first power signal line.

15. The display substrate according to claim 14, wherein, The crack detection circuit is disposed on the same layer as the at least one auxiliary trace.

16. The display substrate according to claim 14, wherein, The thin-film transistor further includes an active layer disposed on the side of the gate near the substrate. The display area further includes a light-shielding pattern disposed between the active layer and the substrate. The orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the light-shielding pattern on the substrate.

17. The display substrate according to claim 16, wherein, The crack detection circuit is arranged on the same layer as the light-shielding pattern.

18. The display substrate according to claim 17, wherein, The orthographic projection of the crack detection circuit on the substrate at least partially overlaps with the orthographic projection of the at least one auxiliary trace on the substrate.

19. The display substrate according to claim 14, wherein, It also includes a crack barrier dam, disposed in the surrounding area and on the side of the first barrier dam closer to the display area, at least partially surrounding the display area. The orthographic projection of the crack barrier dam on the substrate at least partially overlaps with the orthographic projection of the first power signal line on the substrate.

20. The display substrate according to claim 19, wherein, The crack barrier dam is disposed in the same layer as at least one of the gate and the second capacitor electrode.

21. The display substrate according to claim 19, wherein, In the direction of extension of the crack barrier dam, the crack barrier dam includes a plurality of sub-crack barrier dams spaced apart.

22. The display substrate according to claim 21, wherein, In the extension direction of the crack barrier dam, the length of each of the plurality of sub-crack barrier dams is less than 50 mm.

23. The display substrate according to claim 19, further comprising: The second barrier dam is disposed on the side of the first barrier dam closer to the display area, and on the side of the crack barrier dam farther from the substrate. Wherein, the orthographic projection of the crack barrier dam on the substrate overlaps at least partially with the orthographic projection of the second barrier dam on the substrate.

24. The display substrate according to claim 1, wherein, The first power signal line is configured to provide a first power signal to the display area. The display substrate further includes a second power signal line, which is configured to provide a second power signal to the display area, wherein the potential of the second power signal is higher than that of the first power signal.

Images