Chip stripping crack self-detection circuit and method and ASIC chip

Abstract

The invention provides a chip stripping crack self-detection circuit and method and an ASIC chip, and relates to the technical field of semiconductor device testing. According to the circuit, a detection resistor module is formed in a semiconductor substrate of a chip and is arranged around the periphery of a core circuit area of the chip on the layout of the chip; the detection resistor module is formed by connecting a plurality of resistor units in series; the adjacent resistor units are connected through a multi-layer metal interconnection structure; the detection resistor module and the reference resistor module are connected with the voltage output end of the core circuit area of the chip. The first bias current source is respectively connected with the in-phase input ends of the detection resistor module and the comparator; the second bias current source is respectively connected with the reference resistor module and the inverted input end of the comparator; and the comparator outputs a comparison result to indicate whether the chip has a stripping crack or not. According to the invention, the scribing damage and the stripping crack of the multilayer metal in the chip can be detected in real time, so that the invalid chip is effectively removed, and the product yield and the long-term reliability are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, and in particular to a self-detection circuit, method, and ASIC chip for chip peeling cracks. Background Technology

[0002] In high-reliability applications such as automotive electronics, the functional safety and long-term reliability of semiconductor devices, especially integrated sensors that combine micro-electro-mechanical system (MEMS) sensing units with application-specific integrated circuits (ASICs), are crucial. These devices typically employ chip-level packaging, integrating separately manufactured MEMS wafers and ASIC wafers through bonding processes. Their performance and reliability are highly dependent on the integrity of the back-end packaging process.

[0003] In the back-end processes of semiconductor packaging, wafer dicing is a critical step in separating the wafer into individual chips. However, the mechanical stress generated during dicing can cause chip edge chipping and internal crack formation, which directly affects the electrical connectivity and long-term reliability of the circuit. Current quality control mainly relies on random inspection or electrical testing after dicing, making it difficult to achieve full coverage and real-time detection of hidden cracks inside each chip.

[0004] Therefore, existing technologies cannot efficiently and in real-time detect the multi-layered metals that may be damaged inside the chip after dicing, thus failing to effectively remove defective chips and reducing product yield and long-term reliability. Summary of the Invention

[0005] This invention provides a chip peeling crack self-detection circuit, method, and ASIC chip to solve the problem that peeling cracks that may damage the internal multilayer metal of the chip after dicing cannot be detected efficiently and in real time, thus failing to effectively remove defective chips and reducing product yield and long-term reliability.

[0006] In a first aspect, embodiments of the present invention provide a self-detection circuit for chip peeling cracks, including a detection resistor module, a reference resistor module, a first bias current source, a second bias current source, and a comparator; The sensing resistor module is formed in the semiconductor substrate of the chip and is arranged around the core circuit area of ​​the chip in the chip layout; the sensing resistor module is composed of multiple resistor units connected in series; adjacent resistor units are connected by a multilayer metal interconnect structure. Both the first terminal of the sensing resistor module and the first terminal of the reference resistor module are connected to the voltage output terminal of the core circuit area of ​​the chip. The current inflow terminal of the first bias current source is connected to the second terminal of the sensing resistor module and the non-inverting input terminal of the comparator, respectively. The current inflow terminal of the second bias current source is connected to the second terminal of the reference resistor module and the inverting input terminal of the comparator, respectively. The comparator's output is used to output the comparison result; the comparison result is used to indicate whether the chip has peeling cracks.

[0007] In one possible implementation, for any two adjacent resistor units, the adjacent resistor units include a first adjacent resistor unit and a second adjacent resistor unit. The multilayer metal interconnect structure includes all metal layers from the first metal layer to the top metal layer; the connection path between adjacent resistor units sequentially passes through the first metal layer connected to the first adjacent resistor unit to the top metal layer and then returns to the first metal layer connected to the second adjacent resistor unit.

[0008] In one possible implementation, the spacing between adjacent resistor units is less than 10µm.

[0009] In one possible implementation, the detection resistor module has a first resistance value; the reference resistor module has a second resistance value; the first resistance value is less than the second resistance value.

[0010] In one possible implementation, the second bias current source is a programmable bias current source; The second bias current source is configured for two operating modes: Normal detection mode: The second bias current source is set to have an output current equal to the output current of the first bias current source; Fault test mode: The second bias current source is set to have an output current that is less than the output current of the first bias current source by a preset multiple; the preset multiple is the ratio of the first resistance value to the second resistance value.

[0011] In one possible implementation, under normal detection mode, if the chip does not have a peeling crack, the comparator output is positive; if the chip has a peeling crack that causes the detection resistor module to open, the comparator output is negative. In fault test mode, if the chip does not have peeling cracks, the comparator output is negative; if the self-detection circuit itself malfunctions, causing the comparator output to always be positive, the detection circuit is determined to be faulty.

[0012] In one possible implementation, the first resistance value is half of the second resistance value.

[0013] In one possible implementation, in fault test mode, the second bias current source is set to have an output current equal to 1 / 4 of the output current of the first bias current source.

[0014] Secondly, embodiments of the present invention provide a chip peeling crack self-detection method, applied to the chip peeling crack self-detection circuit as described above, comprising: For any given testing cycle: The output current of the second bias current source is controlled to be equal to the output current of the first bias current source, and the first comparison result output by the comparator is obtained; The output current of the second bias current source is controlled to be less than the output current of the first bias current source by a preset multiple, and the second comparison result output by the comparator is obtained; Based on the first comparison result, determine whether the chip has peeling cracks; Based on the second comparison result, determine whether the self-test circuit is functioning normally.

[0015] Thirdly, embodiments of the present invention provide an ASIC chip, including the chip peel crack self-detection circuit as described above; a detection resistor module is formed in the semiconductor substrate of the chip, surrounding the periphery of the core circuit region inside the chip; wherein the detection resistor module is composed of multiple resistor units made of semiconductor substrate material connected in series.

[0016] This invention provides a self-detection circuit for chip peel cracks. By utilizing a detection resistor module formed from semiconductor substrate material and arranged in series around the chip periphery, combined with an interconnect structure penetrating all metal layers, it achieves highly sensitive, full-coverage electrical detection of deep peel cracks that may have damaged any metal layer within the chip during the dicing process. Simultaneously, it integrates a bias current source and a comparator. By configuring the bias current source, it enables real-time self-diagnosis of the detection circuit's own functionality while detecting chip cracks, meeting high functional safety requirements. The entire circuit can be integrated inside the chip, achieving online real-time detection without external intervention, significantly improving chip yield and long-term reliability. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the chip peeling crack self-detection circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the detection resistor module provided in the embodiment of the present invention in the layout of an ASIC chip; Figure 3 This is a schematic diagram of the interconnection structure between resistor units provided in an embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0019] Peeling cracks refer to the breakage of metal traces at the edge or inside of the chip after dicing of an ASIC wafer, or the delamination between metal layers or between metal and substrate.

[0020] Peeling cracks can originate from the chip edge, extend inwards, and damage the internal multilayer interconnect structure, leading to open circuits in metal interconnects or abrupt changes in resistance characteristics, posing a potential reliability risk. Currently, the industry generally uses optical inspection or sampling electrical testing for quality control, making it difficult to achieve non-destructive full inspection and real-time monitoring of hidden cracks inside each chip, especially in deep interconnect structures.

[0021] The inventors also discovered that existing technologies lack an effective monitoring mechanism for the operating status of the detection circuit itself, which may lead to undetected failure of the detection function. These problems directly affect chip yield and long-term product reliability, and cannot meet the stringent requirements for high functional safety levels of semiconductor devices in fields such as automotive electronics, nor can they meet the requirements for latent fault coverage in the high functional safety levels of automotive electronics.

[0022] Therefore, this invention proposes a self-detection circuit for peeling cracks suitable for ASIC chips. This circuit can be applied to the interface circuits of automotive electronic sensors to achieve functional safety self-detection of whether peeling cracks damaging the internal structure of the ASIC chip exist after dicing. Furthermore, a fault testing function is incorporated into this self-detection circuit to monitor its functionality in real time.

[0023] The implementation of the present invention will be described in detail below with reference to the accompanying drawings: Figure 1 This is a schematic diagram of a chip peeling crack self-detection circuit provided in an embodiment of the present invention. (Refer to...) Figure 1 The chip peel crack self-detection circuit includes a detection resistor module R. total Reference resistor module R ref The system consists of a first bias current source, a second bias current source, and a comparator CMP.

[0024] Resistance detection module R total Formed within the semiconductor substrate of the chip, and arranged around the core circuit area of ​​the chip in the chip's layout, such as... Figure 2 As shown; Resistance detection module R totalIt is composed of multiple resistor units connected in series. Figure 2 The positions of the individual resistor units are for illustrative purposes only and do not constitute a limitation on their positions; adjacent resistor units are connected by a multilayer metal interconnect structure, such as... Figure 3 As shown.

[0025] Resistance detection module R total The first terminal and reference resistor module R ref The first end of each is connected to the voltage output terminal of the core circuit area of ​​the chip.

[0026] For example, the resistance detection module R total and reference resistor module R ref It can be designed as a fixed resistor in the tens of kiloohms range, such as 50kΩ.

[0027] The current inflow terminal of the first bias current source is connected to the detection resistor module R. total The second terminal is connected to the non-inverting input of the comparator CMP.

[0028] The current inflow terminal of the second bias current source is connected to the reference resistor module R. ref The second terminal is connected to the inverting input of the comparator CMP.

[0029] For example, the current outflow terminals of both the first bias current source and the second bias current source are grounded to GND.

[0030] In this embodiment, a bias current source is used to provide the current required for measuring resistance or voltage. The peeling crack caused the detection resistance module R... total An open circuit or a sudden increase in resistance can occur. Without a current source, relying solely on resistor voltage division to detect such a change would result in a very weak voltage difference, easily affected by power supply voltage fluctuations. A current source provides a stable current, linearly and significantly amplifying the resistance change into a voltage change, enabling the comparator CMP to make reliable and stable judgments, greatly improving detection sensitivity and anti-interference capabilities.

[0031] The output of the comparator CMP is used to output the comparison result; the comparison result is used to indicate whether there are peeling cracks on the chip.

[0032] For example, this self-detection circuit starts working when the chip powers on and begins operation. The core detection mechanism of the above circuit is: if the chip has peeling cracks that damage the internal metal layer due to dicing, it will inevitably cause the series-connected detection resistor module R to... total If an open circuit occurs or its resistance increases abruptly, the resistance between its two ends, VDD_LDO and TEST, will increase from tens of kΩ to the MΩ level. The circuit uses two symmetrical resistors to detect the resistance module R. total With reference resistor module R refThis converts the physical change in resistance into a comparable voltage signal. Specifically, the first bias current source and the second bias current source provide stable bias current for their respective branches, due to the sensing resistor module R... total The resistance value and reference resistor module R ref The resistance values ​​have a preset magnitude relationship or a preset ratio relationship, thereby detecting the resistance module R. total With reference resistor module R ref A voltage divider is generated. The comparator CMP compares these two voltage divider values ​​in real time, i.e., the voltages at their non-inverting and inverting input terminals, to determine the voltage distribution of the sensing resistor module R. total The integrity of the chip is assessed to diagnose whether it has cracks.

[0033] For example, by programming the current value of the first bias current source to be equal to or less than the current of the second bias current source in two modes, the circuit can switch between two modes: chip crack detection and circuit self-function verification.

[0034] For example, in the normal chip crack detection mode, the circuit responds to external physical damage; in the circuit's own fault test mode, the circuit verifies whether the entire signal chain, including the comparator CMP, is functioning correctly by artificially introducing a known current deviation. This design integrates physical defect detection with circuit self-diagnostic functionality.

[0035] This embodiment provides a chip peel crack self-detection circuit, which utilizes a detection resistor module R formed from a semiconductor substrate material and arranged in series around the periphery of the chip. total By combining an interconnect structure that runs through all metal layers, this system achieves highly sensitive, full-coverage electrical detection of deep peeling cracks that may damage any metal layer inside the chip during the dicing process. It also integrates a bias current source and a comparator (CMP). By configuring the bias current source, it enables real-time self-diagnosis of the detection circuit's own functionality while detecting chip cracks, meeting high functional safety requirements. The entire circuit can be integrated inside the chip, enabling online real-time detection without external intervention, significantly improving chip yield and long-term reliability.

[0036] In one embodiment, see Figure 3 Each resistor unit is a substrate resistor. In this context, substrate resistor refers to a resistor structure constructed using the substrate material of the semiconductor wafer itself.

[0037] For any two adjacent resistor units, the adjacent resistor units include the first adjacent resistor unit R. Psub1 The second adjacent resistor unit R Psub2 .

[0038] The multilayer metal interconnect structure includes all metal layers from the first metal layer Metal1 to the top metal layer MetalTop; the connection path between adjacent resistor units passes sequentially through the first adjacent resistor unit R. Psub1 The connection extends from the first metal layer (Metal1) to the top metal layer (MetalTop) and then back to the second adjacent resistor unit (R). Psub2 The first metal layer connected is Metal1.

[0039] For example, the interconnection method between two adjacent resistor units is R Psub1 -Metal1-…-MetalTop-…-Metal1-R Psub2 The structure ensures that if any metal layer of the chip is peeled off and cracked, the series-connected resistor units will be disconnected.

[0040] For example, the spacing between adjacent resistor units is less than 10µm. This setup improves the spatial resolution and sensitivity of the detection, enabling the detection of even very fine or localized cracks.

[0041] This embodiment utilizes the substrate itself as a resistive unit, ensuring that the detection structure and the chip body are physically integrated. Any peeling cracks that damage the chip will directly disrupt the continuity of resistance. Employing an interconnect structure that runs from the bottom metal (Metal1) through to the top metal (MetalTop) and then back, if a crack damages the interconnect interface from the substrate to any metal layer or the metal line itself, the entire series resistance path will be severed. This allows the detection capability to move beyond the surface or a single metal layer, enabling sensitive and reliable detection of peeling cracks in multi-layered metal structures at any depth within the chip.

[0042] In one embodiment, the resistance detection module R total It has a first resistance value; reference resistor module R ref It has a second resistance value; the first resistance value is less than the second resistance value.

[0043] The second bias current source is a programmable bias current source; the second bias current source is configured to operate in two modes: Normal detection mode: The second bias current source is set to have an output current equal to the output current of the first bias current source.

[0044] Fault test mode: The second bias current source is set to have an output current less than a preset multiple of the output current of the second bias current source; the preset multiple is the ratio of the first resistance value to the second resistance value.

[0045] In normal detection mode, if the chip has not experienced any peeling cracks, the comparator CMP output will be positive; if the chip has experienced peeling cracks, causing the detection resistor module R to...total In case of an open circuit, the output of comparator CMP is negative.

[0046] Exemplarily, in the normal detection mode, the output current I2 of the second bias current source is set equal to the output current I1 of the first bias current source. The input voltages at both ends of comparator CMP are V1 = VDD_LDO - I1R total and V2 = VDD_LDO - I2R ref . Since R total < R ref and I1 = I2, in the initial state of an intact chip, V1 > V2, and the output of comparator CMP is positive. Once a scribing crack causes the detection resistance module R total to have an open circuit or a sharp increase in resistance value, V1 will decrease significantly and become lower than V2, and the output of comparator CMP will flip to negative. This distinct level flip is the clear electrical sign that the circuit detects a peeling crack in the chip.

[0047] In the fault test mode, if there is no peeling crack in the chip, the output of comparator CMP is negative; if a self-detection circuit failure causes the output of comparator CMP to always be positive, it is determined that the detection circuit has failed.

[0048] Exemplarily, on the premise that the chip is intact, that is, R total has not changed, V1 = VDD_LDO - I1R total , since , so

[0049] At this time, V1 < V2, and the output of comparator CMP should flip to negative as expected. If after applying a self-test instruction in this mode, the output of comparator CMP fails to flip to negative as expected but remains positive, it indicates that comparator CMP or its front-end path may have a fault such as being fixed at a high level, resulting in its loss of normal comparison function. Thus, the circuit realizes the diagnosis of its own faults.

[0050] In addition, the reason for赋予可编程功能 to the second bias current source instead of the first bias current source in this embodiment is that the second bias current source is located in the reference branch where the reference resistance module R ref is located. The reference branch is an internal circuit that is known, stable, and not easily affected by cracks physically, and is usually designed in a safe area inside the chip. While the first bias current source is located in the detection branch where the detection resistance module R total is located. The detection branch directly senses external physical changes, and its signal must accurately and without interference reflect the resistance value change of R total , and this change can only be caused by whether there is a peeling crack in the chip.

[0051] If the first bias current source is made programmable, then in the fault test mode, when I1 is changed, the change in V1 will be a combination of two reasons: one is the artificial programming change, and the other is the possible unknown physical crack. This will lead to untrustworthy self-test results and make it impossible to distinguish whether the change in V1 is caused by the self-test instruction or the chip is really damaged.

[0052] By setting the second bias current source to be programmable and the first bias current source not to be programmable, the fault injection action of the circuit self-test can be completely isolated from the signal sensing path of external physical cracks both electrically and logically. By only programmatically changing the reference current I2 of the reference branch, the output of the comparator CMP can be deterministically flipped when the chip is intact, thus creating a pure and controllable self-test verification condition; at the same time, ensuring that the current I1 in the detection branch remains constant, making the change in its output voltage V1 uniquely and accurately reflect the actual physical state of the detection resistance module R total This design realizes reliable operation with no interference between the crack detection mode and the circuit self-diagnosis mode, clear logic and clear expectations, providing a key hardware foundation for meeting the fault detection coverage rate and the online self-test of the safety mechanism required by the high functional safety level.

[0053] In this embodiment, through the collaborative design of the resistance ratio and the current ratio, a closed-loop and self-verifying safety detection system is constructed, which can not only sensitively capture external physical damages such as peeling cracks, but also periodically perform self-tests to confirm that its internal diagnostic ability is always effective. This dual protection mechanism is a typical hardware implementation solution to meet the requirement for the self-diagnosis coverage rate of the safety mechanism in the modern functional safety standard, fundamentally improving the reliability of the chip and the system safety level.

[0054] In one embodiment, the difference from the above embodiment is that the present invention is described by taking specific current relationships and resistance relationships as examples.

[0055] Exemplarily, the first resistance value is 1 / 2 of the second resistance value. In the fault test mode, the second bias current source is set so that its output current is equal to 1 / 4 of the output current of the first bias current source.

[0056] In the normal detection mode, I1 = I2. When there is no chip peeling crack, R total is 1 / 2 of R ref , at this time V1 > V2, and the output of the comparator CMP is positive. When the chip has a peeling crack, R total becomes much larger than R ref due to an open circuit. At this time, V1 < V2, and the output of the comparator CMP is negative. By detecting the output of the comparator CMP, the detection of chip peeling failure can be completed.

[0057] In the fault test mode, , when there is no chip peeling crack, R total is 1 / 2 of R ref . At this time, V1 < V2, and the output of the comparator CMP is negative. When there is a chip peeling crack, R total becomes much larger than R ref due to an open circuit. At this time, V1 < V2, and the output of the comparator CMP is still negative. When the chip does not fail due to a peeling crack, the comparison output result in the normal detection mode is positive, while the comparison output result in the fault test mode is negative.

[0058] In summary, the fault test mode can perform functional safety detection on the above detection circuit, avoiding the output result of the comparator CMP being continuously pulled up due to a certain fault and losing the function of detecting chip peeling cracks.

[0059] The embodiment of the present application further provides a method for self-detecting chip peeling cracks, which is applied to the chip peeling crack self-detection circuit as described in the above embodiment. The method for self-detecting chip peeling cracks includes: For any detection period: Step 101, control the output current of the second bias current source to be equal to the output current of the first bias current source, and obtain the first comparison result output by the comparator CMP.

[0060] Step 102, control the output current of the second bias current source to be less than a preset multiple of the output current of the first bias current source, and obtain the second comparison result output by the comparator CMP.

[0061] Step 103, based on the first comparison result, determine whether there is a peeling crack in the chip.

[0062] Step 104, based on the second comparison result, determine whether the self-detection circuit is functioning normally.

[0063] Exemplarily, the normal detection mode includes Step 101 and Step 103, and the fault test mode includes Step 102 and Step 104. When the chip starts to power on and work, the self-detection circuit will start to work. The normal detection mode and the fault test mode automatically work in periodic alternation. For example, the chip internally controls the current magnitude of the second bias current source to alternate at a frequency of 100 Hz.

[0064] Exemplarily, in the normal detection mode, by configuring the second bias current source and the first bias current source to output equal values, the circuit works in the standard detection state; the first comparison result obtained at this time directly reflects the detection resistance module R totalThe integrity of the signal chain is determined by the following: if the result is a preset "positive" logic value, the chip is considered intact; if the result is a "negative" logic value, the detection resistor may be open-circuited due to a crack. Subsequently, in fault test mode, the output current of the second bias current source I2 is reduced by a preset ratio (related to the ratio of R_total / R_ref) through programming, thereby changing the input balance condition of the comparator CMP. The expected value of the second comparison result obtained in this mode should be the opposite of the result in normal mode, for example, becoming negative. If the actual result matches the expectation, it proves that the entire signal chain, including the comparator CMP, is functioning normally; if it does not match, for example, remaining positive, it clearly indicates that the detection circuit itself has a sticky or other fault.

[0065] By periodically alternating between the two steps described above and performing separate assessments, not only can the physical failure of the chip—such as peeling cracks—be continuously monitored, but the health and effectiveness of the safety mechanism itself responsible for monitoring can also be confirmed in real time. This timing control method, which integrates functional testing and self-diagnosis, greatly enhances the reliability and trustworthiness of the testing system, providing a systematic solution to meet the online diagnostic and fault coverage requirements of high-functional safety applications.

[0066] This application also provides an ASIC chip, including a chip peel crack self-detection circuit as described in the above embodiment; a detection resistor module is formed in the semiconductor substrate of the chip, surrounding the core circuit region inside the chip; wherein the detection resistor module is composed of multiple resistor units made of semiconductor substrate material connected in series.

[0067] For example, the chip peel crack self-detection circuit is a circuit module in an ASIC chip, and VDD_LDO is a low-dropout linear regulated output generated internally by the power module in the chip, which serves as a reference voltage.

[0068] The wafers mentioned above generally refer to the undivided state. A wafer typically contains several thousand chips, and each chip is equipped with this self-testing circuit.

[0069] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A self-detection circuit for chip peeling cracks, characterized in that, include: The system includes a detection resistor module, a reference resistor module, a first bias current source, a second bias current source, and a comparator. The detection resistor module is formed in the semiconductor substrate of the chip and is arranged around the core circuit area of ​​the chip in the chip layout; the detection resistor module is composed of multiple resistor units connected in series; adjacent resistor units are connected by a multilayer metal interconnect structure. The first terminal of the detection resistor module and the first terminal of the reference resistor module are both connected to the voltage output terminal of the core circuit area of ​​the chip. The current inflow terminal of the first bias current source is connected to the second terminal of the detection resistor module and the non-inverting input terminal of the comparator, respectively. The current inflow terminal of the second bias current source is connected to the second terminal of the reference resistor module and the inverting input terminal of the comparator, respectively. The output of the comparator is used to output the comparison result; The comparison results are used to indicate whether the chip has peeling cracks.

2. The chip peeling crack self-detection circuit as described in claim 1, characterized in that, For any two adjacent resistor units, the adjacent resistor units include a first adjacent resistor unit and a second adjacent resistor unit; The multilayer metal interconnect structure includes all metal layers from the first metal layer to the top metal layer; the connection path between adjacent resistor units sequentially passes through the first metal layer connected to the first adjacent resistor unit to the top metal layer and then returns to the first metal layer connected to the second adjacent resistor unit.

3. The chip peeling crack self-detection circuit as described in claim 1, characterized in that, The spacing between adjacent resistor units is less than 10µm.

4. The chip peeling crack self-detection circuit as described in any one of claims 1 to 3, characterized in that, The detection resistor module has a first resistance value; the reference resistor module has a second resistance value; the first resistance value is less than the second resistance value.

5. The chip peeling crack self-detection circuit as described in claim 4, characterized in that, The second bias current source is a programmable bias current source; The second bias current source is configured to operate in two modes: Normal detection mode: The second bias current source is set to have an output current equal to the output current of the first bias current source; Fault test mode: The second bias current source is set to have an output current that is less than a preset multiple of the output current of the first bias current source; The preset multiple is the ratio of the first resistance value to the second resistance value.

6. The chip peeling crack self-detection circuit as described in claim 5, characterized in that, In the normal detection mode, if the chip does not have a peeling crack, the comparator output is positive; if the chip has a peeling crack that causes the detection resistor module to open circuit, the comparator output is negative. In the fault test mode, if the chip does not have peeling cracks, the comparator output is negative; if the self-detection circuit itself malfunctions, causing the comparator output to always be positive, the detection circuit is determined to be faulty.

7. The chip peeling crack self-detection circuit as described in claim 5, characterized in that, The first resistance value is 1 / 2 of the second resistance value.

8. The chip peeling crack self-detection circuit as described in claim 7, characterized in that, In the fault test mode, the second bias current source is set to have an output current equal to 1 / 4 of the output current of the first bias current source.

9. A method for self-detection of chip peeling cracks, applied to the chip peeling crack self-detection circuit as described in any one of claims 5 to 8, characterized in that, include: For any given testing cycle: The output current of the second bias current source is controlled to be equal to the output current of the first bias current source, and the first comparison result output by the comparator is obtained; The output current of the second bias current source is controlled to be less than the output current of the first bias current source by a preset multiple, and the second comparison result output by the comparator is obtained; Based on the first comparison result, determine whether the chip has peeling cracks; Based on the second comparison result, it is determined whether the self-testing circuit is functioning normally.

10. An ASIC chip, characterized in that, The chip peel crack self-detection circuit as described in any one of claims 1 to 8 is included; a detection resistor module is formed in the semiconductor substrate of the chip, which surrounds the core circuit region inside the chip; wherein the detection resistor module is composed of a plurality of resistor units made of the semiconductor substrate material connected in series.

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