Double-path management system and method and server
By introducing a switching mechanism between dual-socket BMC and CPLD in a split-board dual-socket server, the problem of monitoring and management failure caused by BMC anomalies is solved, achieving stable system operation and data security, and improving server reliability and redundancy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG ZHISUO INFORMATION TECHNOLOGY CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-17
AI Technical Summary
In a split-board dual-socket server, monitoring and management functions may fail due to BMC malfunctions, affecting system stability and data security.
A dual-path management system is adopted, which sets up BMC and CPLD on each motherboard to realize the health status monitoring and rapid switching of BMC. This ensures that when one BMC is abnormal, the other BMC can take over the management and ensure the stable operation of the system.
This improved system stability and security, reduced downtime caused by single point of failure in the BMC, and ensured the integrity of business data and system continuity.
Smart Images
Figure CN121880107A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a dual-channel management system, method and server. Background Technology
[0002] In cloud computing, big data, and enterprise-level applications, split-board dual-socket servers, with their high-efficiency computing power and flexible scalability, have become the core hardware carriers for data processing and storage. The security management system of this type of server directly determines the continuity of business operations and data integrity. The BMC (Baseboard Management Controller), as the core component for hardware monitoring and control, is responsible for collecting hardware status information such as temperature and voltage, managing power modules, recording system logs, and responding to fault alarms. The server's security management system is a crucial component for ensuring continuous business operations and data security, especially in fields such as finance and healthcare where data integrity requirements are extremely high, placing stringent demands on the redundancy and fault self-healing capabilities of the security management system.
[0003] Therefore, how to design a security management system in a split-board dual-socket server to ensure that the system can still maintain effective monitoring and management of the motherboard even if the BMC malfunctions is an urgent problem to be solved. Summary of the Invention
[0004] This application provides a dual-path management system, method, and server to at least solve the technical problem in related technologies where a single controller cannot ensure stable system operation once the controller malfunctions when monitoring and managing two motherboards.
[0005] This application provides a dual-channel management system, including: a first motherboard and a second motherboard; the first motherboard includes a first connector, a first controller, and a first logic unit, the first logic unit being connected to the second controller of the second motherboard via a first pin, for sending a first interrupt request signal to the second controller when an anomaly is detected in the first controller, so that the second controller manages multiple management modules on the first motherboard; the second motherboard includes a second connector, a second controller, and a second logic unit, the second logic unit being connected to the first controller of the first motherboard via a second pin, for sending a second interrupt request signal to the first controller when an anomaly is detected in the second controller, so that the first controller manages multiple management modules on the second motherboard; the first connector of the first motherboard and the second connector of the second motherboard are connected by a cable; wherein, the first motherboard further includes: A first chip, connected to a first logic device, is used to transmit status information of multiple management modules on the first motherboard to the first logic device. The second motherboard further includes a second chip, connected to a second logic device, used to transmit status information of multiple management modules on the second motherboard to the second logic device. A first controller is interconnected with the first logic device via a first interface signal to manage multiple management modules on the first motherboard. A second controller is interconnected with the second logic device via a second interface signal to manage multiple management modules on the second motherboard. The first logic device is connected to the second logic device on the second motherboard via a first pin to receive a first interrupt request signal. The second logic device is connected to the first logic device on the first motherboard via a second pin to receive a second interrupt request signal.
[0006] This application also provides a dual-path management method, comprising: a first logic unit on a first motherboard receiving a health monitoring signal sent by a first controller; and, in the event of an abnormal health monitoring signal, a second controller on a second motherboard receiving a first interrupt request signal and managing multiple management modules on the first motherboard.
[0007] This application also provides a server that includes components of any of the dual-path management systems described above.
[0008] According to the embodiments of this application, the dual-path management system includes a first motherboard and a second motherboard. Logic units are added to the first motherboard and the second motherboard respectively, and the first motherboard and the second motherboard are connected by cables. This allows the controller on each motherboard to manage both the first and second motherboards. In other words, when the controller of the first motherboard (second motherboard) malfunctions, the controller of the second motherboard (first motherboard) can take over and manage it in a timely manner, so as to ensure the stable operation of the server. This solves the technical problem in the split-board dual-path management system where a single controller monitors and manages the two motherboards. Once the controller malfunctions, the monitoring and management functions of the entire system will fail, resulting in abnormal system operation. This achieves the technical effect of ensuring stable system operation and improving system security. Attached Figure Description
[0009] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 A structural block diagram of a dual-path management system provided in this application embodiment;
[0011] Figure 2 This is a schematic diagram of the structure of a first motherboard provided in an embodiment of this application;
[0012] Figure 3 This is a schematic diagram of the structure of a second motherboard provided in an embodiment of this application;
[0013] Figure 4 This is a schematic diagram of the structure of a motherboard identifier setting module provided in an embodiment of this application;
[0014] Figure 5 A flowchart illustrating a dual-path management method provided in this application embodiment;
[0015] Figure 6 The overall flowchart of the dual-path management method provided for the scenario embodiment of this application. Detailed Implementation
[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0017] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0018] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0019] In current management systems for split-board dual-socket servers, the BMC (Block Controller) is typically separated from the motherboard, with a dedicated BMC management board. This board connects to both motherboards via cables for monitoring and management. However, separating the BMC management board from the motherboards not only increases the number of server boards and cables but also complicates server installation and maintenance. Furthermore, with a single BMC monitoring and managing both motherboards, a malfunction in the BMC can cause the entire system's monitoring and management functions to fail, leading to system malfunctions and disrupting normal operation.
[0020] In view of the above problems, this application provides a management system for a split-board dual-socket server. The system consists of a first motherboard, a second motherboard, and a motherboard identification setting module. By introducing the switching capability of a dual-socket BMC (Browser Control Center), i.e., both the first and second motherboards are equipped with BMCs, the stability of the split-board dual-socket server system is significantly improved, and downtime caused by single-point failures of the BMC is reduced. Furthermore, by using a CPLD (Complex Programmable Logic Device) as an intermediate logic layer, not only can the health status of the BMC be monitored in real time, but control permissions can also be quickly switched when necessary, greatly enhancing the security of the server system and ensuring the integrity of business data.
[0021] Figure 1 A structural block diagram of a dual-path management system provided in this application embodiment is shown below. Figure 1 As shown, the dual-path management system includes: a first motherboard and a second motherboard.
[0022] In some exemplary embodiments, the first motherboard includes a first connector, a first controller, and a first logic device. The first logic device is connected to the second controller of the second motherboard via a first pin and is used to send a first interrupt request signal to the second controller when an abnormality is detected in the first controller, so that the second controller manages multiple management modules on the first motherboard. The second motherboard includes a second connector, a second controller, and a second logic device. The second logic device is connected to the first controller of the first motherboard via a second pin and is used to send a second interrupt request signal to the first controller when an abnormality is detected in the second controller, so that the first controller manages multiple management modules on the second motherboard. The first connector of the first motherboard and the second connector of the second motherboard are connected by a cable.
[0023] In some embodiments, the first motherboard includes a first connector, a first controller (i.e., a first BMC), and a first logic unit (i.e., a first CPLD). Specifically, Figure 2 A schematic diagram of the structure of the first motherboard provided in the embodiments of this application is shown below. Figure 2As shown, the first connector on the first motherboard is connected to the second connector on the second motherboard via a cable, forming a bridge for signal and data communication between the two motherboards. This connection method ensures data synchronization and command transmission between the two motherboards.
[0024] Furthermore, the first CPLD on the first motherboard is connected to the second BMC on the second motherboard via a first pin (i.e., GPIO (General Purpose Input / Output)). This connection channel is used to send a first interrupt request signal (i.e., "First Motherboard_Interrupt Request Signal") to the second BMC when an anomaly is detected in the first BMC, so that the second BMC can manage multiple management modules on the first motherboard. The first BMC on the first motherboard periodically sends a WatchDog signal to the first CPLD to detect whether an anomaly has occurred in the state of the first BMC.
[0025] The first motherboard has multiple management modules, including but not limited to voltage monitoring module, temperature monitoring module, fan management module, power management module, backplane / hard disk management module, AIC (Application Interface Card) card management module, CPU (Central Processing Unit) management module, and memory management module.
[0026] In some embodiments, the second motherboard includes a second connector, a second controller (i.e., a second BMC), and a second logic unit (i.e., a second CPLD). Specifically, Figure 3 A schematic diagram of the structure of the first motherboard provided in the embodiments of this application is shown below. Figure 3 As shown, the second connector on the second motherboard is connected to the first connector on the first motherboard via a cable, forming a bridge for signal and data communication between the two motherboards. This connection method ensures data synchronization and command transmission between the two motherboards.
[0027] The second CPLD on the second motherboard is connected to the first BMC on the first motherboard via a second pin (i.e., GPIO). This connection channel is used to send a second interrupt request signal (i.e., "Second Motherboard_Interrupt Request Signal") to the first BMC when an abnormality is detected in the second BMC, so that the first BMC can manage multiple management modules on the second motherboard. The second BMC on the second motherboard periodically sends a WatchDog signal to the second CPLD to detect whether the state of the second BMC is abnormal.
[0028] The second motherboard has multiple management modules, including but not limited to voltage monitoring module, temperature monitoring module, fan management module, power management module, backplane / hard drive management module, AIC card management module, CPU management module, and memory management module.
[0029] The dual-path management system described in the above embodiments enables the healthy BMC to take over the monitoring and management of the faulty motherboard when the BMC of either motherboard malfunctions. This approach not only simplifies server redundancy design but also improves system reliability, ensuring service continuity and data security.
[0030] It should be noted that the PCBA (Printed Circuit Board Assembly) of the first and second motherboards mentioned above is the same and can be interchanged.
[0031] In some exemplary embodiments, the first motherboard further includes: a first chip connected to a first logic device, used to transmit the acquired status information of multiple management modules on the first motherboard to the first logic device; the second motherboard further includes: a second chip connected to a second logic device, used to transmit the acquired status information of multiple management modules on the second motherboard to the second logic device.
[0032] In some embodiments, such as Figure 2 As shown, the first motherboard also includes a first chip (i.e., the first IO (Input / Output) expansion chip). The first CPLD communicates with the first IO expansion chip through the LTPI3 (LVDS Tunneling Protocol Interface) signal. The first CPLD acts as a host and communicates with the first IO expansion chip through the LTPI3 signal to monitor and manage multiple monitoring and management modules.
[0033] The first IO expansion chip supports ADC (Analog to Digital Converter) interface, I2C (Inter-Integrated Circuit) interface and I3C (Improved Inter-Integrated Circuit) interface. Through these interfaces, it performs voltage monitoring, temperature monitoring, fan management, power management, backplane / hard disk management, AIC card management, CPU management, memory management, etc., and transmits the status information (such as voltage, temperature, power, etc.) of multiple management modules on the first motherboard to the first CPLD.
[0034] In some embodiments, such as Figure 3As shown, the second motherboard also includes a second chip (i.e., a second IO (Input / Output) expansion chip). The second CPLD communicates with the second IO expansion chip through the LTPI3 (LVDS Tunneling Protocol Interface) signal. The second CPLD acts as a host and communicates with the second IO expansion chip through the LTPI3 signal to monitor and manage multiple monitoring and management modules.
[0035] The second IO expansion chip supports ADC interface, I2C interface and I3C interface. Through the above interfaces, voltage monitoring, temperature monitoring, fan management, power management, backplane / hard disk management, AIC card management, CPU management, memory management, etc. are performed, and the status information (such as voltage, temperature, power, etc.) of multiple management modules on the second motherboard is transmitted to the second CPLD.
[0036] In the above embodiments, by setting the first chip and the second chip on the first motherboard and the second motherboard respectively, the direct connection between the BMC and the management module is simplified, the use of cables is reduced, and the installation complexity of the server is reduced.
[0037] In some exemplary embodiments, the first controller is interconnected with the first logic device via a first interface signal to manage multiple management modules on the first motherboard; the second controller is interconnected with the second logic device via a second interface signal to manage multiple management modules on the second motherboard.
[0038] In some embodiments, the first BMC of the first motherboard is interconnected with the first CPLD via a first interface signal (i.e., LTPI1). The first BMC acts as the host and the first CPLD acts as the slave. The first BMC communicates with the first CPLD via the LTPI1 signal, allowing the first CPLD to feed back the status information of multiple management modules on the first motherboard to the first BMC, thereby realizing indirect monitoring and management of multiple management modules on the first motherboard.
[0039] It should be noted that in a dual-channel management system, if the first motherboard and the second motherboard are operating normally, and the first BMC of the first motherboard directly monitors and manages the management modules of the first motherboard, and indirectly monitors and manages the management modules of the second motherboard, then the LTPI1 signal and the "second motherboard_LTPI2 signal" of the second BMC on the second motherboard are not used by default.
[0040] Specifically, when the first BMC of the first motherboard indirectly monitors and manages the various management modules of the second motherboard, the first BMC of the first motherboard connects to the first connector through the "1st Motherboard_LTPI2 signal", and then connects to the second connector of the second motherboard through a cable, thereby transmitting the "1st Motherboard_LTPI2 signal" to the second CPLD. That is, the first BMC communicates with the second CPLD through the "1st Motherboard_LTPI2 signal" to indirectly monitor and manage the various management modules of the second motherboard.
[0041] In some embodiments, the second BMC of the second motherboard is interconnected with the second CPLD via a second interface signal (i.e., LTPI1). The second BMC acts as the host, and the second CPLD acts as the slave. The second BMC communicates with the second CPLD via the LTPI1 signal, allowing the second CPLD to feed back the status information of multiple management modules on the second motherboard to the second BMC, thereby realizing indirect monitoring and management of multiple management modules on the second motherboard.
[0042] It should be noted that in a dual-channel management system, if the first motherboard and the second motherboard are operating normally, and the second BMC of the second motherboard is used to directly monitor and manage the management modules of the second motherboard, and indirectly monitor and manage the management modules of the first motherboard, then the LTPI1 signal and the "first motherboard_LTPI2 signal" of the first BMC on the first motherboard are not used by default.
[0043] Specifically, when the second BMC of the second motherboard indirectly monitors and manages the various management modules of the first motherboard, the second BMC of the second motherboard is connected to the second connector through the "Second Motherboard_LTPI2 signal", and then connected to the first connector of the first motherboard through the cable, thereby transmitting the "Second Motherboard_LTPI2 signal" to the first CPLD. That is, the second BMC communicates with the first CPLD through the "Second Motherboard_LTPI2 signal" to indirectly monitor and manage the various management modules of the first motherboard.
[0044] In the above embodiments, the split-board dual-socket server system can monitor and manage the management modules on both motherboards, while ensuring the stable operation and high reliability of the system.
[0045] In some exemplary embodiments, the first logic device is connected to a second logic device on the second motherboard via a first pin, so that the second logic device receives a first interrupt request signal; the second logic device is connected to the first logic device on the first motherboard via a second pin, so that the first logic device receives a second interrupt request signal.
[0046] In some embodiments, if the first BMC of the first motherboard directly monitors and manages each management module of the first motherboard, the LTPI1 signal of the second BMC on the second motherboard is not used by default. Then, the first CPLD is connected to the second CPLD on the second motherboard through the first pin. When the first BMC on the first motherboard malfunctions, the second CPLD can receive the "first motherboard_interrupt request signal" to notify the second motherboard to take over the management capabilities of the first motherboard. In this way, the second BMC can directly monitor and manage each management module of the second motherboard, and indirectly monitor and manage each management module of the first motherboard.
[0047] In some embodiments, if the management modules of the second motherboard are directly monitored and managed by the second BMC of the second motherboard, the LTPI1 signal of the first BMC on the first motherboard is not used by default. Then, the second CPLD is connected to the first CPLD on the first motherboard through the second pin. When the second BMC on the second motherboard malfunctions, the first CPLD can receive the "Second Motherboard_Interrupt Request Signal" to notify the first motherboard to take over the management capabilities of the second motherboard. In this way, the first BMC can directly monitor and manage the management modules of the first motherboard and indirectly monitor and manage the management modules of the second motherboard.
[0048] In the above embodiments, the interconnection mechanism between the first CPLD and the second CPLD provides rapid anomaly response and intelligent switching, significantly enhancing the stability and reliability of the split-board dual-socket server system.
[0049] In some exemplary embodiments, the dual-path management system further includes: a motherboard identification setting module; the motherboard identification setting module is used to set the identification signal levels of the first motherboard and the second motherboard respectively.
[0050] In some embodiments, the dual-channel management system further includes a motherboard identifier setting module. Figure 4 This is a schematic diagram of the structure of the motherboard identifier setting module provided in an embodiment of this application, as shown below. Figure 4 As shown, the motherboard identification setting module sets the first motherboard identification signal to low level (i.e., connected to GND) and the second motherboard identification signal to high level (i.e., connected to VDD) through the connector at end A of the cable.
[0051] For example, a first motherboard identification signal (low level) is input to the CPLD and BMC. The CPLD and BMC determine whether the current motherboard is the first motherboard or the second motherboard through the first motherboard identification signal. The first CPLD of the first motherboard communicates with the first BMC by default through the LTPI1 signal, and the second CPLD of the second motherboard communicates with the first motherboard by default through the "first motherboard_LTPI2 signal".
[0052] It should be noted that the motherboard identification setting module can also set the first motherboard identification signal to a high level (i.e., connected to VDD) and the second motherboard identification signal to a low level (i.e., connected to GND) via the cable A connector. The identification signal levels of the first and second motherboards can be set according to actual needs. For example, the identification signal levels... Figure 2 and Figure 3 In the configuration, "First Motherboard_In-Situ Signal" and "Second Motherboard_In-Situ Signal" are configured such that the "First Motherboard_In-Situ Signal" of the first motherboard is set to a high level, and the "Second Motherboard_In-Situ Signal" of the second motherboard is set to a low level.
[0053] This application provides a dual-path management method, in which a processing process for dual-path management runs on the dual-path management system. The dual-path management method is described in detail below, along with its execution flow. Figure 5 As shown, in the event of a malfunction in the first controller on the first motherboard, the method includes the following steps S502-S504:
[0054] In step S502, the first logic unit of the first motherboard receives a health monitoring signal sent by the first controller;
[0055] In some embodiments, during normal operation of the dual-path management system, the first controller (i.e., the first BMC) on the first motherboard can periodically send health monitoring signals (i.e., watchdog signals) to the first logic unit (i.e., the first CPLD) on the first motherboard with which it communicates. By periodically sending the watchdog signal, the health status of the first BMC is indicated. If the watchdog signal is not sent, it indicates that the status of the first BMC is abnormal and it cannot operate normally.
[0056] In step S504, if the health monitoring signal is abnormal, the second controller of the second motherboard receives the first interrupt request signal and manages multiple management modules on the first motherboard.
[0057] In some embodiments, when the first CPLD detects an abnormality in the WatchDog signal sent by the first BMC (e.g., the WatchDog signal times out and is not sent), it indicates that the first BMC is in a faulty or unstable state. At this time, the first CPLD will send a first interrupt request signal (i.e., "first motherboard_interrupt request signal") to the second controller (i.e., the second BMC) on the second motherboard. That is, the second controller of the second motherboard receives the first interrupt request signal and manages multiple management modules on the first motherboard.
[0058] The sending of the "First Motherboard_Interrupt Request Signal" mentioned above triggered the system's abnormal recovery process, requesting the Second BMC to take over multiple management modules on the First Motherboard, such as... Figure 2As shown, the multiple management modules on the first motherboard include, but are not limited to, a voltage monitoring module, a temperature monitoring module, a fan management module, a power management module, a backplane / hard drive management module, an AIC card management module, a CPU management module, and a memory management module.
[0059] In response to the "First Motherboard_Interrupt Request Signal", the second BMC manages multiple management modules on the first motherboard. Specifically, by activating the previously unused "Second Motherboard_LTPI2 Signal", the second BMC establishes a communication link with the first CPLD on the first motherboard, thereby monitoring and managing the first motherboard.
[0060] Steps S502-S504 above, through the collaborative operation between the first CPLD and the second BMC, ensure that even in the event of a first BMC malfunction, the server's operation and service continuity can be maintained by quickly switching management units. Furthermore, the sending of the first interrupt request signal triggers an automated takeover mechanism, allowing the second BMC to take over the management capabilities of the first motherboard. This enables the dynamic reallocation of resources in the server system (such as monitoring and management functions) based on real-time needs, avoiding the need for manual intervention, significantly shortening the time interval from fault detection to system recovery, and improving the overall stability and redundancy of the system. This solves the technical problem in a split-board dual-path management system where a single controller monitors and manages two motherboards, causing the entire system's monitoring and management functions to fail if the controller malfunctions, thus leading to system malfunctions. This achieves the technical effect of ensuring stable system operation and improving system security.
[0061] In some exemplary embodiments, before the first logic unit of the first motherboard receives the health monitoring signal sent by the first controller, the method further includes: the first logic unit of the first motherboard managing multiple management modules on the first motherboard through a first chip, wherein the first chip is used to obtain the status information of the multiple management modules on the first motherboard; and the first controller of the first motherboard managing multiple management modules on the second motherboard through a first motherboard signal, wherein the first motherboard signal is used to transmit the status information of the multiple management modules on the second motherboard.
[0062] In some embodiments, before the first CPLD of the first motherboard receives the WatchDog signal sent by the first BMC, the first chip (first IO expansion chip) communicates with the first CPLD via the LTPI3 signal. The first CPLD acts as a host and monitors and manages multiple management modules via the LTPI3 signal.
[0063] The first IO expansion chip supports ADC interface, I2C interface and I3C interface. Through the above interfaces, it can perform voltage monitoring, temperature monitoring, fan management, power management, backplane / hard disk management, AIC card management, CPU management, memory management, etc., and transmit the status information (such as voltage, temperature, power, etc.) of multiple management modules on the first motherboard to the first CPLD.
[0064] Furthermore, when the first BMC of the first motherboard indirectly monitors and manages the various management modules of the second motherboard, the first BMC of the first motherboard is connected to the first connector through the first motherboard signal (i.e., the "first motherboard_LTPI2 signal"), and then connected to the second connector of the second motherboard through a cable, thereby transmitting the "first motherboard_LTPI2 signal" to the second CPLD. That is, the first BMC communicates with the second CPLD through the "first motherboard_LTPI2 signal" to indirectly monitor and manage multiple management modules of the second motherboard. The "first motherboard_LTPI2 signal" is used to transmit the status information (such as voltage, temperature, power supply, etc.) of multiple management modules on the second motherboard.
[0065] In some exemplary embodiments, after the first logic unit of the first motherboard receives the health monitoring signal sent by the first controller, the dual-path management method further includes: the first logic unit of the first motherboard is connected to the second controller of the second motherboard through a first pin; in the event of an abnormal health monitoring signal, the first logic unit of the first motherboard sends a first interrupt request signal to the second controller of the second motherboard and cuts off communication with the first controller.
[0066] In some embodiments, a first CPLD on a first motherboard is connected to a second BMC on a second motherboard via a first pin (i.e., GPIO). This connection channel is used to send a first interrupt request signal (i.e., "First Motherboard_Interrupt Request Signal") to the second BMC on the second motherboard when an abnormality is detected in the first BMC, and the first CPLD disconnects the LTPI1 communication with the first BMC, so that the second BMC can manage multiple management modules on the first motherboard.
[0067] In some exemplary embodiments, the dual-path management method further includes: a first logic of the first motherboard is connected to a second logic of the second motherboard via a first pin; the first logic of the first motherboard sends a first interrupt request signal to the second logic of the second motherboard, so that the second motherboard manages multiple management modules on the second motherboard through the second logic.
[0068] In some embodiments, the first CPLD of the first motherboard is connected to the second CPLD on the second motherboard through a first pin. When the first BMC on the first motherboard malfunctions, the second CPLD of the second motherboard can receive the "first motherboard_interrupt request signal" sent by the first CPLD, notifying the second motherboard to take over the management capabilities of the first motherboard. Then, the second BMC can directly monitor and manage each management module of the second motherboard, and indirectly monitor and manage each management module of the first motherboard.
[0069] In some exemplary embodiments, in the event of an abnormal health monitoring signal from the first controller, a first interrupt request signal is received, and multiple management modules on the first motherboard are managed.
[0070] In some embodiments, when the first CPLD detects an anomaly in the WatchDog signal sent by the first BMC (e.g., the WatchDog signal times out and is not sent), it indicates that the first BMC is in a faulty or unstable state. The second BMC on the second motherboard receives the "first motherboard_interrupt request signal" and takes over multiple management modules on the first motherboard.
[0071] In the above embodiments, by receiving the first interrupt request signal, the second BMC can take over the management capabilities of the first motherboard, enabling the resources in the server system (such as monitoring and management functions) to be dynamically reallocated according to real-time needs, avoiding the need for manual intervention, greatly shortening the time interval from fault detection to system recovery, and improving the overall stability and redundancy of the system.
[0072] In some exemplary embodiments, before the second controller of the second motherboard receives the first interrupt request signal and manages the multiple management modules on the first motherboard, the dual-path management method further includes: the second logic unit of the second motherboard transmits the status information of the multiple management modules on the second motherboard through the first motherboard signal.
[0073] In some embodiments, when the first BMC of the first motherboard indirectly monitors and manages each management module of the second motherboard, the second CPLD transmits the status information (such as voltage, temperature, power supply, etc.) of multiple management modules on the second motherboard to the first BMC through the received first motherboard signal (i.e., "first motherboard_LTPI2 signal").
[0074] In some exemplary embodiments, the second controller of the second motherboard receives a first interrupt request signal and manages multiple management modules on the first motherboard, including: the second controller of the second motherboard is connected to a first logic device of the first motherboard through a first pin and receives the first interrupt request signal; based on the first interrupt request signal, the second controller of the second motherboard manages multiple management modules on the first motherboard through second motherboard signals, wherein the second motherboard signals are used to transmit status information of multiple management modules on the first motherboard.
[0075] In some embodiments, the second BMC is connected to the first CPLD on the first motherboard via a first pin. When the first BMC on the first motherboard malfunctions, the second BMC can receive the "1st Motherboard_Interrupt Request Signal". Based on the "1st Motherboard_Interrupt Request Signal", the second BMC establishes a communication link with the first CPLD on the first motherboard via the second motherboard signal ("2nd Motherboard_LTPI2 Signal"), thereby monitoring and managing the first motherboard. The "2nd Motherboard_LTPI2 Signal" is used to transmit the status information of multiple management modules on the first motherboard.
[0076] In some exemplary embodiments, the dual-path management method further includes: a second logic unit on the second motherboard manages multiple management modules on the second motherboard through a second chip, wherein the second chip is connected to the second logic unit and is used to obtain status information of the multiple management modules on the second motherboard.
[0077] In some embodiments, when the first motherboard and the second motherboard are operating normally in the dual-path management system, the first BMC of the first motherboard directly monitors and manages each management module of the first motherboard, and indirectly monitors and manages each management module of the second motherboard.
[0078] In the event of an anomaly in the first BMC of the first motherboard, the second motherboard takes over the monitoring and management capabilities of the first motherboard. That is, the second motherboard directly monitors and manages the various management modules on the second motherboard, and indirectly monitors and manages the various management modules of the first motherboard. At this time, the second chip (the second IO expansion chip) communicates with the second CPLD through the LTPI3 signal. The second CPLD acts as the host and monitors and manages multiple monitoring and management modules through the LTPI3 signal.
[0079] The second IO expansion chip supports ADC interface, I2C interface and I3C interface. Through the above interfaces, voltage monitoring, temperature monitoring, fan management, power management, backplane / hard disk management, AIC card management, CPU management, memory management, etc. are performed, and the status information (such as voltage, temperature, power, etc.) of multiple management modules on the second motherboard is transmitted to the second CPLD.
[0080] In some exemplary embodiments, the first motherboard and the second motherboard are determined according to the level corresponding to the motherboard identification signal, and the printed circuit boards of the first motherboard and the second motherboard are the same.
[0081] In some embodiments, the motherboard identification signal can distinguish between a first motherboard and a second motherboard by setting different levels (voltage levels) to indicate the motherboard.
[0082] Specifically, the level value (high or low) of the motherboard identification signal determines whether the current motherboard is the first motherboard or the second motherboard. For example, by default, the motherboard identification signal of the first motherboard can be set to a low level, while the motherboard identification signal of the second motherboard can be set to a high level, thereby clearly identifying the identity of each motherboard.
[0083] In some embodiments, the PCBAs of the first and second motherboards are identical. Therefore, the PCBAs of the first and second motherboards follow the same template and standards in terms of circuit layout, component placement, and signal routing. Either motherboard can replace the other in both position and function, improving system flexibility and ease of maintenance. Furthermore, the identical PCBA design reduces production costs and simplifies quality control processes.
[0084] The embodiments described above are merely some embodiments of this application, and not all embodiments. To better understand the above methods, the following description, in conjunction with embodiments, illustrates the process, but is not intended to limit the technical solutions of the embodiments of this application. Specifically:
[0085] Figure 6 The overall flowchart of the dual-path management method provided in the scenario embodiment of this application is as follows: Figure 6 As shown, in the event of an anomaly in the first controller on the first motherboard, the dual-channel management method includes the following steps:
[0086] Step S601, Begin;
[0087] Step S602: The first motherboard BMC monitors and manages the first motherboard and the second motherboard.
[0088] Specifically, after power-on, under normal operation of the first motherboard and the second motherboard in the dual-channel management system, the first motherboard BMC acts as the host, communicating with the first motherboard CPLD through the LTPI1 signal and monitoring and managing the first motherboard. At the same time, the first motherboard BMC communicates with the second motherboard CPLD through the "first motherboard_LTPI2 signal" and monitors and manages the second motherboard. The first motherboard BMC periodically sends a watchdog timer signal to the first motherboard CPLD to indicate the health status of the first motherboard BMC.
[0089] Step S603: The first motherboard CPLD and the second motherboard CPLD acquire status information of multiple management modules;
[0090] Specifically, the first motherboard CPLD and the second motherboard CPLD, acting as hosts, communicate with the IO expansion chip via the LTPI3 signal to monitor and manage the ADC / I2C / I3C devices. The first motherboard CPLD obtains the status information of each management module on the first motherboard and feeds it back to the first motherboard BMC via LTPI1. The first motherboard CPLD obtains the status information of each management module on the second motherboard via the "first motherboard_LTPI2 signal".
[0091] Step S604: Determine if the WatchDog signal of the first motherboard BMC is abnormal;
[0092] Specifically, the first motherboard CPLD periodically detects the WatchDog signal of the first motherboard BMC. If the health status of the first motherboard BMC is abnormal, step S604 is executed.
[0093] If the health status of the first motherboard BMC is normal, return to step S603 and continue to periodically check whether the WatchDog signal of the first motherboard BMC is abnormal.
[0094] In step S605, the first motherboard CPLD sends a "First Motherboard_Interrupt Request Signal" to the second motherboard, requesting the second motherboard BMC to take over the monitoring and management capabilities of the first motherboard;
[0095] Specifically, in the event of an anomaly in the first BMC, the first motherboard CPLD sends a "First Motherboard_Interrupt Request Signal" to the second motherboard BMC and the second motherboard CPLD, requesting the second motherboard BMC to take over the monitoring and management capabilities of the first motherboard. At the same time, the first motherboard CPLD disconnects the LTPI1 communication with the first motherboard BMC and communicates with the second motherboard BMC through the "Second Motherboard_LTPI2 Signal". The second motherboard BMC then monitors and manages the first motherboard.
[0096] Step S606: The second motherboard BMC takes over the monitoring and management capabilities of the first motherboard.
[0097] Specifically, the second motherboard BMC monitors and manages the first motherboard through the "Second Motherboard_LTPI2 signal", while the second motherboard BMC monitors and manages the second motherboard through the LTPI1 signal;
[0098] Step S607, End.
[0099] Through steps S601-S607, status information is collected from multiple monitoring and management modules and control signals are output via the IO expansion chip. Simultaneously, a CPLD is added between the BMC and the IO expansion chip for switching. The first and second motherboards are connected via cables, enabling the BMC on each motherboard to manage both. This means that when the first motherboard's BMC malfunctions, the second motherboard's BMC can promptly take over and manage the system, ensuring stable server operation. This solves the technical problem in a split-board dual-path management system where a single BMC monitors and manages two motherboards, causing the entire system's monitoring and management functions to fail and leading to system malfunctions. This achieves the technical effect of ensuring stable system operation and improving system security.
[0100] It should be noted that the above steps S601-S607 are the procedures executed when the first BMC on the first motherboard malfunctions. If the second BMC on the second motherboard malfunctions, the procedures executed in steps S601-S607 are the same or similar, and will not be described in detail here.
[0101] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0102] Embodiments of this application also provide a server including components of any of the dual-path management systems described above.
[0103] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0104] The dual-path management system and method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A dual-path management system, characterized in that, include: First motherboard, second motherboard; The first motherboard includes a first connector, a first controller, and a first logic unit. The first logic unit is connected to the second controller of the second motherboard via a first pin and is used to send a first interrupt request signal to the second controller when an abnormality is detected in the first controller, so that the second controller can manage multiple management modules on the first motherboard. The second motherboard includes a second connector, a second controller, and a second logic unit. The second logic unit is connected to the first controller of the first motherboard via a second pin and is used to send a second interrupt request signal to the first controller when an abnormality is detected in the second controller, so that the first controller can manage multiple management modules on the second motherboard. The first connector of the first motherboard is connected to the second connector of the second motherboard via a cable; The first motherboard further includes: a first chip connected to the first logic device, used to transmit the acquired status information of multiple management modules on the first motherboard to the first logic device; the second motherboard further includes: a second chip connected to the second logic device, used to transmit the acquired status information of multiple management modules on the second motherboard to the second logic device; the first controller is interconnected with the first logic device through a first interface signal to manage multiple management modules on the first motherboard; the second controller is interconnected with the second logic device through a second interface signal to manage multiple management modules on the second motherboard. The first logic device is connected to the second logic device of the second motherboard via a first pin, so that the second logic device can receive the first interrupt request signal; the second logic device is connected to the first logic device of the first motherboard via a second pin, so that the first logic device can receive the second interrupt request signal.
2. A dual-path management method, characterized in that, include: The first logic unit of the first motherboard receives a health monitoring signal sent by the first controller; In the event of an abnormal health monitoring signal, the second controller on the second motherboard receives a first interrupt request signal and manages multiple management modules on the first motherboard.
3. The method according to claim 2, characterized in that, Before the first logic unit of the first motherboard receives the health monitoring signal sent by the first controller, the method further includes: The first logic unit of the first motherboard manages multiple management modules on the first motherboard through a first chip, wherein the first chip is used to obtain the status information of the multiple management modules on the first motherboard; The first controller of the first motherboard manages multiple management modules on the second motherboard through a first motherboard signal, wherein the first motherboard signal is used to transmit the status information of the multiple management modules on the second motherboard.
4. The method according to claim 2, characterized in that, After the first logic unit of the first motherboard receives the health monitoring signal sent by the first controller, the method further includes: The first logic of the first motherboard is connected to the second controller of the second motherboard via a first pin; In the event of an abnormal health monitoring signal, the first logic unit of the first motherboard sends a first interrupt request signal to the second controller of the second motherboard and cuts off communication with the first controller.
5. The method according to claim 4, characterized in that, Also includes: The first logic of the first motherboard is connected to the second logic of the second motherboard via a first pin; The first logic of the first motherboard sends a first interrupt request signal to the second logic of the second motherboard, so that the second motherboard can manage multiple management modules on the second motherboard through the second logic.
6. The method according to claim 2, characterized in that, Before the second controller of the second motherboard receives the first interrupt request signal and manages the multiple management modules on the first motherboard, the method further includes: The second logic unit of the second motherboard transmits status information of multiple management modules on the second motherboard through the first motherboard signal.
7. The method according to claim 2, characterized in that, The second controller of the second motherboard receives the first interrupt request signal and manages multiple management modules on the first motherboard, including: The second controller of the second motherboard is connected to the first logic unit of the first motherboard via the first pin and receives the first interrupt request signal; Based on the first interrupt request signal, the second controller of the second motherboard manages multiple management modules on the first motherboard through the second motherboard signal, wherein the second motherboard signal is used to transmit the status information of the multiple management modules on the first motherboard.
8. The method according to claim 2, characterized in that, Also includes: The second logic unit of the second motherboard manages multiple management modules on the second motherboard through a second chip, wherein the second chip is connected to the second logic unit and is used to obtain the status information of the multiple management modules on the second motherboard.
9. The method according to claim 2, characterized in that, in, The first motherboard and the second motherboard are determined according to the level corresponding to the motherboard identification signal, and the printed circuit boards of the first motherboard and the second motherboard are the same.
10. A server, characterized in that, Includes the dual-path management system described in claim 1.