Delay search method and system of delay phase-locked loop, computer and medium

Abstract

The invention discloses a delay search method and system for a delay phase-locked loop, a computer and a medium, and the method comprises the following steps: enabling a signal to activate a finite-state machine, and jumping to a search state; based on the preset configuration of the finite-state machine, linear step length search is carried out in the guard band range to locate a target phase, if the target phase is not found in the guard band range, linear step length search is carried out again after the guard band range is expanded, and when the real-time phase is equal to the target phase, a symbol state is entered; in the symbol state, the slope of real-time phase change is calculated, and symbol matching is verified; and if the symbols are matched, entering a phase-locked state, fixing a real-time delay change value in the phase-locked state, and pulling up a phase-locked loop activation signal. According to the invention, the digital code which is output by the phase discriminator and represents the phase relationship between the reference clock and the input clock can be received, the delay is searched in a linear search mode, the control signal is sent to the delay line, and the clock delay is changed until the clock meeting the requirement is generated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor phase-locked loop (PLL) circuit technology, and particularly to a delay search method and approach for a delay PLL. Background Technology

[0002] A delay-locked loop (PLL) can be considered a further development of PLL technology. It is a negative feedback control system based on phase delay, consisting of a phase detector, a charge pump, a loop filter, and a voltage-controlled delay line (VCD). Unlike traditional PLLs, the delay-locked loop adjusts the phase delay of the reference clock through the VCD, ensuring that the output clock is in phase with the reference clock.

[0003] Compared to phase-locked loops (PLLs), delay-locked loops (DLLs) offer the following advantages: No jitter accumulation – As a first-order system, DLLs do not suffer from jitter accumulation, resulting in better output clock jitter performance; Shorter lock time – DLLs have a faster response speed and shorter lock time; Higher stability – The DLL loop exhibits unconditional stability and will not experience instability; Smaller area – As a first-order system, it occupies less chip area than second-order PLL systems.

[0004] A digital delay-locked loop (DLL) mainly consists of a phase detector, a digital control module, and a digitally controlled delay line. The DLL replaces the charge pump and filter in a traditional DLL with a delay search algorithm, resulting in a simpler circuit structure, faster locking speed, stronger anti-interference capability, and greater flexibility. Summary of the Invention

[0005] To address the shortcomings of the prior art, the technical problem to be solved by this invention is: to propose a delay search method for a delay phase-locked loop, which can receive a digital code representing the phase relationship between the reference clock and the input clock output by a phase detector, search for the delay using a linear search method and send a control signal to the delay line, thereby changing the clock delay until a clock that meets the requirements is generated.

[0006] One technical solution adopted by this invention is: providing a delay search method for a delay phase-locked loop, the method comprising the following steps: S1. The enable signal activates the finite state machine, causing it to jump from the idle state to the search state; S2. Based on the preset configuration of the finite state machine, a linear step search is performed within the protection zone to locate the target phase. If the target phase is not found within the protection zone, the protection zone is expanded and a linear step search is performed again. When the real-time phase is equal to the target phase, the finite state machine enters the symbol state. S3. In the symbol state, calculate the slope of the real-time phase change by testing the increase or decrease of the delay, and verify the symbol matching; S4. If the symbols match, the finite state machine enters the phase-locked loop (PLL) state, where the real-time delay change value is fixed and the PLL activation signal is pulled high.

[0007] Furthermore, the method also includes the following steps: S5. In phase-locked state, monitor real-time phase changes. If the absolute value of the difference between the real-time phase and the target phase is greater than the preset threshold, re-enter the search state.

[0008] Furthermore, step S1 includes the following sub-steps: S11. In response to the activation of an external enable signal, the finite state machine exits the idle state; S12. The finite state machine automatically enters the search state and begins phase search.

[0009] Furthermore, step S2 includes the following sub-steps: S21. According to the preset search mode, control the delay increase / decrease signals to alternately assign values ​​to the real-time delay change value, and cause a change in the real-time phase; S22. Compare the real-time phase with the target phase. If they are equal, it means that the target phase has been found and the system enters the symbol state.

[0010] Furthermore, step S3 includes the following sub-steps: S31. The real-time delay change value is increased or decreased cyclically according to a preset step size, and the trend of the real-time delay change value is recorded. S32. Calculate the actual slope based on the change data of the real-time delay value; S33. Compare the actual slope with the preset slope. If the directions are the same, enter the phase-locked state. Otherwise, return to step S2.

[0011] Furthermore, step S4 includes the following sub-steps: S41. The finite state machine enters the phase-locked loop state, fixes the real-time delay change value, and pulls the phase-locked loop activation signal high. S42. Based on the preset configuration, select to maintain phase-locked state or switch to tracking state.

[0012] Furthermore, step S5 includes the following sub-steps: S51. In tracking mode, continuously calculate the absolute value of the real-time phase difference and the target phase difference; S52. If the absolute value of the difference between the real-time phase and the target phase is greater than the preset threshold, the real-time phase change exceeds the limit. S53, the finite state machine jumps back to the search state and readjusts the phase.

[0013] The second technical solution adopted in this invention is a delay search system for a delay phase-locked loop, which includes the following modules: The enable entry module is used to activate the finite state machine with an enable signal, causing it to jump from the idle state to the search state; The phase search module, based on the preset configuration of the finite state machine, performs a linear step search within the protection zone to locate the target phase. If the target phase is not found within the protection zone, the protection zone is expanded and the linear step search is performed again. When the real-time phase is equal to the target phase, the finite state machine enters the symbol state. The symbol entry module is used to calculate the slope of the real-time phase change and verify the symbol match by testing the increase or decrease of the delay in the symbol state. The phase-locked module is used to put the finite state machine into a phase-locked state when the symbol is matched. In the phase-locked state, the real-time delay change value is fixed and the phase-locked loop activation signal is pulled high.

[0014] The third technical solution adopted by the present invention is a computer device, the computer device including a processor and a memory, the memory storing at least one instruction, at least one program, code set or instruction set, the at least one instruction, the at least one program, the code set or instruction set being loaded and executed by the processor to implement the delay search method of delay phase-locked loop as described in any of the above.

[0015] The fourth technical solution adopted by the present invention is a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the delay search method of delay phase-locked loop as described in any of the above claims.

[0016] The delay search method, system, computer, and medium of the delay phase-locked loop of the present invention have at least the following beneficial effects: 1. Simplified circuit structure and reduced hardware complexity: The algorithm directly replaces the charge pump and loop filter in traditional DLLs with digital delay search mechanisms (such as FSM and logic control). This design eliminates the dependence on complex analog components, reduces chip area and power consumption, and is particularly suitable for high-performance integrated circuits (such as RF-DACs). The simplified circuit structure also improves manufacturability and maintainability.

[0017] 2. Faster locking speed and higher response efficiency: By combining linear step-size search with a guard band function, the algorithm prioritizes phase search within a preset range (e.g., guard0=208, guard1=223), avoiding full-range scanning. Linear search is easy to converge, and the guard band mechanism limits the initial search area, thus significantly shortening the locking time and adapting to high-speed application scenarios.

[0018] 3. Enhanced anti-interference capability and improved system stability: The algorithm introduces symbolic states for slope verification and real-time monitoring of the tracking state, effectively responding to external changes such as temperature and voltage. Symbolic matching ensures reliable locking points, while the tracking state can automatically readjust when phase drift exceeds a threshold. This design enhances the system's robustness in dynamic environments.

[0019] 4. Flexible search methods and wide adaptability: Supports multi-mode search (such as upward, downward, or alternating search), and the search direction can be configured via a programmable counter (such as counter4_1_delay). The guard band range is adjustable (such as guard0+guard1=431), and the algorithm can dynamically expand the search range based on boundary signals. This flexibility allows the algorithm to adapt to the needs of different phase and frequency changes. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of the delay search method for the delay phase-locked loop of the present invention.

[0021] Figure 2 This is a simulation waveform diagram of the search state of the present invention.

[0022] Figure 3 This is a simulation waveform diagram after the search is completed in this invention.

[0023] Figure 4 This is a simulation waveform diagram of the symbol state of the present invention.

[0024] Figure 5 The waveform diagram for the phase-locked state simulation of the present invention is shown.

[0025] Figure 6 This is a block diagram of the delay search system of the delay phase-locked loop of the present invention.

[0026] Figure 7 This is a schematic diagram of the state transitions of the finite state machine of the present invention. Detailed Implementation

[0027] The invention will now be further described with reference to the accompanying drawings.

[0028] Please see Figure 1 This is a flowchart of the delay search method for the delay phase-locked loop of the present invention. The method may include the following steps: S1. The enable signal activates the finite state machine, causing it to transition from the idle state to the search state. This S1 step implements the entire search process using a digital finite state machine (FSM), replacing the analog charge pump and filter components in a traditional delay-locked loop. This reduces hardware complexity, lowers chip area and power consumption, and makes the circuit easier to integrate and more reliable. See also... Figure 7 This is a state transition diagram of a finite state machine. The finite state machine in this scheme has seven main states: idle, search, single0, single1, sign, Ph_lock, and track. See the state transition diagram for details. Figure 1 Idle indicates the idle state, search indicates the search state, single0 indicates the single 0 state, single1 indicates the single 1 state, sign indicates the sign state, Ph_lock indicates the phase-locked state, and track indicates the tracking state.

[0029] This S1 step may include the following sub-steps: S11. In response to the activation of an external enable signal, the finite state machine exits the idle state. This S11 step ensures that the algorithm only starts when the enable signal is valid, avoiding accidental operation caused by unintended entry or power interference. This improves the stability and security of the system, making the initialization process controllable and reliable.

[0030] S12: The finite state machine automatically enters the search state and begins phase search. This S12 step enables seamless transitions between states, reducing human intervention or external delays. This improves the algorithm's response speed, ensures that phase search can begin immediately, and enhances overall efficiency.

[0031] S2. Based on the preset configuration of the finite state machine, a linear step search is performed within the guard band to locate the target phase. If the target phase is not found within the guard band, the guard band is expanded and the linear step search is performed again. When the real-time phase equals the target phase, the finite state machine enters the symbol state. The guard band search in step S2 (e.g., initial range guard0=208, guard1=223) limits the initial search area, avoiding full-range scanning. Combined with the linear step search, it improves the convergence speed and achieves faster phase locking.

[0032] This S2 step may include the following sub-steps: S21. According to the preset search mode, the control delay increment / decrement signal alternately assigns values ​​to the real-time delay change value, causing a real-time phase change. This step S21 optimizes the search path through multi-mode search (such as upward, downward, or alternating search), avoiding blind adjustment in a single direction. This reduces unnecessary delay changes, accelerates convergence, and improves the algorithm's adaptability to different phase change trends. The preset search mode is configured through three search directions via the counter counter4_1_delay: upward search, downward search, and alternating search. These modes are preset during algorithm initialization and are used to control the direction of delay adjustment. Setting counter4_1_delay to always high level enables upward search; setting it to always low level enables downward search; and setting its duty cycle to 50% enables alternating search.

[0033] S22. Compare the real-time phase with the target phase. If they are equal, the target phase has been found, and the system enters the symbol state. This step, S22, achieves high-precision phase matching detection, ensuring that the state transition only occurs when there is a perfect match. This reduces the risk of false locking, improves the accuracy of the search results, and lays the foundation for subsequent symbol verification. The assignment process involves alternately activating the finite state machine (FSM) control signals delay_minus and delay_plus, and assigning their values ​​to the output signal out_mu_delay to adjust the delay value. Specifically, delay_minus controls the delay to decrease, while delay_plus controls the delay to increase; both take turns in the alternating search mode.

[0034] S3. In the symbol state, the slope of the real-time phase change is calculated by testing the increase or decrease of the delay, and the symbol match is verified. This S3 step ensures the accuracy of the symbol match through preset step size cyclic testing and slope comparison. This reduces the risk of false locks and improves the accuracy of phase locking, making it particularly suitable for high-precision timing applications.

[0035] This S3 step may include the following sub-steps: S31. The real-time delay change value is cyclically increased and decreased according to a preset step size, and the trend of the real-time delay change value is recorded. This step S31 collects phase change data through step-size cyclic testing, providing sufficient basis for slope calculation. This enhances the scientific nature of the verification process, avoids misjudgment caused by temporary fluctuations, and improves the reliability of the locking point. The cyclic increase and decrease refers to the delay value being cyclically increased and then decreased or decreased and then increased according to a preset step size to collect phase change data. For example, the delay value is increased from the current point to the upper limit, and then decreased back to the original value to form a complete cycle. For example, in the symbol state, the delay value (out_mu_delay) is cyclically executed according to a programmable step size (such as step size 1): First increase: gradually increase from the initial value (such as 203) to the upper limit (such as 219), increasing by 1 unit each time. Then decrease: gradually decrease from the upper limit (219) back to the initial value (203), decreasing by 1 unit each time. The trend of the real-time phase (mu_phase) is recorded through this cycle and used to calculate the slope. The number of iterations (e.g., 16 times) and step size can be preset to ensure sufficient data.

[0036] S32. Based on the change data of the real-time delay value, calculate the actual slope. This step, S32, quantifies the phase change behavior with delay, shifting the verification process from qualitative to quantitative. This improves the objectivity of the locking point, reduces subjective errors, and is particularly suitable for high-precision applications.

[0037] S33. Compare the actual slope with the preset slope. If the directions are the same, enter phase-locked state; otherwise, return to step S2. This step S33 introduces a direction matching mechanism to effectively filter noise or abnormal phase points. This significantly improves anti-interference capability, ensuring that only phases that conform to expected behavior are locked, enhancing the system's robustness in dynamic environments. The preset slope is a user-configured expected slope value used to define the expected direction of phase change with delay (a positive slope indicates that the phase increases with increasing delay, and a negative slope indicates the opposite). Its core requirement is directional matching, that is, the sign (positive / negative) of the actual slope (slope_read) must be consistent, rather than precise numerical matching. It should be set based on system characteristics (such as delay line parameters) to ensure that its direction conforms to theoretical expectations.

[0038] S4. If the signs match, the finite state machine enters the phase-locked loop (PLL) state. In the PLL state, the real-time delay change value is fixed, and the PLL activation signal is pulled high. This S4 step enhances the performance of the delay-locked loop in high-speed, high-precision applications by locking the delay value and the activation signal.

[0039] This S4 step may include the following sub-steps: S41. The finite state machine enters phase-locked state, fixes the real-time delay change value, and pulls the phase-locked loop activation signal high. This step S41 permanently locks the delay value, eliminating jitter caused by subsequent adjustments. This improves the stability of the output clock, reduces power consumption, and simplifies system maintenance. The phase-locked loop activation signal (mu_lock) is a digital signal pulled high by the FSM in phase-locked state (Ph_lock). Its function is to indicate that the system has successfully locked the phase and entered a stable operating mode. After pulling this signal high, the delay value is fixed, the system stops searching and adjusting, and the output clock phase remains stable.

[0040] S42. According to the preset configuration, select to maintain phase-locked state or switch to tracking state. This S42 step provides a configurable operating mode, allowing users to balance power consumption and reliability based on application scenarios (such as static or dynamic environments). This enhances the algorithm's adaptability, enabling it to flexibly respond to different needs.

[0041] This method may also include the following steps: S5. In phase-locked state, monitor real-time phase changes. If the absolute value of the difference between the real-time phase and the target phase is greater than a preset threshold, re-enter the search state. This S5 step allows selection to maintain lock or switch to tracking state according to preset configuration, increasing the configurability of the algorithm. This enables the system to balance power consumption and reliability, adapt to static or dynamic working scenarios, and improve overall flexibility.

[0042] This S5 step may include the following sub-steps: S51. In tracking mode, continuously calculate the absolute value of the difference between the real-time phase and the target phase. This step S51 enables real-time phase drift monitoring, providing a data basis for lock-off detection. This allows the system to detect potential problems in advance and improves its sensitivity to external changes such as temperature and voltage.

[0043] S52. If the absolute value of the difference between the real-time phase and the target phase is greater than a preset threshold, the real-time phase change exceeds the limit. This step S52 sets a clear unlock threshold, ensuring the objectivity and consistency of the judgment. This avoids overly sensitive or sluggish responses and optimizes the system's behavior under critical conditions.

[0044] In step S53, the finite state machine jumps back to the search state and readjusts the phase. This step S53 enables an automatic recovery mechanism, correcting phase deviations without external intervention. This improves the system's fault tolerance and long-term operational stability, while reducing maintenance costs.

[0045] The principle of this method is as follows: When the circuit is powered on and enabled, the FSM exits the idle state and begins operation, searching for the desired phase within the guard band in an alternating increment / decrement manner. When the desired phase is found, the sign state is entered and the phase slope is calculated. If both the phase and sign match the expected settings, the FSM enters the phase-locked state (Ph_lock), and the corresponding delay value is locked. If no sign matches, the search continues until the next preset phase is found. Once the phase is locked, the FSM can be configured to remain in the Ph_lock state or the track state. In both states, the delay remains locked; the difference is that the track state records phase changes due to factors such as temperature, time, and power supply variations. If the phase change is too large, the FSM will lose lock, and the search state will restart.

[0046] First, let's explain the signals in the waveform: guard0 and guard1 are the guard band boundaries. To improve the speed of the linear search algorithm, guard bands are set to limit the initial search range. Since the delay range provided by the delay line controlled by this algorithm is at most 432, the initial delay setpoint is 216. Here, the lower guard band guard0 is set to 208, and the upper guard band guard1 is set to 223. When the boundary0 and boundary1 signals are high, it indicates that the search has reached the lower and upper guard bands. When the system detects the high level of boundary0 and boundary1, it will expand the range of the guard band to the entire search range. delay_minus and delay_plus control the decrease and increase of the delay, respectively, and alternately assign values ​​to out_mu_delay. counter4_1_delay controls the delay search method, namely upward search, downward search, and alternating search. When it is high, the delay is increased; when it is low, the delay is decreased. The delay in the waveform is shown in the figure. The delayed search method is an alternating search; `set_phase` sets the target phase; `find_phase` indicates whether the target phase has been found, a high level indicates it has been found, and a low level indicates it has not been found; `mu_phase` represents the real-time phase change, and when its value is the same as `set_phase`, it will pull the level of `find_phase` high; `out_mu_delay` represents the real-time delay change, and its value is alternately assigned by `delay_minus` and `delay_plus`; `mu_lock` is the phase-locked loop's phase-locked signal, and when it is high, it indicates that it has entered the phase-locked state; `state` is the state code of the state machine. Since there are seven states in total, 3 bits are needed for binary encoding: 000 represents the idle state, 001 represents the search state, 010 represents the single 0 state, 011 represents the single 1 state, 100 represents the sign state, 101 represents the phase-locked state (ph_lock), and 110 represents the tracking state.

[0047] Please see Figure 2 and Figure 3A multi-mode search function is implemented by introducing a counter, counter4_1_delay. Setting counter4_1_delay to a high level enables upward searching; setting it to a low level enables downward searching; and setting its duty cycle to 50% enables alternating searching. Furthermore, the guard band function is implemented using the two signals guard0 and guard1. The guard band range is adjustable and symmetrical. The adjustable delay range of the delay line ensures that guard0 + guard1 = 431. It is worth noting that regardless of the guard band settings, as long as boundary0 and boundary1 are detected to be high, the guard band will be activated, setting guard0 to 0 and guard1 to 431.

[0048] The addition of a protective band is to improve search speed. Besides search speed, to ensure the reliability of the algorithm, two states, "sign" and "track," are also designed. The "sign" state is the sign state, and the "track" state is the tracking state. The waveforms for the two states are shown below. Figure 4 and Figure 5 .

[0049] When the target phase is detected, the state machine enters the symbol state, and the delay value begins to increase in programmable steps. Figure 4 As can be seen, the delay value increases 16 times from 203 to 219, and then decreases 16 times from 219 back to 203. During this process, the phase change is continuously recorded, and the slope is determined based on the phase change. When slope_read matches the input slope, con_slope is set to 01, and the system enters phase-locked state.

[0050] Once in phase-locked state, you can choose whether to enter tracking state. When in tracking state, the current phase mu_phase is continuously compared with the target phase set_phase. The difference between the two values ​​is stored in the sign count mu_phase_delta. Once the sign count is detected to be greater than 2 or less than -2, the state machine will jump back to the search state. Figure 5 As can be seen, when mu_phase suddenly becomes 3, the difference between it and the value of set_phase is 5. At this time, the phase_drift signal is pulled high, and the control state machine enters the search state.

[0051] The following example illustrates the process of this method: A high-performance RF-DAC with 16-bit precision and a speed of up to 20 GSPS is designed using TSMC's 12nm FinFET process. This delay search algorithm is used to optimize the timing between the internal digital and analog domains of the RF-DAC. The core data signal and sampling clock of the D / A converter have an uncertain phase relationship. If the data is directly synchronized back to the analog sampling clock domain using the D / A converter's sampling clock, metastability may occur, leading to bit errors in the D / A converter's core data input and degrading the D / A converter's performance. To reduce crosstalk between the digital and analog circuits in the D / A converter, the digital domain clock and analog domain clock need to be separated. The input data of the high-speed data synchronization unit is synchronized with the digital domain clock, while the synchronization clock is the analog domain clock. Due to different path lengths, the phase relationship between the digital domain clock and the analog domain clock will change with the external environment. To ensure operational stability, a high-precision delay search algorithm is needed to adjust the timing of the high-speed data synchronization unit to meet requirements under various operating conditions.

[0052] Because the delay search algorithm can achieve timing adjustment by modifying the delay time in the delay circuit, it has high accuracy and stability, enabling precise adjustment of the phase and frequency of the clock signal to meet the system's timing requirements. Furthermore, the delay search algorithm has a wide search range, adapting to changes in the phase and frequency of different input signals. Compared to other timing adjustment circuits, it has a faster lock-in time. Once in search mode, the algorithm can quickly track and lock the input signal, reducing timing errors during system state transitions. Compared to other complex timing adjustment circuits, this algorithm achieves lower power consumption and a simpler circuit structure.

[0053] Please see Figure 6 The present invention provides a block diagram of a delay search system for a delay phase-locked loop. The system is used in the aforementioned delay search method for the delay phase-locked loop. The system may include the following modules: an enable entry module 100, a phase search module 200, a symbol entry module 300, and a phase locking module 400. Specifically, it includes: Enable module 100 is used to activate the finite state machine with an enable signal, causing it to jump from the idle state to the search state; The phase search module 200, based on the preset configuration of the finite state machine, performs a linear step search within the protection zone to locate the target phase. If the target phase is not found within the protection zone, the protection zone range is expanded. The symbol entry module 300 is used to monitor real-time phase changes by linearly adjusting the delay, so that the phase changes approach the target phase. If the real-time phase is equal to the target phase, the symbol state is entered. The phase-locked module 400 is used to calculate the slope of the real-time phase change by increasing or decreasing the test delay and to verify the sign match. If the match is found, it enters the phase-locked state.

[0054] In one embodiment of this application, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the delay search method for a delay phase-locked loop as described in any of the above embodiments.

[0055] In one embodiment of this application, a computer-readable storage medium is provided, which stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the delay search method of delay phase-locked loop as described in any of the above embodiments.

[0056] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0057] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A delay search method of a delay-locked loop, characterized by, The method includes the following steps: S1. The enable signal activates the finite state machine, causing it to jump from the idle state to the search state; S2. Based on the preset configuration of the finite state machine, a linear step search is performed within the protection zone to locate the target phase. If the target phase is not found within the protection zone, the protection zone is expanded and a linear step search is performed again. When the real-time phase is equal to the target phase, the finite state machine enters the symbol state. S3. In the symbol state, calculate the slope of the real-time phase change by testing the increase or decrease of the delay, and verify the symbol matching; S4. If the symbols match, the finite state machine enters the phase-locked loop (PLL) state, where the real-time delay change value is fixed and the PLL activation signal is pulled high.

2. The delay search method of a delay-locked loop as recited in claim 1, wherein, The method also includes the following steps: S5. In phase-locked state, monitor real-time phase changes. If the absolute value of the difference between the real-time phase and the target phase is greater than the preset threshold, re-enter the search state.

3. The delay search method of a delay-locked loop as recited in claim 1, wherein, Step S1 includes the following sub-steps: S11. In response to the activation of an external enable signal, the finite state machine exits the idle state; S12. The finite state machine automatically enters the search state and begins phase search.

4. The delay search method for a delay phase-locked loop as described in claim 1, characterized in that, Step S2 includes the following sub-steps: S21. According to the preset search mode, control the delay increase / decrease signals to alternately assign values ​​to the real-time delay change value, and cause a change in the real-time phase; S22. Compare the real-time phase with the target phase. If they are equal, it means that the target phase has been found and the system enters the symbol state.

5. The delay search method for a delay phase-locked loop as described in claim 1, characterized in that, Step S3 includes the following sub-steps: S31. The real-time delay change value is increased or decreased cyclically according to a preset step size, and the trend of the real-time delay change value is recorded. S32. Calculate the actual slope based on the change data of the real-time delay value; S33. Compare the actual slope with the preset slope. If the directions are the same, enter the phase-locked state. Otherwise, return to step S2.

6. The delay search method of a delay-locked loop as recited in claim 1, wherein, Step S4 includes the following sub-steps: S41. The finite state machine enters the phase-locked loop state, fixes the real-time delay change value, and pulls the phase-locked loop activation signal high. S42. Based on the preset configuration, select to maintain phase-locked state or switch to tracking state.

7. The delay search method of delay-locked loop as claimed in claim 2, wherein, Step S5 includes the following sub-steps: S51. In tracking mode, continuously calculate the absolute value of the real-time phase difference and the target phase difference; S52. If the absolute value of the difference between the real-time phase and the target phase is greater than the preset threshold, the real-time phase change exceeds the limit. S53, the finite state machine jumps back to the search state and readjusts the phase.

8. A delay search system of a delay-locked loop, characterized by, The system includes the following modules: The enable entry module is used to activate the finite state machine with an enable signal, causing it to jump from the idle state to the search state; The phase search module, based on the preset configuration of the finite state machine, performs a linear step search within the protection zone to locate the target phase. If the target phase is not found within the protection zone, the protection zone is expanded and the linear step search is performed again. When the real-time phase is equal to the target phase, the finite state machine enters the symbol state. The symbol entry module is used to calculate the slope of the real-time phase change and verify the symbol match by testing the increase or decrease of the delay in the symbol state. The phase-locked module is used to put the finite state machine into a phase-locked state when the symbol is matched. In the phase-locked state, the real-time delay change value is fixed and the phase-locked loop activation signal is pulled high.

9. A computer device, comprising: The computer device includes a processor and a memory, the memory storing at least one instruction, at least one program, a code set, or an instruction set, the at least one instruction, the at least one program, the code set, or the instruction set being loaded and executed by the processor to implement the delay search method for the delay phase-locked loop as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the delay search method for the delay phase-locked loop as described in any one of claims 1-7.

Images