Clock selection method and routing equipment

Abstract

The invention provides a method for selecting a clock and routing equipment, and the method comprises the steps: a branching device is connected with a data selector through multiple paths of signals, the data selector is also connected with a plurality of frequency point clocks, a target signal at a high level in the multiple paths of signals of the data selector is identified, and the target signal is sent to the branching device; and obtaining a target frequency point clock corresponding to the target signal according to the corresponding relationship, and outputting the target frequency point clock to an interface chip through a clock driver. Through the method, the frequency point clock can be automatically selected.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a method for selecting a clock and a routing device. Background Technology

[0002] MUX: Multiplexer (data selector); GPIO: General-Purpose Input / Output; In a distributed router architecture, the main control board is primarily responsible for highly complex tasks such as route calculation, protocol processing, and system management. It typically uses a general-purpose CPU as the main chip, while the service daughter cards (service boards) are responsible for providing different types of interfaces, such as gigabit optical ports. These generally use switching chips or FPGAs to achieve flexible interface type configuration. Both the main control board and the service daughter cards are connected to the backplane to establish data connectivity. The data path between them is typically a high-speed bus such as PCIe or SGMII. Additionally, some lower-speed buses such as IIC, SPI, and UART are used for management and control.

[0003] like Figure 1 As shown, current service daughter cards typically support multiple high-speed buses to adapt to different interface types and speeds. For different high-speed buses, the clock frequency requirements vary depending on their protocol requirements. For example, PCIe requires a 100MHz clock, SGMII requires a 125MHz clock, XAUI requires 156.2MHz, etc., posing a challenge for service daughter cards in clock source selection and switching. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this specification provides a method for selecting a clock and a routing device.

[0005] According to a first aspect of the embodiments of this specification, a method for selecting a clock is provided, the method being applied to a service board, the service board including: a splitter, a data selector, and a clock driver; The splitter is connected to a data selector via multiple signals. The data selector is also connected to multiple frequency clocks. The data selector is configured with a correspondence between different signals and different frequency clocks. Identify the target signal that is at a high level among the multiple signals of the data selector, and obtain the target frequency clock corresponding to the target signal according to the correspondence. The target frequency clock is output to the interface chip via a clock driver.

[0006] The splitter device includes: a GPIO chip; The GPIO chip is connected to the main control board via a low-speed bus, converting the low-speed signals from the main control board into multiple signals.

[0007] The data selector includes a MUX circuit.

[0008] The splitter is connected to the data selector via a multi-channel signal and includes: The multiplexing device's multiplexing signal is connected to the channel selection pin of the data selector.

[0009] The data selector is also connected to multiple frequency clocks, including: The input ports of the data selector are connected to multiple frequency clock crystals.

[0010] The splitter and / or data selector is a CPLD chip.

[0011] The methods described in the above embodiments enable the main control board to switch clock frequencies via a low-speed bus.

[0012] According to a second aspect of the embodiments of this specification, a routing device is provided, the routing device comprising: a service board, the service board comprising: a splitter, a data selector, a clock driver, and an interface chip; One end of the splitter is connected to the main control board via a low-speed bus, and the other end is connected to a data selector via a multiplexer to send multiple signals to the data selector. The data selector is also connected to multiple frequency clocks to acquire different frequency clocks; The data selector is configured with a correspondence between different signals and clocks at different frequencies; The data selector identifies a target signal that is at a high level among multiple signals and obtains the target frequency clock corresponding to the target signal according to the correspondence. The data selector outputs the target frequency clock to the interface chip via the clock driver.

[0013] The splitter device includes: a GPIO chip; The GPIO chip is connected to the main control board via a low-speed bus, converting the low-speed signals from the main control board into multiple signals.

[0014] The data selector is also connected to multiple frequency clocks, including: The input ports of the data selector are connected to multiple frequency clock crystals.

[0015] The splitter and / or data selector is a CPLD chip.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0018] Figure 1 This is a schematic diagram illustrating the connection between a main control board and a service sub-card according to an exemplary embodiment.

[0019] Figure 2 This is a schematic diagram illustrating the connection between a main control board and a service sub-card according to an exemplary embodiment.

[0020] Figure 3 This is a flowchart illustrating a method for selecting a clock according to an exemplary embodiment of this specification.

[0021] Figure 4 This is a schematic diagram illustrating the connection between a main control board and a service sub-card according to an exemplary embodiment. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0023] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0024] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0025] like Figure 2 As shown, existing clocking schemes that involve switching between multiple clock sources typically place a dedicated phase-locked loop (PLL) chip on the board. The main control board sends configurations to the PLL via a low-speed bus, and the PLL outputs the clock at the corresponding frequency for use by the interface chip, thus meeting the high-speed bus clock requirements.

[0026] In this embodiment, a phase-locked loop (PLL) typically includes four parts: a phase detector, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. Among them, the phase detector compares the phase difference between the input reference signal and the feedback signal, and outputs an error voltage signal that is proportional to the phase difference; Loop filter: Filters out high-frequency noise and spurious components from the phase detector output to obtain a smooth DC or low-frequency control voltage. It is a key component determining the dynamic performance of the PLL (such as stability, acquisition speed, and bandwidth). Voltage-controlled oscillator (VCO): The frequency of its output signal is linearly controlled by the control voltage output from the loop filter. The VCO is the frequency generation unit of the PLL. Frequency divider: Divides the VCO output frequency by N and feeds it back to the phase detector. By changing the division ratio N, different frequency output signals can be flexibly synthesized.

[0027] However, based on Figure 2 The clocking scheme for the phase-locked loop (PLL) chip in the text has the following problems: 1. Complex configuration: The clock frequency synthesis of phase-locked loop (PLL) chips is quite complex, involving many coupling parameters such as loop bandwidth and frequency division coefficient, making the configuration process overly complicated.

[0028] 2. High cost of the solution: Phase-locked loop (PLL) chips require programming and configuration, the chip technology is difficult, the material cost is high, and the product requires a large investment.

[0029] To address the aforementioned technical problems, this disclosure provides a method for selecting a clock. The method is applied to a service board, which includes a splitter, a data selector, and a clock driver. Figure 3 As shown, the method includes: The splitter described in S301 is connected to a data selector via multiple signals. The data selector is also connected to multiple frequency clocks. The data selector is configured with a correspondence between different signals and different frequency clocks. S302 identifies the target signal that is at a high level among the multiple signals of the data selector and obtains the target frequency clock corresponding to the target signal according to the correspondence. S303 outputs the target frequency clock to the interface chip through a clock driver.

[0030] In this embodiment, a splitter, a data selector, and a clock driver are used to replace the phase-locked loop to achieve automatic selection of clocks at different frequencies, which can effectively avoid cumbersome manual configuration and product hardware costs.

[0031] In this embodiment, the splitter can be a GPIO chip (General Purpose Input / Output), which is a programmable digital signal pin. Its core characteristic lies in its "versatility"—the same physical pin can be configured by software to determine whether its function is input or output, as well as its operating state (such as voltage level, drive capability, etc.).

[0032] The data selector can be a MUX circuit, and the clock driver can be a buffer (clock driver, ClockBuffer).

[0033] In one example, such as Figure 4 As shown, the existing PLL is replaced with a GPIO chip, MUX, and BUFFER. Specifically, the GPIO chip is connected to the main control board via a low-speed bus (e.g., IIC). The GPIO chip converts signals into multiple GPIO signals (e.g., ...). Figure 4 The GPIO chip is connected to the MUX via multiplexed signals (4 GPIO signals). Specifically, the multiplexed signals of the GPIO chip are connected to the channel selection pins of the data selector, such as... Figure 4 In this configuration, each GPIO signal is connected to SELECT1-SELECT4 on the MUX.

[0034] The input ports of the MUX are connected to multiple frequency clock crystals, such as... Figure 4 In the MUX, INPUT1-INPUT4 are connected to CLOCK1-CLOCK4 respectively (it should be noted that...) Figure 4 This is just an exemplary solution; in other embodiments, other crystal oscillator links may be connected.

[0035] In this embodiment, it is also necessary to set the correspondence between each multi-channel signal and each frequency clock. For example, configure INPUT1 to correspond to CLOCK1, INPUT2 to correspond to CLOCK2, INPUT3 to correspond to CLOCK3, and INPUT4 to correspond to CLOCK4.

[0036] In its implementation, the MUX can identify which pin among SELECT1-SELECT4 is at a high potential and set the pin at the high potential as the target signal. For example, if the MUX identifies that SELECT2 is at a high potential, then the MUX obtains CLOCK2 corresponding to SELECT2 and uses CLOCK2 as the target frequency clock.

[0037] For example, if the MUX detects that SELECT3 is at a high level, then the MUX obtains CLOCK3 corresponding to SELECT3 and uses CLOCK3 as the target frequency clock, thereby enabling the multiplexer to automatically output the clock source selected by the main control board.

[0038] In this embodiment, after the MUX obtains the target frequency clock, it sends the target frequency clock to the clock driver and uses the clock driver to send the target frequency clock to the interface chip.

[0039] In other embodiments, the GPIO chip and multiplexer section can be replaced by a programmable logic device (CPLD).

[0040] In this embodiment, the low-speed bus connected to the GPIO chip from the main control board may include: IIC, SPI, UART, etc.

[0041] As can be seen from the above embodiments, by connecting multiple frequency clock crystals and GPIO chips through a multiplexer, the corresponding frequency clock can be obtained based on the high potential signal of the selection pin, thereby realizing the method of automatic frequency clock selection. This replaces the PLL and achieves the technical effect of low cost and easy configuration.

[0042] Based on the above method embodiments, this disclosure also provides a routing device, the routing device including: a service board, the service board including: a splitter, a data selector, a clock driver and an interface chip; One end of the splitter is connected to the main control board via a low-speed bus, and the other end is connected to a data selector via a multiplexer to send multiple signals to the data selector. The data selector is also connected to multiple frequency clocks to acquire different frequency clocks; The data selector is configured with a correspondence between different signals and clocks at different frequencies; The data selector identifies a target signal that is at a high level among multiple signals and obtains the target frequency clock corresponding to the target signal according to the correspondence. The data selector outputs the target frequency clock to the interface chip via the clock driver.

[0043] The splitter includes a GPIO chip; the GPIO chip is connected to the main control board via a low-speed bus to convert the low-speed signals from the main control board into multiple signals.

[0044] The data selector is also connected to multiple frequency clocks, including: The input ports of the data selector are connected to multiple frequency clock crystals.

[0045] The splitter and / or data selector is a CPLD chip.

[0046] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0047] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0048] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0049] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0050] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A method of selecting a clock, characterized by, The method is applied to a service board, which includes: a splitter, a data selector, and a clock driver; The splitter is connected to a data selector via multiple signals. The data selector is also connected to multiple frequency clocks. The data selector is configured with a correspondence between different signals and different frequency clocks. Identify the target signal that is at a high level among the multiple signals of the data selector, and obtain the target frequency clock corresponding to the target signal according to the correspondence. The target frequency clock is output to the interface chip via a clock driver.

2. The method of claim 1, wherein, The splitter includes: a GPIO chip; The GPIO chip is connected to the main control board via a low-speed bus, converting the low-speed signals from the main control board into multiple signals.

3. The method of claim 1, wherein, The data selector includes a MUX circuit.

4. The method of claim 1, wherein, The splitter is connected to the data selector via multiplexing signals, and includes: The multiplexing device's multiplexing signal is connected to the channel selection pin of the data selector.

5. The method of claim 1, wherein, The data selector is also connected to multiple frequency clocks, including: The input ports of the data selector are connected to multiple frequency clock crystals.

6. The method according to claim 1, characterized in that, The branching device and / or data selector is a CPLD chip.

7. A routing device, characterized in that, The routing device includes: a service board, which includes: a splitter, a data selector, a clock driver, and an interface chip; One end of the splitter is connected to the main control board via a low-speed bus, and the other end is connected to a data selector via a multiplexer to send multiple signals to the data selector. The data selector is also connected to multiple frequency clocks to acquire different frequency clocks; The data selector is configured with a correspondence between different signals and clocks at different frequencies; The data selector identifies a target signal that is at a high level among multiple signals and obtains the target frequency clock corresponding to the target signal according to the correspondence. The data selector outputs the target frequency clock to the interface chip via the clock driver.

8. The routing device according to claim 7, characterized in that, The splitter includes: a GPIO chip; The GPIO chip is connected to the main control board via a low-speed bus, converting the low-speed signals from the main control board into multiple signals.

9. The routing device according to claim 7, characterized in that, The data selector is also connected to multiple frequency clocks, including: The input ports of the data selector are connected to multiple frequency clock crystals.

10. The routing device according to claim 7, characterized in that, The branching device and / or data selector is a CPLD chip.

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