Low-dropout linear voltage stabilizing circuit

Abstract

The invention discloses a low-dropout linear voltage stabilizing circuit. The low-dropout linear voltage stabilizing circuit comprises a power tube, a control module and a transient response module, the first end of the power tube is connected with power voltage, and the second end of the power tube is used for generating output voltage. The control module is used for controlling the output voltage to carry out voltage following on the input voltage and driving the power tube. The transient response module is used for generating a transient response signal based on the transient change of the output voltage. The control module also adjusts the driving capability of the power tube and / or adjusts the output voltage based on the transient response signal. According to the low-dropout linear voltage stabilizing circuit, the transient response speed is further improved through the extremely simple circuit extension design, meanwhile, the loop analysis difficulty is simplified, and the hardware cost is reduced. And the control module adopts a folded voltage follower architecture, naturally has a speed advantage, and is matched with the transient response module to further accelerate the driving of the power tube so as to realize quick response to the output voltage.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a low dropout linear voltage regulator circuit. Background Technology

[0002] Low dropout linear regulators (LDLs) are a type of core power management circuit. Their core function is to provide a stable supply voltage to the downstream load through a negative feedback regulation mechanism when the input voltage and load current change. With their outstanding advantages such as simple structure, small size, high integration, low output voltage noise, and high power supply rejection ratio, LDLs are widely used in many fields, including consumer electronics, communication equipment, industrial control systems, medical instruments, and automotive electronics.

[0003] As the complexity of various electronic systems continues to increase, more stringent requirements are being placed on the transient response performance of low-dropout linear regulators (LDLs). For example, signal chain circuits such as sensors, analog-to-digital converters (ADCs), and RF front-ends rely on fast-response LDLs to suppress power fluctuations caused by load current fluctuations, ensuring the reliability of signal measurement, transmission, and reception. High-performance digital circuits (such as central processing units and graphics processing units) can experience ampere-level current changes within nanoseconds; using fast-response LDLs as a power supply solution can effectively avoid digital logic errors and system crashes. The power supply stability of core circuits in medical electronic systems directly determines the accuracy of bioelectrical signal measurements. Industrial control equipment also requires a power supply that can quickly recover stability under significant load fluctuations to prevent equipment malfunctions or production accidents. In summary, in various modern electronic systems, the fast response capability of the power supply is a key factor determining the overall reliability of the system and has become a core indicator to consider when selecting LDLs.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a low-dropout linear voltage regulator circuit that can achieve high-speed transient response.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] A low-dropout linear regulator circuit includes:

[0008] A power transistor, wherein the first terminal of the power transistor is connected to the power supply voltage, and the second terminal of the power transistor is used to generate an output voltage;

[0009] The control module is connected to the input voltage, the second terminal of the power transistor, and the control terminal of the power transistor. It is used to control the output voltage to follow the input voltage and drive the power transistor.

[0010] A transient response module, connected to the second terminal of the power transistor, is used to generate a transient response signal based on the transient change of the output voltage;

[0011] The control module is also connected to the transient response module to adjust the driving capability of the power transistor and / or adjust the output voltage based on the transient response signal.

[0012] In one or more embodiments of the present invention, the control module includes a first transistor, a second transistor, a current control unit, and a driving unit. A first terminal of the first transistor is connected to an input voltage. A control terminal of the first transistor and a second terminal of the first transistor are connected to a control terminal of the second transistor. A first terminal of the second transistor is connected to a second terminal of a power transistor. The current control unit is connected to the second terminals of the first and second transistors to control the current on the first and second transistors. The driving unit is connected to the control terminal of the power transistor to drive the power transistor.

[0013] The current control unit is connected to the transient response module and adjusts the current on the second transistor to regulate the output voltage based on the transient response signal, and / or the drive unit is connected to the transient response module to adjust the drive capability of the power transistor based on the transient response signal.

[0014] In one or more embodiments of the present invention, the current control unit includes a first current subunit and a second current subunit, wherein the first current subunit is connected to a second terminal of a first transistor to control the current on the first transistor, and the second current subunit is connected to a second terminal of a second transistor to control the current on the second transistor.

[0015] In one or more embodiments of the present invention, the second current unit includes a third transistor, a first terminal of the third transistor being connected to ground voltage, a second terminal of the third transistor being connected to the second terminal of the second transistor, and a control terminal of the third transistor being connected to a first bias voltage.

[0016] In one or more embodiments of the present invention, the second current unit further includes a first resistor, the control terminal of the third transistor is connected to a first bias voltage through the first resistor, and the control terminal of the third transistor is connected to a transient response module to receive a transient response signal.

[0017] In one or more embodiments of the present invention, the driving unit includes a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the fourth transistor is connected to a power supply voltage, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, the second terminals of the fifth transistor and the sixth transistor are connected to the control terminal of a power transistor, the first terminal of the sixth transistor is connected to the second terminal of the second transistor, the control terminal of the sixth transistor is connected to a second bias voltage, the control terminal of the fifth transistor is connected to a third bias voltage, and the control terminal of the fourth transistor is connected to a fourth bias voltage.

[0018] In one or more embodiments of the present invention, the first terminal of the fifth transistor is also connected to a transient response module to receive a transient response signal; and / or

[0019] The first terminal of the sixth transistor is also connected to the transient response module to receive transient response signals; and / or

[0020] The driving unit further includes a second resistor. The control terminal of the sixth transistor is connected to a second bias voltage through the second resistor. The control terminal of the sixth transistor is connected to a transient response module to receive a transient response signal.

[0021] In one or more embodiments of the present invention, the transient response module includes a first capacitor, a first terminal of which is connected to a second terminal of a power transistor, and the second terminal of the first capacitor is used to generate a transient response signal; and / or

[0022] The transient response module includes a second capacitor, a third capacitor, a third resistor, and a reference current unit. The reference current unit is connected to the second terminal of the power transistor through the second capacitor. The reference current unit is used to generate a reference current and adjust the reference current based on the transient change of the output voltage. The first terminal of the third resistor is connected to ground voltage, and the second terminal of the third resistor is connected to the reference current unit to generate a conversion signal based on the reference current. The first terminal of the third capacitor is connected to the second terminal of the third resistor, and the second terminal of the third capacitor is used to generate a transient response signal.

[0023] In one or more embodiments of the present invention, the reference current unit includes a seventh transistor, an eighth transistor, a ninth transistor, and a fourth resistor. The first terminal of the seventh transistor is connected to ground voltage. The second terminal of the seventh transistor is connected to the second terminal of the eighth transistor, the control terminal of the eighth transistor, and the first terminal of the fourth resistor. The first terminals of the eighth transistor and the ninth transistor are connected to the input voltage. The control terminal of the ninth transistor is connected to the second terminal of the fourth resistor and a second capacitor. The second terminal of the ninth transistor is connected to the second terminal of the third resistor.

[0024] In one or more embodiments of the present invention, the low-dropout linear regulator circuit further includes a buffer module connected to the input voltage and the voltage follower module to buffer the input voltage.

[0025] Compared with existing technologies, the low-dropout linear regulator circuit of this invention achieves a further improvement in transient response speed through a simplified circuit extension design, while simplifying loop analysis and reducing hardware costs. The control module adopts a folded voltage follower architecture, which inherently possesses a speed advantage. Combined with the transient response module, it further accelerates the driving of the power transistor, achieving a rapid response to the output voltage. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a circuit diagram of a low-dropout linear voltage regulator circuit in one embodiment of the present invention.

[0028] Figure 2 This is a circuit diagram of a buffer module in one embodiment of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0030] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0031] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0032] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0033] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0034] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.

[0035] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0036] Currently, the mainstream fast-response low-dropout regulator technologies mainly include loop control technology, nonlinear loop control technology, and digital control technology.

[0037] Loop control technology achieves superior transient response performance through complex loop control design, and its core can be divided into the following two categories: 1. Composite loop technology: This uses a series architecture to control the P-type power MOSFET. A low-noise, high-precision operational amplifier is used as the first stage to improve the output voltage accuracy of the low-dropout linear regulator; a high-drive-capability operational amplifier is used as the second stage to achieve rapid driving of the P-type power MOSFET, thereby improving the transient response speed of the low-dropout linear regulator. 2. Multi-loop feedback technology: This uses a parallel "fast loop + slow loop" architecture design to achieve a synergistic effect of "high-speed transient response + precise steady-state voltage regulation". The fast loop circuit has a built-in transient detection device that can capture sudden changes in output voltage in real time and quickly drive the P-type power MOSFET to compensate for output voltage changes in a timely manner; the slow loop uses a traditional voltage feedback structure to ensure high-precision stability of the output voltage.

[0038] The drawbacks of this technology are that, although the series high-precision and high-drive-capacity architecture and the parallel fast-slow loop architecture can achieve complementary advantages of different control circuits, significant defects still exist: In the series architecture, the series design of two-stage control units produces a higher overall delay than the single-stage architecture, resulting in limited bandwidth improvement potential; in the fast-slow loop parallel architecture, the control of the P-type field-effect transistors by the two controllers is prone to conflict due to differences in circuit delays, significantly increasing the complexity of loop analysis. This may not only cause the response speed of the low-dropout linear regulator to be lower than expected, but also easily lead to output voltage instability. In addition, both schemes require the design of two independent circuits, directly resulting in increased static power consumption and increased silicon wafer area.

[0039] Nonlinear loop control technology, in the control loop of a low-dropout regulator, improves the circuit's response speed when output voltage errors occur by designing the controller parameters nonlinearly, resulting in a faster response than in steady-state operation. The core technologies fall into two categories: 1. Slew Rate Enhancement Technology: A fluctuation detection and slew rate enhancement circuit is added to the error amplifier of the low-dropout linear regulator. When a large error in the output voltage due to fluctuation is detected, the quiescent current of the error amplifier is automatically increased to accelerate its drive slew rate to the P-type power MOSFET. After the output voltage fluctuation ends, the initial bias current is restored, achieving a saving in static power consumption. 2. Zero-Pole Following Technology: A linear region MOSFET with its gate connected to the P-type power MOSFET is used to implement the left half-plane zero-point resistance, allowing the left half-plane zero to follow changes in load current. This ensures that the low-dropout linear regulator possesses both fast response characteristics and good loop stability over a wide load range.

[0040] The drawback of this technology is that while slew rate enhancement and zero-pole follower techniques can improve the operating condition adaptability and response speed of low-dropout linear regulators to a certain extent, their defects are also prominent: the optimal fluctuation detection threshold of slew rate enhancement technology is easily affected by process-temperature-voltage (PVT). If the threshold is too wide, the transient enhancement effect will be insufficient, and if the threshold is too narrow, unnecessary transient enhancement will be triggered, which will instead cause voltage fluctuations; the linear field-effect transistor that implements zero-pole follower technology has a conduction impedance that varies with the load current, but the correlation between the absolute value deviation of the impedance and the PVT is at least one order of magnitude higher than that of ordinary polysilicon resistors, resulting in lower zero-point position accuracy in the left half-plane; at the same time, the zero-point adjustment effect may lag behind the load change, so that the technology has limited effect on improving the response speed in scenarios with rapid load changes.

[0041] The digital control technology employs an "analog-to-digital converter + digital control technology + segmented P-type power MOSFET drive" scheme to replace the traditional low-dropout linear regulator loop control architecture based on error amplifiers. Leveraging the advantages of digital signal processing—which is far faster than analog signal processing and has no slew rate limitation—it improves transient response speed. Its core logic is as follows: the analog-to-digital converter compares the current linear regulator's output voltage with a reference voltage; the digital controller quickly calculates the optimal control value using algorithms such as binary search, thereby controlling the number of P-type power MOSFETs in the array to achieve rapid and precise control of the output voltage. Utilizing advanced processes such as 7nm and 5nm further enhances the fast response performance of the digitally controlled low-dropout linear regulator.

[0042] The drawback of this technology is that, although the slew rate of the P-type field-effect transistor gate of the digitally controlled low-dropout linear regulator is much better than that of analog control, there are still key defects: the digital control adopts a discrete-time feedback mechanism, which can only adjust the P-type field-effect transistor array once per clock cycle, resulting in millivolt-level ripple in the output voltage, which is much higher than the microvolt-level ripple of analog control. This cannot meet the low-noise operating requirements of signal chain circuits such as sensors, analog-to-digital converters, and RF front-ends. In addition, the control speed of the digital controller on the output voltage is limited by the sampling rate of the analog-to-digital converter. A higher sampling rate requires greater static power consumption, making it difficult to balance the requirements of high-speed response and low power consumption.

[0043] like Figure 1 As shown, the low dropout linear regulator circuit in one embodiment of the present invention includes: a power transistor PM10, a buffer module 10, a control module, and a transient response module 20.

[0044] In this circuit, the first terminal of power transistor PM10 is connected to the power supply voltage, and the second terminal of power transistor PM10 is used to generate the output voltage Vout. Buffer module 10 is connected to the input voltage Vref to buffer the input voltage Vref. Control module is connected to buffer module 10, the second terminal of power transistor PM10, and the control terminal of power transistor PM10, and is used to control the output voltage Vout to voltage-follow the buffered input voltage Vref and drive power transistor PM10. Transient response module 20 is connected to the second terminal of power transistor PM10 and is used to generate a transient response signal based on the transient changes in output voltage Vout.

[0045] The control module is also connected to the transient response module 20 to adjust the drive capability of the power transistor PM10 and regulate the output voltage Vout based on the transient response signal.

[0046] like Figure 2 As shown, in one embodiment, the buffer module 10 includes a twelfth transistor PM11, a thirteenth transistor PM12, a fourteenth transistor NM10, a fifteenth transistor NM11, a sixteenth transistor NM12, a seventeenth transistor NM14, an eighteenth transistor NM13, a nineteenth transistor PM13, and a current source IB2.

[0047] The first terminal of the twelfth transistor PM11 and the first terminal of the thirteenth transistor PM12 are connected to the power supply voltage. The control terminals of the twelfth transistor PM11, PM11, and PM12 are connected to the second terminal of the fourteenth transistor NM10. The second terminal of the thirteenth transistor PM12 is connected to the second terminal of the fifteenth transistor NM11. The control terminal of the fourteenth transistor NM10 serves as the first input terminal of the buffer module 10, and the control terminal of the fifteenth transistor NM11 serves as the second input terminal of the buffer module 10, used to receive the input voltage Vref. The first terminals of the fourteenth transistor NM10 and NM11 are connected to the second terminal of the sixteenth transistor NM12. The first terminal of the sixteenth transistor NM12 is connected to the ground voltage. The twelfth transistor PM11, thirteenth transistor PM12, fourteenth transistor NM10, fifteenth transistor NM11, and sixteenth transistor NM12 form a classic five-transistor amplifier circuit, constituting the amplification stage of the buffer module 10.

[0048] The first terminal of current source IB2 is connected to the power supply voltage. The second terminal of current source IB2 is connected to the second terminal of the seventeenth transistor NM14, the control terminal of the seventeenth transistor NM14, the control terminal of the sixteenth transistor NM12, and the control terminal of the eighteenth transistor NM13, to provide the corresponding bias voltages to the sixteenth transistor NM12 and the eighteenth transistor NM13. The first terminals of the seventeenth transistor NM14 and the eighteenth transistor NM13 are connected to ground.

[0049] The first terminal of the nineteenth transistor PM13 is connected to the power supply voltage. The control terminal of the nineteenth transistor PM13 is connected to the second terminal of the thirteenth transistor PM12. The second terminal of the nineteenth transistor PM13 is connected to the second terminal of the eighteenth transistor NM13 to form the output terminal of the buffer module 10. The nineteenth transistor PM13 and the eighteenth transistor NM13 constitute the output stage of the buffer module 10. The output terminal of the buffer module 10 is also connected to the first input terminal of the buffer module 10. For example, the first input terminal of the buffer module 10 is an inverting input terminal, and the second input terminal of the buffer module 10 is a non-inverting input terminal.

[0050] Furthermore, the buffer module 10 may also include a fourth capacitor C6. The first terminal of the fourth capacitor C6 is connected to the second terminal of the thirteenth transistor PM12, and the second terminal of the fourth capacitor C6 is connected to the second terminal of the nineteenth transistor PM13. The fourth capacitor C6 serves as a Miller compensation capacitor to achieve stability compensation for the unity negative feedback loop of the buffer module 10.

[0051] In one embodiment, current source IB2 provides a bias current of 0.1 μA, the amplification stage consumes a total quiescent current of 1.6 μA, the output stage consumes a quiescent current of 0.4 μA, and the nineteenth transistor PM13 is a P-type field-effect transistor forming a common source stage to ensure that the buffer has sufficient output current driving capability.

[0052] It is understandable that in other embodiments, the buffer module 10 may not be provided, and the control module and other circuit structures can be directly connected to the input voltage Vref.

[0053] like Figure 1 As shown, in one embodiment, the control module includes a voltage follower unit and a drive unit. The voltage follower unit is connected to the output terminal of the buffer module 10 and the second terminal of the power transistor PM10, and is used to control the output voltage Vout to follow the buffered input voltage Vref. The drive unit is connected to the control terminal of the power transistor PM10 to drive the power transistor PM10. The voltage follower unit is connected to the transient response module 20 to adjust the output voltage Vout based on the transient response signal, and the drive unit is connected to the transient response module 20 to adjust the driving capability of the power transistor PM10 based on the transient response signal.

[0054] Specifically, the voltage follower unit includes a first transistor PM1, a second transistor PM2, and a current control unit. The first terminal of the first transistor PM1 is connected to the output terminal of the buffer module 10, the control terminal of the first transistor PM1 and the second terminal of the first transistor PM1 are connected to the control terminal of the second transistor PM2, and the first terminal of the second transistor PM2 is connected to the second terminal of the power transistor PM10.

[0055] The current control unit is connected to the second terminal of the first transistor PM1 and the second terminal of the second transistor PM2 to control the current on the first transistor PM1 and the second transistor PM2. The current control unit is connected to the transient response module 20 and adjusts the current on the second transistor PM2 based on the transient response signal to adjust the output voltage Vout.

[0056] Furthermore, the current control unit includes a first current subunit and a second current subunit. The first current subunit is connected to the second terminal of the first transistor PM1 to control the current on the first transistor PM1, and the second current subunit is connected to the second terminal of the second transistor PM2 to control the current on the second transistor PM2. The second current subunit is also connected to the transient response module 20 and adjusts the current on the second transistor PM2 based on the transient response signal to adjust the output voltage Vout.

[0057] Furthermore, the first current sub-unit includes a tenth transistor NM1 and an eleventh transistor NM3. The first terminal of the tenth transistor NM1 is connected to ground voltage, the second terminal of the tenth transistor NM1 is connected to the first terminal of the eleventh transistor NM3, the second terminal of the eleventh transistor NM3 is connected to the second terminal of the first transistor PM1, the control terminal of the tenth transistor NM1 is connected to a first bias voltage, and the control terminal of the eleventh transistor NM3 is connected to a second bias voltage.

[0058] The second current unit includes a third transistor NM2 and a first resistor R1. The first terminal of the third transistor NM2 is connected to ground voltage, the second terminal of the third transistor NM2 is connected to the second terminal of the second transistor PM2, the control terminal of the third transistor NM2 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to a first bias voltage, and the control terminal of the third transistor NM2 is also connected to the transient response module 20 to receive transient response signals.

[0059] like Figure 1As shown, in one embodiment, the driving unit includes a fourth transistor PM6, a fifth transistor PM8, a sixth transistor NM4, and a second resistor R2. The first terminal of the fourth transistor PM6 is connected to the power supply voltage. The second terminal of the fourth transistor PM6 is connected to the first terminal of the fifth transistor PM8. The second terminals of the fifth transistor PM8 and the sixth transistor NM4 are connected to the control terminal of the power transistor PM10. The first terminal of the sixth transistor NM4 is connected to the second terminal of the second transistor PM2. The control terminal of the sixth transistor NM4 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to a second bias voltage. The control terminal of the sixth transistor NM4 is also connected to a transient response module 20 to receive transient response signals. The control terminal of the fifth transistor PM8 is connected to a third bias voltage, and the control terminal of the fourth transistor PM6 is connected to a fourth bias voltage. The first terminal of the fifth transistor PM8 and the first terminal of the sixth transistor NM4 are also connected to the transient response module 20 to receive transient response signals.

[0060] like Figure 1 As shown, in one embodiment, the transient response module 20 includes a first capacitor, the first end of which is connected to the second end of the power transistor PM10, and the second end of the first capacitor is used to generate a transient response signal.

[0061] Furthermore, two first capacitors are provided, namely first capacitor C1 and first capacitor C2. The second terminal of first capacitor C1 generates a transient response signal Va1, and the second terminal of first capacitor C2 generates a transient response signal Va2. The first terminal of the sixth transistor NM4 is connected to the second terminal of first capacitor C1 to receive the transient response signal Va1, and the first terminal of the fifth transistor PM8 is connected to the second terminal of first capacitor C2 to receive the transient response signal Va2.

[0062] like Figure 1 As shown, in one embodiment, the transient response module 20 further includes a second capacitor C5, a third capacitor, a third resistor R3, and a reference current unit. The second capacitor C5, the third capacitor, the third resistor R3, and the reference current unit together form a slew rate enhancement unit. The first terminal of the second capacitor C5 is connected to the second terminal of the power transistor PM10, and the reference current unit is connected to the second terminal of the second capacitor C5. The reference current unit is used to generate a reference current and adjust the reference current based on the transient change of the output voltage Vout. The first terminal of the third resistor R3 is connected to ground, and the second terminal of the third resistor R3 is connected to the reference current unit to generate a conversion signal based on the reference current. The first terminal of the third capacitor is connected to the second terminal of the third resistor R3, and the second terminal of the third capacitor is used to generate a transient response signal.

[0063] The reference current unit includes a seventh transistor NM5, an eighth transistor PM3, a ninth transistor PM4, and a fourth resistor R4. The first terminal of the seventh transistor NM5 is connected to ground voltage. The second terminal of the seventh transistor NM5 is connected to the second terminal of the eighth transistor PM3, the control terminal of the eighth transistor PM3, and the first terminal of the fourth resistor R4. The first terminals of the eighth transistor PM3 and the ninth transistor PM4 are connected to the output terminal of the buffer module 10. The control terminal of the ninth transistor PM4 is connected to the second terminal of the fourth resistor R4 and the second terminal of the second capacitor C5. The second terminal of the ninth transistor PM4 is connected to the second terminal of the third resistor R3.

[0064] Furthermore, two third capacitors are provided, namely third capacitor C3 and third capacitor C4. The second terminal of third capacitor C3 generates a transient response signal Va3, and the second terminal of third capacitor C4 generates a transient response signal Va4. The control terminal of the third transistor NM2 is connected to the second terminal of the third capacitor C3 to receive the transient response signal Va3, and the control terminal of the sixth transistor NM4 is connected to the second terminal of the third capacitor C4 to receive the transient response signal Va4.

[0065] like Figure 1 As shown, in one embodiment, the low-dropout linear regulator circuit further includes a bias module 30 for providing each bias voltage.

[0066] Specifically, the bias module 30 includes the twentieth transistor NM9, the twenty-first transistor NM8, the twenty-second transistor NM7, the twenty-third transistor NM6, the twenty-fourth transistor PM9, the twenty-fifth transistor PM7, the twenty-sixth transistor PM5, the current source IB1, and the fifth resistor R5.

[0067] The first terminal of current source IB1 is connected to the power supply voltage. The second terminal of current source IB1 is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is connected to the second terminal of the twentieth transistor NM9. The first terminal of the twentieth transistor NM9 is connected to the second terminal of the twenty-first transistor NM8. The first terminals of the twenty-first transistor NM8, the twenty-second transistor NM7, and the twenty-third transistor NM6 are connected to ground. The control terminals of the twenty-first transistor NM8, the twenty-second transistor NM7, and the twenty-third transistor NM6 are connected to the second terminal of the fifth resistor R5 to generate a first bias voltage. The control terminal of the twentieth transistor NM9 is connected to the first terminal of the fifth resistor R5 to generate a second bias voltage.

[0068] The second terminal of transistor NM7 (22nd) is connected to the second terminal of transistor PM9 (24th). The first terminal of transistor PM9 (24th) is connected to the power supply voltage. The second terminal of transistor NM6 (23rd) is connected to the second terminal of transistor PM7 (25th). The first terminal of transistor PM7 (25th) is connected to the second terminal of transistor PM5 (26th). The first terminal of transistor PM5 (26th) is connected to the power supply voltage. The control terminals of transistors PM9 (24th) and PM7 (25th) are connected to the second terminal of transistor PM9 (24th) to generate a third bias voltage. The control terminal of transistor PM5 (26th) is connected to the second terminal of transistor PM7 (25th) to generate a fourth bias voltage.

[0069] Each bias node in the control module and transient response module 20 is connected to the corresponding bias voltage mentioned above.

[0070] In one embodiment, the first transistor PM1, the second transistor PM2, the fourth transistor PM6, the fifth transistor PM8, the eighth transistor PM3, the ninth transistor PM4, the twelfth transistor PM11, the thirteenth transistor PM12, the nineteenth transistor PM13, the twenty-fourth transistor PM9 to the twenty-sixth transistor PM5 are P-channel MOS transistors.

[0071] The third transistor NM2, the sixth transistor NM4, the seventh transistor NM5, the tenth transistor NM1, the eleventh transistor NM3, the fourteenth transistor NM10 to the eighteenth transistor NM13, and the twentieth transistor NM9 to the twenty-third transistor NM6 are N-channel MOSFETs.

[0072] The first terminal of each of the above transistors is the source, the second terminal is the drain, and the control terminal is the gate.

[0073] For example, the substrates of the first transistor PM1, the second transistor PM2, the eighth transistor PM3, and the ninth transistor PM4 are all connected to the output terminal of the buffer module 10, while the substrates of the remaining P-channel MOS transistors are connected to the power supply voltage. If the substrates of the first transistor PM1, the second transistor PM2, the eighth transistor PM3, and the ninth transistor PM4 are connected to the power supply voltage, the body effect of these transistors will be severe, resulting in a very high threshold voltage, making it difficult to meet the application requirements of low output voltage. Connecting the substrates of these transistors to the input voltage Vref can avoid this problem.

[0074] For example, the substrate of all N-channel MOSFETs is connected to ground.

[0075] In other embodiments, the first transistor PM1, the second transistor PM2, the fourth transistor PM6, the fifth transistor PM8, the eighth transistor PM3, the ninth transistor PM4, the twelfth transistor PM11, the thirteenth transistor PM12, the nineteenth transistor PM13, and the twenty-fourth transistors PM9 through PM5 can also be N-channel MOSFETs or other devices. The third transistor NM2, the sixth transistor NM4, the seventh transistor NM5, the tenth transistor NM1, the eleventh transistor NM3, the fourteenth transistors NM10 through NM13, and the twentieth transistors NM9 through NM6 can also be P-channel MOSFETs or other devices. The connection method of the above transistors can then be adjusted accordingly.

[0076] In actual operation, the input voltage Vref is first buffered by the buffer module 10 to ensure that the subsequent circuit obtains a stable input voltage Vref.

[0077] Next, the input voltage Vref is folded and output through the control module of the folded voltage follower structure to achieve the design goal of output voltage Vout equal to input voltage Vref. Specifically, the current on the first transistor PM1 is obtained by replicating the bias current IB1 through a current mirror composed of the tenth transistor NM1, the eleventh transistor NM3, and the bias module 30; the current on the second transistor PM2 is the difference between the current on the third transistor NM2 and the current in the branch from the fourth transistor PM6 to the sixth transistor NM4, and both the current on the third transistor NM2 and the current in the branch from the fourth transistor PM6 to the sixth transistor NM4 are replicated from the bias current IB1. The aforementioned current can be adjusted by changing the width-to-length ratio of the corresponding transistors. For example, the current on the first transistor PM1 is twice the bias current IB1, the current on the third transistor NM2 is 32 times the bias current IB1, and the current on the branch from the fourth transistor PM6 to the sixth transistor NM4 is 30 times the bias current IB1. At this time, the current on the first transistor PM1 is equal to the current on the second transistor PM2. As long as the width-to-length ratio of the first transistor PM1 and the second transistor PM2 is consistent, the source voltage of the second transistor PM2 will also be consistent with the source voltage of the first transistor PM1, thus ensuring that the output voltage Vout matches and follows the input voltage Vref.

[0078] In the circuit described above, the branch from the fourth transistor PM6 to the sixth transistor NM4 determines the driving speed of the power transistor PM10. Therefore, a larger current is allocated to this branch. At the same time, appropriate currents are allocated to the branches from the first transistor PM1 to the tenth transistor NM1, the second transistor PM2 to the third transistor NM2, and the twenty-sixth transistor PM5 to the twenty-third transistor NM6 to avoid the current mirror replication ratio increasing due to the current being too small in the above branches, which would exacerbate the replication error.

[0079] Furthermore, in the bias module 30, the 20th transistor NM9, the 21st transistor NM8, and the fifth resistor R5 form a common-gate-common-source current mirror to improve the replication accuracy of the bias current IB1.

[0080] Next, in the transient response module 20, by setting the first capacitor C1 and the first capacitor C2, the pull-down channel and pull-up channel of the driving transistor are controlled respectively, thereby improving the transient response capability of the power transistor PM10. Taking the transient downward fluctuation of the output voltage Vout due to a sudden increase in the output load current as an example: when the load current changes abruptly, the downward change of the output voltage Vout is coupled to the source of the sixth transistor NM4 through the first capacitor C1. The common-gate structure of the sixth transistor NM4 amplifies the fluctuation signal, driving the gate of the power transistor PM10 to pull down quickly. At the same time, the fluctuation of the output voltage Vout is also coupled to the source of the fifth transistor PM8 through the first capacitor C2, causing the fifth transistor PM8 to be temporarily turned off to weaken the pull-up driving capability and ensure that the pull-down enhancement effect is fully utilized. The first capacitors C1 and C2 together realize the driving capability of the push-pull transient enhancement power transistor PM10, enabling the circuit to drive the power transistor PM10 more quickly to restore the output voltage to stability when the load current suddenly increases. In addition, the first capacitor C1 also serves as the stability compensation function for the folded voltage reversal loop composed of the second transistor PM2, the sixth transistor NM4, and the power transistor PM10. The first capacitor C1, which is connected across the output voltage Vout and the source of the sixth transistor NM4, forms a compensator with a folded common gate-common source structure. Here, the capacitance value of the first capacitor C1 can be appropriately increased. On the one hand, it can make the output voltage disturbance more completely coupled to the drive unit, ensuring the fast response of the output voltage. On the other hand, since the first capacitor C1 also has the function of folded voltage reversal loop compensation, increasing its capacitance value can simultaneously enhance the stability of the loop, achieving synergistic optimization of fast response and stability.

[0081] Finally, the slew rate enhancement unit further enhances the transient response. When the output voltage Vout fluctuates downwards, the second capacitor C5 synchronously couples the gate voltage of the ninth transistor PM4 downwards, causing a temporary increase in the current on the ninth transistor PM4. This current change causes the switching voltage across the third resistor R3 to rise rapidly. This change is then coupled to the gate of the third transistor NM2 by the third capacitor C3, further increasing the pull-down current of the power transistor PM10. Simultaneously, this change is also coupled to the gate of the sixth transistor NM4 by the third capacitor C4, reducing the impedance of the sixth transistor NM4 in the pull-down channel. The combined effect significantly improves the pull-down slew rate of the power transistor PM10. Furthermore, the duration of the slew rate enhancement can be adjusted by regulating the values ​​of the first resistor R1, the second resistor R2, and the fourth resistor R4.

[0082] During steady-state operation, the circuit generates extremely low static current loss, with the eighth transistor PM3 branch and the ninth transistor PM4 branch each consuming only 1μA, thus meeting the requirements of low-power design.

[0083] It is understood that in other embodiments, the first capacitor C1 may not be provided, or the first capacitor C2 may not be provided, or both the first capacitor C1 and the first capacitor C2 may not be provided, in which case the above circuit will not have the corresponding transient response effect.

[0084] In other embodiments, the third capacitor C3 and the first resistor R1 may be omitted, and the control terminal of the third transistor NM2 may be directly connected to the control terminal of the twenty-third transistor NM6 in the bias module 30 to receive the first bias voltage.

[0085] In other embodiments, the third capacitor C4 and the second resistor R2 may be omitted, and the control terminal of the sixth transistor NM4 may be directly connected to the control terminal of the twentieth transistor NM9 in the bias module 30 to receive the second bias voltage.

[0086] Understandably, if the third capacitor C3, the first resistor R1, the third capacitor C4, and the second resistor R2 are not simultaneously provided, then the second capacitor C5, the third resistor R3, and the reference current unit in the transient response module 20 can also be omitted. In this case, the circuit achieves transient enhancement functionality solely through the first capacitor C1 and / or the first capacitor C2.

[0087] In summary, the low-dropout linear regulator circuit of this invention utilizes the inherent speed advantage of the folded voltage follower architecture, allocating limited power consumption budget to the branches of the fourth transistor PM6 to the sixth transistor NM4, which actually determine the circuit response speed. This allows the gate of the driver transistor PM10 to achieve a faster drive speed and respond more promptly to load changes. Simultaneously, the circuit combines a push-pull transient enhancement circuit with a slew rate enhancement unit, significantly improving the drive response speed of the power transistor PM10 and achieving a rapid response of the output voltage Vout.

[0088] The circuit adopts a purely analog design approach, with negligible output ripple, fully meeting the low power noise application requirements of signal chain circuits such as sensors, analog-to-digital converters, and RF front-ends. Compared with the complex architecture of multi-stage / multi-loop control, integrated analog-to-digital converters and digital controllers used in existing technologies, this invention can enhance the response speed by adding only a small number of capacitors and transistors on the basic architecture of a folded voltage follower. This not only effectively reduces the silicon wafer footprint but also allows for precise allocation of the limited power consumption budget to the core branches that determine the response speed, while significantly reducing design complexity and shortening the development cycle.

[0089] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0090] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A low-dropout linear voltage regulator circuit, characterized in that, include: A power transistor, wherein the first terminal of the power transistor is connected to the power supply voltage, and the second terminal of the power transistor is used to generate an output voltage; The control module is connected to the input voltage, the second terminal of the power transistor, and the control terminal of the power transistor. It is used to control the output voltage to follow the input voltage and drive the power transistor. A transient response module, connected to the second terminal of the power transistor, is used to generate a transient response signal based on the transient change of the output voltage; The control module is also connected to the transient response module to adjust the driving capability of the power transistor and / or adjust the output voltage based on the transient response signal.

2. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The control module includes a first transistor, a second transistor, a current control unit, and a drive unit. The first terminal of the first transistor is connected to the input voltage. The control terminal of the first transistor and the second terminal of the first transistor are connected to the control terminal of the second transistor. The first terminal of the second transistor is connected to the second terminal of the power transistor. The current control unit is connected to the second terminal of the first transistor and the second terminal of the second transistor to control the current on the first transistor and the second transistor. The drive unit is connected to the control terminal of the power transistor to drive the power transistor. The current control unit is connected to the transient response module and adjusts the current on the second transistor to regulate the output voltage based on the transient response signal, and / or the drive unit is connected to the transient response module to adjust the drive capability of the power transistor based on the transient response signal.

3. The low-dropout linear voltage regulator circuit according to claim 2, characterized in that, The current control unit includes a first current subunit and a second current subunit. The first current subunit is connected to the second terminal of the first transistor to control the current on the first transistor, and the second current subunit is connected to the second terminal of the second transistor to control the current on the second transistor.

4. The low-dropout linear voltage regulator circuit according to claim 3, characterized in that, The second current unit includes a third transistor, the first terminal of which is connected to ground voltage, the second terminal of which is connected to the second terminal of the second transistor, and the control terminal of which is connected to a first bias voltage.

5. The low-dropout linear voltage regulator circuit according to claim 4, characterized in that, The second current unit also includes a first resistor. The control terminal of the third transistor is connected to a first bias voltage through the first resistor. The control terminal of the third transistor is connected to a transient response module to receive a transient response signal.

6. The low-dropout linear voltage regulator circuit according to claim 2, characterized in that, The driving unit includes a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the fourth transistor is connected to the power supply voltage. The second terminal of the fourth transistor is connected to the first terminal of the fifth transistor. The second terminals of the fifth transistor and the sixth transistor are connected to the control terminal of the power transistor. The first terminal of the sixth transistor is connected to the second terminal of the second transistor. The control terminal of the sixth transistor is connected to a second bias voltage. The control terminal of the fifth transistor is connected to a third bias voltage. The control terminal of the fourth transistor is connected to a fourth bias voltage.

7. The low-dropout linear voltage regulator circuit according to claim 6, characterized in that, The first terminal of the fifth transistor is also connected to the transient response module to receive transient response signals; and / or The first terminal of the sixth transistor is also connected to the transient response module to receive transient response signals; and / or The driving unit further includes a second resistor. The control terminal of the sixth transistor is connected to a second bias voltage through the second resistor. The control terminal of the sixth transistor is connected to a transient response module to receive a transient response signal.

8. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The transient response module includes a first capacitor, a first terminal of which is connected to a second terminal of a power transistor, and the second terminal of the first capacitor is used to generate a transient response signal. and / or The transient response module includes a second capacitor, a third capacitor, a third resistor, and a reference current unit. The reference current unit is connected to the second terminal of the power transistor through the second capacitor. The reference current unit is used to generate a reference current and adjust the reference current based on the transient change of the output voltage. The first terminal of the third resistor is connected to ground voltage, and the second terminal of the third resistor is connected to the reference current unit to generate a conversion signal based on the reference current. The first terminal of the third capacitor is connected to the second terminal of the third resistor, and the second terminal of the third capacitor is used to generate a transient response signal.

9. The low-dropout linear voltage regulator circuit according to claim 8, characterized in that, The reference current unit includes a seventh transistor, an eighth transistor, a ninth transistor, and a fourth resistor. The first terminal of the seventh transistor is connected to ground voltage. The second terminal of the seventh transistor is connected to the second terminal of the eighth transistor, the control terminal of the eighth transistor, and the first terminal of the fourth resistor. The first terminals of the eighth transistor and the ninth transistor are connected to the input voltage. The control terminal of the ninth transistor is connected to the second terminal of the fourth resistor and the second capacitor. The second terminal of the ninth transistor is connected to the second terminal of the third resistor.

10. The low-dropout linear voltage regulator circuit according to claim 1, characterized in that, The low-dropout linear regulator circuit also includes a buffer module, which is connected to the input voltage and the voltage follower module to buffer the input voltage.

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