Image data processing method, electronic device, chip system, storage medium and program product

Abstract

The embodiment of the invention provides an image data processing method, electronic equipment, a chip system, a storage medium and a program product, and relates to the technical field of terminals. The method comprises the steps of dividing a to-be-displayed interface (or a display area of a display screen) into a plurality of areas based on a plurality of layers included in the to-be-displayed interface, wherein the numbers of corresponding layers in adjacent display areas in the plurality of areas are different. For the area covering more layers, the transmission rate required for reading the data corresponding to the area is higher, and the higher data transmission rate can be correspondingly allocated; for the area covering fewer layers, the transmission rate required for reading the data corresponding to the area is smaller, and the smaller data transmission rate can be correspondingly allocated. Therefore, when the electronic equipment allocates data to each region and can meet the requirement of reading data from a memory, the electronic equipment does not need to run at a relatively high data transmission rate all the time when reading the data of each layer in the to-be-displayed interface, so that the power consumption of the electronic equipment can be reduced.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to an image data processing method, electronic device, chip system, storage medium and program product. Background Technology

[0002] To improve the display effect of the user interface (UI) and / or enhance application performance, the user interface displayed by an electronic device can be composed of multiple layers. Each layer can display different content, and overlaying multiple layers can enrich the content of the user interface. Before composing the user interface, the electronic device can first acquire the data used to compose each layer of the user interface.

[0003] However, the electronic device may consume a significant amount of power while reading the data used to synthesize the various layers in the user interface. Summary of the Invention

[0004] The image data processing method, electronic device, chip system, storage medium, and program product provided in this application are applied in the field of terminal technology. When the interface to be displayed on the electronic device includes multiple layers, the electronic device can partition the display screen based on these multiple layers, and can allocate matching bandwidth to each area based on the data transmission rate required by each area. This allows the electronic device to avoid continuously operating at a high transmission rate when reading data from each area, thereby reducing the power consumption of the electronic device.

[0005] In a first aspect, embodiments of this application propose an image data processing method applied to an electronic device including a display screen. The method includes: when the interface to be displayed is a first interface, dividing the display screen into E display areas; in the E display areas, the number of layers used to synthesize the first interface differs in adjacent display areas; allocating bandwidth suitable for the required transmission rate to each of the E display areas; when the interface to be displayed is a second interface, dividing the display screen into E display areas; in the E display areas, the number of layers used to synthesize the second interface differs in adjacent display areas; wherein E and F are different, and E and F are integers greater than or equal to 1; allocating bandwidth suitable for the required transmission rate to each of the F display areas.

[0006] The first or second interface may include multiple layers (or multiple windows), each displaying different content. For example, the first interface could be... Figure 1 The interface (a) can include a status bar layer, a short video application layer, and a video layer. The second interface could be, for example, a... Figure 7The second interface may include a short video application layer and a video layer.

[0007] E display areas or F display areas can be understood as multiple areas in the following text; or, when the layer sizes and display positions on the screen are consistent across multiple layers included in the interface to be displayed, E display areas or F display areas can be a single area, such as the first interface or the second interface. Figure 7 In interface (b), the display area is the entire display area of ​​the screen. This display area can be a rectangular area. Adjacent display areas can be understood as two adjacent areas on the screen, that is, areas that include adjacent pixel rows. For example, areas 1 and 2 in the following text are adjacent display areas. Area 1 includes the 141st pixel row and area 2 includes the 142nd pixel row. The 141st and 142nd pixel rows are adjacent. Similarly, area 2 and area 3 are also adjacent display areas; however, area 1 and area 3 or area 4 are not adjacent display areas.

[0008] For example, the first interface is, for instance, Figure 1 The interface (a) or Figure 7 In the interface (a), the E display areas can be, for example, area 1, area 2, area 3, and area 4 as described below; the second interface is, for example, Figure 7 In the interface (b), the F display areas can be, for example, one of the areas corresponding to the b+x2+1th frame image in the following text, that is, the b+x2+1th frame image is divided into one area.

[0009] Furthermore, the required transmission rate can be understood as the AXI bandwidth of each region (hereinafter referred to as the region's bandwidth) and the data transmission rate required by the electronic device to transmit data in each region. Allocating bandwidth to each of the E display regions to a bandwidth appropriate for its required transmission rate can be, for example, using frequency points set based on the AXI bandwidth of each region (hereinafter referred to as frequency points 4 to 7).

[0010] Each of the F display areas is allocated a bandwidth that matches its required transmission rate. For example, this could be a frequency point set based on the AXI bandwidth of each area, such as frequency point 12.

[0011] The image data processing method of this application allows an electronic device to partition the interface to be displayed (or the display screen) based on multiple layers, thereby allocating bandwidth suitable for the required transmission rate to different display areas. This avoids the need for the electronic device to continuously transmit data at a high bandwidth while acquiring data from the layers of the interface to be displayed, thus helping to reduce the power consumption of the electronic device.

[0012] Furthermore, for a display interface, the electronic device partition is based on the multiple layers included in the display interface. The transmission rates required by adjacent display areas may be different. Therefore, bandwidth adapted to the required transmission rate is allocated to different display areas respectively, so that the bandwidth allocated to each display area meets the data transmission requirements, and there is no need to allocate a large bandwidth to different display areas.

[0013] For different interfaces to be displayed, such as the first interface and the second interface, the electronic device can partition the screen based on the multiple layers actually included in each interface. This allows the electronic device to dynamically partition the screen as the interface to be displayed changes, so that the bandwidth allocated to each interface meets the data transmission requirements of each interface.

[0014] For example, the first interface is as follows: Figure 1 In interface (a), the E display areas are area 1, area 2, area 3, and area 4 as described below; the electronic device allocates bandwidth to each of these four areas according to their respective required transmission rates, and the bandwidth allocated to each area can be different to meet the data transmission requirements of the first interface. In the second interface, as described below... Figure 7 When the interface (b) is in the middle, F display areas are equal to 1 area. The electronic device allocates bandwidth to the second interface that is compatible with the transmission rate required by the entire area of ​​the second interface, so as to meet the data transmission needs of the second interface.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, before allocating bandwidth adapted to their respective required transmission rates to the E display areas, the image data processing method further includes: calculating the required transmission rate for each of the E display areas based on the refresh rate, the layer size of each layer in the first interface, and the pixel bit width of each layer in the first interface.

[0016] Here, refresh rate can be understood as the refresh rate of an electronic device's display screen. Layer size, also known as layer dimensions, can be understood as the size of each layer in the layers used to composite the first interface.

[0017] The required transmission rate for each display area can be understood as the actual data transmission rate required by the electronic device to transmit data from each layer in the display area, which is the AXI bandwidth calculated below based on the layer size and pixel width of each layer in each display area according to the refresh rate. The calculation of the required transmission rate for each of the E display areas can be referenced from the process of calculating AXI bandwidth 4 in S601.

[0018] In this way, the transmission rate required by each display area calculated by the electronic device is closer to the actual needs of each display area.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the E display areas include a first area; the first area includes y layers in the layers that compose the first interface; the required transmission rate of the first area is determined based on the layer size of each of the y layers in the first area, the pixel bit width of each of the y layers, and the refresh rate.

[0020] Here, the first region can be understood as any one of the E display regions. y is a positive integer. The required transmission rate of the first region can be understood as the AXI bandwidth of the first region. For example, the first region can be region 1 as described below, y layers can be understood as m layers as described below, and the required transmission rate of the first region can be understood as AXI bandwidth 4 as described below.

[0021] In this way, electronic devices can calculate the required transmission rate for each area separately.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the E display areas include a first area; the image data processing method further includes: acquiring data of the layer used to synthesize the first interface in the first area based on the bandwidth allocated to the first area.

[0023] The first region can be any one of the E display regions. When the electronic device acquires data of the layer used to synthesize the first interface in the first region, it can transmit data based on the bandwidth allocated to the first region. The first region can be, for example, region 1 in S601 to S604. The bandwidth allocated to the first region can be understood as the AXI bandwidth indicated by frequency point 4, and the electronic device can acquire data in region 1 (the first region) based on the AXI bandwidth indicated by frequency point 4.

[0024] In this way, electronic devices can acquire data from each display area based on the bandwidth allocated to each area. When a display area requires a lower data transfer rate, data can be acquired with a smaller bandwidth; conversely, when a display area requires a higher data transfer rate, data can be acquired with a larger bandwidth. This helps to meet the data transfer needs of each display area while preventing the electronic device from constantly transmitting data at a high bandwidth, thus contributing to lower power consumption.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the electronic device further includes a display processing unit (DPU) and double data rate (DDR) memory; allocating bandwidth adapted to the required transmission rate for each of the E display areas, including: the electronic device instructing the DPU on the required transmission rate for each of the E display areas; the electronic device instructing the DDR memory on the required transmission rate for each of the E display areas via the DPU; and the electronic device allocating bandwidth adapted to the required transmission rate for each of the E display areas via the DDR memory.

[0026] The required transmission rate for each of the E display areas can be understood as the AXI bandwidth of each of the E display areas. The electronic device can write the AXI bandwidth of each of the E display areas into a register, and the DPU can determine the AXI bandwidth of each of the E display areas by reading the register. DDR memory allocates bandwidth to each of the E display areas according to its required transmission rate; that is, the DDR memory sets the frequency point based on the AXI bandwidth of each display area indicated by the DPU.

[0027] For example, the electronic device instructs the DDR memory via the DPU on the required transmission rates for each of the E display areas, as described in S602 below. The electronic device allocates bandwidth to each of the E display areas via the DDR memory to match their respective required transmission rates, as described in the overall S603 below.

[0028] In this way, the bandwidth allocated to DDR memory (i.e., the frequency point mentioned below) is allocated based on the transmission rate required by each display area, so that DDR memory does not need to operate at a high data transmission rate (i.e., a large frequency point) all the time, thereby reducing the power consumption of DDR memory.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, after allocating bandwidth adapted to the required transmission rate for each of the E display areas, the image data processing method further includes: dividing the display screen into E display areas when the interface to be displayed is a third interface and the layer used to synthesize the first interface is the same as the layer used to synthesize the third interface; before the electronic device obtains the data for the layer used to synthesize the first interface from the DDR memory via the DPU, it instructs the DPU on the required transmission rate for each of the E display areas, and instructs the DPU on the required transmission rate for each of the E display areas to the DDR memory; the electronic device allocates bandwidth adapted to the required transmission rate for each of the E display areas via the DDR memory.

[0030] The first interface can be, for example, the b-th frame image; the third interface can be, for example, the b+j-th frame image (described below), meaning the layer used to composite the first interface is the same as the layer used to composite the third interface. In this case, similar to the first interface, the electronic device can also divide the third interface into E display areas. Furthermore, if the electronic device determines that the partitioning method of the third interface is the same as that of the first interface, and the required transmission rate of each display area remains unchanged, the electronic device does not need to instruct the DPU again on the required transmission rate of each of the E display areas. This reduces the number of communications between the processor and the DPU, lowering computational and communication overhead.

[0031] In conjunction with the first aspect, in some implementations of the first aspect, bandwidth adapted to the required transmission rate of each of the F display areas is allocated to each of the F display areas, including: the electronic device instructing the DPU on the required transmission rate of each of the F display areas; the electronic device instructing the DDR memory on the required transmission rate of each of the F display areas through the DPU; and the electronic device allocating bandwidth adapted to the required transmission rate of each of the F display areas through the DDR memory.

[0032] It is understandable that the process by which the electronic device allocates bandwidth to the F display areas in the second interface according to their respective required transmission rates is similar to that in the first interface. For details, please refer to the description above, which will not be repeated here.

[0033] In this way, electronic devices can dynamically partition the display interface in real time according to changes in the display interface, so that the partitioning result of each display interface is adapted to each display interface.

[0034] For example, when an electronic device switches from displaying a first interface to displaying a second interface, the device can partition the changed second interface in real time. This allows the device to allocate bandwidth suitable for the required transmission rate to each of the F display areas (i.e., each area in the changed second interface) via DDR memory. In this way, the bandwidth allocated by DDR memory to each area of ​​the display interface is updated in real time with the partitioning results, which helps to reduce the power consumption of DDR memory.

[0035] In conjunction with the first aspect, in some implementations of the first aspect, the F display areas include the second area; the image data processing method further includes: based on the bandwidth allocated to the second area, reading data of the layer used to synthesize the second interface from DDR memory via DPU in the second area.

[0036] The second region can be any of the F display regions. Alternatively, if the F display regions are considered as one region, the second region is that single region.

[0037] Similar to the first region, for the second region of the second interface, when the electronic device reads data for the layers used to synthesize the second interface from DDR memory via the DPU, it can do so based on the bandwidth allocated to the second region. This allows for reading at a lower data transfer rate when less bandwidth is needed for transmitting data from each layer in the display area, helping to reduce the power consumption of the electronic device. Conversely, when more bandwidth is needed, it allows for reading at a higher data transfer rate, thereby reducing display anomalies such as screen tearing and frame drops that may occur due to insufficient bandwidth.

[0038] In conjunction with the first aspect, in some implementations of the first aspect, each of the E display areas includes one or more complete rows of pixels, and each of the F display areas includes one or more complete rows of pixels.

[0039] It is understandable that when electronic devices read data from DDR memory via the DPU, they can read the data for each pixel row one by one. Therefore, when dividing the display area, each area can also include complete pixel rows.

[0040] Furthermore, when the electronic device reads data from each layer in each region of the first or second interface using the DPU, it can sequentially transmit pixel data of each row in the region based on the bandwidth allocated to each region, thus making the power consumption of the electronic device relatively low.

[0041] Secondly, embodiments of this application provide an image data processing apparatus. The image data processing apparatus can be an electronic device, or a chip or chip system within an electronic device. The image data processing apparatus may include a display screen, a display processing unit (DPU), double data rate (DDR) memory, and a processing unit. The processing unit may be a processor. The apparatus may also include a storage unit, which may be a memory. The storage unit stores instructions, and the processing unit executes the instructions stored in the storage unit to cause the electronic device to implement an image data processing method described in the first aspect or any possible implementation of the first aspect. When the apparatus is a chip or chip system within an electronic device, the processing unit may be a processor. The processing unit executes the instructions stored in the storage unit to cause the electronic device to implement an image data processing method described in the first aspect or any possible implementation of the first aspect. The storage unit may be a storage unit within the chip (e.g., a register, cache, etc.), or a storage unit located outside the chip within the electronic device (e.g., read-only memory, random access memory, etc.).

[0042] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, the memory for storing code instructions, and the processor for running the code instructions to perform the methods described in the first aspect or any possible implementation of the first aspect.

[0043] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program or instructions that, when executed on a computer, cause the computer to perform the methods described in the first aspect or any possible implementation thereof.

[0044] Fifthly, embodiments of this application provide a computer program product including a computer program, which, when run on a computer, causes the computer to perform the methods described in the first aspect or any possible implementation thereof.

[0045] Sixthly, this application provides a chip or chip system including at least one processor and a communication interface. The communication interface and the at least one processor are interconnected via a circuit. The at least one processor is used to run computer programs or instructions to perform the methods described in the first aspect or any possible implementation of the first aspect. The communication interface in the chip can be an input / output interface, pins, or circuits, etc.

[0046] In one possible implementation, the chip or chip system described above in this application further includes at least one memory storing instructions. The memory can be an internal storage unit of the chip, such as a register or cache, or it can be a storage unit of the chip itself (e.g., read-only memory, random access memory, etc.).

[0047] It should be understood that the second to sixth aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the interface for a different application.

[0049] Figure 2 This is a schematic diagram of a process for creating an interface using multiple layers.

[0050] Figure 3 This is a flowchart illustrating a bandwidth determination method.

[0051] Figure 4 A schematic diagram of a partitioned display interface provided in an embodiment of this application;

[0052] Figure 5 A schematic block diagram of the hardware architecture of the electronic device provided in the embodiments of this application;

[0053] Figure 6 A flowchart illustrating an image data processing method provided in an embodiment of this application;

[0054] Figure 7 A schematic diagram of a short video interface switching provided in an embodiment of this application;

[0055] Figure 8 A schematic block diagram of the software architecture of an electronic device provided in the embodiments of this application;

[0056] Figure 9 This is a schematic block diagram of an image data processing apparatus provided in an embodiment of this application. Detailed Implementation

[0057] To facilitate a clear description of the technical solutions in the embodiments of this application, some terms and technologies involved in the embodiments of this application will be briefly introduced below:

[0058] 1. Window

[0059] A window is a rectangular area on the screen of an electronic device that can be drawn on and interacted with. A window is characterized by accepting input, outputting images, and occupying a rectangular area. The rectangular area occupied by the window is its extent. Images drawn by the electronic device can be displayed within the window's extent. In some scenarios, a window may also be referred to as a layer.

[0060] 2. System-on-a-Chip (SOC)

[0061] A System-on-a-Chip (SoC) is a highly integrated microprocessor that integrates multiple functional components onto a single chip and can be used in electronic devices. In electronic devices, an SoC can integrate a processor, GPU, memory, communication modules, etc., to provide computing, graphics processing, and communication functions.

[0062] 3. Double Data Rate (DDR)

[0063] DDR memory is a memory technology used to improve data transfer rates. Compared to traditional single data rate (SDR) memory, DDR memory can transfer data twice per clock cycle: once on the rising edge of the clock signal and once on the falling edge. Thus, DDR memory can achieve twice the data transfer rate at the same clock frequency, thereby improving system performance.

[0064] 4. DDR frequency

[0065] It can refer to the operating frequency (clock frequency) of DDR memory, that is, the number of clock cycles that DDR memory can complete per second. Since DDR memory can transfer data twice within each clock cycle, it can be understood that the DDR frequency indicates the data transfer rate of DDR memory, and the DDR frequency is positively correlated with the data transfer rate of DDR memory, that is, the higher the DDR frequency, the faster the data transfer rate of DDR memory.

[0066] 5. Display Processing Unit (DPU)

[0067] It refers to a hardware component used to process graphics and video data, which can convert raw image data into a form that can be displayed on a monitor.

[0068] 6. Advanced Extensible Interface (AXI)

[0069] AXI is a bus protocol that can be applied in a System-on-a-Chip (SoC). The AXI bus protocol defines independent read and write channels, allowing read and write operations to occur simultaneously without blocking each other. This improves the data transfer efficiency and throughput of the SoC. For ease of description, the bus using the AXI bus protocol will be referred to as the AXI bus in the following text.

[0070] 7. The relationship between DPU, DDR memory and AXI bus

[0071] In a SoC, the DPU and DDR memory can be connected via the AXI bus. That is, the DPU can read data from the DDR memory via the AXI bus, or the DPU can transfer data to the DDR memory via the AXI bus.

[0072] 8. AXI bandwidth

[0073] It can refer to the data transfer rate via the AXI bus protocol. The unit of AXI bandwidth can be bytes transferred per second (e.g., MB / s or GB / s), or the unit of AXI bandwidth can be bits transferred per second (e.g., Mbps or Gbps).

[0074] 9. Refresh Rate

[0075] A refresh rate can refer to the number of frames of images that an electronic device's screen needs to display per second, or the number of times the electronic device needs to draw images per second. The unit can be expressed in Hertz (Hz). For example, a refresh rate of 60Hz means that the electronic device will display 60 frames of the user interface per second, which means that the electronic device needs to draw images 60 times per second.

[0076] 10. Pixel bit width

[0077] It can refer to the number of binary bits of color information for each pixel in an image, or it can be understood as the number of color information that each pixel can store, and can be represented by "bits". The size of the pixel bit width can be, for example, 16 bits or 32 bits.

[0078] 11. Terminology

[0079] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with substantially the same function and purpose. For example, "first chip" and "second chip" are used only to distinguish different chips and do not limit their order of execution. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0080] It should be noted that, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0081] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, and c can be single or multiple.

[0082] 12. Electronic equipment

[0083] The electronic devices in this application embodiment can also be any form of terminal device. For example, electronic devices may include: mobile phones, tablet computers, handheld computers, laptops, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, wearable devices, electronic devices in 5G networks, or future evolved public land mobile communication networks (PLANs). The embodiments of this application do not limit the scope of electronic devices in a mobile network (PLMN).

[0084] By way of example and not limitation, in this embodiment, the electronic device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0085] Furthermore, in this application embodiment, the electronic device can also be an electronic device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection.

[0086] The electronic equipment in the embodiments of this application may also be referred to as: user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device, etc.

[0087] In this embodiment, the electronic device or various network devices include a hardware layer, an operating system layer running on top of the hardware layer, and an application layer running on top of the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also called main memory). The operating system can be any one or more computer operating systems that implement business processing through processes, such as Linux, Unix, Android, iOS, or Windows. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0088] With the development of terminal technology, the user interface (UI) displayed on electronic devices is becoming increasingly sophisticated. To improve the display effect of the user interface, or to improve the running efficiency of applications, the user interface displayed on electronic devices can be composed of multiple layers. These multiple layers can be layers of a single application, or layers of different applications.

[0089] It should be understood that the user interface can also be called the interface or screen, etc. For the sake of brevity, the following description will use the interface as an example.

[0090] Furthermore, each layer in the multiple layers used to composite the interface to be displayed can display different content. For example, the lower layer can display a background image, the middle layer can display the main content of the application, and the upper layer can display notification information. In this way, when displaying the user interface, overlaying multiple layers can achieve richer visual effects and improve the user experience.

[0091] It should be noted that, in the embodiments of this application, "one layer is above another layer" can also be understood as one layer covering or overlapping another layer. For example, the electronic device can set the vertical position of layers using the Z-order parameter. The Z-order parameter can be understood as the coordinate of the layer on the Z-axis, which can refer to the axis perpendicular to the display screen of the electronic device and pointing from the back of the electronic device to the display screen. When one layer is above another, the electronic device can set the Z-order parameter of the one layer to be greater than the Z-order parameter of the other layer, so that the one layer covers the other layer. For simplicity, this will not be elaborated further below.

[0092] The following is combined with Figure 1 This section describes the interfaces of different applications displayed on electronic devices.

[0093] like Figure 1 As shown in interface (a), interface (a) can be understood as the interface of the short video application, and interface (a) can be composed of the following layers: status bar layer 101, short video application layer 102, and video layer 103.

[0094] Among them, the short video application layer 102 can be a layer with a size equal to that of the display screen, and the short video application layer can display controls such as "Home", "Friends", "+", "Messages" and "Me" at the bottom, and can also display controls such as "Experience", "Following" and "Recommended" located below the status bar, as well as a search box and other text information.

[0095] The status bar layer 101 is used to display information such as battery level, time, network status, and Bluetooth, and the status bar layer 101 can be overlaid on the short video application layer 102.

[0096] Video layer 103 can be used to display video, and video layer 103 can be overlaid on short video application layer 102.

[0097] By overlaying the status bar layer 101, the short video application layer 102, and the video layer 103, electronic devices can create composites. Figure 1 The interface (a) in the text.

[0098] It should be noted that in this embodiment, each layer can be drawn in a different window. For example, the status bar layer 101 can be drawn in the system UI window, the short video application layer 102 can be drawn in the short video application UI window, and the video layer 103 can be drawn in the short video application's video window. Therefore, the interface displayed on an electronic device, composed of multiple layers, can also be understood as a multi-window interface, or an interface displayed in a multi-window scenario, etc. For the sake of simplicity, this will not be elaborated further below.

[0099] like Figure 1 As shown in interface (b), interface (b) can be understood as the desktop of an electronic device, and interface (b) can be composed of the following layers: status bar layer 104, capsule layer 105, wallpaper layer 106 and desktop launcher layer 107.

[0100] Wallpaper layer 106 can be a layer with the same size as the display screen, and it can display the wallpaper of the electronic device. Wallpaper layer 106 can be located at the bottom layer.

[0101] The desktop launcher layer 107 can also be a layer with the same size as the screen size. The desktop launcher layer 107 can display application icons, as well as widgets for providing dynamic information and shortcuts (such as the weather widget, express delivery widget, and other dynamic widgets in interface (b)). It can also display a search box and controls for "health code," "ride code," "scan," and "payment code." The desktop launcher layer 107 can overlay the wallpaper layer 106.

[0102] Status bar layer 104 is similar to status bar layer 101, as described above, and will not be repeated here. Optionally, status bar layer 104 can overlap desktop launcher layer 107.

[0103] Capsule layer 105 can be located at the top of the display screen, and capsule layer 105 can be used to display notification messages, and capsule layer 105 can cover status bar layer 104.

[0104] Electronic devices can be composited by overlaying status bar layer 104, capsule layer 105, wallpaper layer 106, and desktop launcher layer 107. Figure 1 The interface (b) in the text.

[0105] From the above, it can be understood that the interface displayed on an electronic device can be created by combining multiple layers. The following example... Figure 1 The process of composing an electronic device interface based on multiple layers is illustrated using interface (a) as an example. Details are as follows.

[0106] For example, Figure 2 A schematic diagram illustrating the process of creating a multi-layer composite interface is shown. For example... Figure 2 As shown, this interface (a) can be understood as a... Figure 1 A diagram of interface (a) in the document. And... Figure 2 The multiple layers corresponding to interface (a) can include: layer 201, layer 202, and layer 203, that is... Figure 2 The interface (a) can be composed of layers 201, 202 and 203.

[0107] Layer 201 can be understood as Figure 1 The diagram illustrates layer 102 in the short video application. Layer 202 can be understood as an illustration of status bar layer 101, and layer 203 can be understood as an illustration of video layer 103. For simplicity, the specific content displayed in the interface and the layers are not shown here.

[0108] In electronic device synthesis Figure 2 When using interface (a), data from layer 201, layer 202, and layer 203 can be acquired sequentially. Then, the electronic device can process these three layers based on their data into a format suitable for display on the electronic device, and can combine the processed three layers into a single display. Figure 2 The interface (a) in the middle, that is Figure 1 The interface (a) in the text.

[0109] It is understandable that the data of a layer can also be understood as the data in the layer's buffer, which may include, but is not limited to, the layer's pixel data, size, and Z-Order parameters, etc. There are no restrictions here.

[0110] Optionally, when an electronic device overlays or combines multiple layers, the multiple layers can be overlaid based on the Z-Order parameters corresponding to the multiple layers. That is, the electronic device can overlay the layers sequentially from bottom to top according to the Z-Order parameters corresponding to the multiple layers, in ascending order of the Z-Order parameters, to obtain the interface to be displayed.

[0111] It should be noted that the above description of the process of superimposing layers 201, 202, and 203 to form user interface a is merely an illustrative description, intended to illustrate that multiple layers in an electronic device can be superimposed to form the final user interface. Furthermore, this embodiment does not limit the order in which layer data of multiple layers are acquired, nor the number, size, or positional relationship of layers in the user interface. In practical applications, the number of layers can be more or less, and the size and position of the layers can be flexibly adjusted according to actual needs.

[0112] Based on the above, it can be understood that when drawing an interface on an electronic device, it is necessary to first obtain data from multiple layers of the interface. The data of each layer can be stored in different buffers. That is, when compositing the interface, the electronic device can first obtain the data in the buffers corresponding to each layer, and then the electronic device can compose the interface to be displayed based on the data stored in the buffers corresponding to each layer.

[0113] by Figure 2 Taking the process of compositing interface a in the embodiment as an example, when compositing interface a on the electronic device, data in buffer 1 corresponding to layer 201, data in buffer 2 corresponding to layer 202, and data in buffer 3 corresponding to layer 203 can be obtained. Then, based on the data in buffer 1, layer 201 can be processed into a format suitable for display on the electronic device; based on the data in buffer 2, layer 202 can be processed into a format suitable for display on the electronic device; and based on the data in buffer 3, layer 203 can be processed into a format suitable for display on the electronic device. The electronic device will then overlay or combine the processed layers 201, 202, and 203 to generate the final product. Figure 2 Interface a in the middle.

[0114] It should be noted that the above process of reading data from the buffer and synthesizing interface 'a' based on the read data is merely an illustrative description and does not limit the execution order of the steps. In practical applications, some processes can be executed in parallel. That is, the electronic device can process the data layer based on the read data while reading data from a portion of the buffer, instead of having to wait until all data from all buffers has been acquired before starting to process the layer.

[0115] It should be understood that processing the layer into a format suitable for display on electronic devices based on the data in the buffer may include, but is not limited to, color conversion, scaling, rotation, etc., and this application does not make any specific limitations on this.

[0116] In some scenarios, layer buffers can be stored in DDR memory, and electronic devices can retrieve the buffers of each layer from DDR memory via the DPU (Data Processing Unit) to composite the interface to be displayed based on these layers. That is, when an electronic device needs to display a particular frame of the interface, the DPU can first read the buffers of the corresponding layers in DDR memory, process the layers into a format suitable for display by the electronic device based on the data in the buffers, and then overlay the processed layers to generate the interface to be displayed.

[0117] For example, with Figure 2Taking the process as an example, buffer1, buffer2, and buffer3 can be stored in DDR memory, and the DPU synthesizes... Figure 2 When accessing interface a, you can first read the data from buffer1, buffer2 and buffer3 in DDR memory. The specific process will not be described here.

[0118] It's understandable that for electronic devices to display various interfaces correctly, the data transfer rate between the DPU and DDR memory needs to meet the DPU's requirements for reading data from relevant layers. Otherwise, display anomalies such as screen tearing and frame drops may occur, thus affecting the user experience.

[0119] Taking an electronic device's display refresh rate of 60Hz and the sum of the layer data of multiple layers in the next frame of the user interface as an example, based on 60Hz and 6MB, the amount of data that needs to be transmitted per second can be calculated as follows:

[0120] 6MB × 60Hz = 360MB / s

[0121] In other words, if the data transfer rate between the DPU and DDR memory is less than 360MB / s, it may not meet the actual data transfer rate required by the DPU when reading data from each layer. Consequently, the electronic device may not be able to synthesize the next frame in time, resulting in dropped frames and impacting the user experience. Conversely, if the data transfer rate between the DPU and DDR memory is greater than or equal to 360MB / s, it meets the actual data transfer rate required by the DPU when reading data from each layer, allowing the electronic device to display the next frame normally.

[0122] In some scenarios, the DPU and DDR memory can be connected via an AXI bus. This means the DPU can read layer data from DDR memory via the AXI bus, and the AXI bandwidth of the AXI bus can be used to indicate the data transfer rate between the DPU and DDR memory. Therefore, DDR memory can allocate AXI bandwidth to the DPU based on its actual AXI bandwidth requirements.

[0123] Based on the above, electronic devices can currently employ, for example... Figure 3 The AXI bandwidth determination method 300 shown determines the AXI bandwidth that can satisfy the sum of layer data from multiple layers of the user interface in the next frame. Specifically, it includes the following steps.

[0124] Figure 3 This is a flowchart illustrating a bandwidth determination method 300. Method 300 includes the following steps:

[0125] Assume that the images displayed by the electronic device from frame a to frame a+x1 are all... Figure 1 The interface (a) is similar, that is, the difference between the a-th frame to the a+x1-th frame displayed by the electronic device is that the content displayed in the video layer 103 is different. Of course, the information displayed in the status bar layer 101 may also change as time and / or the state of the electronic device changes.

[0126] S301, DPU determines the AXI bandwidth of the a-th frame image.

[0127] Here, AXI bandwidth 1 can also be referred to as bandwidth, which is the AXI bandwidth required to transmit the buffers of the multiple layers needed to synthesize the image of frame a. The image of frame a can be, for example,... Figure 1 The interface (a) in the text. And the image of frame a can be synthesized from n layers, where n is an integer greater than or equal to 2.

[0128] AXI bandwidth 1 can be calculated by the processor in the electronic device based on the layer size, pixel width and refresh rate of each of the n layers, and the processor can indicate AXI bandwidth 1 to the DPU.

[0129] The size of a layer can be represented by the width × height of the layer. For example, if a layer is 800 pixels wide and 600 pixels high, then the size of the layer can be represented as 800 × 600 pixels.

[0130] Alternatively, the AXI bandwidth 1(D) can satisfy the following formula:

[0131]

[0132] Where i represents the i-th layer among the n layers used to synthesize the a-th frame image, i∈{1,2,...,n}; Wi is the width of the i-th layer, which can be in pixels; Hi is the height of the i-th layer, which can be in pixels; Bi is the pixel bit width of the i-th layer; and G is the refresh rate.

[0133] It can be understood that the result of pixel width × pixel height × pixel bit width of a layer can be the data volume of a frame of layer data corresponding to that layer. The product of the data volume of a frame of layer data and the refresh rate can be understood as the amount of data required to display a frame of layer data in one second.

[0134] It can be understood that the sum of the amount of data required to display the data of each of the multiple layers corresponding to the interface within one second can be understood as the data transmission rate required to actually transmit the interface frame, that is, the AXI bandwidth.

[0135] by Figure 1Taking interface (a) as an example, assuming the size of each layer in interface (a) is the same as the layer sizes shown in Table 1, and assuming the pixel width of status bar layer 101 and short video application layer 102 is 32 bits, the pixel width of video layer 103 is 16 bits, and the refresh rate is 120 frames / second, then its corresponding AXI bandwidth 1 can be:

[0136] 1312×2848×32×120+960×540×16×120+1312×141×32×120=16054149120Mbps

[0137] Table 1

[0138] Layers Layer size Status bar layer 101 1312×141 pixels Short video application layer 102 1312×2848 pixels Video layer 103 960×540 pixels

[0139] It should be understood that the layer size mentioned above can also be understood as the window size, that is, the size of a rectangular area occupied when drawing the layer.

[0140] S302, DPU indicates AXI bandwidth 1 to DDR memory.

[0141] S303, DDR memory is set to frequency point 1 based on AXI bandwidth 1.

[0142] Here, "frequency point" can be understood as the DDR memory frequency. Memory frequency refers to the clock frequency of DDR memory when it is working, that is, the speed (or rate) at which DDR memory transfers data.

[0143] To ensure that the DDR memory frequency setting 1 can meet the DPU's data retrieval requirements (frame a), the AXI bandwidth allocated to the DPU by frequency setting 1 is greater than or equal to AXI bandwidth 1. In other words, the AXI bandwidth allocated by the DDR memory to the DPU, or the bandwidth actually used to transmit data to the DPU, is greater than or equal to AXI bandwidth 1.

[0144] For the (a+1)th to (a+x1)th frames displayed on the electronic device, each frame includes n layers, and the layer size and pixel width of each layer in the (a+1)th to (a+x1)th frames remain unchanged, and the refresh rate of the electronic device remains unchanged. Therefore, the AXI bandwidth corresponding to any frame in the (a+1)th to (a+x1)th frames is the same as AXI bandwidth 1.

[0145] For any frame image from frame a+1 to frame a+x1, denoted as frame a+j, the AXI bandwidth used by the buffer for transmitting the n layers included in that frame image can be determined in accordance with the following methods S304 to S306.

[0146] It should be noted that, in this embodiment of the application, for ease of distinction, AXI bandwidth represents the data transfer rate required by the DPU to read data from the DDR memory; frequency point represents the actual data transfer rate allocated by the DDR memory to the DPU based on the AXI bandwidth indicated by the DPU. This will not be elaborated further below.

[0147] S304, DPU determines the AXI bandwidth 2 of the (a+j)th frame image, where j is an integer greater than or equal to 1 and less than or equal to x1.

[0148] Here, AXI bandwidth 2 can also be determined by the processor and instructed to the DPU.

[0149] S305, DPU indicates AXI bandwidth 2 to DDR memory.

[0150] S306, DDR memory is set to frequency point 2 based on AXI bandwidth 2.

[0151] When AXI bandwidth 1 and AXI bandwidth 2 are the same, frequency point 2 may be the same as or different from frequency point 1. That is, DDR memory can set its frequency point based on the AXI bandwidth indicated to it by all modules. For example, in addition to the DPU, modules such as the GPU and image decoder can also indicate the AXI bandwidth to the DDR memory.

[0152] Alternatively, if AXI bandwidth 2 is the same as AXI bandwidth 1, the DPU may not execute S305 to S306, so that the DDR memory continuously transmits data to the DPU based on the AXI bandwidth allocated to the DPU indicated by frequency point 2.

[0153] It is understood that the implementation methods of S304 to S306 are similar to those of S301 to S303. For details, please refer to the relevant descriptions of S301 to S303, which will not be repeated here.

[0154] Assume the interface of the (a+x1+1)th frame displayed on the electronic device is the interface of a short video application displaying a video in full screen. That is, compared to... Figure 1 In the interface (a), the interface of the a+x1+1 frame image does not include the status bar layer 101, and the size of the video layer 103 and the short video application layer 102 is consistent with the screen size.

[0155] S307, DPU determines the AXI bandwidth 3 of the image in frame a+x1+1.

[0156] It should be understood that the AXI bandwidth 3 can be calculated by the processor and indicated to the DPU, etc., and the AXI bandwidth 3 can also be calculated according to the formula for calculating D mentioned above.

[0157] Therefore, the AXI bandwidth 3 can be, for example, 1312×2848×32×120+1312×2848×16×120=21522677760Mbps.

[0158] S308, DPU indicates AXI bandwidth 3 to DDR memory.

[0159] S309, DDR memory is set to frequency point 3 based on AXI bandwidth requirement 3.

[0160] Frequency point 3 indicates that the AXI bandwidth allocated to the DPU is greater than or equal to AXI bandwidth 3.

[0161] It is understood that the implementation methods of S307 to S309 are similar to those of S301 to S303. For details, please refer to the relevant descriptions of S301 to S303, which will not be repeated here.

[0162] For example, if x1 is 100, meaning the DPU needs to acquire 100 frames of interface data, and assuming that the AXI bandwidth calculated by the electronic device for each frame within these 100 frames is the same (i.e., the AXI bandwidth for frames a+1 to a+100 is the same as the AXI bandwidth 1 for frame a), then when the DPU acquires interface data from frames a+1 to a+100, the DPU does not need to instruct the DDR memory to set the frequency. However, if the layers included in frame a+101 change compared to frames a+1 to a+100, with one or more layers becoming larger, then the calculated AXI bandwidth for frame a+101 will also change. In this case, the DPU can instruct the DDR memory to set the frequency, meaning the DDR memory will set its frequency according to the changed AXI bandwidth indicated by the DPU.

[0163] By combining method 300, it can be determined that the AXI bandwidth indicated by the DPU to the DDR memory is calculated based on the data volume of all layers included in the interface to be displayed.

[0164] It should be noted that when the DPU reads image data from DDR memory, it can read it line by line, pixel by pixel, on the display screen. That is, the data for all layers in a single frame includes the data corresponding to each pixel row on the display screen (the image data used for display). Furthermore, the DPU can read the pixel data of each row sequentially from the top to the bottom of the display screen.

[0165] In method 300, during the process of the DPU reading data of each layer in a frame of the interface from the DDR memory, the transmission rate (the frequency point allocated by the DDR memory in method 300) used by the DDR memory to transmit each row of pixel data to the DPU is the same, and the frequency point is determined based on the AXI bandwidth required by the DPU to transmit data of all layers in a frame of the interface.

[0166] However, for a single frame of the interface that includes multiple layers, not all of these layers may be displayed in full screen. For example... Figure 1 In the interface (a), the status bar layer 101 is relatively small and covers only a portion of the top of the display screen. Typically, when the DPU reads data corresponding to each pixel row from DDR memory, the amount of data corresponding to that pixel row is usually larger if the number of layers covering that pixel row is large, and smaller if the number of layers covering that pixel row is small. Therefore, as the number of layers covering each pixel row on the display screen varies, the amount of data the DPU reads from DDR memory varies, and consequently, the transfer rate required for the DPU to read data corresponding to each pixel row from DDR memory varies.

[0167] Since the AXI bandwidth calculated by the electronic device in method 300 can be understood as the bandwidth required for the DDR memory to transmit data of all layers included in a complete frame of the interface to the DPU, that is, during the process of the DPU reading data of each layer in a frame of the interface from the DDR memory, the frequency allocated by the DDR memory to the DPU can meet the transmission rate required for the data of the pixel row with the largest amount of data. This may cause the frequency allocated by the DDR memory to the DPU to exceed the actual transmission rate required for the DPU to read the data corresponding to each pixel row, thus causing the operating frequency of the DDR memory to exceed the actual transmission rate required for the DPU to read data from the DDR memory, resulting in higher power consumption of the DDR memory.

[0168] In view of this, embodiments of this application provide an image data processing method in which an electronic device can partition the interface to be displayed (or the display area of ​​the display screen) based on multiple layers included in the interface to be displayed, wherein the number of corresponding layers in adjacent display areas is different.

[0169] In this way, the data transfer rate required for the electronic device to read data from DDR memory is consistent across all regions. The electronic device can allocate matching frequency points for reading layer data in each region based on the actual needs of each region in the display interface. For regions covering more layers, the data transfer rate required to read the corresponding data in that region is higher, and a larger AXI bandwidth can be allocated accordingly; for regions covering fewer layers, the data transfer rate required to read the corresponding data in that region is lower, and a smaller AXI bandwidth can be allocated accordingly.

[0170] In other words, when the DPU reads data from each layer of the interface to be displayed, it can dynamically adjust the frequency of the DDR memory based on the actual transfer rate required by each partition. This ensures that the frequency of the DDR memory can meet the needs of reading data from the DDR memory, while also preventing the DDR memory from constantly operating at a high frequency when reading data from each layer of the interface to be displayed, thereby reducing the power consumption of the DDR memory.

[0171] Still using the interface to be displayed Figure 1 Taking interface (a) as an example, based on Figure 1 The interface (a) includes three layers, which can... Figure 1 The interface (a) or display screen is divided into four areas.

[0172] For example, Figure 4 This application provides an interface diagram of a partition for displaying an interface in an embodiment of the present application, and Figure 4 The interface to be displayed in the middle can be understood as Figure 1 A schematic diagram of the interface (a).

[0173] Combination Figure 2 The synthesis shown in the figure Figure 1 The process in interface (a) determines that layer 201 is a layer with a size equal to the screen size, and layers 202 and 203 respectively overlap layer 201. Then the screen or Figure 1 In the middle interface (a), layer 202 covers the area above layer 201 (or the area where layer 202 is located), and there are 2 layers, namely layer 201 and layer 202.

[0174] Similarly, layer 203 covers the area above layer 201 (or the area where layer 203 is located), and there are 2 layers, namely layer 201 and layer 203.

[0175] For the area that only displays layer 201, that is, the area other than layers 202 and 203, the number of layers is 1.

[0176] Then as Figure 4As shown, the electronic device can divide the interface to be displayed (the display area of ​​the screen) into region 1, region 2, region 3, and region 4 in sequence. Among them, region 1 has 2 layers, region 2 has 1 layer, region 3 has 2 layers, and region 4 has 1 layer.

[0177] It should be understood that since the multiple layers included in the interface to be displayed can also be understood as layers drawn in multiple windows, that is, each layer in the multiple layers corresponds to one window. Therefore, the interface to be displayed can also be understood as a multi-window interface. Furthermore, the number of layers in each area can also be understood as the number of windows or the window thickness. This application does not make specific limitations in this regard.

[0178] Furthermore, the location of each region can be represented by rows of pixels. Assume that the areas (i.e., display areas) and sizes of layers 201, 202, and 203 displayed on the screen are as shown in Table 2. The display area can be understood as the area shown on the screen, and it can be represented by two coordinates in the display coordinate system. These two coordinates can represent the top-left and bottom-right corner coordinates of the display area in the display coordinate system, respectively. Therefore, the top-left ordinate indicates the first row of pixels in the display area, and the bottom-right ordinate indicates the last row of pixels in the display area.

[0179] For example, the upper left corner coordinates of the display area of ​​layer 201 can be (0, 0), and the lower right corner coordinates can be (1312, 2848), which can represent the entire display area of ​​the electronic device's screen.

[0180] The top-left corner of the display area of ​​layer 202 can be (0, 0), and the bottom-right corner can be (1312, 141), indicating that the display area of ​​layer 202 is located at the top of the display screen area, and the width of the display area of ​​layer 202 is the same as the width of the display screen area. Furthermore, the display area containing layer 202, and area 1, extends from the first row of pixels to the 141st row of pixels on the interface to be displayed.

[0181] The top-left corner coordinates of the display area of ​​layer 203 can be (0, 942), and the bottom-right corner coordinates can be (1312, 1680). Furthermore, the display area of ​​layer 203 and area 3 are located from the 942nd row of pixels to the 1680th row of the interface to be displayed.

[0182] Region 2 is from row 142 (the row below the last row of pixels in layer 202) to row 941 (the row above the first row of pixels in layer 203); Region 4 is from row 1681 (the row below the last row of pixels in layer 203) to row 2848 (the last row of pixels in layer 201).

[0183] Table 2

[0184] Layers Display area Layer size Layer 201 (0，0)(1312，2848) 1312×2848 pixels Layer 202 (0，0)(1312，141) 1312×141 pixels Layer 203 (0，942)(1312，1680) 960×540 pixels

[0185] Based on the above embodiments, the electronic device can determine the AXI bandwidth corresponding to each of the multiple regions in the following way: the AXI bandwidth is the AXI bandwidth required to transmit the data of the layers in each region. Similar to method 300, the AXI bandwidth corresponding to each region can also be calculated based on the layer size, pixel bit width, and refresh rate of each layer in each region. The difference is that the layer size used to calculate the AXI bandwidth of each region is the size of the layer in that region, rather than the overall size of all layers.

[0186] Referring back to Table 2, the overall size of layer 201 can be 1312×2848 pixels; the overall size of layer 202 can be 1312×141 pixels; and the overall size of layer 203 can be 960×540 pixels. The sizes of each layer within each of the multiple regions can be shown in Table 3.

[0187] It should be noted that in this embodiment, the screen display area corresponding to a layer may be the same as or different from the layer size. Because the electronic device may perform rotation, scaling, or other processing when displaying the content of each layer, the size of each layer included in the interface to be displayed on the electronic device may be different from the screen display area corresponding to that layer. Taking layer 203 as an example, layer 203 is used to display videos in short video applications. When the electronic device displays videos in short video applications, the images in the videos may be rotated, scaled, or processed, so the size of layer 203 used to display the video content may be different from the screen display area of ​​that layer.

[0188] It should also be noted that the coordinate system in the display screen of an electronic device can also be called the screen coordinate system, which is a coordinate system used to position elements such as graphics or text on the display screen of an electronic device. The origin of the screen coordinate system can be, for example, the upper left corner of the screen, the x-axis can be a horizontal axis pointing to the right side of the display screen, and the y-axis can be a vertical axis pointing to the bottom of the display screen. This application does not make specific limitations in this regard.

[0189] Referring to Table 3, Region 1 includes Layer 201 and Layer 202, with both Layer 201 and Layer 202 having a size of 1312×141 pixels; Region 2 includes Layer 201, with a size of 1312×800 pixels; Region 3 includes Layer 201 and Layer 203, with both Layer 201 and Layer 203 having a size of 1312×739 pixels and Layer 203 having a size of 960×540 pixels; Region 4 includes Layer 201, with a size of 1312×1168 pixels.

[0190] Table 3

[0191]

[0192] After the electronic device divides the interface to be displayed into multiple areas, the AXI bandwidth can be calculated for each area separately according to the formula shown in S301.

[0193] by Figure 1 The interface (a) is divided into regions 1, 2, 3, and 4 as shown in Table 3. Taking the position (pixel row) of each region and the corresponding layer size as an example, assuming that the pixel width of layer 201 and layer 202 is 32 bits, the pixel width of layer 203 is 16 bits, and the refresh rate is 120 frames / second, then the AXI bandwidth of each region of interface (a) can be:

[0194] AXI bandwidth 4 for region 1: 1312×141×32×120 + 1312×141×32×120 = 1420738560Mbps;

[0195] The AXI bandwidth of region 2 is 5: 1312×80×32×120=4035402080Mbps;

[0196] The AXI bandwidth of region 3 is 6: 1312×739×32×120+960×540×16×120=4713431040Mbps;

[0197] The AXI bandwidth of region 4 is 7: 1312×1168×32×120=5884477440Mbps.

[0198] It can be seen that the AXI bandwidth in each region is less than that based on Figure 1 The interface (a) includes all layers with calculated AXI bandwidth 1 (16054149120Mbps).

[0199] Therefore, during the process of the DPU reading pixel data in each row of region 1 (rows 1 to 141 of the display), the frequency point 4 allocated by the DDR memory to the DPU is based on the AXI bandwidth 4. That is, the AXI bandwidth indicated by frequency point 4 is greater than or equal to 5884477440 Mbps.

[0200] Compared to method 300, DPU read Figure 1 In the process of processing each row of pixel data in interface (a), the frequency point 1 allocated by DDR memory to the DPU is based on the AXI bandwidth 1 (16054149120Mbps). That is, the AXI bandwidth indicated by frequency point 1 is greater than or equal to 16054149120Mbps.

[0201] It can be seen that the AXI bandwidth indicated by frequency point 4 allocated to the DDR memory is likely less than the AXI bandwidth indicated by frequency point 1. That is, in this embodiment of the application, the DDR memory can transmit image data in region 1 to the DPU at a smaller transmission rate, so that the power consumption of the DDR memory can be smaller during the transmission of image data in region 1.

[0202] Similarly, for region 2, during the process of the DPU reading each row of pixel data in region 2 (pixels from row 142 to row 941 of the display), the frequency point 5 allocated by the DDR memory to the DPU is based on the AXI bandwidth 5 (4035402080Mbps). Compared with the frequency point 1 allocated based on the AXI bandwidth 1 (16054149120Mbps) in method 300, the AXI bandwidth indicated by frequency point 5 is likely smaller than the AXI bandwidth indicated by frequency point 1. Therefore, in this embodiment, the DDR memory can transmit the image data in region 2 to the DPU at a smaller transmission rate, so that the power consumption of the DDR memory can be smaller during the transmission of the image data in region 2.

[0203] For region 3, during the process of the DPU reading each row of pixel data in region 3 (pixels from row 942 to row 1680 of the display screen), the frequency point 6 allocated by the DDR memory to the DPU is based on the AXI bandwidth 6 (4713431040Mbps). Compared with the frequency point 1 allocated based on the AXI bandwidth 1 (16054149120Mbps) in method 300, the AXI bandwidth indicated by frequency point 6 is likely smaller than the AXI bandwidth indicated by frequency point 1. Therefore, in this embodiment, the DDR memory can transmit the image data in region 3 to the DPU at a smaller transmission rate, so that the power consumption of the DDR memory can be smaller during the transmission of the image data in region 3.

[0204] For region 4 (whose AXI bandwidth is the highest among the four regions), during the process of the DPU reading each row of pixel data in region 4 (pixels from row 1681 to row 2848 of the display screen), the frequency point 7 allocated by the DDR memory to the DPU is based on the AXI bandwidth 7 (5884477440Mbps). Compared with the frequency point 1 allocated based on the AXI bandwidth 1 (16054149120Mbps) in method 300, the AXI bandwidth indicated by frequency point 7 is likely smaller than the AXI bandwidth indicated by frequency point 1. Therefore, in this embodiment, the DDR memory can transmit the image data in region 4 to the DPU at a smaller transmission rate, resulting in lower power consumption of the DDR memory during the transmission of image data in region 4.

[0205] Therefore, it can be seen that in the process of reading data of the layers included in the interface to be displayed from DDR memory through the embodiments of this application, the operating frequency of DDR memory can be relatively low, thereby reducing the power consumption of DDR memory.

[0206] The following is combined with Figures 5 to 9 The technical solutions of this application and how they solve the aforementioned technical problems are described in detail with specific embodiments. The following specific embodiments can be implemented independently or in combination with each other. Identical or similar concepts or processes may not be described again in some embodiments.

[0207] The embodiments shown in this application can be executed by an electronic device, which may be an electronic device equipped with a display screen. The specific form and number of the devices shown are merely examples and should not be construed as limiting the implementation of the methods provided in this application.

[0208] It should be understood that an electronic device can be the electronic device itself, or a chip, chip system or processor that supports the electronic device in implementing image data processing methods, or a logic module or software that can implement all or part of the functions of the electronic device. This application does not make any specific limitations in this regard.

[0209] The image data processing method of this application embodiment will be described in detail below, taking an electronic device as the execution subject.

[0210] First, to facilitate understanding of the embodiments of this application, the following will be combined with... Figure 4 The hardware architecture of electronic devices is described in detail.

[0211] Figure 5 This is a schematic diagram of the structure of the electronic device 500 provided in an embodiment of this application. Figure 5 As shown, the electronic device 500 may include a processor 510, an external memory interface 520, an internal memory 521, a universal serial bus (USB) interface 530, a charging management module 540, a power management module 541, a battery 542, an antenna 1, an antenna 2, a mobile communication module 540, a wireless communication module 560, an audio module 570, a sensor module 580, buttons 590, an indicator 592, a camera 593, and a display screen 594, etc.

[0212] The audio module 570 may include, but is not limited to, a speaker, a receiver, a microphone, and a headphone jack.

[0213] The sensor module 580 may include, but is not limited to, one or more of the following sensors: pressure sensor, gyroscope sensor, barometric pressure sensor, magnetic sensor, accelerometer, distance sensor, proximity sensor, fingerprint sensor, temperature sensor, touch sensor, ambient light sensor, and bone conduction sensor, etc.

[0214] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 500. In other embodiments of this application, the electronic device 500 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0215] Processor 510 may include one or more processing units, such as: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc. Optionally, processor 510 may also include memory for storing instructions and data. The different processing units may be independent devices or integrated into one or more processors.

[0216] The wireless communication function of electronic device 500 can be implemented through antenna 1, antenna 2, mobile communication module 540, wireless communication module 560, modem processor, and baseband processor.

[0217] Electronic device 500 implements display functions through a GPU, a display screen 594, and an application processor. The GPU is a microprocessor for image processing, connecting the display screen 594 and the application processor. The GPU performs mathematical and geometric calculations and is used for graphics rendering. Processor 510 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0218] Display screen 594 can be used for the interface to be displayed, such as Figure 1 Interfaces (a) and (b) are shown in the image. It can be understood that the interface displayed on screen 594 can be composed of multiple layers, and different layers can have the same or different sizes and display different content.

[0219] It is understood that the interface displayed on the display screen 594 may also include multiple windows, and the different layers included in the interface may be drawn in different windows. This application does not make any specific limitations on this.

[0220] In some embodiments, the electronic device 500 may include one or N displays 594, where N is a positive integer greater than 1.

[0221] Optionally, the electronic device 500 may also include a DPU, and the data of the interface displayed on the display screen 594 may be indicated by the DPU. That is, the DPU can transmit the data of the interface to be displayed to the display screen 594, so that the display screen 594 displays the corresponding interface based on the data.

[0222] For example, the DPU can acquire data from each of the multiple layers included in the interface to be displayed. It can also synthesize the interface to be displayed based on the data from each of the multiple layers; and it can transmit the data of the interface to be displayed to the display screen 594, so that the display screen 594 displays the corresponding interface based on the data.

[0223] Optionally, the electronic device 500 may also include DDR memory, which can be used to store layer data. The DPU can read data from the DDR memory for each of the multiple layers included in the interface to be displayed.

[0224] It should be understood that layer data may include, but is not limited to, the layer's pixel data, size, and Z-Order parameters. Layer data can also be understood as data in the layer's buffer. Each layer's buffer can correspond to a storage space in DDR memory. Taking the interface (a) above as an example, the data corresponding to the three layers in interface (a) can be understood as the data in buffer1, buffer2, and buffer3, and buffer1, buffer2, and buffer3 can each correspond to a storage space in DDR memory.

[0225] Based on the above embodiments, the DPU and / or DDR memory can be integrated onto the processor 510 and connected via the AXI bus. Alternatively, the DPU and DDR memory can also be connected to the processor 510 as separate modules; this application does not specifically limit this.

[0226] When the DPU and DDR memory are connected via an AXI bus, the DPU can read data from the buffer stored in the DDR memory through the AXI bus. Therefore, the AXI bandwidth affects the data transfer rate between the DPU and the DDR memory. Before the DPU reads data, the DDR memory can allocate AXI bandwidth to the DPU based on the actual AXI bandwidth required for the DPU to read the data.

[0227] Optionally, the processor 510 can also be used to calculate the actual AXI bandwidth required for the DPU to read data and instruct the DPU on the AXI bandwidth. For example, the processor 510 can calculate the AXI bandwidth based on the layer size, pixel width, and refresh rate of each of the multiple layers of the interface to be displayed.

[0228] In one possible implementation, the electronic device 500 can configure registers that the DPU can read, which can be used to store instructions, data, and control information. In a possible implementation, when the processor 510 calculates the actual AXI bandwidth required for the DPU to read data, it can store this AXI bandwidth in a register that the DPU can read. The AXI bandwidth stored in this register can be read before the DPU reads data from the DDR memory layer. Furthermore, the DPU can indicate this AXI bandwidth to the DDR memory so that the DDR memory can set its frequency based on this AXI bandwidth. This ensures that the frequency set by the DDR memory can meet the DPU's data acquisition needs from the DDR memory.

[0229] It should be understood that the number of registers that the DPU can read can be one or more, and this application does not specifically limit this.

[0230] The external memory interface 520 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 500. The internal memory 521 can be used to store computer executable program code, which includes instructions.

[0231] The following is combined with Figure 6 The image data processing method 600 of this application will be described in detail through specific embodiments. The following embodiments can be implemented in combination with each other or independently, and the same or similar concepts or processes may not be described again in some embodiments.

[0232] It should be understood that method 600 can be executed by an electronic device, and the hardware structure of the electronic device can be as follows: Figure 5 As shown, Figure 6 The functions of each hardware module shown can be found in [link / reference]. Figure 5 Method 600 includes the following steps:

[0233] Assume the electronic device is about to display the b-th frame image. Figure 1 If the interface (a) is similar to or the same as the interface, then the DPU can read the buffer of multiple layers included in the b-th frame image from DDR memory in the following manner.

[0234] Based on the description of the above embodiments, it can be understood that before the electronic device displays the b-th frame image (the interface to be displayed), the processor 510 can partition the display screen (the interface to be displayed) and calculate the AXI bandwidth required for the DPU to read data from the layer in each region. Furthermore, the processor 510 can indicate the AXI bandwidth corresponding to each region to the DPU. For example, the processor 510 can store the position of each region (including the pixel rows) and the AXI bandwidth of each region in a register that the DPU can read.

[0235] Specifically, the image in frame b is divided into the following segments: Figure 4 In the case of regions 1, 2, 3, and 4 shown, the pixel rows of each region can be represented as shown in Table 3. The AXI bandwidths of each region are as follows: Region 1 AXI bandwidth 4: 1420738560Mbps; Region 2 AXI bandwidth 5: 4035402080Mbps; Region 3 AXI bandwidth 6: 4713431040Mbps; Region 4 AXI bandwidth 7: 5884477440Mbps. The DPU can then store the pixel rows corresponding to Region 1 (pixels from row 1 to row 141 of the display screen) and AXI bandwidth 4 into registers that the DPU can read. Similarly, the row pixels and AXI bandwidths corresponding to each region in Regions 2, 3, and 4 can also be stored in registers. For simplicity, further details are omitted here.

[0236] In this way, before the DPU reads the pixel data of each layer of the b-th frame image stored in the DDR memory, it can read the AXI bandwidth of each region stored in the register and indicate the AXI bandwidth to the DDR memory so that the DDR memory can set the frequency point (the data transmission rate actually allocated to the DPU, i.e., the actual allocated AXI bandwidth) based on the AXI bandwidth.

[0237] It should be noted that method 600 is illustrated by dividing the interface to be displayed into region 1, region 2, region 3, and region 4. Region 1, region 2, region 3, and region 4 can be obtained by the processor 510 partitioning the image of frame b based on the number of layers superimposed on each region in the image of frame b. For details, please refer to the description above, which will not be repeated here.

[0238] S601, DPU determines the AXI bandwidth 4 of region 1 of the b-th frame image.

[0239] Here, the b-th frame image can be understood as the interface to be displayed on the electronic device. AXI bandwidth 4, also known as bandwidth, refers to the AXI bandwidth required for the DDR memory to transmit data from region 1 to the DPU. The data in region 1 is the portion of the data used to synthesize the multiple layers of the b-th frame image within that region. Region 1 could, for example, be the topmost region of the b-th frame image.

[0240] Taking the interface (b) in frame b as an example, region 1 of frame b can be, for example, Figure 4 Region 1 in the interface shown. The multiple layers used to composite the b-th frame image can be composed of n layers. Region 1 in the b-th frame image can include m layers, and the b-th frame image is... Figure 1 When the interface (a) is displayed, the m layers can include layer 202 and layer 201, that is, the number of layers in region 1 is 2.

[0241] AXI bandwidth 4 can be calculated by processor 510 based on the layer size, pixel bit width and refresh rate of each layer in m layers in region 1, and processor 510 can indicate AXI bandwidth 4 to DPU.

[0242] Alternatively, the AXI bandwidth 4(D2) can satisfy the following formula:

[0243]

[0244] Where i represents the i-th layer among the m layers in region 1, i∈{1,2,...,m}; W i H represents the width of the i-th layer in region 1, in pixels. i B is the height of the i-th layer in region 1, in pixels; i G is the pixel width of the i-th layer; G is the refresh rate.

[0245] The specific calculation process for AXI bandwidth 4 can be found in the relevant description of the corresponding embodiment in Table 3, and will not be repeated here.

[0246] It is understandable that before the DPU reads data from region 1 of DDR memory, the DPU can determine the AXI bandwidth 4 based on the information stored in the register.

[0247] S602, DPU indicates AXI bandwidth 4 to DDR memory.

[0248] S603, DDR memory is set to frequency point 4 based on AXI bandwidth 4.

[0249] Frequency point 4 indicates the actual AXI bandwidth used by the DDR memory for data in transmission area 1 allocated to the PDU. The AXI bandwidth indicated by frequency point 4 is greater than or equal to AXI bandwidth 4. That is, the actual data transfer rate allocated by the DDR memory to the DPU, or the actual AXI bandwidth used to transfer data to the DPU, is greater than or equal to AXI bandwidth 4, to meet the DPU's data reading needs in area 1.

[0250] It's important to note that DDR memory can be configured with a frequency point (i.e., allocated AXI bandwidth) based on the AXI bandwidth indicated by all modules to the DDR memory. In other words, besides the DPU, other modules, such as the GPU or image decoder, may also read data from DDR memory, and these other modules will also indicate the required AXI bandwidth to the DDR memory. Therefore, DDR memory can be configured with a frequency point based on the AXI bandwidth indicated by all modules to meet the needs of each module. The process by which each module (e.g., the DPU) indicates AXI bandwidth to the DDR memory can also be called voting for the DDR memory, and the AXI bandwidth indicated by each module (e.g., the DPU) can be referred to as the "votes."

[0251] Optionally, the number of "votes" each module casts for the DDR memory can be positively correlated with the AXI bandwidth allocated to that module by the DDR memory. That is, the more "votes" a module has, the greater the AXI bandwidth that the DDR memory may allocate to the module.

[0252] S604, DDR memory transmits pixel data 1 of each layer in region 1 to DPU based on frequency point 4.

[0253] Here, pixel data 1 can be understood as the data in region 1. For example, if region 1 is the first to the 141st row of pixels on the display screen, and region 1 includes layer 201 and layer 202, pixel data 1 can include the data of the first to the 141st row of pixels stored in the buffer of layer 201 and the buffer of layer 202.

[0254] After transmitting the data (pixel data 1) in region 1, the DPU can continue reading the data in region 2. Before transmitting the data in region 2, the DPU can determine the AXI bandwidth 5 corresponding to region 2 and read the data in region 2 via steps S605 to S608.

[0255] S605, DPU determines the AXI bandwidth 5 of region 2 of the b-th frame image.

[0256] The AXI bandwidth 5 can also be determined by the processor 510 and instructed to the DPU (stored in a register that the DPU can read). This AXI bandwidth 5 can be determined by the processor 510 and instructed to the DPU before the DPU reads the data in region 1.

[0257] Furthermore, when the DPU is about to read the pixel row where region 2 is located, that is, when switching from reading pixel data in region 1 to reading pixel data in region 2, the DPU can determine the AXI bandwidth 5 of region 2 based on the AXI bandwidth actually required for the pixel data of each region stored in the register.

[0258] S606, DPU indicates AXI bandwidth 5 to DDR memory.

[0259] S607, DDR memory is set to frequency point 5 based on AXI bandwidth 5.

[0260] The S608 and DDR memory transmit pixel data 2 of each layer in region 2 to the DPU based on frequency point 5.

[0261] Pixel data 2 can be understood as the data in region 2. For example, if region 2 consists of pixels from row 142 to row 941, and the layer in region 2 includes layer 201, then pixel data 2 can be the data of pixels from row 142 to row 941 cached in the buffer corresponding to layer 201.

[0262] Similar to S602-S604, in order to ensure that the frequency point 5 set by the DDR memory can meet the requirements of the DPU in obtaining data from region 2 (pixel data of layer 201 in region 2 of the b-th frame image), the AXI bandwidth allocated to the DPU by the frequency point 5 is greater than or equal to AXI bandwidth 5. That is, the AXI bandwidth allocated by the DDR memory to the DPU, or the bandwidth actually used to transmit data to the DPU, is greater than or equal to AXI bandwidth 5.

[0263] In this way, DDR memory can transmit pixel data 2 of each layer in region 2 to the DPU based on frequency point 5 (that is, a transmission rate greater than or equal to AXI bandwidth 5). Figure 4 (Pixel data of layer 201 in region 2).

[0264] It is understood that the implementation methods of S605 to S608 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0265] S609, DPU determines the AXI bandwidth 6 of region 3 of the b-th frame image.

[0266] Similarly, AXI bandwidth 6 and AXI bandwidth 7 mentioned below can also be determined by the processor 510 and indicated to the DPU before the DPU reads region 1 of the b-th frame image. For the sake of brevity, they will not be described in detail below.

[0267] S610, DPU indicates AXI bandwidth 6 to DDR memory.

[0268] S611, DDR memory is set to frequency point 6 based on AXI bandwidth 6.

[0269] S612, DDR memory transmits pixel data 3 of each layer in the DPU region 3 based on frequency point 6.

[0270] Here, pixel data 3 can be understood as the data in region 3. For example, if region 3 consists of pixels from row 942 to row 1680, and the layers in region 3 include layer 201 and layer 203, then pixel data 3 can be the data of pixels from row 942 to row 1680 cached in the buffers corresponding to layer 201 and layer 203.

[0271] Similarly, when the DPU is about to read the pixel row where region 3 is located, that is, when switching from reading pixel data in region 2 to reading pixel data in region 3, the DPU can determine the AXI bandwidth 6 of region 3 based on the AXI bandwidth actually required for the pixel data of each region stored in the register, and the DPU can instruct the DDR memory on the AXI bandwidth 6.

[0272] In order for the DDR memory frequency setting 6 to meet the DPU's needs for retrieving data from the DDR memory (pixel data of layers 201 and 203 in region 3 of frame b), the AXI bandwidth allocated to the DPU by frequency setting 6 is greater than or equal to AXI bandwidth 6. That is, the actual data transfer rate allocated by the DDR memory to the DPU, or the AXI bandwidth actually used to transfer data to the DPU, is greater than or equal to AXI bandwidth 6.

[0273] Furthermore, DDR memory can transmit pixel data 3 of each layer in region 3 to the DPU based on frequency point 6 (i.e., a data transfer rate greater than or equal to AXI bandwidth 6). Figure 4 (Pixel data of layers 201 and 203 in region 3).

[0274] It is understood that the implementation methods of S609 to S612 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0275] S613, DPU determines the AXI bandwidth 7 of region 4 of the b-th frame image.

[0276] S614, DPU indicates AXI bandwidth 7 to DDR memory.

[0277] S615, DDR memory is set to frequency 7 based on AXI bandwidth 7.

[0278] The S616 and DDR memory transmit pixel data 4 of each layer in the DPU region 4 based on frequency point 7.

[0279] Similarly, when the DPU is about to read the pixel row of region 4, that is, when switching from reading pixel data in region 3 to reading pixel data in region 4, the DPU can determine the AXI bandwidth 7 of region 4 based on the AXI bandwidth actually required for the pixel data of each region stored in the register, and the DPU can instruct the DDR memory on the AXI bandwidth 7.

[0280] In order for the DDR memory frequency setting 7 to meet the requirements of the DPU in retrieving data from the DDR memory (pixel data of layer 201 in region 4 of the b-th frame image), the AXI bandwidth allocated to the DPU by frequency setting 7 is greater than or equal to AXI bandwidth 7. That is, the actual data transfer rate allocated by the DDR memory to the DPU, or the AXI bandwidth actually used to transfer data to the DPU, is greater than or equal to AXI bandwidth 7.

[0281] Furthermore, the DDR memory can transmit pixel data 7 of each layer in region 7 to the DPU based on frequency 7 (i.e., a data transfer rate greater than or equal to the AXI bandwidth 7). Figure 4 (Pixel data of layer 201 in region 4).

[0282] It is understood that the implementation methods of S613 to S616 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0283] Optionally, when the DPU reads the buffers corresponding to multiple layers included in the b-th frame image from the DDR memory, it can read the pixel rows and AXI bandwidth corresponding to each region in region 1, region 2, region 3, and region 4 stored in the register. Before reading the data in region 1 (pixels from row 1 to row 141 on the display), it can indicate AXI bandwidth 4 to the DDR memory; before reading the data in region 2 (pixels from row 142 to row 941 on the display), it can indicate AXI bandwidth 5 to the DDR memory; before reading the data in region 3 (pixels from row 942 to row 1680 on the display), it can indicate AXI bandwidth 6 to the DDR memory; and before reading the data in region 4 (pixels from row 1681 to row 2848 on the display), it can indicate AXI bandwidth 7 to the DDR memory.

[0284] Correspondingly, the DDR memory can be set to a frequency point 4 based on the AXI bandwidth 4 to satisfy the DPU's acquisition of data from region 1 (pixel data from row 1 to row 141 of the display screen) from the DDR memory (that is, the AXI bandwidth allocated to the DPU is greater than or equal to the AXI bandwidth 4); similarly, the DDR memory can be set to a frequency point 5 based on the AXI bandwidth 5 to satisfy the DPU's acquisition of data from the DDR memory (pixel data from row 142 to row 941 of the display screen), and the DDR memory can be set to a frequency point 6 based on the AXI bandwidth 6 to satisfy the DPU's acquisition of data from the DDR memory (pixel data from row 942 to row 1680 of the display screen), and the DDR memory can be set to a frequency point 7 based on the AXI bandwidth 7 to satisfy the DPU's acquisition of data from the DDR memory (pixel data from row 1681 to row 2848 of the display screen).

[0285] In this way, when the DPU reads pixel data of each layer in the interface to be displayed, the DDR memory can dynamically adjust its frequency based on the actual bandwidth requirements of each area in the interface read by the DPU. This allows the DDR memory to allocate a smaller data transfer rate (AXI bandwidth indicated by the frequency point) to the DPU when it needs less AXI bandwidth, thereby reducing the power consumption of the DDR memory. Conversely, when the DPU needs more bandwidth, the DDR memory can allocate more bandwidth to the DPU, reducing display anomalies such as screen tearing and frame drops that may occur due to insufficient bandwidth, thus improving the user experience.

[0286] Assume the electronic device, after the b-th frame, is... Figure 7 Similar to interface (a) in the image, the x2 interfaces to be displayed are similar to those in frame b, except that the content displayed in video layer 103 is different. Of course, the information displayed in status bar layer 101 may also change as time and / or the electronic device's status changes. Therefore, the multiple regions divided into the x2 interfaces to be displayed are the same as the multiple regions divided into in frame b.

[0287] In other words, the x2 interfaces to be displayed can be understood as frames b+1 to b+x2, and each frame in frames b+1 to b+x2 can be divided into region 1, region 2, region 3, and region 4. Furthermore, assuming that the layer size and pixel width of each layer remain unchanged from frame b to b+x2, and the refresh rate of the electronic device remains unchanged, then for any frame in frames b+1 to b+x2, the AXI bandwidth of region 1 is the same as AXI bandwidth 4, the AXI bandwidth of region 2 is the same as AXI bandwidth 5, the AXI bandwidth of region 3 is the same as AXI bandwidth 6, and the AXI bandwidth of region 4 is the same as AXI bandwidth 7.

[0288] That is, for any frame from frame b+1 to frame b+x2, denoted as frame b+j, the DPU can read the buffers corresponding to multiple layers of the frame b+j stored in the DDR memory in the manner described in S617 to S632 below.

[0289] It is understandable that, if the layers in each area of ​​the interface to be displayed remain unchanged (i.e., the layer size, resolution, and pixel width), the processor 510 may not indicate the four areas and their corresponding AXI bandwidths to the DPU (the DPU reads the actual AXI bandwidth required by the four areas), so that the DPU can continue to instruct the DDR memory based on the unchanged AXI bandwidth. That is, even if the information stored in the registers remains unchanged, the DPU still votes according to the AXI bandwidth of each of the four areas in the b-th frame image indicated by the processor 510, thereby reducing the power consumption of the electronic device.

[0290] Alternatively, the processor 510 may indicate the AXI bandwidth of each region corresponding to a frame of image to the DPU before the DPU reads the data of each frame of image from the DDR memory. That is, the processor 510 re-indicates the AXI bandwidth of each of the four regions in the b+j-th frame of image to the DPU. This application does not impose specific limitations on this.

[0291] S617, DPU determines the AXI bandwidth 8 of region 1 of the b+j frame image.

[0292] Among them, AXI bandwidth 8 and AXI bandwidth 4 can be the same.

[0293] It is understandable that the processor 510 can keep the AXI bandwidth 4 stored in the register unchanged, provided that region 1 remains unchanged and AXI bandwidth 8 is the same as AXI bandwidth 4.

[0294] Alternatively, if the AXI bandwidth 8 calculated by the processor 510 is different from the AXI bandwidth 4 stored in the register, the processor 510 can update the AXI bandwidth 4 in the register to the AXI bandwidth 8.

[0295] S618, DPU indicates AXI bandwidth 8 to DDR memory.

[0296] S619, DDR memory is set to frequency point 8 based on AXI bandwidth 8.

[0297] The S620 and DDR memory transmit pixel data 5 of each layer in region 1 to the DPU based on frequency point 8.

[0298] Among them, pixel data 5 can be the data in region 1 corresponding to the b+j frame image.

[0299] Furthermore, similar to S602-S604, in order to ensure that the frequency point 8 set by the DDR memory can meet the requirements of the DPU reading pixel data 5 (data of layers 201 and 202 in region 1 of the b+j frame image) from the DDR memory, the AXI bandwidth allocated to the DPU indicated by the frequency point 8 is greater than or equal to the AXI bandwidth 8. That is, the AXI bandwidth allocated by the DDR memory to the DPU, or actually used to transmit data to the DPU, is greater than or equal to the AXI bandwidth 8.

[0300] In this way, the DDR memory can transmit pixel data 5 of each layer in region 1 to the DPU based on frequency point 8 (that is, a transmission rate greater than or equal to AXI bandwidth 8).

[0301] It is understood that the implementation methods of S617 to S620 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0302] S621, DPU determines the AXI bandwidth 9 of region 2 of the b+j frame image.

[0303] Among them, AXI bandwidth 9 can be the same as AXI bandwidth 5.

[0304] Optionally, when the DPU is about to read the pixel row of region 2 of the b+j frame image, that is, when switching from reading pixel data in region 1 of the b+j frame image to reading pixel data in region 2, it can vote to the DDR memory based on the AXI bandwidth 9 (AXI bandwidth 5) stored in the register.

[0305] S622, DPU indicates AXI bandwidth 9 to DDR memory.

[0306] S623, DDR memory is set to frequency point 9 based on AXI bandwidth 9.

[0307] S624, DDR memory transmits pixel data 6 of each layer in DPU region 2 based on frequency point 9.

[0308] Among them, pixel data 6 can be the data in region 2 of the b+j frame image.

[0309] Furthermore, similar to S601 to S604, in order to ensure that the frequency point 9 of the DDR memory can meet the requirements of the DPU reading pixel data 6 (pixel data of layer 201 in region 2 of the b+j frame image) from the DDR memory, the AXI bandwidth allocated to the DPU indicated by the frequency point 9 is greater than or equal to the AXI bandwidth 9. That is, the AXI bandwidth allocated by the DDR memory to the DPU, or actually used to transmit data to the DPU, is greater than or equal to the AXI bandwidth 9.

[0310] In this way, the DDR memory can transmit the pixel data 6 of each layer in region 2 of the b+j frame image to the DPU based on frequency 9 (that is, a transmission rate greater than or equal to the AXI bandwidth 9).

[0311] It is understood that the implementation methods of S621 to S624 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0312] S625, DPU determines the AXI bandwidth of region 3 of the b+j frame image as 10.

[0313] AXI bandwidth 10 can be the same as AXI bandwidth 6.

[0314] S626, DPU indicates AXI bandwidth 10 to DDR memory.

[0315] S627, DDR memory is set to frequency point 10 based on AXI bandwidth 10.

[0316] The S628 and DDR memory transmit pixel data 7 of each layer in region 3 to the DPU based on frequency point 10.

[0317] Among them, pixel data 7 can be the data in region 3 of the b+j frame image.

[0318] Similarly, when the DPU is about to read the pixel row of region 3 of the b+j frame image, that is, when switching from reading pixel data in region 2 of the b+j frame image to reading pixel data in region 3 of the b+j frame image, the DPU can determine the AXI bandwidth 10 of region 3 based on the AXI bandwidth actually required for the pixel data of each region stored in the register, and the DPU can indicate the AXI bandwidth 10 to the DDR memory.

[0319] In order for the DDR memory frequency setting 10 to meet the requirements of the DPU in retrieving data from the DDR memory (pixel data of layers 201 and 203 in region 3 of the b+j frame image), the AXI bandwidth allocated to the DPU indicated by frequency 10 is greater than or equal to AXI bandwidth 10. That is, the actual data transfer rate allocated by the DDR memory to the DPU, or the AXI bandwidth actually used to transfer data to the DPU, is greater than or equal to AXI bandwidth 10.

[0320] Furthermore, the DDR memory can transmit pixel data 7 of each layer in region 3 of the b+j frame image to the DPU based on frequency 10 (that is, a data transfer rate greater than or equal to AXI bandwidth 10).

[0321] It is understood that the implementation methods of S625 to S628 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0322] S629, DPU determines the AXI bandwidth 11 of region 4 of the image in frame b+j.

[0323] Among them, AXI bandwidth 11 can be the same as AXI bandwidth 7.

[0324] The S630 and DPU indicate AXI bandwidth 11 to the DDR memory.

[0325] S631, DDR memory is set to frequency point 11 based on AXI bandwidth 11.

[0326] S632, DDR memory transmits pixel data 8 of each layer in region 4 to DPU based on frequency point 11.

[0327] Among them, pixel data 8 can be the data in region 4 of the b+j frame image.

[0328] Similarly, when the DPU is about to read the pixel row of region 4 of the b+j frame image, that is, when switching from reading pixel data in region 3 of the b+j frame image to reading pixel data in region 4 of the b+j frame image, the DPU can determine the AXI bandwidth 11 of region 4 based on the AXI bandwidth actually required for the pixel data of each region stored in the register, and the DPU can instruct the DDR memory on the AXI bandwidth 11.

[0329] In order for the DDR memory frequency setting 11 to meet the requirements of the DPU to read pixel data 8 (pixel data of layer 201 in region 4 of the b+j frame image) from the DDR memory, the AXI bandwidth allocated to the DPU indicated by frequency 11 is greater than or equal to AXI bandwidth 11. That is, the actual data transfer rate allocated by the DDR memory to the DPU, or the AXI bandwidth actually used to transfer data to the DPU, is greater than or equal to AXI bandwidth 11.

[0330] Furthermore, the DDR memory can transmit pixel data 8 of each layer in region 4 of the b+j frame image to the DPU based on frequency 11 (that is, a data transmission rate greater than or equal to the AXI bandwidth 11).

[0331] It is understood that the implementation methods of S629 to S632 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0332] For example, when x2 is 100, meaning the DPU needs to read 100 frames of interface data from DDR memory, assuming the processor 510 calculates that the AXI bandwidth corresponding to each region in each display interface is consistent—that is, in the 100 frames, the AXI bandwidth of region 1 is consistent with the AXI bandwidth of region 1 in frame b, the AXI bandwidth of region 2 is consistent with the AXI bandwidth of region 2 in frame b, the AXI bandwidth of region 3 is consistent with the AXI bandwidth of region 3 in frame b, and the AXI bandwidth of region 4 is consistent with the AXI bandwidth of region 4 in frame b—then, during the process of the DPU reading the 100 frames of the interface to be displayed, the processor 510 can indicate the corresponding AXI bandwidth of each region to the DPU once. This reduces the number of communications between the processor 510 and the DPU, lowering computational and communication overhead.

[0333] Furthermore, similar to reading buffers for multiple layers in the b-th frame image, the DPU can also vote based on the AXI bandwidth corresponding to each region in region 1, region 2, region 3, and region 4. In this way, the DDR memory can set its frequency based on the actual transfer rate (AXI bandwidth) required to transmit data in each region, so that the DDR memory does not need to operate at a consistently high frequency, thereby reducing the power consumption of the DDR memory.

[0334] When the amount of data, layer size, or relative position of each layer in the interface to be displayed by the electronic device changes, the area divided by the processor 510 for the interface to be displayed (or the display area of ​​the screen) can change. Specifically, as follows.

[0335] For example, such as Figure 7 As shown in interface (b), assume that the b+x2+1 frame image displayed by the electronic device is the interface of the short video application displaying the video in full screen. That is, compared with the b frame or b+j frame image, the b+x2+1 frame image does not include the status bar layer 101, and the size of the video layer 103 and the short video application layer 102 is consistent with the screen size.

[0336] Compared to the multiple layers included in frames b to b+x2, the number of multiple layers included in frame b+x2+1 is reduced, and the layer size of some of these layers changes. Therefore, the way the processor 510 partitions the frame b+x2+1 may change.

[0337] It is understandable that for the b+x2+1th frame image to be displayed (the interface to be displayed), excluding the status bar layer 101, and with the video layer 103 and the short video application layer 102 having the same size as the display screen, the window thickness of the original regions 1, 2, 3, and 4 in the interface to be displayed in the b+x2+1th frame becomes 2 (all including the video layer 103 and the short video application layer 102). Therefore, the processor 510 may not partition the b+x2+1th frame image, or it can be understood as dividing the b+x2+1th frame image into one region.

[0338] It should be noted that during the operation of an electronic device, the interface displayed on the device is constantly changing. Some interfaces can be divided into multiple regions, for example, based on the image of frame b; other interfaces are similar to the image of frame b+x2+1, i.e., divided into a single region. In other words, as the interface to be displayed on the electronic device changes, the electronic device can dynamically partition the interfaces to adapt to the data transmission requirements of each interface.

[0339] The processor 510 can calculate the AXI bandwidth of the b+x2+1 frame image, i.e., AXI bandwidth 12, based on the entire area of ​​the interface to be displayed, i.e., the area with the same display area size as the display screen: from the first row of pixels to the 2848th row of pixels, and the processor 510 can indicate (stored in a register that the DPU can read) the AXI bandwidth 12 to the DPU.

[0340] S633, DPU determines the AXI bandwidth of frame b+x2+1.

[0341] Here, AXI bandwidth 12 can be the data transfer rate required for the DPU, calculated by processor 510, to read the buffers of all layers in the b+x2+1 frame image from DDR memory. The b+x2+1 frame image can be understood as the next interface displayed after the electronic device displays the b+x2 frame image.

[0342] Alternatively, the AXI bandwidth 12 can also satisfy the formula for calculating D2 above, so the AXI bandwidth 12 can be, for example, 1312×2848×32×120+1312×2848×16×120=21522677760Mbps.

[0343] That is, the bandwidth (data transfer rate) required for the DPU to read each row of pixel data in the b+x2+1 frame image calculated by the processor 510 is 21522677760Mbps.

[0344] S634, DPU indicates AXI bandwidth 12 to DDR memory.

[0345] S635, DDR memory is set to frequency 12 based on AXI bandwidth 12.

[0346] The S636 DDR memory transmits pixel data 9 of each layer of the b+x2+1 frame image (i.e., the area with the same size as the display screen) to the DPU based on frequency point 12.

[0347] Among them, pixel data 9 can be understood as the buffer of all layers included in the b+x2+1 frame image, that is, the buffer of video layer 103 and the buffer of short video application layer 102.

[0348] It should be understood that, in the embodiments of this application, reading the layer's buffer can also be understood as reading the data cached in the layer's buffer from DDR memory, or it can also be understood as reading the data of the layer. This application does not specifically limit this.

[0349] To ensure that the DDR memory frequency setting 12 can meet the requirements of the DPU reading pixel data 9 from the DDR memory, the AXI bandwidth allocated to the DPU by frequency setting 12 is greater than or equal to AXI bandwidth 12. In other words, the actual data transfer rate allocated by the DDR memory to the DPU, or the actual AXI bandwidth used to transfer data to the DPU, is greater than or equal to AXI bandwidth 12. Therefore, the DDR memory can transfer pixel data 9 to the DPU based on frequency setting 12.

[0350] It is understood that the implementation methods of S633 to S636 are similar to those of S601 to S604. For details, please refer to the relevant descriptions of S601 to S604, which will not be repeated here.

[0351] It should be noted that in some possible implementations, Figure 7 The interface (b) can also include a status bar layer 101. In this case, Figure 7 The interface (b) can be divided into two regions, such as region 5 at the top and region 6 at the bottom; region 5 may include a status bar layer 101, a short video application layer 102, and a video layer 103; region 6 may include the short video application layer 102 and the video layer 103. The electronic device can then calculate the AXI bandwidth of region 5 and the AXI bandwidth of region 6; so that the DDR memory can allocate a frequency point for the DPU to read data in region 5 based on the AXI bandwidth of region 5, and can allocate a frequency point for the DPU to read data in region 6 based on the AXI bandwidth of region 6. The implementation of this process is similar to that of S610 to S616, or S617 to S632, and can be referred to the description above, which will not be repeated here.

[0352] It is understandable that when the display area of ​​each layer in the interface to be displayed changes, the processor 510 can repartition the changed display interface based on the number of layers superimposed on each area in the changed interface to be displayed. It can also calculate the actual AXI bandwidth required for the DPU to read the pixel data of each layer in each area of ​​the new partition based on the position of the new partition (the pixel row), as well as the layer size, pixel width and refresh rate of each layer in the new partition, and indicate (stored in the DPU's register) the corresponding AXI bandwidth of each area in the new partition to the DPU.

[0353] In this way, before the DPU reads data from the DDR memory, it can vote on the DDR memory based on the AXI bandwidth of each region in the new partition, so that the DDR memory can set a new frequency point based on the new AXI bandwidth of each region. That is, the processor 510 partitions the memory in real time based on each interface to be displayed, and the DDR memory can set its frequency point based on the AXI bandwidth of each region indicated by the DPU, so that the DDR memory can set its frequency point based on the AXI bandwidth required to transmit data in each region. This prevents the DDR memory frequency point from always being kept at a high level, which helps to reduce the power consumption of the DDR memory.

[0354] It should be noted that, in the embodiments of this application, each frame image can also be understood as a separate interface to be displayed. For example, the b-th frame image to the b+x2+1-th frame image can be understood as x2+1 interfaces to be displayed, and these x2+1 interfaces to be displayed can be x2+1 interfaces displayed consecutively; or, these x2+1 interfaces to be displayed may not be x2+1 interfaces displayed consecutively, for example, the electronic device may display other interfaces between the b+x2+1-th frame image and the b+x2-th frame image. This application does not impose specific limitations in this regard.

[0355] It should be understood that in the above embodiments, the relative size of each step number does not indicate the order in which the steps are executed, but is determined by the internal logic between each step.

[0356] It should be noted that the module names involved in the embodiments of this application can all be defined as other names, as long as they can achieve the function of each module, and no specific restrictions are placed on the module names.

[0357] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0358] The software architecture of the electronic device application in the embodiments of this application will be described below.

[0359] Figure 8 This is a software structure block diagram of the electronic device 500 according to an embodiment of this application.

[0360] A layered architecture divides software into several layers, each with a clear role and function. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.

[0361] The application layer can include a series of application packages.

[0362] like Figure 8 As shown, the application package may include applications such as camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, short video, and desktop.

[0363] Electronic devices can display the interfaces of various applications, and the interfaces displayed by electronic devices can simultaneously include windows of one or more applications.

[0364] For example, such as Figure 1 As shown in interface (a), this interface may include a status bar layer 101, a short video application layer 102, and a video layer 103; or, as shown in the image. Figure 1 As shown in interface (b), the interface may include a status bar layer 104, a capsule layer 105, a wallpaper layer 106, and a desktop launcher layer 107.

[0365] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0366] like Figure 8 As shown, the application framework layer may include a window manager, content provider, view system, phone manager, resource manager, notification manager, etc.

[0367] The window manager is used to manage windowed applications. It can retrieve screen size, determine the presence of a status bar, lock the screen, and capture screenshots, among other things.

[0368] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views. For example, a display interface including a text notification icon could include views for displaying text and views for displaying images.

[0369] The phone manager is used to provide communication functions for electronic devices 500. For example, it manages call status (including connection and disconnection).

[0370] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, video files, and more.

[0371] The notification manager allows applications to display notifications in the status bar. These notifications can be used to convey informational messages and can disappear automatically after a short pause, requiring no user interaction. For example, the notification manager can be used to notify of download completion or message alerts. The notification manager can also display notifications as icons or scrolling text in the system's top status bar, such as notifications from background applications, or as dialog boxes on the screen. Examples include displaying text messages in the status bar, emitting sounds, vibrating electronic devices, and flashing indicator lights. For instance, such as... Figure 1 As shown in interface (b), the notification manager can display notification information in the status bar layer 104 or the capsule layer 105.

[0372] The Android Runtime consists of core libraries and a virtual machine. The Android runtime is responsible for the scheduling and management of the Android system.

[0373] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.

[0374] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0375] System libraries can include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing libraries (e.g., OpenGL ES), 2D graphics engines (e.g., SGL), etc.

[0376] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0377] A 2D graphics engine is a graphics engine for 2D drawing.

[0378] The kernel layer is the layer between hardware and software. The kernel layer may contain, for example, display drivers, camera drivers, audio drivers, sensor drivers, and GPU drivers.

[0379] The GPU driver can pass graphics data generated by the application to the hardware. For example, the GPU driver can write layer data into DDR memory.

[0380] Optionally, in method 600, the interface to be displayed (or the display area of ​​the screen) is partitioned, and the calculation of the AXI bandwidth of each region can be performed by the GPU driver. Furthermore, the GPU driver can also instruct the DPU on the calculated AXI bandwidth of each region.

[0381] Alternatively, the steps of partitioning and calculating the AXI bandwidth of each region can also be performed by other software modules in the operating system, and this application does not specifically limit this.

[0382] The image data processing method according to the embodiments of this application has been described above. The apparatus for performing the above method provided in the embodiments of this application is described below. Those skilled in the art will understand that the methods and apparatus can be combined with and referenced by each other, and the related apparatus provided in the embodiments of this application can perform the steps in the above list sorting method.

[0383] Figure 9 This is a schematic block diagram of an image data processing apparatus 900 provided in an embodiment of this application. The apparatus 900 includes a processor 901, a communication interface 902, and a memory 903. The processor 901, communication interface 902, and memory 903 communicate with each other via internal connection paths. The memory 903 stores instructions, and the processor 901 executes the instructions stored in the memory 903. The communication interface 902 can be used to send signals to other devices (e.g., the processor 901 or a touchscreen of a terminal device) and to receive signals from other devices (e.g., the memory 903). Exemplarily, the communication interface 902 reads instructions stored in the memory 903 and sends the instructions to the processor 901.

[0384] It should be understood that the device 900 may specifically be the terminal device in the above embodiments, and may be used to execute the various steps and / or processes corresponding to the terminal device in the above method embodiments. Optionally, the memory 903 may include read-only memory and random access memory, and provide instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store device type information. The processor 901 may be used to execute instructions stored in the memory, and when the processor 901 executes instructions stored in the memory, the processor 901 is used to execute the various steps and / or processes in the above method embodiments.

[0385] It should be understood that, in the embodiments of this application, the processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0386] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly manifested as execution by a hardware processor, or as a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor executes the instructions in the memory, combining them with its hardware to complete the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0387] The image data processing method provided in this application can be applied to electronic devices with communication functions. The electronic devices include terminal devices, and the specific device form of the terminal devices can be referred to the above-described related descriptions, which will not be repeated here.

[0388] This application provides an electronic device, which includes a processor and a memory; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory, causing the terminal device to perform the above-described method.

[0389] This application provides a chip. The chip includes a processor, which calls a computer program in memory to execute the technical solutions in the above embodiments. Its implementation principle and technical effects are similar to those in the related embodiments described above, and will not be repeated here.

[0390] This application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, it implements the methods described above. The methods described in the above embodiments can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted over the computer-readable medium. The computer-readable medium can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium accessible by a computer.

[0391] In one possible implementation, a computer-readable medium may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage or other magnetic storage devices, or any other medium targeted to carry or to store the required program code in the form of instructions or data structures, and accessible by a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include optical discs, laser discs, optical discs, Digital Versatile Discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0392] This application provides a computer program product, which includes a computer program that, when run, causes a computer to perform the above-described method.

[0393] This application describes embodiments of methods, apparatus (systems), and computer program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable device to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing device, generate instructions for implementing the flowchart illustrations. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0394] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. An image data processing method, characterized in that, Applied to an electronic device including a display screen, the method includes: When the interface to be displayed is the first interface, the display screen is divided into E display areas; in the E display areas, the number of layers used to compose the first interface is different in adjacent display areas; Each of the E display areas is allocated bandwidth adapted to its respective required transmission rate; When the interface to be displayed is the second interface, the display screen is divided into F display areas; the number of layers used to synthesize the second interface is different in adjacent display areas among the F display areas; wherein, E and F are different, and E and F are integers greater than or equal to 1; Each of the F display areas is allocated bandwidth adapted to its respective required transmission rate.

2. The method according to claim 1, characterized in that, Before allocating bandwidth adapted to the respective required transmission rates for each of the E display areas, the method further includes: Based on the refresh rate, the layer size of each layer in the first interface, and the pixel width of each layer in the first interface, calculate the required transmission rate for each of the E display areas.

3. The method according to claim 1 or 2, characterized in that, The E display areas include a first area, which includes y layers from the layers that synthesize the first interface; the required transmission rate for the first area is determined based on the layer size of each of the y layers in the first area, the pixel bit width of each of the y layers, and the refresh rate.

4. The method according to any one of claims 1 to 3, characterized in that, The E display areas include a first area; The method further includes: Based on the bandwidth allocated to the first region, data for the layer used to synthesize the first interface in the first region is obtained.

5. The method according to any one of claims 1 to 4, characterized in that, The electronic device also includes a display processing unit (DPU) and double data rate DDR memory; The allocation of bandwidth to the E display areas, each adapted to its required transmission rate, includes: The electronic device instructs the DPU on the required transmission rate for each of the E display areas; The electronic device instructs the DDR memory, via the DPU, on the required transmission rates for each of the E display areas; The electronic device allocates bandwidth to each of the E display areas via DDR memory, each bandwidth being adapted to its required transmission rate.

6. The method according to claim 5, characterized in that, After allocating bandwidth suitable for the respective required transmission rates to the E display areas, the method further includes: When the interface to be displayed is a third interface, and the layer used to synthesize the first interface is the same as the layer used to synthesize the third interface, the display screen is divided into the E display areas. Before the electronic device obtains the data for compositing the first interface from the DDR memory via the DPU, it instructs the DPU on the required transmission rates for each of the E display areas, and then instructs the DDR memory via the DPU on the required transmission rates for each of the E display areas. The electronic device allocates bandwidth to each of the E display areas via DDR memory, each bandwidth being adapted to its required transmission rate.

7. The method according to claim 5 or 6, characterized in that, The allocation of bandwidth to the F display areas, each adapted to its required transmission rate, includes: The electronic device instructs the DPU on the required transmission rate for each of the F display areas; The electronic device instructs the DDR memory, via the DPU, on the required transmission rates for each of the F display areas; The electronic device allocates bandwidth to each of the F display areas via DDR memory, each bandwidth being adapted to its required transmission rate.

8. The method according to claim 7, characterized in that, The F display areas include a second area; The method further includes: Based on the bandwidth allocated to the second region, the DPU reads data from the DDR memory in the second region for compositing the layer of the second interface.

9. The method according to any one of claims 1 to 8, characterized in that, Each of the E display areas includes one or more complete rows of pixels, and each of the F display areas includes one or more complete rows of pixels.

10. An electronic device, characterized in that, The electronic device includes: one or more processors and memory; The memory is coupled to the one or more processors, the memory being used to store computer program code, the computer program code including computer instructions, the one or more processors invoking the computer instructions to cause the electronic device to perform the method as described in any one of claims 1-9.

11. A chip system, characterized in that, The chip system is applied to an electronic device, the chip system including one or more processors, the one or more processors being used to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method as described in any one of claims 1-9.

13. A computer program product, characterized in that, The computer program product includes computer program code that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1-9.

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