Memory area management method and device, electronic equipment and medium
By receiving memory region requests through the memory access system, obtaining table information, and determining the physical address using a preset memory translation table, the problem of limited access speed of RDMA network cards is solved, and the performance of the memory access system is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA TELECOM CLOUD TECH CO LTD
- Filing Date
- 2025-12-03
- Publication Date
- 2026-04-21
AI Technical Summary
When an RDMA network card reads the physical address from the memory translation table of the host memory through the PCIe bus, the access speed is limited, affecting the overall performance of the data plane.
The memory access system receives memory region requests, obtains the table information of the memory region table, determines the input parameters based on the starting virtual address and the virtual address, and uses a preset memory translation table to determine the physical address, reducing direct interaction with slow storage interfaces.
By quickly determining the physical address, the number of interactions between the memory access system and the slow storage interface is reduced, thereby improving the performance of the memory access system.
Smart Images
Figure CN121901124A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a memory region management method, a memory region management device, an electronic device, and a readable storage medium. Background Technology
[0002] Remote Direct Memory Access (RDMA) is a technology that allows computers to directly access remote host memory, bypassing the operating system kernel to significantly improve data transfer speed and efficiency. RDMA is widely used in high-performance computing, data centers, distributed storage systems, and low-latency network communication. In these applications, efficient host memory region management is a key technical aspect for achieving zero-copy data transfer in RDMA. Through memory region (MR) registration and management mechanisms, RDMA network cards can directly access user-space memory. However, when reading the physical address corresponding to a memory region, related technologies typically involve the RDMA network card reading the physical address from the host memory's memory translation table (MTT) via the PCIe (Peripheral Component Interconnect Express) bus. This method limits the speed of physical address access, thus impacting the overall performance of the RDMA data plane. Summary of the Invention
[0003] In view of the above problems, embodiments of the present invention are proposed to provide a memory region management method, a memory region management device, an electronic device, and a readable storage medium that overcome or at least partially solve the above problems.
[0004] In a first aspect, embodiments of the present invention provide a memory region management method, the method being applied to a memory access system, the method comprising: Receive memory region requests; Obtain the table information of the memory region table corresponding to the memory region request; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region; Based on the starting virtual address of the memory region and the virtual address requested by the memory region, determine the input parameters corresponding to the memory region request; Based on the input parameters and the preset memory translation table, the physical address corresponding to the memory region request is determined, and data transmission is performed based on the memory region corresponding to the physical address.
[0005] Optionally, determining the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the requested virtual address of the memory region includes: Based on the memory region request and the table information, determine whether the memory region request is valid; If the memory region request is valid, then the input parameters corresponding to the memory region request are determined based on the starting virtual address of the memory region and the virtual address of the memory region request.
[0006] Optionally, the memory region request further includes: a first protection domain identifier and an operation type; the table information includes: a second protection domain identifier and a permission field; determining whether the memory region request is valid based on the memory region request and the table information includes: Determine whether the first protection domain identifier field is consistent with the second protection domain identifier; If the first protection domain identifier is consistent with the second protection domain identifier, then the protection domain verification of the memory region request is determined to be successful; If the protection domain verification of the memory region request passes, then determine whether the field of the operation type is within the scope of the permission field; If the field of the operation type is within the range of the permission field, then the permission verification for the memory region request is deemed successful. If the permission verification of the memory region request passes, then the validity of the memory region request is determined based on the virtual address of the memory region request and the starting virtual address of the memory region.
[0007] Optionally, the memory region request further includes: a request length; the table information further includes: the length of the memory region table; determining whether the memory region request is valid based on the virtual address of the memory region request and the starting virtual address of the memory region includes: Verify whether the sum of the requested virtual address of the memory region and the requested length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; If the sum of the virtual address requested for the memory region and the length of the request is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then the virtual address after offset correction is determined, and the validity of the memory region request is determined based on the virtual address after offset correction.
[0008] Optionally, the table information further includes: page size; determining the virtual address after offset correction, and determining whether the memory region request is valid based on the virtual address after offset correction, includes: Based on the starting virtual address of the memory region, the requested virtual address of the memory region, and the page size, determine the virtual address after offset correction; Based on the corrected offset virtual address, determine whether the memory region request is valid.
[0009] Optionally, determining whether the memory region request is valid based on the corrected virtual address includes: Determine whether the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; If the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then the memory region request is determined to be valid.
[0010] Optionally, the table information further includes: page size; the step of determining the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the requested virtual address of the memory region includes: The page index is determined based on the requested virtual address of the memory region, the starting virtual address of the memory region, and the page size; Page entry blocks are determined based on the page index, and input parameters corresponding to the memory region request are determined based on the base address of the page entry blocks and the page index.
[0011] Optionally, the input parameters include: segment label and page index; determining the physical address corresponding to the memory region request based on the input parameters and a preset memory translation table includes: Determine whether a corresponding preset memory translation table exists based on the segment label and the page index; If a corresponding preset memory translation table exists, the physical address corresponding to the memory region request is determined based on the input parameters.
[0012] Optionally, the input parameters further include: the base address and block size of the page entry block; determining the physical address corresponding to the memory region request based on the input parameters includes: Based on the base address of the page entry block, the page index, and the block size, the physical address corresponding to the memory region request is determined.
[0013] Optionally, performing data transfer based on the memory region corresponding to the physical address includes: Determine the operation permissions corresponding to the physical address, and perform data transmission based on the operation permissions and the memory region corresponding to the physical address.
[0014] Optionally, the method further includes: If the memory access system operates in linear processing mode, then based on the table information of the memory region table and the memory region request, the physical address corresponding to the memory region request is determined, and data transmission is performed based on the memory region corresponding to the physical address.
[0015] Optionally, the table information further includes: the base address of the memory region table; determining the physical address corresponding to the memory region request based on the table information of the memory region table and the memory region request includes: Based on the virtual address of the memory region request, the base address of the memory region table, and the starting virtual address of the memory region, the physical address corresponding to the memory region request is determined.
[0016] In a second aspect, embodiments of the present invention provide a memory region management device, the device being applied to a memory access system, the device comprising: The receiving module is used to receive memory region requests; The acquisition module is used to acquire table information of the memory region table corresponding to the memory region request; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region; The first determining module is used to determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address requested by the memory region. The second determining module is used to determine the physical address corresponding to the memory region request based on the input parameters and a preset memory translation table, and to perform data transmission based on the memory region corresponding to the physical address.
[0017] Optionally, the first determining module includes: The first determining submodule is used to determine whether the memory region request is valid based on the memory region request and the table information; The second determining submodule is used to determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request if the memory region request is valid.
[0018] Optionally, the memory region request further includes: a first protection domain identifier and an operation type; the table information includes: a second protection domain identifier and a permission field; the first determining submodule includes: The first determining unit is used to determine whether the first protection domain identifier and the second protection domain identifier are consistent; The second determining unit is configured to determine that the protection domain verification of the memory region request is successful if the first protection domain identifier field is consistent with the second protection domain identifier. The third determining unit is used to determine whether the field of the operation type is within the scope of the permission field if the protection domain verification of the memory region request passes. The fourth determining unit is configured to determine that the permission verification for the memory region request is successful if the field of the operation type is within the range of the permission field. The fifth determining unit is used to determine whether the memory region request is legitimate based on the virtual address of the memory region request and the starting virtual address of the memory region if the permission verification of the memory region request passes.
[0019] Optionally, the memory region request further includes: a request length; the table information further includes: the length of the memory region table; the fifth determining unit includes: The verification subunit is used to verify whether the sum of the virtual address requested by the memory region and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; A determining subunit is configured to determine the corrected virtual address if the sum of the requested virtual address of the memory region and the requested length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, and to determine whether the memory region request is valid based on the corrected virtual address.
[0020] Optionally, the table information further includes: page size; the determining sub-unit includes: The determining subunit is configured to determine the corrected virtual address based on the starting virtual address of the memory region, the virtual address requested by the memory region, and the page size; and to determine whether the memory region request is valid based on the corrected virtual address.
[0021] Optionally, the determining subunit includes: The determining subunit is used to determine whether the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; if the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then the memory region request is determined to be valid.
[0022] Optionally, the table information further includes: page size; the first determining module includes: The third determining submodule is used to determine the page index based on the virtual address requested by the memory region, the starting virtual address of the memory region, and the page size; The fourth determining submodule is used to determine page entry blocks based on the page index, and to determine the input parameters corresponding to the memory region request based on the base address of the page entry block and the page index.
[0023] Optionally, the input parameters include: segment label and page index; the second determining module includes: The fifth determining submodule is used to determine whether a corresponding preset memory translation table exists based on the segment label and the page index; The sixth determining submodule is used to determine the physical address corresponding to the memory region request based on the input parameters if a corresponding preset memory translation table exists.
[0024] Optionally, the input parameters also include: the base address and block size of the page entry block; the sixth determining submodule includes: The seventh determination submodule is used to determine the physical address corresponding to the memory region request based on the base address of the page entry block, the page index, and the block size.
[0025] Optionally, the second determining module includes: The eighth determination submodule is used to determine the operation permission corresponding to the physical address, and to perform data transmission based on the operation permission and the memory region corresponding to the physical address.
[0026] Optionally, the device further includes: The third determining module is used to determine the physical address corresponding to the memory region request based on the table information of the memory region table and the memory region request if the mode of the memory access system is linear processing mode, and to perform data transmission based on the memory region corresponding to the physical address.
[0027] Optionally, the table information further includes: the base address of the memory region table; the third determining module includes: The ninth determining submodule is used to determine the physical address corresponding to the memory region request based on the virtual address of the memory region request, the base address of the memory region table, and the starting virtual address of the memory region.
[0028] Thirdly, embodiments of the present invention provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the memory region management method as described in the first aspect.
[0029] Fourthly, embodiments of the present invention provide a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, the steps of the memory region management method as described in the first aspect are implemented.
[0030] The embodiments of the present invention have the following advantages: In this embodiment of the invention, the memory access system first receives a memory region request, then obtains the table information of the memory region table corresponding to the memory region request. The memory region request includes the virtual address of the requested memory region; the table information includes the starting virtual address of the memory region. Based on the starting virtual address and the virtual address of the requested memory region, input parameters corresponding to the memory region request are determined. Finally, based on the input parameters and a preset memory translation table, the physical address corresponding to the memory region request is determined, and data transmission is performed based on the memory region corresponding to the physical address. Thus, by setting up the memory region table and memory translation table in the memory access system, the system can quickly determine the physical address, reducing the number of direct interactions between the memory access system and the slow storage interface, thereby improving the performance of the memory access system. Attached Figure Description
[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a flowchart illustrating the steps of a memory region management method provided in an embodiment of the present invention; Figure 2 This is a structural block diagram of a memory access system provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a memory region management device provided in an embodiment of the present invention. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0035] In related technologies, RDMA network cards read physical addresses from the host memory's memory translation table via the PCIe bus. However, this method limits the access speed of physical addresses, thus affecting the overall performance of the RDMA data plane. To address this technical problem, this invention discloses a memory region management method. The core concept is that the memory access system first receives a memory region request, then obtains the table information of the memory region table corresponding to the request. The memory region request includes the virtual address of the requested memory region; the table information includes the starting virtual address of the memory region. Based on the starting virtual address and the virtual address of the requested memory region, input parameters corresponding to the memory region request are determined. Finally, based on the input parameters and a preset memory translation table, the physical address corresponding to the memory region request is determined, and data transmission is performed based on the memory region corresponding to the physical address. Thus, by setting up the memory region table and memory translation table in the memory access system, the system can quickly determine the physical address, reducing the number of direct interactions between the memory access system and slow storage interfaces, thereby improving the performance of the memory access system.
[0036] like Figure 1 The diagram illustrates a flowchart of a memory region management method according to an embodiment of the present invention. The method is applied to a memory access system and may specifically include the following steps: Step 101: Receive memory region request.
[0037] In this embodiment of the invention, the memory access system can be an RDMA system, and the memory access system can include a memory protection check module and an address translation module, wherein the memory protection check module can be an MPC (Memory Protection Check) module, and the address translation module can be an ATU (Address Translate Unit) module. The memory access system can receive memory region requests, wherein the memory region requests can be received by the MPC module in the memory access system from memory region requests sent by other modules in the memory access system.
[0038] Step 102: Obtain the table information of the memory region table corresponding to the memory region request; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region.
[0039] In this invention, after the MPC module in the memory access system obtains a memory region request, the MPC module can obtain the memory region table corresponding to the memory region request and the table information corresponding to the memory region table. The memory region request may include the virtual address of the memory region request. The table information of the memory region table may include the starting virtual address of the memory region. In this invention, the memory region table can be an MR memory region entry (MRE).
[0040] In this invention, the memory access system may further include a cache module. The memory region table can be pre-stored in the cache module. The MPC module can retrieve the corresponding memory region table from the cache module based on the memory region request, thereby obtaining the table information corresponding to the memory region table. In this invention, the memory region request may include information such as a memory region tag, the virtual address of the memory region request, the operation type, the request length, the protection domain identifier, and the internal key. The memory region tag can be a STAG (Segment Tag), the virtual address of the memory region request can be a VA (Virtual Address), the operation type can be an opcode, the request length can be a length, the first protection domain identifier can be a first pd_id, and the internal key can be a driver_key.
[0041] In this invention, after the MPC module receives a memory region request, it can query the MPC cache using STAG to check if a corresponding memory region table exists. During the check, STAG[23:0] can be used as the cache index and tag. The four-way cache is retrieved via tag_ram to check for a hit (set_valid=1 and / pd_id matches). If a hit occurs, the memory region table corresponding to the memory region request can be obtained, along with its corresponding table information. This table information may include a second protection domain identifier, permission fields, the length of the memory region table, the page table mode, the base address of the memory region table, and the page size. The second protection domain identifier can be the second pd_id, the permission field can be access, the length of the memory region table can be mre_length, the base address of the memory region table can be mre_lpbl0~3, and the page size can be page_size.
[0042] In this invention, if the MPC module fails to obtain the memory region table corresponding to the memory region request, it can add the STAG to the DDR (Double Data Rate) request queue, update the tag_ram in the MPC cache (set set_valid=1, write driver_key / pd_id), and then the MPC module can send a load request to DDR. After DDR returns the MRE, the module loads the complete MRE entry from DDR into the cache. If the cache is full, the old entry can be replaced according to the PLRU policy, and dirty data is written back to DDR. After waiting for the DDR response, the cache is updated, and the table information of the memory region table corresponding to the memory region request is retrieved again.
[0043] Step 103: Determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request.
[0044] In this invention, after the MPC module obtains the table information of the memory region table corresponding to the memory region request, the MPC module can determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request.
[0045] In one embodiment, determining the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request may include: determining whether the memory region request is valid based on the memory region request and table information; if the memory region request is valid, then determining the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request.
[0046] In this invention, the MPC module first determines whether the memory region request is valid. Only if the memory region request is valid will it determine the corresponding input parameters. Thus, by verifying the memory region request through the MPC module, the validity of the memory region request is guaranteed.
[0047] In one embodiment, the memory region request further includes: a first protection domain identifier and an operation type; the table information includes: a second protection domain identifier and a permission field; based on the memory region request and the table information, determining whether the memory region request is valid includes: determining whether the first protection domain identifier field and the second protection domain identifier are consistent; if the first protection domain identifier field and the second protection domain identifier are consistent, then the protection domain verification of the memory region request is confirmed to be successful; if the protection domain verification of the memory region request is successful, then the operation type field is determined to be within the scope of the permission field; if the operation type field is within the scope of the permission field, then the permission verification of the memory region request is confirmed to be successful; if the permission verification of the memory region request is successful, then based on the virtual address of the memory region request and the starting virtual address of the memory region, determining whether the memory region request is valid is determined to be valid.
[0048] In this invention, when determining whether a memory region request is valid, the MPC module can first determine whether the first protection domain identifier in the memory region request is consistent with the second protection domain identifier in the table information. If the first protection domain identifier is inconsistent with the second protection domain identifier, it means that the protection domain verification of the memory region request has failed. At this time, the error "Protection Domain Mismatch" can be returned.
[0049] If the first protection domain identifier matches the second protection domain identifier, the protection domain verification for the memory region request is successful. At this point, the permissions for the memory region request can be verified. When verifying the permissions for the memory region request, it can be checked whether the operation type field is within the scope of the permission fields. If the operation type field is not within the scope of the permission fields, the permission verification for the memory region request is unsuccessful, and the error "Access Permission Denied" can be returned.
[0050] If the operation type field is within the scope of the permission field, it means that the permission verification for the memory region request has passed. At this point, the legality of the memory region request can be verified. Verification of the legality of a memory region request can be based on the virtual address of the requested memory region and the starting virtual address of the memory region.
[0051] In one embodiment, the memory region request further includes: a request length; the table information may also include: the length of the memory region table; determining whether the memory region request is valid based on the virtual address of the memory region request and the starting virtual address of the memory region includes: verifying whether the sum of the virtual address of the memory region request and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; if the sum of the virtual address of the memory region request and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then determining the virtual address after offset correction, and determining whether the memory region request is valid based on the virtual address after offset correction.
[0052] In this invention, when verifying the validity of a memory region request, we can first determine whether `req_va + length ≤ mre_vato + mre_length` holds true, where `req_va` is the virtual address of the memory region request, `length` is the request length, `mre_vato` is the starting virtual address of the memory region, and `mre_length` is the length of the memory region table. If true, we can further determine the virtual address after offset correction, and then determine the validity of the memory region request based on the virtual address after offset correction.
[0053] In one embodiment, the table information may further include: page size; determining the virtual address after offset correction, and determining whether the memory region request is valid based on the virtual address after offset correction, including: determining the virtual address after offset correction based on the starting virtual address of the memory region, the virtual address of the memory region request, and the page size; and determining whether the memory region request is valid based on the virtual address after offset correction.
[0054] In this invention, the adjusted virtual address can be calculated using the formula: adjusted_start_va = mre_vato + (req_va - mre_vato) % page_size. Here, adjusted_start_va is the adjusted virtual address, mre_vato is the starting virtual address of the memory region, req_va is the virtual address of the requested memory region, and page_size is the page size. After calculating the adjusted virtual address, the validity of the memory region request can be determined based on this address.
[0055] In one embodiment, determining whether a memory region request is valid based on the corrected virtual address includes: determining whether the sum of the corrected virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; if the sum of the corrected virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then the memory region request is determined to be valid.
[0056] In this invention, when determining whether a memory region request is valid, it can be checked whether `adjusted_start_va + length ≤ mre_vato + mre_length` holds true, where `adjusted_start_va` is the virtual address after offset correction, `length` is the request length, `mre_vato` is the starting virtual address of the memory region, and `mre_length` is the length of the memory region table. If true, the memory region request is valid; if false, the memory region request is invalid, and an error "Address Out of Range" can be returned. In this invention, a valid memory region request also indicates the requested length of the memory region request, i.e., the memory length, which can be accommodated in the current memory space.
[0057] In one embodiment, the table information may further include: page size; determining input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request, including: determining and calculating the page index based on the virtual address of the memory region request, the starting virtual address of the memory region, and the page size; determining page entry blocks based on the page index, and determining the input parameters corresponding to the memory region request based on the base address of the page entry blocks and the page index.
[0058] In this invention, the page table mode can include: linear processing mode and virtual address processing mode. That is, the MPC module in RDMA can be in linear processing mode and virtual address processing mode. If the MPC module is in virtual address processing mode, the page index can be calculated according to the formula: page_index=(req_va-mre_vatoMR) / page_size, where page_index is the page index, req_va is the virtual address requested for the memory region, mre_vato is the starting virtual address of the memory region, and page_size is the page size.
[0059] Then, page entry blocks are determined based on the page index, and the input parameters corresponding to the memory region request are determined based on the base address of the page entry block and the page index. In this invention, PBLE (Page-Based Linear Entry) blocks (lpbl0~3) and their corresponding base addresses can be determined according to page_index and leaf_size. PBLE blocks can also refer to page entry blocks. For example, when leaf_size = 4KB, each block has 512 entries, and the block number = page_index / 512. The base address leaf_base = mre_lpbl[block number]. leaf_size is the block size.
[0060] In this invention, physical addresses are distributed across four memory regions, denoted by lpbl0, lpbl1, lpbl2, and lpbl3, and these addresses are stored in the MRE. The size of each memory block is determined by leaf_size: when leaf_size is 4KB, each block stores 512 physical addresses; when leaf_size is 64KB, each block stores 8K physical addresses; when leaf_size is 512KB, each block stores 64K physical addresses; and when leaf_size is 2MB, each block stores 256K physical addresses. These physical addresses are arranged according to page_index, and the total maximum supported memory region length is 4*(leaf_size / 8)*page_size.
[0061] The input parameters in this invention may include: segment label, virtual address after offset correction, page size, base address of page entry block and block size, etc., wherein the segment label is STAG, the virtual address after offset correction is adjusted_start_va, the page size is page_size, the base address of page entry block is leaf_base, and the block size is leaf_size.
[0062] In one embodiment, the memory region management method may further include: if the memory access system is in a linear processing mode, determining the physical address corresponding to the memory region request based on the table information of the memory region table and the memory region request, and performing data transmission based on the memory region corresponding to the physical address.
[0063] In this invention, the page table mode can include: linear processing mode and virtual address processing mode. That is, the MPC module in RDMA can be in linear processing mode and virtual address processing mode. If the MPC module is in linear processing mode, it can determine the physical address corresponding to the memory region request based on the table information of the memory region table and the memory region request, and then return the physical address to the requesting party that sent the memory region request. The requesting party can then perform data transmission based on the memory region corresponding to the physical address.
[0064] In one embodiment, the table information further includes: the base address of the memory region table; determining the physical address corresponding to the memory region request based on the table information of the memory region table and the memory region request may include: determining the physical address corresponding to the memory region request based on the virtual address of the memory region request, the base address of the memory region table and the starting virtual address of the memory region.
[0065] In this invention, the memory access system operates in a linear processing mode. When the MPC module operates in linear processing mode, the physical address corresponding to the memory region request can be calculated using the formula: PA = mre_lpbl0 + mre_soffset + (req_va - mre_vato), where PA is the physical address corresponding to the memory region request, mre_lpbl0 is the base address of the memory region table, mre_soffset is the memory start offset address preset by the RDMA system, req_va is the virtual address of the memory region request, and mre_vato is the starting virtual address of the memory region.
[0066] Step 104: Determine the physical address corresponding to the memory region request based on the input parameters and the preset memory translation table, and perform data transmission based on the memory region corresponding to the physical address.
[0067] In this invention, after the MPC module determines the input parameters corresponding to the memory region request, the ATU module can receive the input parameters from the MPC module. Then, the ATU module can determine the physical address corresponding to the memory region request based on the input parameters and a preset memory translation table. The RDMA system can then perform data transmission based on the memory region corresponding to the physical address. In this invention, the memory translation table can be an MTT (Memory Translation Table), which can be pre-stored or backed up in the cache module. The ATU module can obtain the MTT from the cache module.
[0068] In one embodiment, the input parameters include: segment label and page index; determining the physical address corresponding to the memory region request based on the input parameters and a preset memory translation table includes: determining whether a corresponding preset memory translation table exists based on the segment label and page index; if a corresponding preset memory translation table exists, then determining the physical address corresponding to the memory region request based on the input parameters.
[0069] In this invention, the ATU module can use STAG+page_index as a cache tag to check if there is a corresponding MTT in the cache module. If there is a corresponding MTT, the physical address corresponding to the memory region request can be determined based on the input parameters.
[0070] If a corresponding MTT does not exist, four consecutive MTT entries (including the current page index) can be prefetched from Host Memory via PCIe. This triggers Host prefetching. Each time the ATU module prefetches four MTT entries, it calculates the physical addresses of subsequent page_index+1 to +3, reducing the cache miss rate for subsequent requests. These are then loaded into the MTT cache, the cache is updated, and marked as valid (set_valid=1). The PLRU algorithm is used to replace the least used path. Finally, it checks whether a corresponding pre-defined memory translation table exists.
[0071] In one embodiment, the input parameters further include: the base address and block size of the page entry block; determining the physical address corresponding to the memory region request based on the input parameters may include: determining the physical address corresponding to the memory region request based on the base address, page index and block size of the page entry block.
[0072] In this invention, when determining the physical address, the ATU module can calculate the physical address using the formula: PA = leaf_base + (page_index % entries_per_leaf, where PA is the physical address corresponding to the memory request, leaf_base is the base address of the page entry block, page_index is the index page, and entries_per_leaf is the block size, which also represents the number of MTT addresses stored under the block.
[0073] In one embodiment, performing data transmission based on the memory region corresponding to the physical address may include: determining the operation permission corresponding to the physical address, and performing data transmission based on the operation permission and the memory region corresponding to the physical address.
[0074] In this invention, after the ATU module determines the PA, it can further obtain the operation permissions corresponding to the physical address and pass the physical address and operation permissions to the requester of the memory region request. The requester then performs data transmission based on the operation permissions and the memory region corresponding to the physical address. In this invention, the ATU module can also pass the physical address and operation permissions to the DMA (Direct Memory Access) engine to execute data transmission.
[0075] In this embodiment of the invention, the MPC module and the ATU module can also perform invalidation request processing. After receiving an invalidation request, the MPC module queries the cache and marks the corresponding MRE as invalid, and synchronously invalidates the cache of the ATU module. The MPC module sends a STAG invalidation signal to the ATU module, and the ATU clears all associated MTT cache entries.
[0076] In this embodiment of the invention, if any check fails, the MPC module or ATU module returns an error code (such as permission error or address out of bounds) to the requesting party, terminating the process.
[0077] like Figure 2 The diagram illustrates a structural block diagram of a memory access system provided by an embodiment of the present invention. The memory access system may include an MPC module, an ATU module, a cache module, DDR memory, and a Host PCIe. When the MPC module receives a memory region request from another module in the memory access system, it performs relevant permission and legality checks. During these checks, it needs to obtain a memory region table. The original content of the memory region table is stored in DDR memory. Since DDR read / write operations are time-consuming, this invention, to speed up the process, stores a backup in the cache module. The MPC module can then quickly read the memory region table from the cache module. After the MPC module passes the checks, it sends the input parameters to the ATU module. The ATU module can obtain a memory translation table to determine the physical address. The original content of the memory translation table needs to be read from the host side via PCIe. Since PCIe read operations are time-consuming, this invention, to speed up the process, stores a backup in the cache module. The ATU module can then quickly read the memory translation table from the cache module.
[0078] In this embodiment of the invention, a memory region request is received; table information of the memory region table corresponding to the memory region request is obtained; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region; input parameters corresponding to the memory region request are determined based on the starting virtual address of the memory region and the virtual address of the memory region request; the physical address corresponding to the memory region request is determined based on the input parameters and a preset memory translation table, and data transmission is performed based on the memory region corresponding to the physical address. Thus, by setting the memory region table and memory translation table in the memory access system, the memory access system can quickly determine the physical address based on the memory region table and memory translation table, reducing the number of direct interactions between the memory access system and the slow storage interface, thereby improving the performance of the memory access system.
[0079] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.
[0080] like Figure 3 As shown in the diagram, an embodiment of the present invention provides a structural block diagram of a memory region management device. The device is applied to a memory access system and may specifically include the following modules: Receiver module 301 is used to receive memory region requests; The acquisition module 302 is used to acquire table information of the memory region table corresponding to the memory region request; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region; The first determining module 303 is used to determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address requested by the memory region. The second determining module 304 is used to determine the physical address corresponding to the memory region request based on the input parameters and the preset memory translation table, and to perform data transmission based on the memory region corresponding to the physical address.
[0081] In one embodiment, the first determining module 303 includes: The first determining submodule is used to determine whether the memory region request is valid based on the memory region request and the table information; The second determining submodule is used to determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request if the memory region request is valid.
[0082] In one embodiment, the memory region request further includes: a first protection domain identifier and an operation type; the table information includes: a second protection domain identifier and a permission field; the first determining submodule includes: The first determining unit is used to determine whether the first protection domain identifier and the second protection domain identifier are consistent; The second determining unit is configured to determine that the protection domain verification of the memory region request is successful if the first protection domain identifier field is consistent with the second protection domain identifier. The third determining unit is used to determine whether the field of the operation type is within the scope of the permission field if the protection domain verification of the memory region request passes. The fourth determining unit is configured to determine that the permission verification for the memory region request is successful if the field of the operation type is within the range of the permission field. The fifth determining unit is used to determine whether the memory region request is legitimate based on the virtual address of the memory region request and the starting virtual address of the memory region if the permission verification of the memory region request passes.
[0083] In one embodiment, the memory region request further includes: a request length; the table information further includes: the length of the memory region table; the fifth determining unit includes: The verification subunit is used to verify whether the sum of the virtual address requested by the memory region and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; A determining subunit is configured to determine the corrected virtual address if the sum of the requested virtual address of the memory region and the requested length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, and to determine whether the memory region request is valid based on the corrected virtual address.
[0084] In one embodiment, the table information further includes: page size; the determining subunit includes: The determining subunit is configured to determine the corrected virtual address based on the starting virtual address of the memory region, the virtual address requested by the memory region, and the page size; and to determine whether the memory region request is valid based on the corrected virtual address.
[0085] In one embodiment, the determining subunit includes: The determining subunit is used to determine whether the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; if the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then the memory region request is determined to be valid.
[0086] In one embodiment, the table information further includes: page size; the first determining module 303 includes: The third determining submodule is used to determine the page index based on the virtual address requested by the memory region, the starting virtual address of the memory region, and the page size; The fourth determining submodule is used to determine page entry blocks based on the page index, and to determine the input parameters corresponding to the memory region request based on the base address of the page entry block and the page index.
[0087] In one embodiment, the input parameters include: segment labels and page indexes; the second determining module 304 includes: The fifth determining submodule is used to determine whether a corresponding preset memory translation table exists based on the segment label and the page index; The sixth determining submodule is used to determine the physical address corresponding to the memory region request based on the input parameters if a corresponding preset memory translation table exists.
[0088] In one embodiment, the input parameters further include: the base address and block size of the page entry block; the sixth determining submodule includes: The seventh determination submodule is used to determine the physical address corresponding to the memory region request based on the base address of the page entry block, the page index, and the block size.
[0089] In one embodiment, the second determining module 304 includes: The eighth determination submodule is used to determine the operation permission corresponding to the physical address, and to perform data transmission based on the operation permission and the memory region corresponding to the physical address.
[0090] In one embodiment, the device further includes: The third determining module is used to determine the physical address corresponding to the memory region request based on the table information of the memory region table and the memory region request if the mode of the memory access system is linear processing mode, and to perform data transmission based on the memory region corresponding to the physical address.
[0091] In one embodiment, the table information further includes: the base address of the memory region table; the third determining module includes: The ninth determining submodule is used to determine the physical address corresponding to the memory region request based on the virtual address of the memory region request, the base address of the memory region table, and the starting virtual address of the memory region.
[0092] In this embodiment of the invention, a receiving module is used to receive a memory region request; an obtaining module is used to obtain table information of a memory region table corresponding to the memory region request; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region; a first determining module is used to determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address of the memory region request; a second determining module is used to determine the physical address corresponding to the memory region request based on the input parameters and a preset memory translation table, and perform data transmission based on the memory region corresponding to the physical address. Thus, by setting up the memory region table and memory translation table in the memory access system, the memory access system can quickly determine the physical address based on the memory region table and memory translation table, reducing the number of direct interactions between the memory access system and the slow storage interface, thereby improving the performance of the memory access system.
[0093] As the apparatus embodiment is basically similar to the method embodiment, it is described in a relatively simple manner. For relevant details, please refer to the description of the method embodiment.
[0094] This invention also provides an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor. When the program or instructions are executed by the processor, they implement the various processes of the above-described memory region management method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.
[0095] This invention also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described memory region management method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.
[0096] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.
[0097] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0098] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0099] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0102] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.
[0103] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0104] The present invention has provided a detailed description of a memory region management method, a memory region management device, an electronic device, and a readable storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A memory region management method, characterized in that, The method is applied to a memory access system, and the method includes: Receive memory region requests; Obtain the table information of the memory region table corresponding to the memory region request; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region; Based on the starting virtual address of the memory region and the virtual address requested by the memory region, determine the input parameters corresponding to the memory region request; Based on the input parameters and the preset memory translation table, the physical address corresponding to the memory region request is determined, and data transmission is performed based on the memory region corresponding to the physical address.
2. The memory region management method according to claim 1, characterized in that, The step of determining the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the requested virtual address of the memory region includes: Based on the memory region request and the table information, determine whether the memory region request is valid; If the memory region request is valid, then the input parameters corresponding to the memory region request are determined based on the starting virtual address of the memory region and the virtual address of the memory region request.
3. The memory region management method according to claim 2, characterized in that, The memory region request further includes: a first protection domain identifier and an operation type; the table information includes: a second protection domain identifier and a permission field; determining whether the memory region request is valid based on the memory region request and the table information includes: Determine whether the first protection domain identifier field is consistent with the second protection domain identifier; If the first protection domain identifier is consistent with the second protection domain identifier, then the protection domain verification of the memory region request is determined to be successful. If the protection domain verification of the memory region request passes, then determine whether the field of the operation type is within the scope of the permission field; If the field of the operation type is within the range of the permission field, then the permission verification for the memory region request is deemed successful. If the permission verification of the memory region request passes, then the validity of the memory region request is determined based on the virtual address of the memory region request and the starting virtual address of the memory region.
4. The memory region management method according to claim 3, characterized in that, The memory region request further includes: a request length; the table information further includes: the length of the memory region table; determining whether the memory region request is valid based on the virtual address of the memory region request and the starting virtual address of the memory region includes: Verify whether the sum of the requested virtual address of the memory region and the requested length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; If the sum of the virtual address requested for the memory region and the length of the request is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then the virtual address after offset correction is determined, and the validity of the memory region request is determined based on the virtual address after offset correction.
5. The memory region management method according to claim 4, characterized in that, The table information also includes: page size; determining the corrected virtual address and, based on the corrected virtual address, determining whether the memory region request is valid includes: Based on the starting virtual address of the memory region, the requested virtual address of the memory region, and the page size, determine the virtual address after offset correction; Based on the corrected offset virtual address, determine whether the memory region request is valid.
6. The memory region management method according to claim 5, characterized in that, The step of determining whether the memory region request is valid based on the corrected offset virtual address includes: Determine whether the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table; If the sum of the corrected offset virtual address and the request length is less than or equal to the sum of the starting virtual address of the memory region and the length of the memory region table, then the memory region request is determined to be valid.
7. The memory region management method according to claim 1, characterized in that, The table information also includes: page size; the step of determining the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the requested virtual address of the memory region includes: The page index is determined based on the requested virtual address of the memory region, the starting virtual address of the memory region, and the page size; Page entry blocks are determined based on the page index, and input parameters corresponding to the memory region request are determined based on the base address of the page entry blocks and the page index.
8. The memory region management method according to claim 1, characterized in that, The input parameters include: segment label and page index; determining the physical address corresponding to the memory region request based on the input parameters and a preset memory translation table includes: Determine whether a corresponding preset memory translation table exists based on the segment label and the page index; If a corresponding preset memory translation table exists, the physical address corresponding to the memory region request is determined based on the input parameters.
9. The memory region management method according to claim 8, characterized in that, The input parameters also include: the base address and block size of the page entry block; determining the physical address corresponding to the memory region request based on the input parameters includes: Based on the base address of the page entry block, the page index, and the block size, the physical address corresponding to the memory region request is determined.
10. The memory region management method according to claim 1, characterized in that, The data transfer based on the memory region corresponding to the physical address includes: Determine the operation permissions corresponding to the physical address, and perform data transmission based on the operation permissions and the memory region corresponding to the physical address.
11. The memory region management method according to claim 1, characterized in that, The method further includes: If the memory access system operates in linear processing mode, then based on the table information of the memory region table and the memory region request, the physical address corresponding to the memory region request is determined, and data transmission is performed based on the memory region corresponding to the physical address.
12. The memory region management method according to claim 11, characterized in that, The table information further includes: the base address of the memory region table; determining the physical address corresponding to the memory region request based on the table information of the memory region table and the memory region request includes: Based on the virtual address of the memory region request, the base address of the memory region table, and the starting virtual address of the memory region, the physical address corresponding to the memory region request is determined.
13. A memory region management device, characterized in that, The apparatus is used in a memory access system, and the apparatus includes: The receiving module is used to receive memory region requests; The acquisition module is used to acquire table information of the memory region table corresponding to the memory region request; the memory region request includes: the virtual address of the memory region request; the table information includes: the starting virtual address of the memory region; The first determining module is used to determine the input parameters corresponding to the memory region request based on the starting virtual address of the memory region and the virtual address requested by the memory region. The second determining module is used to determine the physical address corresponding to the memory region request based on the input parameters and a preset memory translation table, and to perform data transmission based on the memory region corresponding to the physical address.
14. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the memory region management method as described in claims 1-12.
15. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the memory region management method as described in claims 1-12.