Improved YOLOv8n target detection hardware accelerator design method based on FPGA
By making lightweight improvements to the YOLOv8n model and optimizing the heterogeneous computing architecture, the problems of high computational complexity and data transmission redundancy in YOLOv8n hardware deployment were solved, and a low-latency target detection hardware accelerator design was realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HARBIN UNIV OF SCI & TECH
- Filing Date
- 2026-01-05
- Publication Date
- 2026-04-21
AI Technical Summary
The YOLOv8n object detection model suffers from problems in hardware deployment, such as a large number of computational parameters, high computational complexity, and high redundancy in the data transmission path structure, making it difficult to design real-time and low-cost, low-power hardware accelerators.
A lightweight improvement to the YOLOv8n model is adopted by introducing the GhostConv module, ECA attention mechanism, and Efficient Rep structure, combined with unstructured pruning methods to reduce the number of model parameters; weight fusion is performed on convolution operators, batch normalization layers, and activation functions, and the weight points are quantized; a heterogeneous computing hardware accelerator architecture is designed to optimize data storage and transmission paths.
It significantly reduces the number of model parameters and computational complexity, improves the real-time performance and energy efficiency of hardware deployment, and achieves low-latency hardware acceleration for target detection.
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Abstract
Description
Technical Field
[0001] This invention belongs to the fields of computer vision technology and dedicated hardware acceleration, specifically relating to a design method for an improved YOLOv8n target detection hardware accelerator based on FPGA. Background Technology
[0002] Object detection algorithms have gradually become an indispensable technology in intelligent systems. In today's rapidly evolving technological society, artificial intelligence (AI) technology is gradually replacing routine workflows. As the foundation of AI technology, machine learning models based on neural networks have been widely applied in numerous scenarios. Among them, object detection algorithms, due to their crucial role in environmental perception and decision support, are becoming an indispensable technology in intelligent system applications. Current research on FPGA-based hardware acceleration mainly focuses on object detection models with lower computational complexity, such as YOLOv2 and YOLOv3, while the design of hardware accelerators for widely used object detection models like YOLOv8 is still in the exploratory stage. Most of the inference for this algorithm occurs on traditional general-purpose hardware devices, resulting in high power consumption and high inference latency. Therefore, designing a hardware accelerator that can adapt to the algorithm's real-time requirements while maintaining low cost and low power consumption has become an important research topic.
[0003] In traditional central processing unit (CPU) architectures, the latency for processing a single frame of image often reaches hundreds of milliseconds, making it difficult to meet real-time processing requirements due to its computational complexity. With the development of the chip industry, hardware acceleration solutions such as graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs) have emerged. ASICs, through customized circuit architecture design, can achieve high energy efficiency in specific scenarios, exhibiting superior power consumption performance compared to GPUs. However, their long design cycles, high tape-out costs, and fixed hardware logic present a mismatch between these factors and the application requirements of rapid iteration in deep learning algorithm models.
[0004] FPGAs, with their reconfigurable hardware architecture, demonstrate unique advantages in the field of computing acceleration. Through hardware-level pipelined design and parallel computing unit arrays, FPGAs can process multiple data streams simultaneously, significantly improving computational throughput. Their dynamic reconfigurability allows for hardware logic optimization tailored to different algorithm characteristics, achieving significant improvements in computational efficiency while maintaining the strict energy efficiency constraints of embedded platforms. Therefore, designing a hardware accelerator on an FPGA platform that can adapt to the real-time performance and low cost / low power consumption of the YOLOv8n algorithm is a reasonable solution. Summary of the Invention
[0005] To address the problems mentioned above, the present invention aims to provide a hardware accelerator design method for target detection algorithms based on FPGA, which solves the problems of large number of computational parameters, high computational complexity, inefficient design of computational operators, and complex and redundant data transmission path structure in YOLOv8n hardware deployment.
[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0007] An improved YOLOv8n target detection hardware accelerator design method based on FPGA includes the following steps:
[0008] S1: For the YOLOv8n network model, lightweight structural improvements were made to reduce the number of parameters and computational complexity, adapting it to the hardware implementation requirements of FPGA. First, in the backbone network, the pointwise convolutions in the C2f module were replaced with improved GhostConv modules, resulting in the C2f_Ghost module, which enhances feature representation while reducing the number of parameters. In the neck network, the IMBConv module was composed of moving-flipping bottleneck convolutions (MBConv) with efficient channel attention (ECA), and the C2f module was improved to the C2f_IMBC module, which still improved the model accuracy while reducing the number of parameters by about 1 / 3. In the detection head, a reparameterized design based on the Efficient Rep structure was introduced, resulting in an improved decoupled detection head IRDHead, which further compresses the model parameters. Finally, unstructured pruning was performed on the overall model, significantly reducing the number of parameters and computational complexity.
[0009] Furthermore, the specific steps of S1 are as follows:
[0010] S1.1: The C2f module in the YOLOv8n backbone network is improved by replacing its two pointwise convolutions with Ghost convolutions based on the GhostConv structure. This module generates a set of intrinsic feature maps with C / 2 channels through pointwise convolutions; subsequently, these feature maps are transformed linearly through depthwise separable convolutions to generate Ghost feature maps with the same number of channels; finally, the intrinsic feature maps and Ghost feature maps are concatenated along the channel dimension to obtain a result with the same number of channels as the original pointwise convolution output. This design reduces the number of module parameters while maintaining feature expressive power.
[0011] S1.2: In the C2f module of the YOLOv8n neck network, a moving-flip bottleneck convolutional structure is introduced, and its original SE attention mechanism is replaced with an ECA attention mechanism. The ECA mechanism eliminates the channel dimension compression and restoration steps in SE, simplifying the structure. Furthermore, max pooling is used instead of average pooling in this attention module to avoid the resource overhead of division operations in hardware. These improvements reduce the number of parameters in this module by approximately 1M, making it more suitable for deployment on FPGAs.
[0012] S1.3: Based on the Efficient Rep reparameterization method, the parallel dual-branch convolutions in the detection head are merged into a single shared convolutional branch. The output of this branch is then provided to the classification and regression branches respectively, thereby significantly reducing the number of parameters and computational complexity of the detection head. This method reuses convolutional layer parameters, enabling the same branch to simultaneously adapt to classification and regression tasks. This effectively reduces parameter redundancy caused by structural decoupling, improves computational efficiency, and facilitates subsequent hardware deployment.
[0013] S1.4: The improved model is pruned using an unstructured pruning method based on LAMP. LAMP pruning prunes by evaluating the scores of weights in the model, which can accurately remove redundant parameters with low contribution. It can significantly reduce the number of parameters while ensuring that the decrease in model accuracy is within a reasonable range.
[0014] The above steps can solve the problems of large number of algorithm parameters and high computational complexity.
[0015] S2: Adaptive improvements to the YOLOv8n network model at the parameter level were made for hardware deployment. First, weight fusion was performed on the convolution operators, batch normalization layers, and activation functions in the model, and the activation function was replaced with the hardware-friendly Leaky_ReLU to reduce computational complexity. Second, the weights in the model were quantized to fixed points, reducing the data bit width and thus decreasing the storage and computing resource requirements during hardware deployment.
[0016] Furthermore, the specific steps of S2 are as follows:
[0017] S2.1: Weight fusion was performed on the convolution operator, batch normalization layer, and activation function in the model. Weights that would normally require three layers of computation were merged into a single weight, reducing external memory accesses, computational complexity, and accelerator latency. Replacing the activation function with Leaky_ReLU, which is more suitable for hardware deployment, avoids a large amount of nonlinear computation and reduces hardware overhead.
[0018] S2.2: The weight data, originally stored as 32-bit floating-point numbers in the model, is quantized into 8-bit fixed-point numbers. To reduce the loss of data representation capability due to the low bit-width fixed-point numbers, the representation method of S5.3 is adopted, namely, 5 integer bits, 3 decimal bits, and the highest bit is the sign bit, representing a range from -16 to 15.875. This can cover the representation range requirements of the weights in the model and significantly reduce hardware resource consumption.
[0019] The above steps can solve the problems of high inference latency caused by multiple memory accesses in the hardware implementation of the original network model, and the additional hardware resources required by floating-point calculations.
[0020] S3: The overall architecture of the hardware accelerator was designed, and the various computational operators and data paths were designed and optimized. First, a heterogeneous computing hardware accelerator architecture was designed using the overlapping dataflow architecture principle. Second, considering the deployment requirements of the improved YOLOv8n model on FPGA, the required operators were analyzed, and the IP core designs for convolution, pooling, upsampling, and ECA modules were completed. The computation process of each operator was also optimized for pipelined and parallelized processing. Finally, the data storage and transmission paths within the hardware accelerator were designed and optimized, and based on this, the hardware accelerator system-on-a-chip (SoC) was built.
[0021] Furthermore, the specific steps of S3 are as follows:
[0022] S3.1: Based on the principle of overlapping data flow architecture, a heterogeneous computing architecture of CPU+FPGA (i.e. PS-PL) is designed. That is, data caching and computation are implemented on the FPGA, and the input data is mounted in the DDR memory on the CPU. The CPU controls the data transmission and the implementation of the algorithm structure, and calls the corresponding operator according to the algorithm structure implemented on the CPU.
[0023] S3.2: By analyzing the operators with computational parameters that need to be implemented in YOLOv8n, we implemented the IP core design of standard convolution operator, depthwise convolution operator, pointwise convolution operator, max pooling operator, upsampling operator and ECA operator, and pipelined and parallelized the computation process.
[0024] S3.3: Regarding the data input and buffering issues of the hardware accelerator, the data transmission path between the CPU and FPGA, the on-chip BRAM and cache path, and the DDR memory path were designed and optimized. The DDR scheduling mechanism was also designed and optimized. Finally, all modules were integrated into a single accelerator module, and the hardware accelerator SoC was built in Vivado using the BlockDesign method.
[0025] The above steps yield a hardware accelerator SoC based on a CPU+FPGA heterogeneous computing architecture, and the data storage path has been optimized.
[0026] S4: The software portion of the hardware accelerator was designed and deployed on an FPGA platform to realize a hardware accelerator for target detection algorithms.
[0027] Furthermore, the specific steps of S4 are as follows:
[0028] S4.1: The algorithm structure is mapped on the CPU and combined with the hardware accelerator SoC. The accelerator design is completed on the ZYNQ 7020 platform, and the results are displayed on the monitor via HDMI to verify the accelerator's functionality and performance.
[0029] Compared with existing technologies, the advantages of this invention are as follows: Addressing the issues of large parameter count, high computational complexity, and difficulty in hardware implementation of the YOLOv8n network model, an improved object detection model is proposed, reducing the number of model parameters. Weight fusion is implemented for the convolution operator, a core computation in the object detection network, and the weight data of the network model is quantized at fixed points. In terms of hardware implementation, a heterogeneous computing architecture hardware accelerator is designed, and pipeline and parallelization designs are completed. Furthermore, software designs such as network structure mapping are implemented on the CPU, thereby accelerating the object detection network model in hardware. Attached Figure Description
[0030] Figure 1 This is the improved YOLOv8n algorithm structure of this invention;
[0031] Figure 2 This is the IMBConv module structure of the present invention;
[0032] Figure 3 This is the GhostConv module structure of the present invention;
[0033] Figure 4 This is the IRDHead module structure of the present invention;
[0034] Figure 5 This is the C2f_IMBC module structure of the present invention;
[0035] Figure 6 This is the C2f_Ghost module structure of the present invention;
[0036] Figure 7 This invention relates to the parameter changes before and after operator layer fusion.
[0037] Figure 8 This is the fixed-point quantization structure for the parameters of this invention;
[0038] Figure 9 This is the overall architecture of the hardware accelerator of the present invention;
[0039] Figure 10 This is the hardware structure of the standard convolution operator of this invention;
[0040] Figure 11 This is the hardware structure of the depthwise convolution operator of the present invention;
[0041] Figure 12 This is the hardware structure of the pointwise convolution operator of the present invention;
[0042] Figure 13 This is the hardware structure of the max pooling operator in this invention;
[0043] Figure 14 This is the hardware structure of the upsampling operator of the present invention;
[0044] Figure 15 This is the hardware structure of the Conv1d operator in this invention;
[0045] Figure 16 This invention compares the traditional design with the assembly line design.
[0046] Figure 17 This is the state machine for the DDR scheduling mechanism of the present invention; Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention is described below with reference to specific embodiments shown in the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. The structures, proportions, sizes, etc., illustrated in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read the invention, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concept of the invention.
[0048] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.
[0049] The specific embodiments of this invention employ the following technical solutions: including model lightweighting improvements, computation and parameter optimization, accelerator architecture design, computation unit design, data storage path optimization, and accelerator software design. The computation unit design includes the design of IP cores for standard convolution operators, depthwise convolution operators, pointwise convolution operators, max pooling operators, upsampling operators, and ECA operators, and the pipelined and parallelized processing of their computation processes. The data transmission path, on-chip BRAM and cache path, and DDR memory path were designed and optimized, and DDR scheduling was also designed and optimized. Experimental results are ultimately displayed on a monitor by connecting the accelerator IP cores to the HDMI display IP.
[0050] Model lightweighting improvements:
[0051] A target detection network data model that effectively reduces the number of parameters and computational complexity is proposed. Considering the need to reduce memory access frequency and detection latency for hardware accelerator implementation on FPGAs, an improved YOLOv8n algorithm structure is designed, such as... Figure 1 As shown.
[0052] First, in the YOLOv8n backbone network, the pointwise convolutions in the C2f module are replaced with an improved GhostConv module, resulting in the C2f_Ghost module, which enhances feature representation while reducing the number of parameters. In the neck network, the IMBConv module is composed of a moving-flip bottleneck convolution (MBConv) that incorporates efficient channel attention (ECA), and the C2f module is improved to form the C2f_IMBC module, achieving a certain improvement in model accuracy while reducing the number of parameters by about one-third. Finally, a reparameterization design based on the Efficient Rep structure is introduced in the detection head, resulting in an improved decoupled detection head, IRDHead, which further compresses model parameters. The IMBConv module structure is as follows: Figure 2 As shown, the GhostConv module structure is as follows: Figure 3 As shown, the IRDHead module structure is as follows: Figure 4 As shown.
[0053] The MBConv module employing ECA is added to the C2f module of the neck network, eliminating the redundant steps of dimensionality compression and restoration in traditional attention mechanisms. This effectively avoids excessive smoothing loss of channel information and significantly reduces the module's additional computational cost and parameter count, forming the C2f_IMBC module. The C2f_IMBC module is as follows: Figure 5 As shown.
[0054] Replacing the pointwise convolutions in the C2f module of the backbone network with the GhostConv module significantly reduces the number of parameters compared to the original pointwise convolutions, thus maintaining the same feature representation capability. This results in the formation of the C2f_Ghost module. The C2f_Ghost module is as follows: Figure 6 As shown.
[0055] Computation and parameter optimization:
[0056] The convolution operator, batch normalization layer, and activation function in the model were weighted and fused. By merging multiple normalization layers, their means and variances can be integrated, thereby reducing the time and space complexity of calculating the means and variances. The parameter changes before and after layer fusion are as follows: Figure 7 As shown.
[0057] The weights in the model were quantized using fixed-point quantization, reducing the data bit width and thus decreasing the storage and computing resource requirements during hardware deployment. The S5.3 (Q=3) bit width allocation method was adopted, with 5 integer bits, 3 decimal bits, and the highest bit as the sign bit, representing a range from -16 to 15.875, meeting the weight data size requirements. In the Vivado HLS development environment, the quantization scheme was implemented using the ap_fixed data type, setting a positive infinity rounding mode (AP_RND) to ensure numerical stability, and configuring a saturation overflow handling mechanism (AP_SAT) to prevent gradient distortion caused by extreme values. The fixed-point quantization structure of the parameters is as follows: Figure 8 As shown.
[0058] Accelerator architecture design:
[0059] A heterogeneous computing hardware accelerator architecture was designed based on the principle of overlapping data flow. The system employs a CPU+FPGA collaborative processing mechanism. The PL establishes a data path with DDR memory via an AXI4 bus interface. Pre-stored network input data, weights, and bias parameters are transferred in batches to the BRAM on the FPGA side via the DDR controller, and then distributed to the computing unit via independent weight buffer and input buffer units. The calculation results are returned to the DDR memory via the AXI bus through the output buffer unit. The CPU implements a hardware scheduling strategy based on a neural network layer structure, and uses programmable logic to precisely call the FPGA IP cores to complete the hardware acceleration of convolution calculations. The overall architecture of the hardware accelerator is as follows: Figure 9 As shown.
[0060] Computational unit design:
[0061] To address the deployment requirements of the improved YOLOv8n model on FPGA, the required operators were analyzed, and the IP core designs for convolution, pooling, upsampling, and ECA modules were completed.
[0062] The convolution operator computation process is as follows: Multi-channel input feature maps (TRin×TCin data blocks) and weights are loaded synchronously, then multiplied in parallel channel-by-channel and element-by-element by a multiplier array. The products are temporarily stored and rearranged in a cache module, then accumulated through an addition tree and biased to achieve linear fusion and correction. Finally, Leaky_ReLU introduces non-linearity. The entire process is driven by a unidirectional modular pipeline, balancing high throughput and low latency, and is specifically optimized for channel dimension transformation and feature fusion. The standard convolution operator hardware structure is as follows: Figure 10 As shown, the hardware structure of the depthwise convolution operator is as follows: Figure 11 As shown, the hardware structure of the pointwise convolution operator is as follows: Figure 12 As shown.
[0063] In the max pooling module, the input feature map is received from the left. The address register, combined with the convolution kernel parameters, calculates the memory address of each data point within the pooling window using a multiply-accumulate unit. A multiplexer selects the corresponding pixel value based on the address, which is then temporarily stored and aligned by a cache module before being fed into a comparator array. Parallel comparisons are performed, and the maximum value is output from the right-hand port, forming a unidirectional hardware pipeline. The hardware structure of the max pooling operator is as follows: Figure 13 As shown.
[0064] In the nearest neighbor upsampling module, the input feature map is received from the left. The address calculation register, combined with the upsampling ratio, determines the starting address of the output 2×2 region. After the loading unit reads the corresponding pixel value, it is copied into four copies by the data broadcast module and written in parallel to the specified position in the output buffer. Finally, it is output from the right port, forming a unidirectional hardware pipeline. The hardware structure of the upsampling operator is as follows: Figure 13 As shown.
[0065] The ECA IP also requires the implementation of a Conv1d operator. The Conv1d hardware architecture includes an array of input feature map multiply-accumulate units and an addition tree module: after the input feature map and weights are loaded synchronously, multiple sets of multiply-accumulate units perform element-wise multiplication in parallel. The results of each multiplication are then fed into the addition tree for hierarchical accumulation, finally outputting the feature map. This architecture improves the hardware processing efficiency of 1D convolution through parallel computation. The Conv1d operator hardware structure is as follows: Figure 15 As shown.
[0066] Data storage pathway optimization:
[0067] To address the data input and buffering issues of the hardware accelerator, the data transmission path between the CPU and FPGA, the on-chip BRAM and cache path, and the DDR memory path were designed and optimized. DDR scheduling was also designed and optimized. Finally, all modules were integrated into a single accelerator module, and the hardware accelerator SoC was built in Vivado using the Block Design method.
[0068] Pipeline FIFO optimization is introduced into the on-chip BRAM and data cache modules. To cover data loading time and improve design throughput, a first-in-first-out (FIFO) buffer is introduced between the data input and computation units to optimize the pipeline structure. This allows data loading and computation operations to be executed in parallel. A comparison of traditional design and pipelined design is provided. Figure 16 As shown.
[0069] A DDR scheduling data path and a DDR scheduling state machine were designed. The CPU initiates an interrupt to read the DDR initialization and accelerator cache state, confirms this, and then calls the FPGA to write data. The processing unit array reads data, performs calculations, and writes the results back to DDR. If the process is incomplete, it continues reading; upon completion, it relinquishes memory access rights. The CPU can then read data or assign new tasks. At this point, the accelerator again relinquishes access rights and waits for writing, forming a complete interaction process between the CPU and FPGA. The DDR scheduling mechanism state machine is as follows: Figure 17 As shown.
[0070] Accelerator software design:
[0071] The hardware is implemented using a ZYNQ 7020 FPGA, which integrates an ARM CPU. The algorithm structure is mapped on the CPU side and combined with the hardware accelerator SoC. The accelerator design is completed on the ZYNQ 7020 platform, and the results are displayed on the monitor via HDMI to verify the accelerator's functionality and performance.
[0072] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.
[0073] Furthermore, the above description is merely one embodiment of the present invention and is not intended to limit the invention. Those skilled in the art will recognize that the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A design method for an improved YOLOv8n target detection hardware accelerator based on FPGA, characterized in that, Includes the following steps: S1: For the YOLOv8n network model, lightweight structural improvements were made to reduce the number of parameters and computational complexity, adapting it to the hardware implementation requirements of FPGA. First, in the backbone network, the pointwise convolutions in the C2f module were replaced with improved GhostConv modules, resulting in the C2f_Ghost module, which enhances feature representation while reducing the number of parameters. In the neck network, the IMBConv module was composed of moving-flipping bottleneck convolutions (MBConv) with efficient channel attention (ECA), and the C2f module was improved to the C2f_IMBC module, which still improved the model accuracy while reducing the number of parameters by about 1 / 3. In the detection head, a reparameterized design based on the Efficient Rep structure was introduced, resulting in an improved decoupled detection head IRDHead, which further compresses the model parameters. Finally, unstructured pruning was performed on the overall model, significantly reducing the number of parameters and computational complexity. S2: Adaptive improvements to the YOLOv8n network model at the parameter level were made for hardware deployment. First, weight fusion was performed on the convolution operators, batch normalization layers, and activation functions in the model, and the activation function was replaced with the hardware-friendly Leaky_ReLU to reduce computational complexity. Second, the weights in the model were quantized to fixed points, reducing the data bit width and thus decreasing the storage and computing resource requirements during hardware deployment. S3: The overall architecture of the hardware accelerator was designed, and the various computational operators and data paths were designed and optimized. First, a heterogeneous computing hardware accelerator architecture was designed using the overlapping dataflow architecture principle. Second, considering the deployment requirements of the improved YOLOv8n model on FPGA, the required operators were analyzed, and the IP core designs for convolution, pooling, upsampling, and ECA modules were completed. The computation process of each operator was also optimized for pipelined and parallelized processing. Finally, the data storage and transmission paths within the hardware accelerator were designed and optimized, and based on this, the hardware accelerator system-on-a-chip (SoC) was built. S4: The software portion of the hardware accelerator was designed and deployed on an FPGA platform to realize a hardware accelerator for target detection algorithms.
2. The improved YOLOv8n target detection hardware accelerator design method based on FPGA according to claim 1, characterized in that, The specific steps of step S1 are as follows: S1.1: The C2f module in the YOLOv8n backbone network is improved by replacing its two pointwise convolutions with Ghost convolutions based on the GhostConv structure. This module generates a set of intrinsic feature maps with C / 2 channels through pointwise convolutions; subsequently, these feature maps are transformed linearly through depthwise separable convolutions to generate Ghost feature maps with the same number of channels; finally, the intrinsic feature maps and Ghost feature maps are concatenated along the channel dimension to obtain a result with the same number of channels as the original pointwise convolution output. This design reduces the number of module parameters while maintaining feature expressive power. S1.2: In the C2f module of the YOLOv8n neck network, a moving-flip bottleneck convolutional structure is introduced, and its original SE attention mechanism is replaced with an ECA attention mechanism. The ECA mechanism eliminates the channel dimension compression and restoration steps in SE, simplifying the structure. Furthermore, max pooling is used instead of average pooling in this attention module to avoid the resource overhead of division operations in hardware. These improvements reduce the number of parameters in this module by approximately 1M, making it more suitable for deployment on FPGAs. S1.3: Based on the Efficient Rep reparameterization method, the parallel dual-branch convolutions in the detection head are merged into a single shared convolutional branch. The output of this branch is then provided to the classification and regression branches respectively, thereby significantly reducing the number of parameters and computational complexity of the detection head. This method reuses convolutional layer parameters, enabling the same branch to simultaneously adapt to classification and regression tasks. This effectively reduces parameter redundancy caused by structural decoupling, improves computational efficiency, and facilitates subsequent hardware deployment. S1.4: The improved model is pruned using an unstructured pruning method based on LAMP. LAMP pruning prunes by evaluating the scores of weights in the model, which can accurately remove redundant parameters with low contribution. It can significantly reduce the number of parameters while ensuring that the decrease in model accuracy is within a reasonable range.
3. The improved YOLOv8n target detection hardware accelerator design method based on FPGA according to claim 1, characterized in that, The specific steps of step S2 are as follows: S2.1: Weight fusion was performed on the convolution operator, batch normalization layer, and activation function in the model. Weights that would normally require three layers of computation were merged into a single weight, reducing external memory accesses, computational complexity, and accelerator latency. Replacing the activation function with Leaky_ReLU, which is more suitable for hardware deployment, avoids a large amount of nonlinear computation and reduces hardware overhead. S2.2: The weight data, originally stored as 32-bit floating-point numbers in the model, is quantized into 8-bit fixed-point numbers. To reduce the loss of data representation capability due to the low bit-width fixed-point numbers, the representation method of S5.3 is adopted, namely, 5 integer bits, 3 decimal bits, and the highest bit is the sign bit, representing a range from -16 to 15.
875. This can cover the representation range requirements of the weights in the model and significantly reduce hardware resource consumption.
4. The improved YOLOv8n target detection hardware accelerator design method based on FPGA according to claim 1, characterized in that, The specific steps of step S3 are as follows: S3.1: Based on the principle of overlapping data flow architecture, a heterogeneous computing architecture of CPU+FPGA (i.e. PS-PL) is designed. That is, data caching and computation are implemented on the FPGA, and the input data is mounted in the DDR memory on the CPU. The CPU controls the data transmission and the implementation of the algorithm structure, and calls the corresponding operator according to the algorithm structure implemented on the CPU. S3.2: By analyzing the operators with computational parameters that need to be implemented in YOLOv8n, we implemented the IP core design of standard convolution operator, depthwise convolution operator, pointwise convolution operator, max pooling operator, upsampling operator and ECA operator, and pipelined and parallelized the computation process. S3.3: Regarding the data input and buffering issues of the hardware accelerator, the data transmission path between the CPU and FPGA, the on-chip BRAM and cache path, and the DDR memory path were designed and optimized. The DDR scheduling mechanism was also designed and optimized. Finally, all modules were integrated into a single accelerator module, and the hardware accelerator SoC was built in Vivado using the Block Design method.
5. The improved YOLOv8n target detection hardware accelerator design method based on FPGA according to claim 1, characterized in that, The specific steps of step S4 are as follows: S4.1: The algorithm structure is mapped on the CPU and combined with the hardware accelerator SoC. The accelerator design is completed on the ZYNQ 7020 platform, and the results are displayed on the monitor via HDMI to verify the accelerator's functionality and performance.