Image sensor

Abstract

An image sensor is provided. The image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a first pixel region including a first photoelectric conversion region (PD) in the substrate; a second pixel region including a second photoelectric conversion region (PD) in the substrate; a PD separation pattern between the first PD and the second PD; a transfer gate structure including a first lower portion extending into the substrate from the first surface and a first upper portion protruding beyond the first surface; and a control gate structure including a second lower portion extending into the substrate from the first surface and a second upper portion protruding beyond the first surface, in which the PD separation pattern penetrates the substrate, in which the first upper portion is spaced apart from the second upper portion in a first direction parallel to the first surface, the transfer gate structure and the control gate structure are disposed in the first pixel region, and wherein the image sensor is configured to receive light from the second surface.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0142740, filed on October 18, 2024, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present invention relates to image sensors. Background Technology

[0003] An image sensor is a semiconductor device that converts optical information into electrical signals. Such image sensors can include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors.

[0004] Image sensors can be configured in the form of a package. The package protects the image sensor and can be configured to allow light to enter the light-receiving surface or sensing area of ​​the image sensor. Summary of the Invention

[0005] This disclosure provides an image sensor with improved performance and integration.

[0006] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0007] According to one aspect of this disclosure, an image sensor includes: a substrate including a first surface and a second surface opposite to the first surface; a first pixel region including a first photoelectric conversion region (PD) in the substrate; a second pixel region including a second photoelectric conversion region (PD) in the substrate; a PD separation pattern between the first PD and the second PD; a transmission gate structure including a first lower portion extending from the first surface into the substrate and a first upper portion protruding beyond the first surface; and a control gate structure including a second lower portion extending from the first surface into the substrate and a second upper portion protruding beyond the first surface, wherein the PD separation pattern penetrates the substrate, wherein the first upper portion is spaced apart from the second upper portion in a first direction parallel to the first surface, wherein the transmission gate structure and the control gate structure are disposed in the first pixel region, and wherein the image sensor is configured to receive light from the second surface.

[0008] According to one aspect of this disclosure, an image sensor includes: a substrate including a first surface and a second surface opposite to the first surface; a first pixel region including a first photoelectric conversion region (PD) in the substrate; a second pixel region including a second photoelectric conversion region (PD) in the substrate; a third pixel region including a third photoelectric conversion region (PD) in the substrate; a fourth pixel region including a fourth photoelectric conversion region (PD) in the substrate; a PD separation pattern separating the first PD to the fourth PD from each other; a single color filter on the first PD to the fourth PD; and a floating diffusion region configured to store photocharge generated by the first PD to the fourth PD; A transmission gate structure includes a first lower portion extending from a first surface into a substrate and a first upper portion protruding beyond the first surface; and a first control gate structure includes a second lower portion extending from the first surface into the substrate and a second upper portion protruding beyond the first surface, wherein a PD separation pattern penetrates the substrate, wherein the first upper portion is spaced apart from the second upper portion in a first direction parallel to the first surface, wherein the first transmission gate structure and the first control gate structure are disposed in a first pixel region, wherein the first pixel region to the fourth pixel region are arranged sequentially in a clockwise direction in a plan view, and wherein the image sensor is configured to receive light from a second surface. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become clearer by referring to the accompanying drawings and describing exemplary embodiments of the present disclosure in detail.

[0010] Figure 1 This is an exemplary circuit diagram used to explain the shared pixel structure of a pixel array of an image sensor according to some embodiments.

[0011] Figure 2 It is a planar diagram used to explain the pixel array of an image sensor according to some embodiments.

[0012] Figure 3 It is along Figure 2 A schematic cross-sectional view taken from AA.

[0013] Figure 4 It is along Figure 2 A schematic cross-sectional view of BB.

[0014] Figure 5 It is a graph used to explain the performance of an image sensor according to some implementations.

[0015] Figure 6 and Figure 7 These are cross-sectional views used to explain various implementations of image sensors.

[0016] Figure 8It is a planar diagram used to explain the pixel array of an image sensor according to some embodiments.

[0017] Figure 9 It is along Figure 8 A schematic cross-sectional view taken from CC.

[0018] Figures 10 to 13 These are various planar diagrams used to interpret the pixel arrays of an image sensor according to some implementations.

[0019] Figure 14 and Figure 15 It is a layout diagram used to explain various pixel arrays of image sensors according to some implementations.

[0020] Figure 16 This is a schematic exploded perspective view used to explain an image sensor according to some embodiments.

[0021] Figure 17 It is used for explanation Figure 16 A schematic cross-sectional view of the image sensor. Detailed Implementation

[0022] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0023] In the following text, reference will be made to Figures 1 to 17 An image sensor according to an exemplary embodiment is described.

[0024] Figure 1 This is an exemplary circuit diagram used to explain the shared pixel structure of a pixel array of an image sensor according to some embodiments.

[0025] Reference Figure 1 The pixel array may include multiple photodiodes PD1 to PD8, multiple transmission transistors TX1 to TX8, a first floating diffusion region FD1, a second floating diffusion region FD2, a reset transistor RX, a source follower transistor SF, a select transistor SX, and a dual conversion gain transistor DCX.

[0026] The shared pixel structure may include multiple photodiodes PD1 to PD8, comprising a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, a fourth photodiode PD4, a fifth photodiode PD5, a sixth photodiode PD6, a seventh photodiode PD7, and an eighth photodiode PD8. The multiple photodiodes PD1 to PD8 may be divided into two PD groups: a first PD group where the first photodiodes PD1 to PD4 are arranged in a 2×2 matrix centered on a first shared floating diffusion region; and a second PD group where the fifth photodiodes PD5 to PD8 are arranged in a 2×2 matrix centered on a second shared floating diffusion region. In this case, the first and second shared floating diffusion regions may be connected via connecting lines or connecting regions to form a first floating diffusion region FD1. In some embodiments, the multiple photodiodes PD1 to PD8 may also be configured as a single PD group arranged around the first floating diffusion region FD1. In some embodiments, the shared pixel structure may further include a third PD group and a fourth PD group, the third PD group including four additional photodiodes connected to the first floating diffusion region FD1, and the fourth PD group including four additional photodiodes connected to the second floating diffusion region FD2.

[0027] Each pixel described in this disclosure may consist of one photodiode and one microlens, two photodiodes and one microlens, or four photodiodes and one microlens. That is, multiple photodiodes PD1 to PD8 may be included in eight pixels, four pixels, or two pixels. Multiple transmission transistors TX1 to TX8 may include a first transmission transistor TX1, a second transmission transistor TX2, a third transmission transistor TX3, a fourth transmission transistor TX4, a fifth transmission transistor TX5, a sixth transmission transistor TX6, a seventh transmission transistor TX7, and an eighth transmission transistor TX8. However, the number of photodiodes and the number of transmission transistors are not limited thereto.

[0028] Each of a plurality of photodiodes PD1 to PD8 can be formed by forming an n-type semiconductor region on a substrate having a p-type semiconductor region, and converting incident light into charge. Each of the plurality of photodiodes PD1 to PD8 can be coupled to a corresponding transfer transistor that transfers the generated and accumulated charge to a corresponding floating diffusion region. Because the floating diffusion region is a region used to convert charge into voltage and has parasitic capacitance, the charge can be accumulated and stored.

[0029] In some embodiments, the first floating diffusion region FD1 can be connected to the second floating diffusion region FD2 via a dual-conversion gain transistor DCX to adjust the combined capacitance. In some embodiments, the second floating diffusion region FD2 can be a doped region and connected to a capacitor. The capacitor can be a metal-insulator-metal capacitor.

[0030] One end of each of the plurality of transfer transistors TX1 to TX8 may be connected to a corresponding photodiode among the plurality of photodiodes PD1 to PD8. The other end of each of the plurality of transfer transistors TX1 to TX8 may be connected to a first shared floating diffusion region or a second shared floating diffusion region. Each of the plurality of transfer transistors TX1 to TX8 may be formed by a transistor driven by a predetermined bias (e.g., a transfer signal). The transfer signal may be applied to the gate of each of the transfer transistors TX1 to TX8 to transfer charge generated from the corresponding photodiode among the plurality of photodiodes PD1 to PD8 to the first shared floating diffusion region or the second shared floating diffusion region according to the transfer signal.

[0031] The source follower transistor SF amplifies the potential change of charge sent from multiple photodiodes PD1 to PD8 to the first floating diffusion region FD1, and outputs the amplified potential change to the output line VOUT. When the source follower transistor SF is turned on, a predetermined potential (e.g., power supply voltage VPIX) supplied to the drain of the source follower transistor SF can be sent to the drain region of the select transistor SX. In some embodiments, multiple source follower transistors SF may be connected to the first floating diffusion region FD1.

[0032] The select transistor SX can select the pixels to be read on a row-by-row basis. The select transistor SX can be made of a transistor driven by a select line through which a predetermined bias (e.g., a row select signal) is applied. The row select signal can be applied through the gate of the select transistor SX.

[0033] The reset transistor RX can periodically reset the first floating diffusion region FD1. When the reset transistor RX is turned on by a reset signal, a predetermined potential (e.g., power supply voltage VPIX) supplied to the drain of the reset transistor RX can be sent to the first floating diffusion region FD1.

[0034] The dual-gain transistor DCX has an adjustable conversion gain. For example, the conversion gain can be adjusted by applying a logic high-level dual-gain signal to the dual-gate of the dual-gain transistor DCX or by applying a logic low-level dual-gain signal to the dual-gate of the dual-gain transistor DCX. The dual-gain transistor DCX can be located between a first floating diffusion region FD1 and a second floating diffusion region FD2. The conversion gain can be adjusted by adjusting the combined capacitor corresponding to the first floating diffusion region FD1 and the second floating diffusion region FD2 according to whether the dual-gain transistor DCX is driven.

[0035] although Figure 1 An example is shown where eight photodiodes PD1 to PD8 electrically share a first floating diffusion region FD1, but this disclosure is not limited thereto. That is, the number of photodiodes electrically sharing the first floating diffusion region FD1 is not limited to the number shown. In some embodiments, the pixel array includes a non-shared pixel structure in which "one photodiode is connected to the first floating diffusion region FD1".

[0036] Figure 2 It is a planar diagram used to explain the pixel array of an image sensor according to some embodiments. Figure 3 It is along Figure 2 A schematic cross-sectional view taken from AA. Figure 4 It is along Figure 2 A schematic cross-sectional view of BB.

[0037] Reference Figures 1 to 4 An image sensor according to some embodiments includes a first substrate 100, an element separation pattern 110, a PD separation pattern 120, a photoelectric conversion region 101, a first impurity region 102, a second impurity region 104, a transfer gate structure TGS, a control gate structure CGS, a first wiring structure 140, a surface insulating film 150, a grid pattern (or grid film) 160, a color filter 180, and a microlens 190. In some embodiments, a floating diffusion region FD may be configured to store photocharge generated by the photoelectric conversion region 101.

[0038] The first substrate 100 may be a semiconductor substrate. For example, the first substrate 100 may be bulk silicon or SOI (silicon-on-insulator). The first substrate 100 may be a silicon substrate, or may include other materials (e.g., silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide). Optionally, the first substrate 100 may be a substrate in which an epitaxial layer is formed on a base substrate.

[0039] The first substrate 100 may include a first surface 100a and a second surface 100b opposite to each other. In the embodiments described below, the first surface 100a may be referred to as the front side of the first substrate 100, and the second surface 100b may be referred to as the back side of the first substrate 100. In some embodiments, the second surface 100b of the first substrate 100 may be a light-receiving surface on which light is incident. That is, according to some embodiments, the image sensor may be a back-illuminated (BSI) image sensor.

[0040] In some embodiments, the first substrate 100 may have a first conductivity type. In the embodiments described below, the first conductivity type will be described as p-type, but this is merely an example, and it goes without saying that the first conductivity type may be n-type.

[0041] The first substrate 100 may include a plurality of pixel regions PX1 to PX4. Each of the pixel regions PX1 to PX4 may constitute the first substrate 100. Figure 1 The region of a unit pixel PX. Pixel regions PX1 to PX4 can be arranged in two dimensions (e.g., in the form of a matrix) along a horizontal plane (e.g., the XY plane).

[0042] For example, pixel regions PX1 to PX4 may include a first pixel region PX1, a second pixel region PX2, a third pixel region PX3, and a fourth pixel region PX4 that are adjacent to each other. The first pixel region PX1 and the second pixel region PX2 may be adjacent to each other in a first direction X. The first pixel region PX1 and the third pixel region PX3 may be adjacent to each other in a second direction Y that intersects the first direction X. The second pixel region PX2 and the fourth pixel region PX4 may be adjacent to each other in the second direction Y, and the third pixel region PX3 and the fourth pixel region PX4 may be adjacent to each other in the first direction X. That is, the first pixel region PX1 and the fourth pixel region PX4 may be adjacent to each other in the diagonal direction between the first direction X and the second direction Y.

[0043] Component separation pattern 110 may be formed within the first substrate 100. Component separation pattern 110 may be adjacent to (or in contact with) the first surface 100a of the first substrate 100. Component separation pattern 110 may define active regions AP1 and AP2 adjacent to the first surface 100a in each of pixel regions PX1 to PX4. For example, shallow trenches (hereinafter, component separation trenches) extending from the first surface 100a to define active regions AP1 and AP2 may be formed within the first substrate 100. Component separation pattern 110 may fill at least a portion of the component separation trench. The shape, size, number, arrangement, etc., of active regions AP1 and AP2 are merely exemplary and are not limited to those shown in the drawings.

[0044] The component separation pattern 110 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. As an example, the component separation pattern 110 may include a silicon oxide film. Although the component separation pattern 110 is shown only as a single film, this is merely an example, and the component separation pattern 110 may be a multi-film formed by stacking multi-material films.

[0045] In some implementations, the active regions AP1 and AP2 of each of the pixel regions PX1 to PX4 may include a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 may be separated from each other by element separation pattern 110.

[0046] A PD separation pattern 120 may be formed within a first substrate 100. The PD separation pattern 120 may define a plurality of pixel regions PX1 to PX4 within the first substrate 100. For example, a deep trench (hereinafter, a pixel separation trench) defining the plurality of pixel regions PX1 to PX4 may be formed in the first substrate 100. Viewed from a planar perspective (e.g., the XY plane), the pixel separation trench may be formed in a lattice shape and may surround each of the pixel regions PX1 to PX4. The PD separation pattern 120 may fill at least a portion of the pixel separation trench. In some embodiments, the PD separation pattern 120 may be between and separate the plurality of photoelectric conversion regions in the plurality of pixel regions (e.g., PX1 to PX4) from each other.

[0047] The PD separation pattern 120 prevents photocharge generated in a specific unit pixel (e.g., the first unit pixel PX1) from moving to other adjacent unit pixels (e.g., the second unit pixels PX2 to the fourth unit pixels PX4) due to random drift. Furthermore, the PD separation pattern 120 prevents optical crosstalk caused by light incident on a specific unit pixel (e.g., the first unit pixel PX1) onto other adjacent unit pixels (e.g., the second unit pixels PX2 to the fourth unit pixels PX4).

[0048] In some embodiments, the width of the PD separation pattern 120 may decrease from the first surface 100a toward the second surface 100b. Here, the width of the PD separation pattern 120 refers to the width measured along a horizontal plane (e.g., the XY plane). This may be due to the fact that the etching process used to form the PD separation pattern 120 is performed toward the first surface 100a of the first substrate 100. For example, the PD separation pattern 120 may be a front-side DTI (FDTI) formed on the front side of the first substrate 100 (i.e., the first surface 100a) by a deep trench isolation (DTI) process.

[0049] In some embodiments, the PD separation pattern 120 may completely penetrate the first substrate 100. For example, the PD separation pattern 120 may be adjacent to (or in contact with) both the first surface 100a and the second surface 100b.

[0050] In some embodiments, the PD separation pattern 120 may include a liner insulating film 121, a gap-filling film 123, and a buried insulating film 125.

[0051] The insulating film 121 may be stacked on the inner wall of the first substrate 100. The insulating film 121 may be placed between the first substrate 100 and the gap-filling film 123. For example, the insulating film 121 may extend along the contour of the inner wall of the first substrate 100.

[0052] The insulating film 121 may comprise at least one of the insulating materials, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and combinations thereof. Although the insulating film 121 is shown as a single film, this is merely exemplary, and the insulating film 121 may be a multilayer film. Although the boundary between the component separation pattern 110 and the insulating film 121 is shown to exist, this is merely exemplary, and the boundary between the component separation pattern 110 and the insulating film 121 may not exist. For example, when the component separation pattern 110 and the insulating film 121 comprise the same material (e.g., a silicon oxide film), the boundary between the component separation pattern 110 and the insulating film 121 may not be distinguished.

[0053] The gap-filling film 123 may be stacked on the insulating film 121. The gap-filling film 123 may fill at least a portion of the area remaining in the PD separation pattern 120 after the insulating film 121 has been filled. In some embodiments, the gap-filling film 123 may be spaced apart from the first surface 100a and may be in contact with the second surface 100b.

[0054] The interstitial filling film 123 may include, but is not limited to, conductive materials (e.g., at least one of undoped polycrystalline silicon film, undoped silicon-germanium film, impurity-doped polycrystalline silicon film, impurity-doped silicon-germanium film, and metal film). As an example, the interstitial filling film 123 may include a polycrystalline silicon film doped with p-type impurities (e.g., boron (B)) or n-type impurities (e.g., phosphorus (P)). The interstitial filling film 123 may also include oxide materials (e.g., at least one of aluminum oxide, hafnium oxide, silicon oxide, tantalum oxide, and tantalum silicon oxide).

[0055] In some embodiments, a negative (-) bias voltage may be applied to the gap filler film 123. Such a gap filler film 123 can capture holes that may exist on the surface of the first substrate 100 adjacent to the PD separation pattern 120, thereby improving the dark current characteristics of the image sensor.

[0056] The buried insulating film 125 may be stacked on the liner insulating film 121 and the gap filling film 123. The gap filling film 123 may be spaced apart from the first surface 100a by the buried insulating film 125. In some embodiments, a portion of the liner insulating film 121 may be placed between the component separation pattern 110 and the buried insulating film 125.

[0057] Although the depth at which the buried insulating film 125 is formed is shown to be the same as the depth at which the component separation pattern 110 is formed, with reference to the first surface 100a, this is merely exemplary, and it goes without saying that the depth at which the buried insulating film 125 is formed may be different from the depth at which the component separation pattern 110 is formed.

[0058] The buried insulating film 125 may include, but is not limited to, at least one of insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof). Although the buried insulating film 125 is shown as a single film, this is merely exemplary, and the buried insulating film 125 may be a multilayer film. Although the boundary between the liner insulating film 121 and the buried insulating film 125 is shown to exist, this is merely exemplary, and the boundary between the liner insulating film 121 and the buried insulating film 125 may not exist. For example, when the liner insulating film 121 and the buried insulating film 125 comprise the same material (e.g., a silicon oxide film), the boundary between the liner insulating film 121 and the buried insulating film 125 may not be distinguished.

[0059] A photoelectric conversion region 101 may be formed inside the first substrate 100. The photoelectric conversion region 101 may be formed inside each of the pixel regions PX1 to PX4. The photoelectric conversion region 101 may have a second conductivity type different from the first conductivity type. For example, the photoelectric conversion region 101 may be formed by implanting n-type impurity ions into the p-type first substrate 100. The region surrounding the photoelectric conversion region 101 and the first substrate 100 may be configured as follows: Figure 1 Photoelectric conversion element PD (e.g., Figure 1 (Multiple photodiodes PD1 to PD8). In the embodiments described below, the photoelectric conversion region 101 is also referred to as PD.

[0060] In some embodiments, the photoelectric conversion region 101 may be spaced apart from the first surface 100a of the first substrate 100. For example, the photoelectric conversion region 101 may be an n-type impurity region formed in the first substrate 100 and spaced apart from the first surface 100a.

[0061] The first impurity region 102 may be formed within the first substrate 100 adjacent to the first surface 100a. For example, the first impurity region 102 may be formed within the first active pattern AP1. The first impurity region 102 may have a second conductivity type. For example, the first impurity region 102 may be an n-type impurity region formed by implanting n-type impurity ions into the first active pattern AP1. The first impurity region 102 may be spaced apart from the photoelectric conversion region 101. In some embodiments, at least a portion of the first impurity region 102 may be spaced apart from the photoelectric conversion region 101 in a third direction Z intersecting the first surface 100a. The first impurity region 102 may be configured as follows: Figure 1 The floating diffusion region FD.

[0062] In some embodiments, with reference to the first surface 100a, the depth at which the first impurity region 102 is formed may be less than the depth at which the element separation pattern 110 is formed.

[0063] In some embodiments, the first impurity region 102 may be disposed in the center surrounded by the first pixel region PX1 to the fourth pixel region PX4. In some embodiments, the first pixel region PX1 to the fourth pixel region PX4 may share a single color filter. For example, a single color filter may be disposed in the first pixel region PX1 to the fourth pixel region PX4.

[0064] The second impurity region 104 may be formed within the first substrate 100 adjacent to the first surface 100a. For example, the second impurity region 104 may be formed within the second active pattern AP2. The second impurity region 104 may have a first conductivity type. For example, the second impurity region 104 may be a high-concentration p-type impurity region formed by implanting a high concentration of p-type impurity ions into the second active pattern AP2. The second impurity region 104 may be spaced apart from the photoelectric conversion region 101. The second impurity region 104 may be configured as a ground region to which a ground voltage is applied.

[0065] A transfer gate structure TGS may be formed on a first surface 100a of a first substrate 100. The transfer gate structure TGS may be formed on a first active pattern AP1. The transfer gate structure TGS may be adjacent to a first impurity region 102. For example, the first impurity region 102 may be formed inside the first active pattern AP1 on a side surface of the transfer gate structure TGS.

[0066] In some embodiments, the transfer gate structure TGS may include a transfer gate dielectric film 131, a transfer gate electrode TG, and a transfer gate spacer 136.

[0067] A transfer gate dielectric film 131 may be disposed between the first substrate 100 and the transfer gate electrode TG. The transfer gate dielectric film 131 may include a dielectric material (e.g., at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant higher than that of silicon oxide). The high-k material may include, for example, but not limited to, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0068] The transfer gate electrode TG can be stacked on the transfer gate dielectric film 131. The transfer gate electrode TG may include a conductive material, such as, but not limited to, at least one of a metal film, a metal silicide film, an undoped polycrystalline silicon film, an undoped silicon-germanium film, a polycrystalline silicon film doped with impurities, and a silicon-germanium film doped with impurities. As an example, the transfer gate electrode TG may include a polycrystalline silicon film doped with n-type impurities. The transfer gate electrode TG may be configured as follows: Figure 1 The gate of the transfer transistor TX.

[0069] The transfer gate spacer 136 may extend along the side surface of the transfer gate electrode TG. The transfer gate spacer 136 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon oxycarbide, and combinations thereof.

[0070] In some embodiments, at least a portion of the transfer gate structure TGS may extend into the first substrate 100 in the third direction Z toward the photoelectric conversion region 101. For example, a first gate trench TGt may be formed in the first substrate 100. The first gate trench TGt may extend from a first surface 100a. The first gate trench TGt may be spaced apart from the photoelectric conversion region 101 in the third direction Z. At least a portion of the transfer gate structure TGS may fill the first gate trench TGt. For example, a transfer gate dielectric film 131 may extend conformally along the contour of the first gate trench TGt. The transfer gate electrode TG may fill the area of ​​the first gate trench TGt remaining after the transfer gate dielectric film 131 has been filled.

[0071] In some embodiments, the transfer gate electrode TG may include a first lower electrode TGa and a first upper electrode TGb. The first lower electrode TGa may be disposed within the first gate trench TGt. The first upper electrode TGb is connected to the first lower electrode TGa and may protrude beyond the first surface 100a. That is, the first lower electrode TGa may be the region of the transfer gate electrode TG located in the first substrate 100, and the first upper electrode TGb may be the region of the transfer gate electrode TG located outside the first substrate 100. For example, the transfer gate structure TGS may include a first lower portion extending into the first substrate 100 and a first upper portion protruding beyond the first surface 100a.

[0072] The transfer gate dielectric film 131 may be disposed between the first substrate 100 and the first lower electrode TGa and between the first substrate 100 and the first upper electrode TGb. The transfer gate spacer 136 may extend along the side surface of the first upper electrode TGb.

[0073] In some embodiments, with reference to the first surface 100a, the depth at which the transfer gate structure TGS is formed may be greater than the depth at which the first impurity region 102 is formed. For example, as Figure 3 As shown, with reference to the first surface 100a, the depth D1 of the first gate trench TGt can be greater than the depth at which the first impurity region 102 is formed. In some embodiments, with reference to the first surface 100a, the depth at which the transfer gate structure TGS is formed can be greater than the depth at which the element separation pattern 110 is formed. For example, as... Figure 3 As shown, with the first surface 100a as a reference, the depth D1 of the first gate trench TGt can be greater than the depth on which the element separation pattern 110 is formed.

[0074] A control gate structure CGS may be formed on a first surface 100a of the first substrate 100. The control gate structure CGS may be spaced apart from the floating diffusion region FD and the transfer gate structure TGS. For example, the control gate structure CGS may be formed on the element separation pattern 110. Figure 2 In this example, although the transfer gate structure TGS and the control gate structure CGS are shown only as being diagonally spaced between the first direction X and the second direction Y, this is merely exemplary, and it goes without saying that the form in which the transfer gate structure TGS and the control gate structure CGS are configured can vary.

[0075] In some embodiments, the control gate structure CGS may include a control gate dielectric film 132, a control gate electrode CG, and a control gate spacer 137.

[0076] A control gate dielectric film 132 may be disposed between the first substrate 100 and the control gate electrode CG. The control gate dielectric film 132 may include at least one of a dielectric material (e.g., silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material having a dielectric constant greater than that of silicon oxide). The control gate dielectric film 132 may comprise the same material as the transport gate dielectric film 131, or it may comprise a different material from the transport gate dielectric film 131.

[0077] The control gate electrode CG may be stacked on the control gate dielectric film 132. The control gate electrode CG may include at least one of the following conductive materials, such as, but not limited to, a metal film, a metal silicide film, an undoped polycrystalline silicon film, an undoped silicon-germanium film, a doped polycrystalline silicon film, or a doped silicon-germanium film. The control gate electrode CG may be made of the same material as the transport gate electrode TG, or it may be made of a different material than the transport gate electrode TG.

[0078] The control gate spacer 137 may extend along the side surface of the control gate electrode CG. The control gate spacer 137 may include, for example, an insulating material, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon oxycarbide, and combinations thereof. The control gate spacer 137 may comprise the same material as the transfer gate spacer 136, or may comprise a different material than the transfer gate spacer 136.

[0079] At least a portion of the control gate structure CGS may be adjacent to the photoelectric conversion region 101. For example, a second gate trench CGt may be formed across the element separation pattern 110 and the first substrate 100. The second gate trench CGt may contact the photoelectric conversion region 101. At least a portion of the control gate structure CGS may fill the second gate trench CGt. For example, the control gate dielectric film 132 may extend conformally along the contour of the second gate trench CGt. The control gate electrode CG may fill the remaining area of ​​the second gate trench CGt after the control gate dielectric film 132 has been filled.

[0080] Viewed from a plane parallel to the first surface 100a, at least a portion of the photoelectric conversion region 101 may be positioned between the transmission gate structure TGS and the control gate structure CGS. For example, as Figure 2 As shown, from a planar perspective, a portion of the photoelectric conversion region 101 can be positioned diagonally between the transmission gate structure TGS and the control gate structure CGS in the direction between the first direction X and the second direction Y.

[0081] In some embodiments, at least a portion of the control gate structure CGS may contact a side surface of the photoelectric conversion region 101. For example, the photoelectric conversion region 101 may include a first side surface 101a and a second side surface 101b that intersect each other. As an example, the first side surface 101a may intersect a first direction X, and the second side surface 101b may intersect a second direction Y. A second gate trench CGt may contact at least one of the first side surface 101a and the second side surface 101b. In some embodiments, the second gate trench CGt may contact both the first side surface 101a and the second side surface 101b.

[0082] In some embodiments, a portion of the control gate structure CGS may be stacked with the photoelectric conversion region 101 in the third direction Z, and another portion of the control gate structure CGS may not be stacked with the photoelectric conversion region 101 in the third direction Z. For example, as Figure 2 As shown, from a planar perspective, the photoelectric conversion region 101 may not completely surround the control gate structure CGS.

[0083] In some embodiments, the control gate electrode CG may include a second lower electrode CGa and a second upper electrode CGb. The second lower electrode CGa may be disposed within the second gate trench CGt. The second upper electrode CGb is connected to the second lower electrode CGa and may protrude beyond the first surface 100a. That is, the second lower electrode CGa may be a region of the control gate electrode CG located in the first substrate 100, and the second upper electrode CGb may be a region of the control gate electrode CG located outside the first substrate 100. For example, the control gate structure CGS may include a second lower portion extending into the substrate 100 and a second upper portion protruding beyond the first surface 100a. In some embodiments, the element separation pattern 110 may be located between the first lower portion and the second lower portion.

[0084] In some implementations, a positive (+) bias voltage can be applied to the control gate electrode CG during the cutoff operation of the transfer gate structure TGS. Therefore, the full-well capacity (FWC) of the photoelectric conversion element PD due to the photoelectric conversion region 101 can be increased. This will be discussed later. Figure 5 It is described in more detail in the description.

[0085] In some implementations, the voltage applied to the control gate electrode CG during the turn-on operation of the transfer gate structure TGS may be lower than the voltage applied to the control gate electrode CG during the turn-off operation of the transfer gate structure TGS. As an example, a negative (-) bias voltage may be applied to the control gate electrode CG during the turn-on operation of the transfer gate structure TGS.

[0086] The control gate dielectric film 132 may be disposed between the first substrate 100 and the second lower electrode CGa, and between the first substrate 100 and the second upper electrode CGb. The control gate spacer 137 may extend along the side surface of the second upper electrode CGb.

[0087] In some embodiments, with reference to the first surface 100a, the depth at which the control gate structure CGS is formed can be greater than the depth at which the transfer gate structure TGS is formed. For example, as Figure 3 As shown, with the first surface 100a as a reference, the depth D1 of the first gate trench TGt can be less than the depth D2 of the second gate trench CGt.

[0088] In some implementations, one end of the control gate structure CGS (e.g., Figure 3 The upper end of the control gate structure CGS in the photoelectric conversion region 101 can be located at a horizontal level between the upper surface and the lower surface of the photoelectric conversion region 101. For example, as Figure 3 As shown, with the first surface 100a as a reference, the depth D2 of the second gate trench CGt can be greater than the minimum depth at which the photoelectric conversion region 101 is formed (e.g., Figure 3 The distance between the first surface 100a and the lower surface of the photoelectric conversion region 101, and may be less than the maximum depth at which the photoelectric conversion region 101 is formed (e.g., Figure 3 The distance between the first surface 100a and the upper surface of the photoelectric conversion region 101.

[0089] In some embodiments, the depth D2 of the second gate trench CGt can be about 10% to about 50% or about 20% to about 30% of the height of the first substrate 100 (or its thickness in the third direction Z). For example, when the thickness of the first substrate 100 in the third direction Z is about 4 μm, the depth D2 of the second gate trench CGt can be about 0.4 μm to about 2 μm, or about 0.8 μm to about 1.2 μm. The control performance and fabrication complexity required to control the gate electrode CG can be efficiently provided within these ranges.

[0090] In some embodiments, the width of the first lower portion of the transmission gate structure TGS at the first surface 100a in the first direction X can vary between 90% and 110% of the width of the second lower portion of the control gate structure CGS at the first surface 100a in the first direction X.

[0091] In some embodiments, the width of the first lower portion of the transmission gate structure TGS at the first surface 100a in the first direction X can vary between 95% and 105% of the width of the second lower portion of the control gate structure CGS at the first surface 100a in the first direction X.

[0092] In some embodiments, the width of the first upper portion of the transmission gate structure TGS at the first surface 100a in the first direction X can vary between 90% and 110% of the width of the second upper portion of the control gate structure CGS at the first surface 100a in the first direction X.

[0093] In some embodiments, the width of the first upper portion of the transmission gate structure TGS at the first surface 100a in the first direction X can vary between 95% and 105% of the width of the second upper portion of the control gate structure CGS at the first surface 100a in the first direction X.

[0094] A first wiring structure 140 may be formed on a first surface 100a of a first substrate 100. The first wiring structure 140 may include a plurality of wiring patterns. For example, the first wiring structure 140 may include a first inter-wiring insulating film 142 on the first surface 100a and a first wiring pattern 144 in the first inter-wiring insulating film 142. Figure 3 and Figure 4 In this context, the shape, arrangement, number of layers, etc. of the first wiring pattern 144 are merely exemplary and are not limited thereto.

[0095] The first wiring structure 140 can be electrically connected to the first impurity region 102, the second impurity region 104, the transfer gate structure TGS, and / or the control gate structure CGS.

[0096] For example, a first source / drain contact CA1 connected to the first impurity region 102 may be formed inside the first inter-wiring insulating film 142. The first wiring pattern 144 may be electrically connected to the first impurity region 102 via the first source / drain contact CA1.

[0097] For example, a second source / drain contact CA2 connected to the second impurity region 104 may be formed in the first inter-wiring insulating film 142. The first wiring pattern 144 may be electrically connected to the second impurity region 104 via the second source / drain contact CA2.

[0098] For example, a first gate contact CB1 connected to the transmission gate electrode TG can be formed in the first inter-wiring insulating film 142. The first wiring pattern 144 can be electrically connected to the transmission gate structure TGS through the first gate contact CB1.

[0099] For example, a second gate contact CB2 connected to the control gate electrode CG may be formed in the first inter-wiring insulating film 142. The first wiring pattern 144 may be electrically connected to the control gate structure CGS via the second gate contact CB2. In some embodiments, the control gate structure CGS may be configured to receive a voltage from the second gate contact CB2 (e.g., a voltage may be applied to the control gate electrode CG of the control gate structure CGS).

[0100] A surface insulating film 150 may be formed on a second surface 100b of the first substrate 100. The surface insulating film 150 may extend conformally along the second surface 100b of the first substrate 100. The surface insulating film 150 may include at least one of insulating materials (e.g., but not limited to silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof).

[0101] The surface insulating film 150 is configured as an anti-reflective film and prevents the reflection of light incident on the second surface 100b, which serves as a light-receiving surface. Therefore, the light reception efficiency of the photoelectric conversion region 101 can be improved. Optionally, the surface insulating film 150 is configured as a planarization film, which can facilitate the formation of color filters 180, microlenses 190, etc., at a consistent height.

[0102] In some embodiments, the surface insulating film 150 may be formed of a multilayer film. As an example, unlike the example shown, the surface insulating film 150 may include an alumina film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film sequentially stacked on the second surface 100b of the first substrate 100.

[0103] The mesh film 160 may be formed on the surface insulating film 150. Viewed from a planar perspective (e.g., the XY plane), the mesh film 160 may be formed in a grid shape. For example, the mesh film 160 may be configured to overlap at least a portion of the PD separation pattern 120 in the third direction Z.

[0104] In some embodiments, the mesh film 160 may include a first mesh film 162 and a second mesh film 164. The first mesh film 162 and the second mesh film 164 may be stacked sequentially on the surface insulating film 150.

[0105] The first mesh film 162 may include, for example, but not limited to, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. The first mesh film 162 can prevent the accumulation of charges generated by ESD (electrostatic discharge) on the surface of the first substrate 100 (e.g., the second surface 100b) to effectively prevent ESD damage defects.

[0106] The second mesh film 164 may include a low refractive index material having a refractive index lower than that of silicon (Si). For example, the second mesh film 164 may include, but is not limited to, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. The second mesh film 164 can improve the light collection efficiency of each unit pixel PX by refracting or reflecting light that is obliquely incident on the second surface 100b, which serves as a light receiving surface.

[0107] A first protective film 166 may be formed on the surface insulating film 150 and the mesh film 160. The first protective film 166 may extend conformally along the contours of the surface insulating film 150 and the mesh film 160. The first protective film 166 may prevent damage to the surface insulating film 150 and the mesh film 160. The first protective film 166 may include, for example, but not limited to, aluminum oxide (AlO).

[0108] Color filter 180 may be formed on the first protective film 166. Color filter 180 may have various colors depending on the unit pixel. For example, color filter 180 may include a red color filter, a green color filter, a blue color filter, a yellow color filter, a magenta color filter, and a cyan color filter, and may also include a white color filter.

[0109] Microlens 190 may be formed on color filter 180. Microlens 190 has a convex shape and may have a predetermined radius of curvature. Therefore, microlens 190 can collect light incident on a unit pixel PX. Microlens 190 may include, for example, but not limited to, a light-transmitting resin.

[0110] A second protective film 195 may be formed on the microlens 190. The second protective film 195 may extend along the surface of the microlens 190. The second protective film 195 may include, for example, but not limited to, an inorganic oxide film (such as a silicon oxide film, a titanium oxide film, a zirconium oxide film, or a hafnium oxide film). As an example, the second protective film 195 may include a low-temperature oxide (LTO).

[0111] The second protective film 195 protects the microlens 190 from external influences. For example, the second protective film 195 can protect the microlens 190 containing organic materials by including an inorganic oxide film. Furthermore, the second protective film 195 can improve the quality of the image sensor by increasing the light collection efficiency of the microlens 190. For example, the second protective film 195 can reduce reflection, refraction, scattering, etc., of incident light reaching the space between the microlenses 190 by filling the space between the microlenses 190.

[0112] Figure 5 This is a graph used to explain the performance of an image sensor according to some implementations. For reference, in Figure 5In the diagram, the horizontal axis represents the depth of the first substrate 100 measured between the first surface 100a and the second surface 100b, and the vertical axis represents the electrostatic potential of the first substrate 100. That is, Figure 5 The change in electrostatic potential based on the depth of the first substrate 100 is shown. Furthermore, in Figure 5 In the comparative example, measurements were taken in the off state of the transmission transistor TX for a unit pixel that does not have a control gate structure CGS, and in the experimental example, measurements were taken in the off state of the transmission transistor TX for a unit pixel that has a positive (+) bias voltage applied to the control gate electrode CG.

[0113] Reference Figures 1 to 5 The control gate structure CGS can use the voltage applied to the control gate electrode CG to control the electrostatic potential of the first substrate 100.

[0114] Specifically, such as Figure 5 As shown, the photoelectric conversion region 101 in the first substrate 100 may include a potential control region CGR. The potential control region CGR may be a portion of the photoelectric conversion region 101 adjacent to the control gate structure CGS. The first substrate 100 may also include a channel region TGR between the photoelectric conversion region 101 and the floating diffusion region FD. When Comparative Example 1 is compared with Experimental Example 1, it is confirmed that the electrostatic potential of the potential control region CGR is significantly improved when a positive (+) bias voltage is applied to the control gate electrode CG. As a result, in the off state of the transfer transistor TX, the difference between the electrostatic potential of the channel region TGR and the electrostatic potential of the potential control region CGR increases, and the full-well capacity (FWC) of the photoelectric conversion element PD due to the photoelectric conversion region 101 is improved.

[0115] Due to the ever-increasing need for miniaturization of individual pixels, ensuring field-weighted charge (FWC), the total amount of charge that a photoelectric conversion element can hold in a single pixel, becomes difficult. For example, increasing the doping concentration in the photoelectric conversion region can achieve high FWC in miniaturized pixels, but the resulting increased process dispersion leads to reduced productivity of image sensors.

[0116] Image sensors according to some embodiments can provide improved performance even in miniaturized unit pixels using a control gate structure (CGS). Specifically, as described above... Figure 5 As described, the control gate structure CGS can provide an enhanced FWC by using the voltage applied to the control gate electrode CG.

[0117] Furthermore, in some embodiments, the control gate structure CGS can use the voltage applied to the control gate electrode CG to improve the transmission efficiency of the transmission transistor TX. For example, a negative (-) bias voltage can be applied to the control gate electrode CG during the conduction operation of the transmission transistor TX. Therefore, the charge (i.e., electrons) generated from the photoelectric conversion element PD can be pushed out of the control gate structure CGS and more easily sent toward the floating diffusion region FD.

[0118] Figure 6 and Figure 7 These are cross-sectional views used to explain various embodiments of image sensors. For ease of explanation, the above will be briefly explained or omitted. Figures 1 to 5 The repeated parts of the description.

[0119] Reference Figure 1 , Figure 2 and Figure 6 In an image sensor according to some embodiments, one end of the control gate structure CGS (e.g., Figure 6 The upper end of the control gate structure CGS is located at the horizontal position between the photoelectric conversion region 101 and the second surface 100b.

[0120] For example, as shown in the figure, with the first surface 100a as a reference, the depth D2 of the second gate trench CGt can be greater than the maximum depth at which the photoelectric conversion region 101 is formed (for example, the first surface 100a and...). Figure 6 The distance between the upper surfaces of the photoelectric conversion regions 101 in the first substrate 100 can be less than the thickness of the first substrate 100. In this case, the area of ​​the photoelectric conversion regions 101 adjacent to the control gate structure CGS is increased, and the electrostatic potential of the first substrate 100 can be controlled more effectively.

[0121] Reference Figure 1 , Figure 2 and Figure 7 In an image sensor according to some embodiments, a control gate structure CGS penetrates a first substrate 100.

[0122] For example, as shown in the figure, the control gate structure CGS can be adjacent to (or in contact with) both the first surface 100a and the second surface 100b. In this case, the area of ​​the photoelectric conversion region 101 adjacent to the control gate structure CGS is increased, and the electrostatic potential of the first substrate 100 can be controlled more effectively.

[0123] Figure 8 It is a planar diagram used to explain the pixel array of an image sensor according to some embodiments. Figure 9 It is along Figure 8 A schematic cross-sectional view taken from a CC-based image. For ease of explanation, the above usage is briefly explained or omitted. Figures 1 to 7 The repeated parts of the description.

[0124] Reference Figure 1 , Figure 8 and Figure 9 In an image sensor according to some embodiments, the control gate structure CGS is completely superimposed on the photoelectric conversion region 101 in the third direction Z.

[0125] For example, such as Figure 8 As shown, from a planar viewpoint, the photoelectric conversion region 101 can completely surround the control gate structure CGS. In this case, the region of the photoelectric conversion region 101 adjacent to the control gate structure CGS is increased, and the electrostatic potential of the first substrate 100 can be more effectively controlled.

[0126] Figures 10 to 13 These are various planar diagrams used to explain the pixel arrays of image sensors according to some embodiments. For ease of explanation, the above will be briefly explained or omitted. Figures 1 to 9 The repeated parts of the description.

[0127] Reference Figure 1 and Figure 10 In an image sensor according to some embodiments, the control gate electrode CG includes a first extension GP1 and a second extension GP2 that intersect each other.

[0128] For example, the first extension GP1 may extend elongatedly in the second direction Y, and the second extension GP2 may extend elongatedly in the first direction X. In some embodiments, the first extension GP1 may be adjacent to the first side surface 101a of the photoelectric conversion region 101. In some embodiments, the second extension GP2 may be adjacent to the second side surface 101b of the photoelectric conversion region 101. From a planar viewpoint, the first extension GP1 and the second extension GP2 may extend along the periphery of the photoelectric conversion region 101 in an overall "L" shape. In this case, the area of ​​the photoelectric conversion region 101 adjacent to the control gate electrode CG is increased, and the electrostatic potential of the first substrate 100 can be more effectively controlled.

[0129] Reference Figure 1 and Figure 11 In an image sensor according to some embodiments, the first extension GP1 and the second extension GP2 may extend to different lengths from each other.

[0130] For example, the length L1 of the first extension GP1 extending in the second direction Y may be shorter than the length L2 of the second extension GP2 extending in the first direction X. In some embodiments, the second active pattern AP2 may be arranged together with the first extension GP1 along the second direction Y. In this case, the space efficiency of the control gate electrode CG in the miniaturized unit pixel PX can be enhanced.

[0131] Reference Figure 1 and Figure 12 In an image sensor according to some embodiments, the control gate electrode CG also includes a third extension GP3.

[0132] The third extension GP3 may face the first extension GP1. For example, each of the first extension GP1 and the third extension GP3 may extend from both ends of the second extension GP2 in the second direction Y. In some embodiments, the photoelectric conversion region 101 may also include a third side surface 101c opposite to the first side surface 101a. As an example, the third side surface 101c may intersect the first direction X. The third extension GP3 may be adjacent to the third side surface 101c. From a planar viewpoint, the first extension GP1, the second extension GP2, and the third extension GP3 may extend along the periphery of the photoelectric conversion region 101 in an overall "C" shape. In this case, the area of ​​the photoelectric conversion region 101 adjacent to the control gate electrode CG is increased, and the electrostatic potential of the first substrate 100 can be controlled more effectively.

[0133] Reference Figure 1 and Figure 13 According to some embodiments, the image sensor also includes a third impurity region 106 and a pixel gate electrode PG.

[0134] For example, the active regions AP1, AP2, and AP3 of each of the pixel regions PX1 to PX4 may also include a third active pattern AP3. The third active pattern AP3 can be separated from the first active pattern AP1 and the second active pattern AP2 by the element separation pattern 110. A third impurity region 106 may be formed in the third active pattern AP3. The shape, size, number, arrangement, etc. of the active regions AP1, AP2, and AP3 are merely exemplary and are not limited to those shown in the figures.

[0135] The third impurity region 106 may have a second conductivity type. For example, the third impurity region 106 may be an n-type impurity region formed by implanting n-type impurity ions into the third active pattern AP3. The third impurity region 106 may be spaced apart from the photoelectric conversion region 101.

[0136] A pixel gate electrode PG may be formed on a third active pattern AP3. The pixel gate electrode PG may be adjacent to a third impurity region 106. For example, the third impurity region 106 may be formed in the third active pattern AP3 on a side surface of the pixel gate electrode PG.

[0137] The pixel gate electrode PG may include various transistors for processing electrical signals generated from the photoelectric conversion element PD through the photoelectric conversion region 101. For example, the pixel gate electrode PG may be configured as follows: Figure 1 The gate of at least one of the reset transistor RX, the dual conversion gain transistor DCX, and the select transistor SX.

[0138] Figure 14 and Figure 15 These are various layout diagrams used to explain the pixel arrays of image sensors according to some embodiments. For ease of explanation, the above will be briefly explained or omitted. Figures 1 to 13 The repeated parts of the description.

[0139] Reference Figure 14 and Figure 15 According to some embodiments, the image sensor includes multiple pixel groups PG1 to PG4.

[0140] For example, pixel groups PG1 to PG4 may include a first pixel group PG1, a second pixel group PG2, a third pixel group PG3, and a fourth pixel group PG4 that are adjacent to each other. The first pixel group PG1 and the second pixel group PG2 may be adjacent to each other in a first direction X. The first pixel group PG1 and the third pixel group PG3 may be adjacent to each other in a second direction Y that intersects the first direction X. The second pixel group PG2 and the fourth pixel group PG4 may be adjacent to each other in the second direction Y, and the third pixel group PG3 and the fourth pixel group PG4 may be adjacent to each other in the first direction X. That is, the first pixel group PG1 and the fourth pixel group PG4 may be adjacent to each other in the diagonal direction between the first direction X and the second direction Y.

[0141] Each of pixel groups PG1 through PG4 may include multiple unit pixels (PX). For example, each of pixel groups PG1 through PG4 may include the above-mentioned... Figures 1 to 5 The pixel regions described are PX1 to PX4.

[0142] In some implementations, pixel regions PX1 to PX4 in each of pixel groups PG1 to PG4 may share a color filter 180 of the same color. Furthermore, adjacent pixel groups PG1 to PG4 may have color filters 180 of different colors. For example, pixel groups PG1 to PG4 may include color filters 180 arranged in a Bayer pattern. As an example, a second pixel group PG2 may include a red color filter 180B, and a third pixel group PG3 may include a blue color filter 180C. The first pixel group PG1 and the fourth pixel group PG4 may include green color filters 180A and 180D, respectively.

[0143] Reference Figure 15 In an image sensor according to some embodiments, pixel regions PX1 to PX4 included in each of pixel groups PG1 to PG4 may share a microlens 190.

[0144] For example, multiple microlenses 190 may be arranged to correspond to multiple pixel groups PG1 to PG4. Thus, each of the pixel groups PG1 to PG4 can provide an autofocus (AF) function. As an example, the first pixel group PG1 can use a photoelectric conversion region 101 divided into pixel regions PX1 to PX4 to provide a phase detection AF (PDAF) function.

[0145] Figure 16 This is a schematic exploded perspective view used to explain an image sensor according to some embodiments. Figure 17 It is used for explanation Figure 16 A schematic cross-sectional view of an image sensor. For ease of explanation, the above will be briefly explained or omitted. Figures 1 to 15 The repeated parts of the description.

[0146] Reference Figure 16 and Figure 17 According to some embodiments, the image sensor includes a first stack ST1, a second stack ST2, and a third stack ST3 stacked in sequence.

[0147] The first stack ST1 may include a first substrate 100. Additionally, the first stack ST1 may include a plurality of upper pixels UP1, each including a photoelectric conversion region 101 in the first substrate 100. For example, the first stack ST1 may include the above-described... Figures 1 to 5 The first substrate 100, the element separation pattern 110, the PD separation pattern 120, the photoelectric conversion region 101, the first impurity region 102, the second impurity region 104, the transfer gate structure TGS, the control gate structure CGS, the first wiring structure 140, the surface insulating film 150, the mesh film 160, the color filter 180, and the microlens 190 are described.

[0148] The second stack ST2 may include a plurality of lower pixels UP2 corresponding to a plurality of upper pixels UP1. The upper pixels UP1 and the lower pixels UP2 may form a unit pixel PX. For example, the second stack ST2 may include a second substrate 200, a fourth impurity region 202, a pixel gate structure PGS, and a second wiring structure 240.

[0149] The second substrate 200 may be a semiconductor substrate. For example, the second substrate 200 may be bulk silicon or silicon-on-insulator (SOI). The second substrate 200 may be a silicon substrate, or may include other materials (e.g., silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide). Optionally, the second substrate 200 may be a substrate in which an epitaxial layer is formed on a base substrate.

[0150] The second substrate 200 may include a third surface 200a and a fourth surface 200b opposite to each other. In the embodiments described below, the third surface 200a is also referred to as the front side of the second substrate 200, and the fourth surface 200b may be referred to as the back side of the second substrate 200.

[0151] The fourth impurity region 202 may be formed in the second substrate 200 adjacent to the third surface 200a. For example, the fourth impurity region 202 may be an n-type impurity region formed by implanting n-type impurity ions into the second substrate 200.

[0152] A pixel gate structure PGS may be formed on a third surface 200a of the second substrate 200. The pixel gate structure PGS may be adjacent to a fourth impurity region 202. For example, the fourth impurity region 202 may be formed in the second substrate 200 on a side surface of the pixel gate structure PGS.

[0153] In some implementations, the pixel gate structure PGS may include a pixel gate dielectric film 230 and a pixel gate electrode PG.

[0154] The pixel gate dielectric film 230 may be disposed between the second substrate 200 and the pixel gate electrode PG. The pixel gate dielectric film 230 may include at least one of a dielectric material (e.g., silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide). The pixel gate dielectric film 230 may include the same material as the transport gate dielectric film 131, or it may include a different material from the transport gate dielectric film 131.

[0155] The pixel gate electrode PG can be stacked on the pixel gate dielectric film 230. The pixel gate electrode PG may include a conductive material, such as, but not limited to, at least one of a metal film, a metal silicide film, an undoped polysilicon film, an undoped silicon-germanium film, a doped polysilicon film, and a doped silicon-germanium film. The pixel gate electrode PG may be made of the same material as the transport gate electrode TG, or it may be made of a different material than the transport gate electrode TG. The pixel gate electrode PG may be configured as follows: Figure 1 The gate of at least one of the reset transistor RX, the dual conversion gain transistor DCX, and the select transistor SX. As an example, the first impurity region 102 of the first stack ST1, which is configured as a floating diffusion region FD, may be electrically connected to the fourth impurity region 202 of the second stack ST2 and / or the pixel gate electrode PG of the second stack ST2.

[0156] The second wiring structure 240 may be formed on the third surface 200a of the second substrate 200. The second wiring structure 240 may include multiple wiring patterns. For example, the second wiring structure 240 may include a second inter-wiring insulating film 242 on the third surface 200a and a second wiring pattern 244 in the second inter-wiring insulating film 242. The second wiring structure 240 may be electrically connected to the fourth impurity region 202 and / or the pixel gate structure PGS. Figure 17 In this context, the shape, arrangement, number of layers, etc. of the second wiring pattern 244 are merely exemplary and are not limited thereto.

[0157] In some embodiments, the first stack ST1 and the second stack ST2 can be stacked in a C2C (chip-to-chip) structure. A C2C structure can mean a structure in which an upper chip including the first stack ST1 is fabricated on a first wafer and a lower chip including the second stack ST2 is fabricated on a second wafer different from the first wafer, and the upper and lower chips are then connected to each other by bonding.

[0158] As an example, the bonding method can refer to the way in which the first bonding metal BM1 of the upper chip and the second bonding metal BM2 of the lower chip are connected to each other. For example, when the first bonding metal BM1 and the second bonding metal BM2 are formed of copper (Cu), the bonding method can be a Cu-Cu bonding method. However, this is merely exemplary, and it goes without saying that the first bonding metal BM1 and the second bonding metal BM2 can be formed of various other metals (such as aluminum (Al) or tungsten (W)). When the first bonding metal BM1 and the second bonding metal BM2 are bonded, the first stack ST1 and the second stack ST2 can be electrically connected to each other.

[0159] In some embodiments, the fourth surface 200b of the second substrate 200 may face the first surface 100a of the first substrate 100. For example, the first stack ST1 and the second stack ST2 may be joined in a front-to-back (F2B) manner.

[0160] In some embodiments, a buried insulating film BI may be formed on a fourth surface 200b of the second substrate 200. The buried insulating film BI may be disposed between the second substrate 200 and the first wiring structure 140. For example, the second substrate 200 may be a silicon-on-insulator (SOI) substrate on the buried insulating film BI. A second bonding metal BM2 may be formed in the buried insulating film BI.

[0161] In some embodiments, the second stack ST2 may further include a through-via TV. The through-via TV penetrates the second substrate 200 to electrically connect the second wiring structure 240 and the second bonding metal BM2. For example, an insulating pattern 220 may be formed in the second substrate 200. The insulating pattern 220 may form an insulating region in the second substrate 200. The through-via TV penetrates the insulating pattern 220 to connect the second wiring structure 240 and the second bonding metal BM2.

[0162] The third stack ST3 may include a third substrate 300, logic circuit elements LC, and a third wiring structure 340.

[0163] The third substrate 300 may be a semiconductor substrate. For example, the third substrate 300 may be bulk silicon or silicon-on-insulator (SOI). The third substrate 300 may be a silicon substrate or may include other materials (e.g., silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide). Optionally, the third substrate 300 may be a substrate in which an epitaxial layer is formed on a base substrate.

[0164] The third substrate 300 may include a fifth surface 300a and a sixth surface 300b opposite to each other. In the embodiments described below, the fifth surface 300a may also be referred to as the front side of the third substrate 300, and the sixth surface 300b may also be referred to as the back side of the third substrate 300.

[0165] Logic circuit elements LC may be formed on the fifth surface 300a of the third substrate 300. Logic circuit elements LC may include, but are not limited to, logic circuits (e.g., power supply circuits, input / output interfaces, and / or image signal processors) for controlling each unit pixel PX.

[0166] A third wiring structure 340 may be formed on a fifth surface 300a of a third substrate 300. The third wiring structure 340 may include multiple wiring patterns. For example, the third wiring structure 340 may include a third inter-wiring insulating film 342 on the fifth surface 300a and a third wiring pattern 344 within the third inter-wiring insulating film 342. The third wiring structure 340 may be electrically connected to a logic circuit element LC. Figure 17 In this context, the shape, arrangement, number of layers, etc. of the third wiring pattern 344 are merely exemplary and are not limited thereto.

[0167] In some implementations, the second stack ST2 and the third stack ST3 can be stacked in a C2C (chip-to-chip) structure. A C2C structure means a structure in which an upper chip including the second stack ST2 is fabricated on a second wafer, a lower chip including the third stack ST3 is fabricated on a third wafer different from the second wafer, and the upper and lower chips are then connected to each other by bonding.

[0168] As an example, the bonding method can refer to the way the third bonding metal BM3 of the upper chip and the fourth bonding metal BM4 of the lower chip are connected to each other. For example, when the third bonding metal BM3 and the fourth bonding metal BM4 are formed of copper (Cu), the bonding method can be a Cu-Cu bonding method. However, this is merely exemplary, and it goes without saying that the third bonding metal BM3 and the fourth bonding metal BM4 can be formed of various other metals (such as aluminum (Al) or tungsten (W)). When the third bonding metal BM3 and the fourth bonding metal BM4 are bonded, the second stack ST2 and the third stack ST3 can be electrically connected to each other.

[0169] In some embodiments, the fifth surface 300a of the third substrate 300 may face the third surface 200a of the second substrate 200. For example, the second stack ST2 and the third stack ST3 may be joined in a front-to-front (F2F) manner.

[0170] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims. Specific features described in the context of individual implementations in this disclosure may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may refer to a sub-combination or a variation of the sub-combination.

Claims

1. An image sensor, comprising: The substrate includes a first surface and a second surface opposite to the first surface; The first pixel region includes the first photoelectric conversion region in the substrate; The second pixel region includes the second photoelectric conversion region in the substrate; A photoelectric conversion region separation pattern is located between the first photoelectric conversion region and the second photoelectric conversion region; A transmission gate structure includes a first lower portion extending from a first surface into a substrate and a first upper portion protruding beyond the first surface; as well as The control gate structure includes a second lower portion extending from a first surface into the substrate and a second upper portion protruding beyond the first surface. In this process, the photoelectric conversion region separation pattern penetrates the substrate. The first upper part is spaced apart from the second upper part in a first direction parallel to the first surface. The transmission gate structure and the control gate structure are disposed in the first pixel region, and The second surface is configured to receive light.

2. The image sensor according to claim 1, further comprising: The first contact is perpendicularly connected to the transmission gate structure in a second direction perpendicular to the first direction; as well as The second contact is vertically connected to the control gate structure in the second direction. The first contact element is spaced apart from the second contact element in a first direction.

3. The image sensor according to claim 2, further comprising: The wiring structure includes multiple wiring patterns, wherein the multiple wiring patterns include a first wiring pattern and a second wiring pattern. Among the plurality of wiring patterns, the first wiring pattern and the second wiring pattern are positioned at the closest distance to the first surface in the second direction. The first contact is directly connected to the first wiring pattern, and The second contact is directly connected to the second wiring pattern.

4. The image sensor according to claim 2, wherein, The control gate structure is configured to receive voltage from the second contact.

5. The image sensor according to claim 1, wherein, The first lower part has a first height from the first surface in a second direction perpendicular to the first direction. The second lower part has a second height from the first surface in the second direction, and The first altitude is different from the second altitude.

6. The image sensor according to claim 5, wherein, The second altitude is greater than the first altitude.

7. The image sensor according to claim 1, wherein, The width of the first lower part at the first surface in the first direction varies between 90% and 110% of the width of the second lower part at the first surface in the first direction.

8. The image sensor according to claim 7, wherein, The width of the first lower part at the first surface in the first direction varies between 95% and 105% of the width of the second lower part at the first surface in the first direction.

9. The image sensor according to claim 1, further comprising: The component separation pattern is located between the first lower part and the second lower part.

10. The image sensor according to claim 9, wherein, The first lower part has a first height from the first surface in a second direction perpendicular to the first direction. The component separation pattern has a second height from the first surface in the second direction, and The first altitude is greater than the second altitude.

11. The image sensor according to claim 1, wherein, The width of the first upper part at the first surface in the first direction varies between 90% and 110% of the width of the second upper part at the first surface in the first direction.

12. The image sensor according to claim 10, wherein, The width of the first upper part at the first surface in the first direction varies between 95% and 105% of the width of the second upper part at the first surface in the first direction.

13. An image sensor, comprising: The substrate includes a first surface and a second surface opposite to the first surface; The first pixel region includes the first photoelectric conversion region in the substrate; The second pixel region includes the second photoelectric conversion region in the substrate; The third pixel region includes the third photoelectric conversion region in the substrate; The fourth pixel region includes the fourth photoelectric conversion region in the substrate; A photoelectric conversion region separation pattern separates the first to fourth photoelectric conversion regions from each other. A single color filter is located in the first to fourth photoelectric conversion regions; The floating diffusion region is configured to store photocharge generated from the first photoelectric conversion region to the fourth photoelectric conversion region; A first transmission gate structure includes a first lower portion extending from a first surface into a substrate and a first upper portion protruding beyond the first surface; as well as The first control gate structure includes a second lower portion extending from a first surface into a substrate and a second upper portion protruding beyond the first surface. In this process, the photoelectric conversion region separation pattern penetrates the substrate. The first upper part is spaced apart from the second upper part in a first direction parallel to the first surface. The first transmission gate structure and the first control gate structure are disposed in the first pixel region. In this diagram, the first to fourth pixel regions are arranged sequentially in a clockwise direction, and The second surface is configured to receive light.

14. The image sensor according to claim 13, further comprising: A second transmission gate structure is disposed in the second pixel region, wherein the first transmission gate structure is disposed in the lower right corner region of the first pixel region in the plan view, and In the planar view, the second transmission gate structure is located in the upper left corner of the second pixel region.

15. The image sensor according to claim 14, wherein, The second pixel region is adjacent to the first pixel region in the second direction, and The first direction is neither parallel nor perpendicular to the second direction.

16. The image sensor according to claim 15, further comprising: The first contact is vertically connected to the first transmission gate structure in a third direction perpendicular to the first direction. as well as The second contact is vertically connected to the first control gate structure from the third direction upwards. The first contact element is spaced apart from the second contact element in a first direction.

17. The image sensor of claim 16, further comprising: The wiring structure includes multiple wiring patterns, wherein the multiple wiring patterns include a first wiring pattern and a second wiring pattern. Among the plurality of wiring patterns, the first wiring pattern and the second wiring pattern are positioned at the distance closest to the first surface in the upward direction from the third surface. The first contact is directly connected to the first wiring pattern, and The second contact is directly connected to the second wiring pattern.

18. The image sensor according to claim 17, wherein, The first control gate structure is configured to receive voltage from the second contact.

19. The image sensor according to claim 18, wherein, The first lower part has a first height from the first surface in a third direction. The second lower part has a second height from the first surface in a third direction, and The first altitude is different from the second altitude.

20. The image sensor according to claim 19, wherein, The second altitude is greater than the first altitude.

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