Complementary spin valve device and spin logic circuit

Abstract

The invention discloses a complementary spin valve device and a spin logic circuit. The complementary spin valve device comprises a positive spin valve and a negative spin valve; the structure of the positive spin valve sequentially comprises a top electrode, a semiconductor layer, an interface layer and a bottom electrode from top to bottom. The structure of the negative spin valve sequentially comprises a top electrode, an oxide layer, a semiconductor layer, an interface layer and a bottom electrode from top to bottom, and the top electrode and the bottom electrode in the positive spin valve and the negative spin valve are made of metal iron, cobalt, nickel or a mixture or alloy of any two or three of the metal iron, the cobalt and the nickel. The positive / negative spin valve device is obtained by accurately adjusting the oxide layer of the spin valve device, the complementary magnetic response of the positive / negative organic spin valve under the same magnetic field condition is ensured, and the blank of the complementary device based on electron spin transmission is filled. According to the spin logic gate, breakthrough high gain and high noise margin are achieved, the outstanding cycling stability is achieved, and a new path is created for development of storage and calculation integrated devices.

Description

Technical Field

[0001] This invention relates to a complementary spin valve device and a spin logic circuit, belonging to the fields of semiconductor devices and organic spintronics. Background Technology

[0002] The complementarity of Complementary Metal-Oxide-Semiconductor (CMOS) is the cornerstone of chips. Based on electron charge transport, it has wide applications in fields such as Central Processing Units (CPUs) and Graphics Processing Units (GPUs). However, as Moore's Law approaches its physical limits, there is an urgent need to develop new devices and architectures with dual or multi-dimensional control mechanisms. Spin valve devices have the potential to integrate both electron charge transport and spin transport mechanisms within a single device. Exploring spin-based complementary operation principles and constructing spin logic circuits to improve computing power is of great significance for "going beyond Moore's Law".

[0003] Constructing spin valve devices with complementary structures is a prerequisite for realizing complete spin logic circuits. However, ferromagnetic electrodes respond uniformly to magnetic fields and do not exhibit complementary or opposite responses. Therefore, traditional spin valve devices lack complementary pairs with opposite switching states under the same magnetic field, a limitation that hinders the development of complementary spin valves. This invention is therefore proposed. Summary of the Invention

[0004] One object of the present invention is to control the Ni electrode layer 80 Fe 20 The oxidation coverage of Ox precisely modulates the spin filtering effect at the spin interface, thereby constructing a complementary framework for organic spin valves, namely the positive organic spin valve (POSV) and the negative organic spin valve (NOSV).

[0005] Another objective of this invention is to realize complete spin manipulation logic using spin devices with complementary magnetic responses, constructing an all-spin valve logic gate. Specifically, the all-spin valve logic NOT gate prepared in this invention, which also functions as a spin inverter, features an ultra-low drive voltage of 20mV, achieves an unprecedented high gain of 142 and a high noise margin of 85%, and exhibits excellent stability (maintaining 99.84% operational stability over 8,500 cycles). These results highlight the potential of spin-based technologies to overcome the limitations of traditional charge-based technologies, and hold promise for breakthroughs in computing technology.

[0006] The complementary spin valve device provided by the present invention includes a positive spin valve and a negative spin valve;

[0007] The structure of the positive spin valve, from top to bottom, includes: a top electrode, a semiconductor layer, an interface layer, and a bottom electrode.

[0008] The structure of the negative spin valve, from top to bottom, includes a top electrode, an oxide layer, a semiconductor layer, an interface layer, and a bottom electrode.

[0009] The top electrode and the bottom electrode in the positive spin valve and the negative spin valve are both made of metallic iron, cobalt, nickel, or any two or three of them, or a mixture or alloy thereof.

[0010] The top electrode and the bottom electrode are prepared by any one of molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, and lift-off.

[0011] The thickness of the top electrode and the bottom electrode is 1 to 100 nm.

[0012] The interface layer in the positive spin valve and the negative spin valve is made of any one of magnesium oxide, aluminum oxide, gallium nitride, graphene, and barium titanate.

[0013] The interface layer is prepared by any one of molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, and lift-off.

[0014] The thickness of the interface layer is 0.1 nm to 1 μm.

[0015] The semiconductor layer in the positive spin valve and the negative spin valve is made of any one of the following: poly(2,5-bis(2-octyldodecyl)-3,6-di(thiophen-2-yl)dionepyrrole[3,4-c]pyrrole-1,4-dione-alt-thiophene[3,2-b]thiophene), poly(2,5-bis(3-alkylthiophen-2-yl)thiophene[3,2-b]thiophene, poly(tetrathiophene acetate dionepyrrole), polyisoindigo dithiophene, poly(3-hexylthiophene), poly{2,5-bis(2-octyl)-3,6-dithiopyridylthiophene} and methyl [6,6]-phenyl-C61-butyrate.

[0016] The semiconductor layer is prepared by any one of the following methods: vapor deposition, drop coating, spin coating, blade coating, roller coating, brush coating, and film stretching.

[0017] A solution of the semiconductor layer material is prepared using any one of the following solvents: water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene, with a concentration of 0.1 g / L to 100 g / L.

[0018] The annealing temperature of the semiconductor layer is 20℃~200℃;

[0019] The thickness of the semiconductor thin film is 1 nm to 1 mm.

[0020] The oxide layer in the negative spin valve is made of any one of nickel iron oxide, cobalt oxide, ferrous oxide, ferric oxide, triferric oxide, nickel oxide, nickel trioxide, nickel trioxide, cobalt oxide, cobalt trioxide, and cobalt tetroxide.

[0021] The oxide layer is prepared by any one of plasma oxidation, air oxidation, mixed air oxidation, and oxygen mixture oxidation, with an oxidation time of 1 second to 10 minutes.

[0022] The present invention also provides a spin logic circuit, which is obtained by connecting the positive spin valve and the negative spin valve in the complementary spin valve device in series and in parallel.

[0023] This invention also provides a method for fabricating a spin logic circuit, comprising the following steps:

[0024] S1. The top electrode of the positive organic spin valve and the top electrode of the negative organic spin valve, along with the oxide layer, are respectively fabricated on a clean substrate.

[0025] S2. The semiconductor layer, the interface layer, and the bottom electrode of the positive organic spin valve and the negative organic spin valve are respectively fabricated on a clean substrate;

[0026] S3. The structures obtained in steps S1 and S2 are used as the upper and lower structures of the spintronic device, respectively. After alignment, they are bonded together (performed at room temperature) to assemble the device.

[0027] Among them, those without an oxide layer are positive organic spin valves (POSV), and those with an oxide layer are negative organic spin valves (NOSV).

[0028] Preferably, the substrate is selected from any one of silicon wafers, glass, ceramics, and quartz;

[0029] The substrate is ultrasonically cleaned sequentially with acetone and isopropanol, and then dried with a nitrogen gun. The ultrasonic cleaning conditions are: ultrasonic power of 10-100W, ultrasonic time of 1-30min, and ultrasonic frequency of 10-100kHz.

[0030] Preferably, before preparing the top electrode, a spin-coated tensile-resistant adhesive layer is prepared, which is then annealed and subjected to rapid cooling and quenching treatment before being peeled off.

[0031] The tensile adhesive layer is prepared by any one of the following methods: drop coating, spin coating, blade coating, roller coating, brush coating, and stretch coating.

[0032] The raw material solution for the tensile adhesive layer is prepared using any one of the following solvents: water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene.

[0033] The pre-quenching heating temperature is 50-200℃, the pre-quenching heating time is 1 min-48 h, the quenching temperature is -100-100℃, and the quenching time is 1 min-48 h.

[0034] This invention utilizes the precise control of the spin filtering effect in the spin interface to achieve a breakthrough in constructing organic spin valve devices with complementary magnetic response, which is of great significance for exploring all-spin logic manipulation and expanding the functional range of integrated circuits.

[0035] This invention achieves positive / negative spin valve devices by precisely adjusting the oxide layer of the spin valve device, ensuring complementary magnetic responses of the positive / negative organic spin valves under the same magnetic field conditions, filling the gap in complementary devices based on electron spin transport. By connecting the positive and negative organic spin valves in series and parallel while ensuring magnetoresistance matching of the organic semiconductor layer, a spin logic gate is constructed. The spin logic gate of this invention achieves breakthrough high gain and high noise tolerance, exhibiting outstanding cycle stability, creating a new path for the development of in-memory computing devices. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of directly observing the inverse spin filtering effect using a spin-resolved scanning tunneling microscope.

[0037] Figure 2 Ni measured by 2D-EELS 80 Fe 20 O x The thickness is approximately 1.8 nm.

[0038] Figure 3 Figure A shows the molecular structures of three organic semiconductor materials. Figure B shows the positive magnetoresistance curve of PSV, which shows a sharp, rectangular transition, reaching a magnetoresistance value of +10% at room temperature. Figure C shows the negative magnetoresistance curve of NSV, which shows a sharp, rectangular transition, reaching a magnetoresistance value of -8% at room temperature.

[0039] Figure 4 Figure A shows the basic NOT gate formed by the series connection of PSV and NSV. Figure B shows the NOT operation with the potential between PSV and NSV as the output (Vout).

[0040] Figure 5 The diagram shows the cyclic stability test of the all-spin NOT gate constructed in Embodiment 1 of the present invention. Over 8550 cycles, the on-state and off-state output voltages of the spin inverter remained within 3 standard deviations for 99.84% and 99.81% of the time, respectively, with the off-state voltage reaching 100% within this range in the last 550 cycles.

[0041] Figure 6 Figure A shows the noise margin (noise margin value is 85%) of the spin NOT gate prepared in Example 1 of the present invention, and Figure B shows the gain value (gain value is 142) of the spin NOT gate prepared in Example 1 of the present invention.

[0042] Figure 7 The diagram and truth table are for pure spin valve circuits of the six basic logic gates (AND, OR, NAND, NOR, XOR, and XNOR); "P" represents PSV and "N" represents NSV.

[0043] Figure 8 Analog outputs of all-spin valve logic gates, including AND, OR, NAND, NOR, XOR, and XNOR. Detailed Implementation

[0044] The present invention will now be described in further detail with reference to specific embodiments. The given embodiments are merely illustrative of the invention and not intended to limit its scope. The embodiments provided below can serve as a guide for further improvements by those skilled in the art and do not constitute a limitation on the invention in any way.

[0045] Unless otherwise specified, the experimental methods used in the following examples are conventional methods, performed according to the techniques or conditions described in the literature in this field or according to the product instructions. Unless otherwise specified, the materials and reagents used in the following examples are commercially available.

[0046] Example 1: Preparation of a positive organic spin valve

[0047] 1) Place 2×2cm 2 The silicon substrate (with a 300nm SiO2 layer on the surface) was ultrasonicated with acetone and isopropanol at a power of 40W and a frequency of 30kHz for 20 minutes, and then dried with a nitrogen gun.

[0048] 2) Prepare an 80 mg / ml PVA aqueous solution, place the solution on a hot plate, heat and stir at 90°C for 12 h, and then cool to room temperature.

[0049] 3) Place the cleaned silicon wafer from step 1) on a spin coater, set the spin speed to 2000 rpm and the time to 40 s. Take 0.2 ml of the PVA aqueous solution prepared in step 2) and drop it onto the silicon wafer. Spin coat the PVA solution evenly onto the surface of the silicon wafer. Then, place the silicon wafer on a hot plate and anneal it at 120°C for 20 min. After that, transfer it to a 0°C copper plate for rapid quenching for 1 min.

[0050] 3) In a nitrogen-purified glove box, through 2×10 -5 Pa and Electron beam evaporation deposition of 5–15 nm Ni 80 Fe 20 The upper layer structure of the positive organic spin valve device was prepared, and the sample was then vacuum-sealed for subsequent processing.

[0051] 4) Place 1×1cm 2 A silicon substrate (with a 300nm SiO2 layer on its surface) was sequentially sonicated with acetone and isopropanol at 40W power and 30kHz frequency for 20 minutes, and then dried with a nitrogen gun. Using the cleaned silicon wafer as a substrate, in a nitrogen-filled glove box, it was then subjected to a 2×10⁻⁶ process. -5 Pa and Electron beam evaporation deposition of 20 nm Co and 1.3 nm Al.

[0052] 5) Treat the sample with oxygen plasma at 5% power, using pure oxygen for three atmospheric cycles, and oxidize for 10 seconds.

[0053] 6) Prepare an organic semiconductor solution of 12 mg / ml, P3HT, PCBM or N2200, with chloroform as the solvent. Place the sample on a hot plate and stir at 50°C for 12 h, then cool to room temperature.

[0054] 8) Place the sample prepared in step 7) on a spin coater, set the spin speed to 3000 rpm and the time to 40 s. Drop the organic semiconductor solution from step 8) onto the sample surface, and spin coat the organic semiconductor solution to make it uniformly coated on the sample surface. Obtain the lower layer structure of the positive organic spin valve. Seal the sample in a vacuum container for analysis.

[0055] The above steps yield the upper and lower layer structures used to fabricate the positive organic spin valve. A 0.5 mm thick, 15 cm long, and 10 cm wide PET flexible film was used as the substrate for the upper and lower layers, respectively. The upper half has an 18 mm square cutout at its center and a 1 mm wide polyimide double-sided adhesive strip along its edge for peeling off the Ni-coated material from its SiO2 / Si substrate. 80 Fe 20 The PVA film of the electrode. The electrode faces the front of the PET and includes the device electrode and assembly alignment marks. The lower half is securely fixed to the lower part of the spin valve device at its center using polyimide double-sided adhesive. During assembly, one end of the two halves is fixed together, and the upper half is gradually lowered to align using alignment marks, starting from the left and extending outwards to expel air. After alignment, a surgical blade cuts along the silicon substrate to complete room temperature assembly, yielding a positive organic spin valve.

[0056] Example 2: Preparation of a negative organic spin valve

[0057] 1) Place 2×2cm 2The silicon substrate (with a 300nm SiO2 layer on the surface) was ultrasonicated with acetone and isopropanol at a power of 40W and a frequency of 30kHz for 20 minutes, and then dried with a nitrogen gun.

[0058] 2) Prepare an 80 mg / ml PVA aqueous solution, place the solution on a hot plate, heat and stir at 90°C for 12 h, and then cool to room temperature.

[0059] 3) Place the cleaned silicon wafer from step 1) on a spin coater, set the spin speed to 2000 rpm and the time to 40 s. Take 0.2 ml of the PVA aqueous solution prepared in step 2) and drop it onto the silicon wafer. Spin coat the PVA solution evenly onto the surface of the silicon wafer. Then, place the silicon wafer on a hot plate and anneal it at 120°C for 20 min. After that, transfer it to a 0°C copper plate for rapid quenching for 1 min.

[0060] 4) In a nitrogen-purified glove box, through 2×10 -5 Pa and Electron beam evaporation deposition of 5–15 nm Ni 80 Fe 20 layer.

[0061] 5) The sample was treated with oxygen plasma at 5% power and circulated three times in a pure oxygen environment at 0.1 mPa for 10 seconds each time to perform NOSV modification. The upper structure of the negative organic spin valve device was obtained, and the sample was then vacuum-sealed for subsequent processing.

[0062] 6) Place 1×1cm 2 A silicon substrate (with a 300nm SiO2 layer on its surface) was sequentially sonicated with acetone and isopropanol at 40W power and 30kHz frequency for 20 minutes, and then dried with a nitrogen gun. Using the cleaned silicon wafer as a substrate, in a nitrogen-filled glove box, it was then subjected to a 2×10⁻⁶ process. -5 Pa and Electron beam evaporation deposition of 20 nm Co and 1.3 nm Al.

[0063] 7) Treat the sample with oxygen plasma at 5% power, using pure oxygen for three atmospheric cycles, and oxidize for 10 seconds.

[0064] 8) Prepare a 12 mg / ml organic semiconductor solution of P3HT, PCBM or N2200, with chloroform as the solvent. Place the sample on a hot plate and stir at 50°C for 12 h, then cool to room temperature.

[0065] 9) Place the sample prepared in step 7) on a spin coater, set the spin speed to 3000 rpm and the time to 40 s, drop the organic semiconductor solution from step 8) onto the sample surface, and spin coat the organic semiconductor solution to make it uniformly coated on the sample surface. The lower layer structure of the negative organic spin valve is obtained. Seal the sample in a vacuum container for analysis.

[0066] The above steps yield the upper and lower layer structures used to fabricate the negative organic spin valve. A 0.5 mm thick, 15 cm long, and 10 cm wide PET flexible film was used as the substrate for the upper and lower layers, respectively. The upper half has an 18 mm square cutout at its center and a 1 mm wide polyimide double-sided adhesive strip along its edge for peeling off the Ni-coated material from its SiO2 / Si substrate. 80 Fe 20 O x The PVA film of the electrode. The electrode faces the PET front side and includes the device electrode and assembly alignment marks. The lower half is securely fixed to the lower part of the spin valve device at its center using polyimide double-sided adhesive. During assembly, one end of the two halves is fixed together, and the upper half is gradually lowered to align using alignment marks, starting from the left and extending outward to expel air. After alignment, a surgical blade cuts along the silicon substrate to complete room temperature assembly, yielding the negative organic spin valve.

[0067] Example 3: Fabrication of Complementary Spin Logic Circuits

[0068] 1) Place 2×2cm 2 The silicon substrate (with a 300nm SiO2 layer on the surface) was ultrasonicated with acetone and isopropanol at a power of 40W and a frequency of 30kHz for 20 minutes, and then dried with a nitrogen gun.

[0069] 2) Prepare an 80 mg / ml PVA aqueous solution, place the solution on a hot plate, heat and stir at 90°C for 12 h, and then cool to room temperature.

[0070] 3) Place the cleaned silicon wafer from step 1) on a spin coater, set the spin speed to 2000 rpm and the time to 40 s. Take 0.2 ml of the PVA aqueous solution prepared in step 2) and drop it onto the silicon wafer. Spin coat the PVA solution evenly onto the surface of the silicon wafer. Then, place the silicon wafer on a hot plate and anneal it at 120°C for 20 min. After that, transfer it to a 0°C copper plate for rapid quenching for 1 min.

[0071] 4) In a nitrogen-purified glove box, through 2×10 -5 Pa and Electron beam evaporation deposition of 5–15 nm Ni 80 Fe 20 layer.

[0072] 5) Pattern the electrode layer of the entire logic circuit to block the electrode surface of the positive organic spin valve and prevent its surface Ni from being exposed. 80 Fe 20 The layer was oxidized, and the sample was treated with oxygen plasma at 5% power, cyclically three times in a pure oxygen environment of 0.1 mPa for 10 seconds each time, to perform NOSV modification. The upper structure of the logic circuit composed of positive and negative organic spin valves was obtained, and the sample was then vacuum-sealed for subsequent processing.

[0073] 6) Place 1×1cm 2 A silicon substrate (with a 300nm SiO2 layer on its surface) was sequentially sonicated with acetone and isopropanol at 40W power and 30kHz frequency for 20 minutes, and then dried with a nitrogen gun. Using the cleaned silicon wafer as a substrate, in a nitrogen-filled glove box, it was then subjected to a 2×10⁻⁶ process. -5 Pa and Electron beam evaporation deposition of 20 nm Co and 1.3 nm Al.

[0074] 7) Treat the sample with oxygen plasma at 5% power, using pure oxygen for three atmospheric cycles, and oxidize for 10 seconds.

[0075] 8) Prepare a 12 mg / ml organic semiconductor solution of P3HT, PCBM or N2200, with chloroform as the solvent. Place the sample on a hot plate and stir at 50°C for 12 h, then cool to room temperature.

[0076] 9) Place the sample prepared in step 7) on a spin coater, set the speed to 3000 rpm and the time to 40 s, drop the organic semiconductor solution from step 8) onto the sample surface, and spin coat the organic semiconductor solution to make it evenly coated on the sample surface. The lower layer structure of the logic circuit composed of the positive and negative organic spin valves is obtained. Seal the sample in a vacuum container for analysis.

[0077] The above steps yield the upper and lower layer structures used to fabricate the negative organic spin valve. A 0.5 mm thick, 15 cm long, and 10 cm wide PET flexible film was used as the substrate for the upper and lower layers, respectively. The upper half has an 18 mm square cutout at its center and a 1 mm wide polyimide double-sided adhesive strip along its edge for peeling off the Ni-coated material from its SiO2 / Si substrate. 80 Fe 20 O xThe PVA film of the electrodes. The electrodes face the PET front side and include the device electrodes and assembly alignment marks. The lower half of the spin valve device is securely fixed in its center using polyimide double-sided adhesive. During assembly, one end of each half is held together, and the upper half is gradually lowered to align using alignment marks, starting from the left and extending outwards to expel air. After alignment, a surgical blade cuts along the silicon substrate to complete the room-temperature assembly of the positive and negative organic spin valves, resulting in a complementary spin logic circuit.

[0078] Figure 1 This diagram illustrates the direct observation of the inverse spin filtering effect using spin-resolved scanning tunneling microscopy. To directly verify the inverse spin filtering effect (ISFE) at the atomic level, this invention investigates the effect of oxygen atoms in Ni. 80 Fe 20 Surface magnetism. Oxygen atoms were adsorbed onto Ni using a spin-resolved scanning tunneling microscope / spectroscopy (SP-STM / S) equipped with a ferromagnetic Ni probe. 80 Fe 20 Surface. Oxygen atoms are formed by Ni... 80 Fe 20 Introduced by surface exposure to an oxygen atmosphere in a vacuum. Prior to exposure, Ni... 80 Fe 20 The surface exhibits clean and flat steps. Upon exposure, STM images reveal numerous additional protrusions, approximately 0.09 nm high, randomly distributed within the Ni. 80 Fe 20 Surface. By comparing the features of STM images obtained before and after oxygen exposure, these additional protrusions were identified as oxygen atoms, such as... Figure 1 As shown in Figure B, when using a non-spin-polarized W probe, there is no distinction between oxygen atoms and oxygen-free surface regions. Therefore, there is no intensity contrast between oxygen atoms and oxygen-free surface regions in the dI / dV diagram. Conversely, for a ferromagnetic Ni probe, as... Figure 1 As shown in Figure A, there is a significant difference between the spin-resolved dI / dV spectra of oxygen atoms and the surface. This indicates that the electronic states of oxygen atoms are spin-polarized. Furthermore, in the spin-resolved dI / dV spectra, there is an intensity contrast between the oxygen atom and the oxygen-free surface region, such as... Figure 1 As shown in Figure C, this indicates the presence of oxygen atoms and Ni. 80 Fe 20 The difference in spin orientation between surfaces is dominant, which is very consistent with the ISFE picture obtained from the above calculation.

[0079] Figure 2 Electron energy loss spectroscopy (EELS) measurements were performed using aberration-corrected transmission electron microscopy (Cs-corrected TEM). Ni 80 Fe20 O x The optimal layer thickness is approximately 1.8 nm, Ni 80 Fe 20 O x Ni is oxidized by plasma 80 Fe 20 The obtained process involves transferring Ni using a gold layer to protect it during the transfer from the plasma cavity to the analysis cavity. 80 Fe 20 O x To prevent further oxidation. EELS analysis of the Ni content was divided into two regions: unoxidized Ni. 80 Fe 20 The Ni concentration is high in the region, while the Ni concentration within the dashed box is higher. 80 Fe 20 O x The Ni concentration is low in this region. The decrease in Ni concentration in the latter region is due to oxygen incorporation. By applying multiple linear least-squares fitting to the Ni EELS spectrum, the distribution of Ni's zero-valent and +2 oxidation states can be plotted. The distribution of these states is consistent with the elemental distribution of Ni and O. 0 Distribution of Ni 80 Fe 20 The distributions are highly consistent, while Ni 2+ Matching the distribution of oxygen indicates that Ni 2+ Ni exists in the form of NiO 80 Fe 20 In the Ox layer.

[0080] Figure 3 Figure A shows three widely used optoelectronic organic semiconductors: PCBM, N2200, and P3HT, which are prepared into thin films by spin coating from a chloroform solution. Figure 3 Figure B shows that assembling semiconductor thin films into spin valve devices achieved a breakthrough magnetoresistive reduction of over 10% at room temperature for PSV, and exhibits a sharp, rectangular magnetoresistive curve. Figure 3 The NSV device in Figure C also exhibits a negative magnetoresistance close to -8% at room temperature, with a clear switching between high and low resistance states. The successful room-temperature fabrication of PSV and NSV and their excellent performance demonstrate the superior performance of Ni… 80 Fe 20 The effectiveness of spin interface modification at the device level lays the foundation for constructing spin valve logic circuits.

[0081] Figure 4 In Figure A, the cascaded connection of PSV and NSV forms a basic logic NOT gate, with each device connected to V. dd And ground. The potential between PSV and NSV is used as the output (V). out This demonstrates the NOT operation. Figure 4 In Figure B, because the switching logic within the PSV and NSV is reversed under the same magnetic field, and the resistance of the NSV changes inversely with the direction of the magnetic field, this configuration is set as a magnetic NOT gate (inverter). It is worth noting that due to the low switching field of the cobalt electrode, the output voltage of the spin valve NOT gate changes exceptionally rapidly when the magnetic field switches between ±50 Oe.

[0082] Figure 5 Cyclic stability test diagram of the all-spin NOT gate constructed for Embodiment 1 of the present invention. Stability is crucial for electronic devices, especially in terms of application value. The reliability of the all-spin NOT gate was evaluated through cyclic testing. Statistical analysis over more than 8500 cycles showed that the standard deviation (σ) of the high and low output levels was only 0.0035 and 0.0039, respectively, and the output voltage remained stable for 99.84% and 99.81% of the time within the μ±3σ range. After the initial 8000 cycles, an additional 550 cycles were examined to assess performance degradation. In these subsequent tests, the standard deviations of the high and low outputs decreased to 0.0012 and 0.0014, respectively, indicating improved stability after the initial evaluation period. Within the μ±3σ range, the proportions of high and low outputs reached 99.27% ​​and 100%, respectively, confirming that the all-spin NOT gate maintained optimal operating conditions throughout the extensive cycling process. The stability is also reflected in its extremely low power consumption, at only 8nW (20mV × 0.4μA), generating only 28.8μJ of heat per hour. This low heat generation is crucial because elevated temperatures significantly increase spin scattering, shorten spin relaxation lengths, and enhance magnetoresistance changes, potentially degrading circuit performance. Furthermore, the low operating voltage of 20mV helps stabilize metal atoms within the electrodes, preventing migration that leads to filament formation—a fundamental mechanism in memristor devices but detrimental in spintronic electronics as it compromises device integrity. Therefore, this minimal operating heat ensures the stability of the electromechanical properties of the semiconductor layer and maintains the integrity of the spin interface after 8550 cycles.

[0083] Figure 6 Noise margin and gain are important performance parameters for inverters. In this invention, the all-spin valve inverter exhibits an excellent noise margin of approximately 85%, derived from the magnetoresistive curves of the PSV and NSV. Uniquely, unlike conventional inverters that use voltage as both input and output, the spin inverter's input signal is a magnetic field. The gain is approximately 142. The spin inverter's noise margin, gain, and operating voltage are leading figures among low-voltage inverters constructed using organic polymer semiconductors, a characteristic attributed to the spin's significantly faster response to a magnetic field than the charge's response to an electric field.

[0084] Figure 8The simulation is extended to include six classic logic gates: AND, OR, NAND, NOR, XOR, and XNOR, based on the spin logic NOT gates developed using PSV and NSV. The consistency and speed of the switching behavior of the complementary PSV and NSV ensure rapid switching of the analog outputs of these logic gates.

[0085] The present invention has been described in detail above. Those skilled in the art will recognize that the invention can be practiced in a wide range of ways with equivalent parameters, concentrations, and conditions without departing from its spirit and scope, and without requiring unnecessary experiments. While specific embodiments have been provided, it should be understood that further modifications can be made to the invention. In summary, according to the principles of the invention, this application is intended to include any changes, uses, or improvements to the invention, including changes made using conventional techniques known in the art that depart from the scope disclosed herein.

Claims

1. A complementary spin valve device, comprising a positive spin valve and a negative spin valve; The structure of the positive spin valve, from top to bottom, includes: Top electrode, semiconductor layer, interface layer, bottom electrode; The structure of the negative spin valve, from top to bottom, includes a top electrode, an oxide layer, a semiconductor layer, an interface layer, and a bottom electrode.

2. The complementary spin valve device according to claim 1, characterized in that: The top electrode and the bottom electrode in the positive spin valve and the negative spin valve are both made of metallic iron, cobalt, nickel, or any two or three of them, or a mixture or alloy thereof. The top electrode and the bottom electrode are prepared by any one of molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, and lift-off. The thickness of the top electrode and the bottom electrode is 1 to 100 nm.

3. The complementary spin valve device according to claim 1 or 2, characterized in that: The interface layer in the positive spin valve and the negative spin valve is made of any one of magnesium oxide, aluminum oxide, gallium nitride, graphene, and barium titanate. The interface layer is prepared by any one of molecular beam epitaxy, magnetron sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, thermal evaporation, electron beam evaporation, and lift-off. The thickness of the interface layer is 0.1 nm to 1 μm.

4. The complementary spin valve device according to any one of claims 1-3, characterized in that: The semiconductor layer in the positive spin valve and the negative spin valve is made of any one of the following: poly(2,5-bis(2-octyldodecyl)-3,6-di(thiophen-2-yl)dionepyrrole[3,4-c]pyrrole-1,4-dione-alt-thiophene[3,2-b]thiophene), poly(2,5-bis(3-alkylthiophen-2-yl)thiophene[3,2-b]thiophene, poly(tetrathiopheneacetic acid dionepyrrole), polyisoindigodithiophene, poly(3-hexylthiophene), poly{2,5-bis(2-octyl)-3,6-dithiopyridylthiophene} and methyl [6,6]-phenyl-C61-butyrate. The semiconductor layer is prepared by any one of the following methods: vapor deposition, drop coating, spin coating, blade coating, roller coating, brush coating, and film stretching. A solution of the semiconductor layer material is prepared using any one of the following solvents: water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene, with a concentration of 0.1 g / L to 100 g / L. The annealing temperature of the semiconductor layer is 20℃~200℃; The thickness of the semiconductor thin film is 1 nm to 1 mm.

5. The complementary spin valve device according to any one of claims 1-4, characterized in that: The oxide layer in the negative spin valve is made of any one of nickel iron oxide, cobalt oxide, ferrous oxide, ferric oxide, triferric oxide, nickel oxide, nickel trioxide, nickel trioxide, cobalt oxide, cobalt trioxide, and cobalt tetroxide. The oxide layer is prepared by any one of plasma oxidation, air oxidation, mixed air oxidation, and oxygen mixture oxidation, with an oxidation time of 1 second to 10 minutes.

6. A spin logic circuit, obtained by connecting the positive spin valve and the negative spin valve in the complementary spin valve device according to any one of claims 1-5 in series and parallel.

7. The method for fabricating the spin logic circuit according to claim 6, comprising the following steps: S1. The top electrode of the positive organic spin valve and the top electrode of the negative organic spin valve, along with the oxide layer, are respectively fabricated on a clean substrate. S2. The semiconductor layer, the interface layer, and the bottom electrode of the positive organic spin valve and the negative organic spin valve are respectively fabricated on a clean substrate; S3. The structures obtained in steps S1 and S2 are used as the upper and lower structures of the spintronic device, respectively. After alignment, they are bonded and assembled.

8. The preparation method according to claim 7, characterized in that: The substrate is selected from any one of silicon wafers, glass, ceramics, and quartz; The substrate is ultrasonically cleaned sequentially with acetone and isopropanol, and then dried with a nitrogen gun. The ultrasonic cleaning conditions are: ultrasonic power of 10-100W, ultrasonic time of 1-30min, and ultrasonic frequency of 10-100kHz.

9. The preparation method according to claim 7 or 8, characterized in that: Before preparing the top electrode, a spin-coated tensile-resistant adhesive layer is first prepared, annealed, and then subjected to rapid cooling quenching and peeling. The tensile adhesive layer is prepared by any one of the following methods: drop coating, spin coating, blade coating, roller coating, brush coating, and stretch coating. The raw material solution for the tensile adhesive layer is prepared using any one of the following solvents: water, ethanol, isopropanol, chloroform, acetone, cyclohexane, n-hexane, isohexane, and toluene. The pre-quenching heating temperature is 50-200℃, the pre-quenching heating time is 1 min-48 h, the quenching temperature is -100-100℃, and the quenching time is 1 min-48 h.

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