Method and system for operating double-sided double-base bipolar junction transistor

Abstract

A double-sided, double-base, bipolar junction transistor is operated. One example is a method of operating a switch assembly, the method comprising: blocking, by a transistor, a current flow from an upper terminal to a lower terminal of the switch assembly; and then conducting a first load current from the upper terminal to the lower terminal in response to assertion of a conduction signal. The conducting the first load current may be by closing an upper main FET coupled between the upper terminal and an upper collector-emitter of the transistor; closing a lower main FET coupled between a lower collector-emitter of the transistor and the lower terminal; driving a first turn-on current from an upper current source to an upper base of the transistor; and then providing a first steady-state current from the upper current source to the upper base, the first steady-state current being lower than the first turn-on current.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 586,473, filed September 29, 2023, entitled “Methods and Systems of Operating a Double-Sided Double-Base Bipolar Junction Transistor,” which is incorporated herein by reference in its entirety as repeated below. Background Technology

[0003] A double-sided double-base (DSDB) bipolar junction transistor (BJT) is a junction transistor constructed with a base and collector-emitter junction on a first side of the body region and a different, separate base and collector-emitter junction on a second side of the body region opposite to the first side. When correctly configured by an external driver, current can selectively flow through the collector-emitter junction of the DSDB BJT in either direction, and therefore such devices are considered bidirectional devices.

[0004] Any method or system that simplifies the driving of DSDB BJT will provide a competitive advantage in the market. Summary of the Invention

[0005] At least one example is a method of operating a switch assembly, the method comprising: blocking current flow from an upper terminal of the switch assembly to a lower terminal of the switch assembly by a transistor; and then conducting a first load current from the upper terminal to the lower terminal in response to an assertion of a conduction signal. The conduction of the first load current from the upper terminal to the lower terminal may be achieved by: closing an upper main FET coupled between the upper terminal and the upper collector-emitter of the transistor; closing a lower main FET coupled between the lower collector-emitter of the transistor and the lower terminal; driving a first on-state current from an upper current source to the upper base of the transistor; and then providing a first steady-state current from the upper current source to the upper base, the first steady-state current being lower than the first on-state current.

[0006] The example method may further include interrupting the first load current by disconnecting the lower main FET, and then arranging the transistor to block the current from the upper terminal to the lower terminal. The example method may further include: blocking the current flow from the lower terminal to the upper terminal by the transistor; and then conducting a second load current from the lower terminal to the upper terminal in response to an assertion of a conduction signal. Conducting the second load current from the lower terminal to the upper terminal may be achieved by: closing the lower main FET; closing the upper main FET; driving a second on-state current from the lower current source to the lower base of the transistor; and then providing a second steady-state current from the lower current source to the lower base, the second steady-state current being lower than the second on-state current. In some cases, the first steady-state current may be equal to the second steady-state current. Additionally: driving the first on-state current from the upper current source may include driving the first on-state current from the upper power converter based on a first upper feedback obtained from the output voltage of the upper power converter; providing the first steady-state current from the upper current source may include providing the first steady-state current from the upper power converter based on a second upper feedback obtained from the current provided by the upper power converter; driving the second on-state current from the lower current source may include driving the second on-state current from the lower power converter based on a first lower feedback obtained from the output voltage of the lower power converter; and providing the second steady-state current from the lower current source may include providing the second steady-state current from the lower power converter based on a second lower feedback obtained from the current provided by the lower power converter. The example method may further include extracting energy from the first on-state current and the first steady-state current from the upper terminal, and extracting energy from the second on-state current and the second steady-state current from the upper terminal.

[0007] In the example method: driving the first on-state current from the upper current source may include driving the first on-state current from the upper power converter based on a first feedback obtained from the output voltage of the upper power converter; and providing the first steady-state current from the upper power converter may include providing the first steady-state current from the upper power converter based on a second feedback obtained from the current provided by the upper power converter.

[0008] In the example method: driving the first on-state current from the current source may include driving the first on-state current from the power converter based on a first set point; and providing the first steady-state current from the current source may include driving the first steady-state current from the power converter based on a second set point different from the first set point.

[0009] The example method may further include extracting the energy of the first on-state current and the first steady-state current from the upper terminal.

[0010] Another example is a switching assembly comprising: an upper terminal and a lower terminal; a transistor defining an upper base, an upper collector-emitter junction, a lower base, and a lower collector-emitter junction; an upper current source having a sink input coupled to the upper terminal and a source output; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter junction, and a gate; a lower main FET defining a first lead coupled to the lower collector-emitter junction, a second lead coupled to the lower terminal, and a gate; and a controller coupled to the gate of the upper main FET and the gate of the lower main FET and for applying a first voltage across the upper and lower terminals. The controller may be configured to: assert the gate of the upper main FET; assert the gate of the lower main FET; and configure the upper current source to provide a first on-state current to the upper base of the transistor and subsequently provide a first steady-state current to the upper base, the first steady-state current being lower than the first on-state current.

[0011] The example switching assembly may further include: an upper base FET defining a first lead coupled to the source output of the upper current source, a second lead coupled to the upper base, and a gate; a controller coupled to the gate of the upper base FET, and configured to assert the gate of the upper base FET to couple the source output to the upper base when the controller configures the upper current source.

[0012] The example switching assembly may further include: a lower current source having a sink input coupled to the lower terminal and a source output, wherein for a second applied voltage across the upper and lower terminals, the polarity of the second applied voltage is opposite to the first applied voltage, and the controller is configured to: assert the gate of the lower main FET; assert the gate of the upper main FET; configure the lower current source to provide a second on-state current to the lower base of the transistor and then provide a second steady-state current to the lower base, the second steady-state current being lower than the second on-state current. The switching assembly may further include: an upper base FET defining a first lead coupled to the source output of the upper current source, a second lead coupled to the upper base, and a gate; and a lower base FET defining a first lead coupled to the source output of the lower current source, a second lead coupled to the lower base, and a gate. The controller is coupled to the gate of the upper base FET and the gate of the lower base FET, and when the controller is configured with the upper current source, the controller is configured to assert the gate of the upper base FET to couple the source output of the upper current source to the upper base. And when the controller is configured with the lower current source, the controller is configured to assert the gate of the lower base FET to couple the source output of the lower current source to the lower base.

[0013] The example switch assembly may further include: a power supply defining an upper power rail and a lower power rail; a power converter configured to apply an upper rail voltage to the upper power rail, the upper rail voltage referencing the upper terminal; and the power converter configured to apply a lower rail voltage to the lower power rail, the lower rail voltage referencing the lower terminal. The power supply may have a power input coupled to the upper terminal.

[0014] In the example switch assembly, the current source may be a switching power converter designed and constructed to control the output current as a controlled variable during at least the provision of the first steady-state current. Furthermore, in the example switch assembly, the current source may be a switching power converter designed and constructed to control the output current as a controlled variable during both the provision of the first on-state current and the provision of the first steady-state current. Attached Figure Description

[0015] To describe the exemplary embodiments in detail, reference will now be made to the accompanying drawings, in which:

[0016] Figure 1 Showing partial block diagrams and partial circuit diagrams of a power module using NPN double-base bipolar junction transistors;

[0017] Figure 2Showing partial block diagrams and partial circuit diagrams of a power module using PNP double-base bipolar junction transistors;

[0018] Figure 3A to 3G The PNP double-base bipolar junction transistor is shown in a simplified form, with example external electrical connections to illustrate several operating states;

[0019] Figure 4 Partial block diagrams and partial circuit diagrams of a switch assembly according to at least some embodiments are shown;

[0020] Figure 5 A partial circuit diagram of a switch assembly according to at least some embodiments is shown;

[0021] Figure 6 Partial schematic diagrams and partial block diagrams of example switch assemblies according to at least some embodiments are shown;

[0022] Figure 7 Partial block diagrams and partial circuit diagrams of a buck converter according to at least some embodiments are shown;

[0023] Figure 8 Showing partial schematic diagrams and partial block diagrams of example switch assemblies according to at least some embodiments; and

[0024] Figure 9 The method is illustrated according to at least some embodiments.

[0025] definition

[0026] Various terms are used to refer to specific system components. Different companies may use different names to refer to components, and this invention does not intend to distinguish components by name rather than function. In the following discussion and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to...". Furthermore, the term "coupled" is intended to mean either an indirect or direct connection. Thus, if a first device is coupled to a second device, this connection can be either a direct connection or an indirect connection via other devices and connections.

[0027] The "approximately" in enumeration parameters should mean the enumeration parameters plus or minus 10 percent (+ / - 10%).

[0028] An "assertion" should mean creating or maintaining a first predetermined state of a Boolean signal. Depending on the circuit designer's decision, a Boolean signal can be asserted as high or having a higher voltage, and a Boolean signal can be asserted as low or having a lower voltage. Similarly, a "cancel assertion" should mean creating or maintaining a second predetermined state of the Boolean signal, the opposite of the asserted state.

[0029] “FET” should mean field-effect transistor, such as junction gate FET (JFET) or metal oxide silicon FET (MOSFET).

[0030] The term "closing" in relation to an electronically controlled switch (such as a FET) should mean turning the switch on. For example, closing a FET used as an electronically controlled switch could mean driving the FET to a fully on state.

[0031] "Off" in the context of an electronically controlled switch (e.g., a FET) should mean that the switch is not conducting. Leakage current should not negate the state where the electronically controlled switch is not conducting.

[0032] The “collector-emitter” of a bipolar junction transistor (BJT) should refer to the region of the BJT through which the main load current flows. For the purposes of this specification and claims, the collector-emitter is specified as independent of the underlying device physical characteristics within the BJT. For example, in a double-sided double-base PNP transistor, the main load current can flow from the upper P-type region through the body N-type region and then out of the lower P-type region, and when used in this way, the upper and lower P-type regions are considered as the collector-emitter. However, in other cases, such as in co-pending and co-assigned U.S. Application 63 / 382,924, filed November 9, 2022, entitled “Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor,” the main load current can flow from the upper N-type region through the body N-type region and then through the lower N-type region, and when used in this way, the upper and lower N-type regions are regarded as collector-emitter junctions.

[0033] The “base” of a bipolar junction transistor (BJT) should mean the region through which control current flows in the BJT, and the control current is different from the main load current. For the purposes of this specification and claims, the base is specified as independent of the physical characteristics of the underlying device within the BJT. For example, in a double-sided double-base PNP transistor, control current may flow into either the upper N-type region or the lower N-type region, and when used in this way, both the upper and lower N-type regions are considered the base. However, in other cases, such as those described in the aforementioned co-pending and co-assigned U.S. Application 63 / 382,924, control current may flow into either the upper P-type region or the lower P-type region, and when used in this way, both the upper and lower P-type regions are considered the base.

[0034] The term "upper" in relation to components (e.g., upper collector-emitter, upper base) should not be interpreted as implying the position of the component relative to gravity. "Upper" can be derived from the position of the device in the example diagram.

[0035] The term "down" in relation to components (e.g., upper collector-emitter, upper base) should not be interpreted as implying the position of the listed components relative to gravity. "Down" can be derived from the position of the device in the example diagram.

[0036] In electrical engineering, the terms "voltage source" and "current source" are technical terms. Within its design operating range, a "voltage source" provides the setpoint voltage regardless of the current drawn from the downstream load. Within its design operating range, a "current source" provides the setpoint current to the downstream load regardless of the voltage used to drive the current. Although a "voltage source" provides current, a "voltage source" operated to provide the setpoint voltage should not be considered a "current source," regardless of the current drawn from it.

[0037] The terms “input” and “output”, when used as nouns, refer to connections (e.g., electrical, software) and should not be interpreted as verbs requiring action. For example, a timer circuit may define a clock output. An example timer circuit may create or drive a clock signal on the clock output. In systems implemented directly in hardware (e.g., on a semiconductor substrate), these “inputs” and “outputs” define electrical connections. In systems implemented in software, these “inputs” and “outputs” define parameters that are read or written by instructions that implement the function.

[0038] "Controller" should mean, individually or in combination, an individual circuit component, an application-specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC) with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field-programmable gate array (FPGA), or a programmable system-on-a-chip (PSOC) configured to read inputs and drive outputs in response to inputs. Detailed Implementation

[0039] The following discussion pertains to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as limiting the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is merely illustrative of that embodiment and is not intended to imply that the scope of this disclosure (including the claims) is limited to that embodiment.

[0040] Various examples relate to methods and systems for operating a double-sided, double-base, bipolar junction transistor. One example is a method that includes blocking current flow from the upper terminal of a switching assembly to the lower terminal of the switching assembly by the transistor and then conducting a first load current from the upper terminal to the lower terminal in response to an assertion of a conduction signal. The first load current can be conducted by: closing an upper main FET coupled between the upper terminal and the upper collector-emitter of the transistor; closing a lower main FET coupled between the lower collector-emitter of the transistor and the lower terminal; driving a first on-state current from an upper current source to the upper base of the transistor; and then providing a first steady-state current from the upper current source to the upper base, the first steady-state current being lower than the first on-state current.

[0041] Figure 1 This section shows partial block diagrams and partial circuit diagrams of a power module using double-sided double-base (DSDB) bipolar junction transistors (BJTs) with an NPN configuration. Specifically, in... Figure 1 As shown in the figure, the DSDB BJT 100 defines an upper collector-emitter 112, an upper base 114, a lower collector-emitter 120, and a lower base 122. The NPN configuration is a normally off or normally non-conducting transistor. Driver circuitry is used to arrange the example NPN device to selectively conduct in either direction. Specifically, the upper collector-emitter 112 and upper base 114 may be associated with an upper driver 130, and the lower collector-emitter 120 and lower base may be associated with a lower driver 132. "Upper" and "lower" are specified only based on their respective positions in the figure and do not necessarily imply positions relative to the gravity of the physical device. The upper driver 130 is designed and constructed to selectively: float the upper base 114; short the upper base 114 to the upper terminal 140; and inject charge carriers into the upper base 114 during the conduction period from the upper terminal 140 to the lower terminal 142 to reduce the V00 of the DSDB BJT 100. CEON Similarly, the lower driver 132 is designed and configured to selectively: float the lower base 122; short the lower base 122 to the lower terminal 142; and inject charge carriers into the lower base 122 during the conduction period from the lower terminal 142 to the upper terminal 140 to reduce the V00 of the DSDB BJT 100. CEON .

[0042] exist Figure 1In this example, the DSDB BJT 100 is arranged for cascaded operation, where current flows in either direction. Specifically, the DSDB BJT 100 is associated with a lower control switch (hereinafter referred to as lower master switch 144) coupled between the lower collector-emitter 120 and the lower terminal 142. The lower master switch 144 is selected and implemented to interrupt the load current from the lower collector-emitter 120 to the lower terminal 142 when an externally applied voltage is applied to the upper terminal 140 for correction. Correspondingly, the DSDB BJT 100 is associated with an upper control switch (hereinafter referred to as upper master switch 146) coupled between the upper terminal 140 and the upper collector-emitter 112. The upper master switch 146 is selected and implemented to interrupt the load current from the upper collector-emitter 112 to the upper terminal 140 when an externally applied voltage is applied to the lower terminal 142 for correction.

[0043] Figure 2 This section displays partial block diagrams and simplified circuit diagrams of a DSDB BJT 200 power module constructed using PNP transistors. Specifically, in... Figure 2 The DSDB BJT 200 is visible in the diagram. The DSDB BJT 200 defines an upper collector-emitter 112, an upper base 114, a lower collector-emitter 120, and a lower base 122. The PNP configuration is a normally open or normally conducting device. The upper driver 130 and lower driver 132 are designed and constructed to arrange the DSDB BJT 200 as non-conducting during periods when the power module is blocking current. Again, as previously stated, even when the power module implements a PNP configuration with the DSDB BJT 200, the device can be arranged for cascaded operation, where current interruption is implemented by either the lower main switch 144 or the upper main switch 146, depending on the current flow direction. As described in co-pending and co-assigned U.S. Application 63 / 382,924, filed November 9, 2022, entitled "Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor," in order to reduce V across the device CEON When the main load current flows into the upper N-type region, through the body N-type region, and then through the lower N-type region, charge carriers can be injected into the upper P-type region. Conversely, when the main load current flows into the lower N-type region, through the body N-type region, and then through the upper N-type region, charge carriers can be injected into the lower P-type region.

[0044] This specification continues to assume that the DSDB BJT has a PNP configuration in which the main load current flows through the N-type region and the control current flows into the P-type region. It should be understood that the PNP device can also operate in the reverse configuration (i.e., the main load current flows through the P-type region). Furthermore, the injection technique can also be applied to double-sided devices with an NPN configuration, and the following figures use transistor symbols with outward-pointing arrows as general placeholders for double-sided transistors used in construction or arrangement.

[0045] Figure 3A to 3G A simplified cross-sectional view of the PNP-constructed DSDB BJT 200 is shown, with example external electrical connections to illustrate several operating states of the PNP device. Specifically, Figure 3A to 3G This demonstrates seven example states of a DSDB BJT 200 configured to carry the main load current across or through the N-type region. The seven states are: passive shutdown (…). Figure 3A ), active shutdown ( Figure 3B ); Diode connected ( Figure 3C Passive connection ( Figure 3D Active connection ( ); Figure 3E Pre-shutdown ( Figure 3F ); and bidirectional blocking ( Figure 3G Each of these will be described in turn.

[0046] First refer to Figure 3A , Figure 3A The example demonstrates upper terminal 140 and lower terminal 142. Between upper terminal 140 and lower terminal 142 resides a DSDB BJT 200 with a PNP structure defining upper collector-emitter 112, upper base 114, lower collector-emitter 120, and lower base 122. Figure 3A to 3G In this example, it is assumed that the externally applied voltage has a more positive polarity relative to the lower terminal 142 and associated with the upper terminal 140. Figure 3A In the example passive shutdown arrangement, the upper base 114 is electrically floating, the upper collector-emitter 112 is coupled to the upper terminal 140, the lower base 122 is coupled to the lower terminal 142, and the lower collector-emitter 120 is electrically floating. Figure 3A In this arrangement, the DSDB BJT 200 may have a breakdown voltage of 600 volts or greater, and in some cases about 1200 volts. Therefore, due to the reverse-biased PN junction formed between the lower base 122 and the upper collector-emitter 112, no significant current flows through the example DSDB BJT 200. Figure 3A The instance state is called "passive shutdown" because Figure 3A The electrical arrangement can be implemented using purely passive components (such as diodes and resistors), and therefore the driver circuit does not need to have operating power. Figure 3A The arrangement.

[0047] Figure 3B This demonstrates an optional active shutdown arrangement for the DSDB BJT 200 example. Specifically, the upper base 114 is electrically floating, the upper collector-emitter 112 is coupled to the upper terminal 140, the lower base 122 is coupled to the lower terminal 142 via a voltage source 300, and the lower collector-emitter 120 is electrically floating. The voltage source 300 provides a negative bias to the lower base 122 relative to the lower collector-emitter 120. Figure 3B In this arrangement, the DSDB BJT 200 may have a breakdown voltage of 600 volts or greater, and in some cases approximately 1200 volts. Therefore, again in the active shutdown arrangement, no significant current flows through the DSDB BJT 200 due to the reverse-biased PN junction formed between the lower base 122 and the upper collector-emitter 112. Figure 3B The instance state is called "active shutdown" because... Figure 3B In the electrical arrangement, the associated driver circuitry uses operating power to implement the arrangement (e.g., powering power supply 300).

[0048] Figure 3C This example demonstrates the diode-on arrangement of the DSDB BJT 200. Specifically, the upper base 114 is coupled to the upper terminal 140, the upper collector-emitter 112 is electrically floating, the lower base 122 is electrically floating, and the lower collector-emitter 120 is coupled to the lower terminal 142. In this diode-on arrangement, the PN junction formed by the upper base 114 and the lower collector-emitter 120 is forward biased, and thus current flows from the upper base 114 to the lower collector-emitter 120. Figure 3C In the arrangement, the voltage drop across the DSDB BJT 200 is approximately 0.7 volts of diode forward voltage drop. Figure 3C The diode connection arrangement is as follows: Figure 3A The passive turn-off arrangement is the opposite of the diode turn-on arrangement, but in practice, the diode turn-on arrangement can only be used in limited situations.

[0049] Figure 3D This demonstrates the passive on / off arrangement of the DSDB BJT 200 example. Specifically, the upper base 114 is electrically floating, the upper collector-emitter 112 is coupled to the upper terminal 140, the lower base 122 is electrically floating, and the lower collector-emitter 120 is coupled to the lower terminal 142. Figure 3D The voltage drop across the DSDB BJT 200 in the arrangement is based on the substrate resistance (e.g., about 2 ohms for a 260 μm thick substrate). Figure 3D The instance state is called "passive turn-on" because the turn-on state does not involve injecting charge carriers to attempt to reduce the forward voltage drop V. CEON ,like Figure 3E The active connection setup is shown.

[0050] Figure 3E This demonstrates the active-on arrangement of the example DSDB BJT 200. Specifically, the upper base 114 is coupled to the upper terminal 140 via a voltage source 302, the upper collector-emitter 112 is coupled to the upper terminal 142, the lower base 122 is electrically floating, and the lower collector-emitter 120 is coupled to the lower terminal 142. The voltage source 302 provides a positive bias to the upper base 114 relative to the upper collector-emitter 112, and the voltage source 302 can provide any suitable bias voltage (e.g., 0.2 V to 2 V). The voltage source 302 injects charge carriers into the bulk substrate across the PN junction, which, for a 30 amp (A) main current flow, would be the forward voltage drop V measured from the upper collector-emitter 112 to the lower collector-emitter 120. CEON It drops to about 0.2 V, compared to about 10 to 20 V without charge carrier injection.

[0051] Figure 3F This demonstrates the pre-shutdown arrangement of the DSDB BJT 200 example. Specifically, the upper base 114 is coupled to the upper terminal 140, the upper collector-emitter 112 is coupled to the upper terminal 140, the lower base 122 is coupled to the lower terminal 142, and the lower collector-emitter 120 is coupled to the lower terminal 142. An equivalent arrangement could omit the coupling of the upper base 114 to the upper terminal 140. Figure 3F In the pre-shutdown arrangement, the DSDB BJT 200 presents a resistance of approximately 2 ohms across terminals 140 and 142. Therefore, for the 30 A main load current of the example, Figure 3F In the pre-shutdown arrangement, there is a voltage drop of approximately 60 V from the upper terminal 140 to the lower terminal 142.

[0052] Figure 3G This demonstrates the bidirectional blocking arrangement of the DSDB BJT 200 example. Specifically, the upper base 114 is coupled to the upper terminal 140, the upper collector-emitter 112 is electrically floating, the lower base 122 is coupled to the lower terminal 142, and the lower collector-emitter 120 is electrically floating. Therefore, no significant current flows through the DSDB BJT 200. Figure 3G In any of the applied polarities, the DSDB BJT 200 instance can have a breakdown voltage of 600 volts or greater, and in some cases about 1200 volts.

[0053] In many cases, the DSDB BJT 200 instance will be deployed as a slave of... Figure 3A Passive shutdown arrangement or Figure 3B The active shutdown arrangement is directly transformed into Figure 3E The active connection arrangement requires no intermediate arrangement or state. However, Figure 3C Diode connection arrangement and Figure 3DThe passive switching arrangement can be useful in some situations. Regarding the transition from conductive to non-conductive, in many cases, the DSDB BJT 200 instance will... Figure 3E The active connection arrangement is directly transformed into Figure 3B Active shutdown arrangement, Figure 3A Passive shutdown arrangement or Figure 3G The bidirectional blocking arrangement requires no intermediate arrangement or state. However, Figure 3C diode connection arrangement, Figure 3D Passive connection arrangement and Figure 3F Pre-shutdown arrangements can be useful in some situations.

[0054] Figure 3A to 3G The example is for a case where the externally applied voltage has a positive polarity at the upper terminal 140. However, the example PNP DSDB BJT 200 is a symmetrical device, and it is now understood how to control the current flowing through the DSDB BJT using the polarity of the example shown, and then directly control the current flow in the opposite direction. Furthermore, various operating states of the PNP configuration in which the main load current flows through the N-type region are now understood, and those skilled in the art can obtain equivalent arrangements of the PNP configuration and NPN arrangement in which the main load current flows through the P-type region.

[0055] Figure 4 This section shows a partial block diagram and a partial circuit diagram of an example power module or switching assembly. Specifically, the switching assembly 400 includes an example DSDB BJT 200 with a PNP construction and a driver 402. The example driver 402 defines an upper collector-emitter terminal 408 coupled to the upper collector-emitter 112, an upper conductive terminal 410 coupled to the upper base 114, a lower collector-emitter terminal 412 coupled to the lower collector-emitter 120, and a lower conductive terminal 414 coupled to the lower base 122. The upper collector-emitter 112 can be coupled to the upper terminal 140 of the switching assembly 400 via the upper collector-emitter terminal 408. The lower collector-emitter 120 can be coupled to the lower terminal 142 of the switching assembly 400 via the lower collector-emitter terminal 412.

[0056] Example driver 402 further includes controller 416 and electrical isolator 418. To place the DSDB BJT 200 into various on and off modes, example driver 402 includes multiple electrically controlled switches and charge carrier sources. Specifically, example driver 402 includes switch 422 having a first lead coupled to upper terminal 140, a second lead coupled to upper base 114, and a control input coupled to controller 416. Example switch 422 is shown as a single-pole single-throw switch, but in practice, switch 422 can be a FET, where the control input is the gate of the FET. Therefore, when switch 422 is turned on by asserting its control input, upper base 114 is coupled to upper terminal 140.

[0057] The driver 402 further includes a charge carrier source, illustratively shown as a controlled current source 424 (hereinafter simply referred to as upper current source 424). Upper current source 424 has a sink input coupled to upper terminal 140. Another electrically controlled switch 426 (hereinafter simply referred to as switch 426) has a first lead coupled to the source output of upper current source 424, a second lead coupled to upper base 114, and a control input coupled to controller 416. Example switch 426 is also shown as a single-pole single-throw switch, but in practice, switch 426 could be a FET, where the control input is the gate of the FET. Therefore, when switch 426 is turned on, upper current source 424 is coupled between upper terminal 140 and upper base 114.

[0058] The driver 402 further includes an upper master switch 146 having a first lead coupled to an upper terminal 140, a second lead defining an upper collector-emitter terminal 408 coupled to the upper collector-emitter 112, and a control input coupled to the controller 416. As previously described, the upper master switch 146 is illustrated as a single-pole single-throw switch, but in practice, the upper master switch 146 can be a FET, where the control input is the gate of the FET. Therefore, when the upper master switch 146 is turned on, for example by asserting its control input, the upper terminal 140 is coupled to the upper collector-emitter 112.

[0059] Turning now to the lower side of the DSDB BJT 200, example driver 402 further includes a switch 432 having a first lead coupled to lower terminal 142, a second lead coupled to lower base 122, and a control input coupled to controller 416. Example switch 432 is shown as a single-pole single-throw switch, but in practice, switch 432 could be a FET, where the control input is the gate of the FET. Therefore, when switch 432 is turned on by asserting its control input, lower base 122 is coupled to lower terminal 142.

[0060] The driver 402 further includes a charge carrier source, illustratively shown as a controlled current source 434 (hereinafter simply referred to as lower current source 434). Lower current source 434 has a sink input coupled to lower terminal 142. Another electrically controlled switch 436 (hereinafter simply referred to as switch 436) has a first lead coupled to a source output of lower current source 434, a second lead coupled to lower base 122, and a control input coupled to controller 416. Example switch 436 is shown as a single-pole single-throw switch, but in practice, switch 436 could be a FET, where the control input is the gate of the FET. Therefore, when switch 436 is turned on, lower current source 434 is coupled between lower terminal 142 and lower base 122.

[0061] Example driver 402 further includes a lower master switch 144 having a first lead coupled to a lower terminal 142, a second lead defining a lower collector-emitter terminal 412 coupled to the lower collector-emitter 120, and a control input coupled to the controller 416. As previously described, example lower master switch 144 is shown as a single-pole single-throw switch, but in practice, lower master switch 144 can be a FET, where the control input is the gate of the FET. Therefore, when lower master switch 144 is turned on, for example by asserting its control input, lower terminal 142 is coupled to the lower collector-emitter 120.

[0062] Controller 416 defines control inputs 442 and 444 and control outputs 446, 448, 450, 452, 454, 456, 458, and 460. When implemented, control output 446 is coupled to the control input of the upper current source 424. Control outputs 448, 450, 452, 454, 456, and 458 are coupled to the control inputs of switches 146, 426, 422, 432, 436, and 144, respectively. When implemented, control output 460 is coupled to the control input of the lower current source 434.

[0063] When control input 442 is asserted, controller 416 is designed and configured to arrange DSDB BJT 200 for conduction from upper terminal 140 to lower terminal 142. Conversely, when control input 442 is deasserted, controller 416 is designed and configured to arrange DSDB BJT 200 to block current flow from upper terminal 140 to lower terminal 142. Similarly, when control input 444 is asserted, controller 416 is designed and configured to arrange DSDB BJT 200 for conduction from lower terminal 142 to upper terminal 140. When control input 444 is deasserted, controller 416 is designed and configured to arrange DSDB BJT 200 to block current flow from lower terminal 142 to upper terminal 140. When both control inputs 442 and 444 are asserted, controller 416 arranges the DSDB BJT 200 for current flow in both directions (e.g., AC circuit breaker service), and when both control inputs 442 and 444 are deasserted, controller 416 blocks current flow in both directions.

[0064] The passive and active shutdown arrangements of the instance DSDB BJT 200 depend on the polarity of the applied voltage. Therefore, the instance controller 416 can further define a polarity input 462 that receives a Boolean signal indicating the applied polarity. In the instance driver 402, comparator 464 has a first input coupled to the upper terminal 140 (connection shown by bubble "A") and a second input coupled to the lower terminal 142. Comparator 464 defines a comparison output coupled to the polarity input 462. Although... Figure 4 The first and second inputs are shown directly coupled to their respective conductive terminals, but in practice, when not conducting, the voltage across the DSDB BJT 200 can be very large (e.g., 1200 V), and therefore each of the first and second inputs can be coupled to its respective conductive terminal via a corresponding voltage divider circuit. Alternatively, the applied polarity can be determined by a Boolean signal sent to control input 462 from external systems and devices and the trans-isolator 418 to the switch assembly 400.

[0065] The process of switching the DSDB BJT 200 from non-conducting to conducting and then back to non-conducting can be a multi-step process. To implement this multi-step process, the controller 416 can be an individual circuit component, an application-specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC), a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field-programmable gate array (FPGA), a programmable system-on-a-chip (PSOC), and / or a combination thereof, configured to read control inputs 442, 444, read polarity input 462, and drive control outputs to implement the mode switching of the DSDB BJT 200.

[0066] In the example system, the switch assembly 400 is electrically floating. To receive control inputs 442 and 444 in the electrical domains of the switch assembly 400, the example driver 402 implements an electrical isolator 418. The example electrical isolator 418 can take any suitable form, such as an optocoupler or a capacitive isolation device. Regardless of the exact nature of the electrical isolator 418, external control signals (e.g., Boolean signals) can be coupled to the control inputs 466 and 468 of the electrical isolator 418. The electrical isolator 418 then transmits the control signals to the electrical domains of the switch assembly 400. In this example, the external control signals are transmitted to the control inputs 442 and 444 of the controller 416.

[0067] Consider, for example, the case where the applied voltage has a positive polarity at the upper terminal 140. Further consider the case where the control input 466 applied to the isolator 418 is deasserted, and therefore the control signal applied to the control input 442 of the controller 416 is deasserted. Based on the deassertion state of the control input 442, the controller 416 is designed and constructed such that the example DSDB BJT 200 is arranged in a non-conducting configuration to account for the applied polarity (e.g., as read by the controller 416 via the polarity input 462). Therefore, in the example arrangement, the upper main switch 146 is on, the lower main switch 144 is off, and switch 432 is on (passively off). In some examples, the upper main switch 146 is turned on by the controller 416 asserting the control output 448. However, in other cases, the upper main switch 146 is implemented as a FET with an internal body diode. Therefore, the conduction of the upper main switch 146 may initially be based at least on an applied voltage that forward-biases the body diode of the FET implementing the upper main switch 146. When arranged to block currents of opposite polarity, the lower main switch 144 may have a similar arrangement and / or operation.

[0068] Still considering the example arrangement with positive polarity at the upper terminal 140, it is now assumed that the control signal applied to the control input 466 of the electrical isolator 418 is asserted, and therefore the control signal applied to the control input 442 of the controller 416 is also asserted. Based on this assertion, in the example switch assembly 400, the controller 416 can be designed and constructed to allow the example DSDB BJT 200 to be directly in an active-on arrangement. Figure 3ETo this end, controller 416 may assert control output 448 (if not already asserted) to turn on upper main switch 146, assert control output 450 to turn on switch 426, assert control output 458 to turn on lower main switch 144, and deassert remaining control outputs or leave remaining control outputs deasserted. In some cases, controller 416 may modulate the signal driven to control output 446 coupled to upper current source 424 to provide turn-on current and then steady-state current, as discussed in more detail below; however, in other cases, upper current source 424 provides turn-on current and then steady-state current whenever switch 426 is turned on without specific instruction from controller 146.

[0069] Optionally, when the positive polarity is again at the upper terminal 140, the controller 416 can be designed and configured to place the DSDB BJT 200 in an intermediate conduction arrangement before achieving an active-on arrangement. For example, the controller 416 can temporarily place the DSDB BJT 200 in a passive-on arrangement by asserting control output 448 to turn on the upper main switch 146, asserting control output 458 to turn on the lower main switch 144, and deasserting the remaining control outputs or keeping the remaining control outputs deasserted. Figure 3D When used, the passive turn-on arrangement can be maintained for a predetermined period of time (e.g., from approximately 0.1 μs to 5 μs). As another example of an intermediate turn-on state, the controller 416 can temporarily position the DSDBBJT 200 in a diode-on arrangement by asserting control output 452 to turn on switch 422, asserting control output 458 to turn on the lower main switch 144, and deasserting the remaining control outputs or keeping the remaining control outputs deasserted. Figure 3C When used, the diode-on arrangement can be sustained for a predetermined period of time (e.g., from about 0.1 μs to 5 μs). In practice, the upper main switch 146 may have an internal body diode or be associated with a discrete parallel diode, making the diode-on arrangement impossible to implement because the body diode or discrete parallel diode would be forward biased when the positive polarity is at the upper terminal 140. If the lower main switch 144 has a body diode or discrete parallel diode, a similar inability to implement the diode-on arrangement may exist when the positive polarity is at the lower terminal 142. However, after the intermediate conduction arrangement, the controller 416 puts the DSDB BJT 200 into an active-on arrangement.

[0070] In an active-on configuration, and for the positive polarity at the upper terminal 140, the upper current source 424 injects charge carriers into the upper base 114. Injecting charge carriers into the upper base 114 increases the number of charge carriers in the drift region of the DSDB BJT 200, an example of a PNP structure, which reduces the Vo across the upper collector-emitter 112 to the lower collector-emitter 120. CEONIn one example, for a current of approximately 30 A to 100 A, the injected charge carrier current source 424 can reduce the voltage across collector-emitter 112 and 120. CEON The voltage is reduced to approximately 0.2 V. In some instances, the current source 424 is designed and constructed to provide a turn-on current (e.g., between 5 A and 10 A) and then a steady-state current (e.g., approximately 5 A). Current sources, rather than voltage sources, are used to explain the manufacturing variations between DSDB BJTs. For example, one DSDB BJT might require a bias of approximately 2 V from emitter-collector to base to achieve a base current of 5 A, while a second DSDB BJT, or even the opposite side of the same DSDB BJT, might only require a bias of 1.6 V to achieve the same base current.

[0071] Still referencing Figure 4 Furthermore, the positive polarity at the upper terminal 140 is still considered. Further, consider the change in the control input 466 applied to the isolator 418 from assertion to deassertion, and thus the change in the control signal applied to the control input 442 of the controller 416 from assertion to deassertion. Based on this change, the controller 416 is designed and configured to again place the DSDB BJT 200 in a non-conducting arrangement. In an example, the controller 416 can directly implement a passive shutdown arrangement from the on state of the DSDB BJT 200, as previously discussed. Optionally, the controller 416 can be designed and configured to use the DSDB BJT 200 in an intermediate conducting arrangement before reaching the non-conducting arrangement. For example, the controller 416 can temporarily place the DSDB BJT 200 in a diode-on arrangement (…). Figure 3C ), passive connection arrangement ( Figure 3D ) or pre-shutdown arrangement ( Figure 3F When in use, the intermediate arrangement between active on and active off can last for a predetermined period of time (e.g., from about 0.1 μs to 5 μs).

[0072] about Figure 4 The example operation discussed is for the positive polarity at the upper terminal 140. However, again, the example DSDB BJT200 and its associated driver are symmetrical, and it should now be understood how the DSDB BJT 200 can be arranged in various on and off states to directly control the current flow in the opposite direction.

[0073] Figure 4The example of a switch assembly 400 arranged for cascaded operation is shown in the diagram, specifically the DSDB BJT 200. In this arrangement, interruption of current flowing through the device (e.g., during the transition from on to off) is primarily implemented by the upper main switch 146 and the lower main switch 144. For instance, when the positive polarity is at the upper terminal 140, the current flowing through the switch assembly 400 is first interrupted by the lower main switch 144 and then further blocked by the DSDB BJT 200. Conversely, when the positive polarity is at the lower terminal 142, the current flowing through the switch assembly 400 is first interrupted by the upper main switch 146 and then further blocked by the DSDB BJT 200. Therefore, because the blocking is implemented by the DSDB BJT 200, the breakdown voltages of the upper main switch 146 and the lower main switch 144 can be significantly lower than the breakdown voltage of the DSDB BJT 200. For example, each of the upper main switch 146 and the lower main switch 144 may have a breakdown voltage of 100V or less, and in some cases, 80V or less, while the breakdown voltage of the DSDB BJT 200 may be 600V or greater, and in some cases about 1200V.

[0074] During the transition from a conducting to a non-conducting state via collector-emitter 112 and 120, a relatively small current (cutoff current) can temporarily flow based on the side opposite to the positive polarity. For example, when the positive polarity is on the upper terminal 140 and current flows from the upper collector-emitter 112 to the lower collector-emitter 120, interruption of current flow by the lower main switch 144 can cause a temporary cutoff current to flow through the lower base 122. In other words, when the load current through the DSDB BJT 200 is interrupted by the lower main switch 144, the cutoff current commutates through the lower base 122 for a short period of time because the lower PN junction becomes reverse biased (remember, for these assumptions, the lower base 122 is electrically floating during conduction). Therefore, the passive shutdown arrangement ( Figure 3A This provides a current path to the lower terminal 142 for interrupting the current. It should now be understood that when the correction voltage is at the upper terminal 140, the current is commutated through the lower base 122, and then it can be directly and equivalently stated that when the correction voltage is at the lower terminal 142, the current is commutated through the upper base 114.

[0075] Figure 5 This section shows a partial circuit diagram of the example switch assembly 400. Figure 5 This demonstrates a portion of the PNP-constructed DSDB BJT200 instance and instance driver 402. Driver 402 may also have an electrical isolator, controller, and comparator, but these components are derived from... Figure 5 The abbreviation symbol is omitted. For the purpose of discussion, the upper side... Figure 5Showing switches 422, 426, and 146, as well as current source 424 in the example. Below, showing switches 432, 436, and 144, as well as current source 434 in the example.

[0076] As mentioned above, many switches are implemented as FETs. Figure 5 In the example switch assembly, the upper main switch 146 is shown as a FET, having a source coupled to the upper terminal 140, a drain coupled to the upper collector-emitter 112, a gate defining a control input, and a body diode coupled between the source and drain. When a voltage with positive polarity is applied to the upper terminal 140, the body diode is forward biased to turn on the upper main switch 146 (without controller 416). Figure 4 (The function of the controller 416). During the on-state of the DSDB BJT200, the controller 416 drives the gate to turn on the FET to reduce the total voltage drop. In example cases, the FET used to implement the upper main switch 146 may have a breakdown voltage of 100 V or less, and in some cases about 80 V, although in fact the DSDB BJT 200 may have a breakdown voltage of 600 V or more, and in some cases about 1200 V.

[0077] Example switch 422 is shown as a single FET, having a source coupled to upper terminal 140, a drain coupled to upper base 114, and a gate. The gate of the FET is coupled to controller 416. Figure 4 The FET has a body diode with an anode coupled to the upper terminal 140 and a cathode coupled to the upper base 114. When the positive polarity is on the upper terminal 140, the switch 422 can be arranged in a diode-on configuration. Figure 3C ) or pre-shutdown arrangement ( Figure 3F During the active connection period, conduction occurs. However, in an active connection configuration ( Figure 3E During this period, switch 422 is not turned on to allow the upper current source 424 to inject charge carriers into the upper base 114. That is, in the active-on arrangement, controller 416 cancels the assertion of the FET gate, and because the upper base 114 is forward biased based on the upper current source 424, the body diode is reverse biased (no current flows through switch 422). In the case where the positive polarity is on the lower terminal 142, switch 422 can be turned on when switching to the passive-off arrangement. For example, the interruption current in the passive-off arrangement can be carried by switch 422.

[0078] Similarly, switch 426 is shown as a single FET. Specifically, switch 426 is shown as a single FET having a source coupled to upper base 114, a drain coupled to the source output of upper current source 424, and a gate. The gate of the FET is coupled to controller 416. Figure 4The FET has a body diode, and in the illustrated arrangement, the anode is coupled to the upper base 114 and the cathode is coupled to the source output of the upper current source 424. When the positive polarity is at the upper terminal 140, the active-on arrangement can be implemented by injecting charge carriers into the upper base 114 via the upper current source 424 through the FET. In other modes, when the switch 426 is not turned on, the current flow from the upper current source 424 to the upper base 114 is blocked.

[0079] Still referencing Figure 5 The lower main switch 144 is shown as a FET, having a source coupled to the lower terminal 142, a drain coupled to the lower collector-emitter 120, a gate defining the control input, and a body diode coupled between the source and drain. When a positive voltage is applied to the lower terminal 142, the body diode is forward biased to turn on the lower main switch 144 (without controller 416). Figure 4 (The function of the controller 416). During the on-state of the DSDB BJT 200, the controller 416 drives the gate to turn on the FET to reduce the total voltage drop. In example cases, the FET used to implement the lower main switch 144 may have a breakdown voltage of 100 V or less, and in some cases about 80 V, although in fact the DSDB BJT 200 may have a breakdown voltage of 600 V or more, and in some cases about 1200 V.

[0080] Example switch 432 is shown as a single FET, having a source coupled to lower terminal 142, a drain coupled to lower base 122, and a gate. The gate of the FET is coupled to controller 416. Figure 4 The FET has a body diode with an anode coupled to the lower terminal 142 and a cathode coupled to the lower base 122. When the positive polarity is on the lower terminal 142, the switch 432 can be arranged in a diode-on configuration. Figure 3C ) or pre-shutdown arrangement ( Figure 3F During the active connection period, conduction occurs. However, in an active connection configuration ( Figure 3E During this period, switch 432 is not turned on to allow the lower current source 434 to inject charge carriers into the upper base 114. That is, in the active-on arrangement, controller 416 cancels the assertion of the FET gate, and because the lower base 122 is forward biased based on the lower current source 434, the body diode is reverse biased (no current flows through switch 432). In the case where the positive polarity is on the upper terminal 140, switch 432 can be turned on when switching to the passive-off arrangement. For example, the interruption current in the passive-off arrangement can be carried by switch 432.

[0081] Similarly, switch 426 is shown as a single FET. Specifically, switch 426 is shown as a single FET having a source coupled to the lower base 122, a drain coupled to the source output of the lower current source 434, and a gate. The gate of the FET is coupled to controller 416. Figure 4 The FET has a body diode, and in the illustrated arrangement, the anode is coupled to the lower base 122 and the cathode is coupled to the source output of the lower current source 434. When the positive polarity is on the lower terminal 142, the active-on arrangement can be implemented by injecting charge carriers into the lower base 122 via the lower current source 434 through the FET. In other modes, current flow from the lower current source 434 to the lower base 122 is blocked when the switch 436 is not turned on.

[0082] The body diodes of switches 426 and 436 can be used to implement a power-on safety mode. That is, the body diodes of the switches ensure that race conditions when the switch assembly 400 is powered on do not lead to unintentional conduction through the DSDB BJT 200. Specifically, the switch assembly 400 may have an upper terminal 140 and a lower terminal 142 coupled within the overall system. Voltage may appear across the upper terminal 140 and the lower terminal 142 in either polarity before the controller 416 is powered on and / or before the controller 616 has the opportunity to bootstrap to an operating state. Consider, for example, a power-on condition in which a positive polarity appears at the upper terminal 140 before the controller 416 is operable. In this case, the body diode of the FET implementing the upper main switch 146 is turned on and the body diode of the FET implementing the lower main switch 144 is reverse biased. Leakage current through the DSDB BJT 200 causes the body diode of the FET implementing switch 436 to turn on. By combining a high-value resistor (not explicitly shown) connected in parallel with the lower current source 434, the switch assembly 400 effectively implements a passive shutdown arrangement. Figure 3A A similar arrangement occurs when positive polarity is applied to the lower terminal 142. Therefore, even without the control of the controller 416, the PNP-constructed instance DSDB BJT 200 enters a non-conducting safety mode regardless of the polarity of the voltage applied across the upper terminal 140 and the lower terminal 142.

[0083] In implementation plans in relevant fields, active connection deployments ( ) will evolve over time. Figure 3E This is implemented by multiple voltage sources. For example, in commonly assigned U.S. Patent 11,522,051, and particularly the patent... Figure 9 In this design, two separate voltage sources are used to inject charge carriers on each side of the device, with the 5V source (reference number 826 in this patent) primarily used to rapidly reduce V. CEON And then a 1 V source (reference number 822 in this patent) is used to maintain the reduced V CEONHaving multiple selectively applied voltage sources increases the cost and complexity of the switching module.

[0084] The inventors of this specification have discovered that by using a current source instead of multiple voltage sources, the complexity of the switching assembly can be significantly reduced while still retaining the benefits of dual charge carrier injection. (See also:) Figure 5 And particularly the upper current source 424. In an instance where the polarity is corrected at the upper terminal 140, turning on the switch assembly 400 may involve arranging the DSDB BJT 200 to conduct by first driving an on-state current from the upper current source 424 to the upper base 114 and then providing a steady-state current from the upper current source 424 to the upper base 114 (e.g., Figure 3E In various instances, the steady-state current provided by the current source is lower than the turn-on current. In other words, the turn-on current provided by the current source 424 is used to charge the base-emitter capacitor and enable the DSDB BJT 200 to turn on quickly, while the steady-state current is used to maintain a low V. CEON Conversely, turning on the switch assembly 400 when a polarity correction is applied to the lower terminal 142 may involve arranging the DSDB BJT 200 to conduct by first driving an on-state current from the lower current source 434 to the lower base 122 and then providing a steady-state current from the lower current source 434 to the lower base 122 (e.g., by arranging the DSDB BJT 200 to conduct). Figure 3E Here, the steady-state current supplied from the lower current source is also lower than the turn-on current.

[0085] That is, the inventors of this specification have discovered that a single current source associated with the base of the DSDB BJT 200 can be used instead of multiple voltage sources, thereby significantly reducing the complexity and number of components used to implement the switching assembly 400. Furthermore, the use of a current source instead of a voltage source takes into account manufacturing variations between DSDB BJTs. For example, one DSDB BJT may require approximately 2 V of bias from emitter-collector to base to achieve an example steady-state base current of 5 A, while a second DSDB BJT, or even the opposite side of the same DSDB BJT, may only require a 1.6 V bias to achieve an example steady-state base current of 5 A. An example implementation of the current source is now described.

[0086] Figure 6 Partial schematic diagrams and partial block diagrams of an example switch assembly 400 according to at least some embodiments are shown. Specifically, Figure 6 The upper terminal 140, upper main switch 146, example DBSD BJT 200, lower main switch 144, and lower terminal 142 are shown. Figure 6 Switches 422 and 426 associated with the upper base 114 and switches 432 and 436 associated with the lower base 122 are also shown. Figure 6Electrical isolator 418 and controller 416 are also shown; however, the electrical connection between the electrical isolator 418 and controller 416 is not shown, nor is the electrical connection from controller 416 to the control inputs (e.g., gates) of various switches, so as not to make the diagram too complicated.

[0087] Figure 6 The isolated power supply 600 is further illustrated. In this context, the term "isolated" can have several meanings. In some cases, operating power is supplied to the switch assembly 400 from a power source different from the controlled power source coupled to the upper terminal 140 and the lower terminal 142. In such cases, "isolation" can mean that the switch assembly 400 is electrically floating relative to the power source, and in such cases, the power is supplied via an isolation transformer. The switch assembly 400 can also be described as "self-powered" because the operating power is obtained directly from the controlled power source applied to the upper terminal 140 and / or the lower terminal 142, and examples of "self-powered" switch assemblies are discussed in more detail below.

[0088] In this context, "isolation" can also mean that the isolated power supply 600 provides power rails to the upper and lower parts of the circuit, where these power rails carry voltages relative to different reference voltages or different returns. For this purpose, the example isolated power supply 600 shows a transformer 602 defining a primary winding 604, an upper secondary winding 606, and a lower secondary winding 608. The upper secondary winding 606 is associated with a rectifier 610. The rectifier 610 can take many forms, depending on the operation of the isolated power supply 600. For example, the rectifier 610 can be a half-wave or full-wave bridge and associated voltage regulator. In other cases, the isolated power supply 600 can be an isolated switching power converter (e.g., a flyback converter), and therefore the rectifier 610 can work with the circuitry associated with the primary winding 604 to generate a controlled DC voltage. In any case, the upper secondary winding 606 and the rectifier 610 define an upper power rail 612 carrying a voltage referenced to the upper circuit 614 coupled to the upper terminal 140. In other words, the supply voltage provided to the upper power rail 612 is a DC voltage referenced to the voltage on the upper terminal 140. Therefore, the voltage delivered on the upper power rail 612 can be used to inject charge carriers into the upper base 114.

[0089] Still referencing Figure 6The secondary winding 608 is associated with rectifier 616. Depending on the operation of the isolation power supply 600, rectifier 616 can also take many forms, such as a half-wave or full-wave bridge and associated voltage regulator or flyback converter secondary rectifier. In any case, the secondary winding 608 and rectifier 616 define a lower power rail 618 that carries a voltage referenced to the lower circuit 620 coupled to the lower terminal 142. In other words, the supply voltage provided to the lower power rail 618 is a DC voltage referencing the voltage on the lower terminal 142. Therefore, the voltage carried on the lower power rail 618 can be used to inject charge carriers into the lower base 122. In some cases, the DC voltages on the upper power rail 612 and the lower power rail 618 have the same magnitude and can be between 3.3 V and 20 V, and in some cases about 5 V.

[0090] Example switch assembly 400 shows an upper current source 424, exemplified as a buck converter 622. Example buck converter 622 is designed and constructed to function as a current source, thereby modulating the voltage to supply both on-state and subsequent steady-state currents to the upper base 114. Similarly, example switch assembly 400 shows a lower current source 434, exemplified as a buck converter 624. Example buck converter 624 is designed and constructed to function as a current source, thereby modulating the voltage to supply both on-state and subsequent steady-state currents to the lower base 122. Buck converters 622 and 624 can take any suitable form. In most cases, buck converters 622 and 624 are repetitive circuits, but a repetitive buck converter is not strictly required. An example implementation of a buck converter is now described.

[0091] Figure 7 Partial block diagrams and partial circuit diagrams of a buck converter 622 according to at least some embodiments are shown. Specifically, the example buck converter 622 includes a driver 700, an inductor 702, voltage feedback 704, and current feedback 706. The driver 700 defines a voltage input 708 coupled to an upper power rail 612, a switching node terminal 710 coupled to a first lead of the inductor 702, and a feedback terminal 712 coupled to both voltage feedback 704 and current feedback 706. Additional terminals, such as power terminals, ground or return terminals, and terminals through which startup power is provided to the driver 700, will be present. These additional terminals are not shown to avoid overcomplicating the diagram.

[0092] The driver 700 is designed and constructed to apply a square wave voltage to the switching node terminal 710 by alternately coupling the upper power rail 612 to the switching node terminal 710 and then coupling a voltage reference or return to the switching node terminal 710. During the period when the upper power rail 612 is coupled to the switching node terminal 710, current ramps through the inductor 702 and energy is stored in the field around the inductor (inductor charging mode). During the period when the return is coupled to the switching node terminal 710, the field around the inductor 702 collapses as the inductor 702 continues to supply current to downstream devices (inductor discharging mode). Based on the signal received at the feedback terminal 712, the driver 700 controls the voltage / current supplied from the inductor 702 by controlling the frequency and / or duty cycle of the square wave voltage applied to the switching node. Furthermore, the voltage reference or return of the buck converter 622 is the upper terminal 140 of the switching assembly 400. Figure 7 The voltage on (not shown in the image).

[0093] According to various examples, the feedback to driver 700 has a voltage feedback component provided by voltage feedback 704 and a current feedback component provided by current feedback 706. Example voltage feedback 704 includes a Zener diode 716 with its cathode coupled to a voltage output 714 defined by the second lead of inductor 702 and its anode coupled to a feedback terminal and also coupled to a loop via resistor 718. Once the voltage output 714 overcomes the breakdown voltage of the Zener diode, a feedback signal proportional to the voltage on the voltage output 714 is provided to feedback terminal 712. In other cases, voltage feedback may be provided by a shunt voltage reference or similar analog circuitry. In any case, in example examples, as the output voltage increases, the magnitude of the feedback signal from voltage feedback 704 also increases, and vice versa.

[0094] Current feedback 706 is designed and constructed to generate current supplied from inductor 702 to upper base 114 ( Figure 7(Not shown) Current feedback proportional to the current. Example current feedback 706 includes a shunt or series resistor 720 coupled in series with the current supplied from inductor 702. The series resistor 720 has a relatively small value (e.g., 2 ohms to 10 ohms), and the voltage drop across the series resistor 720 is therefore proportional to the current supplied from inductor 702. In other cases, the signal indicating the current can be extracted by a current transformer or Hall effect sensor coupled in series with voltage output 714. Example current feedback 706 further includes an amplifier 722, which defines a first input coupled to a first lead of the series resistor 720, a second input coupled to a second lead of the series resistor 720, and an amplifier output 724. Amplifier 722 can be, for example, an operational amplifier with various feedback paths to control or set the gain; however, various feedback paths and power connections are omitted to avoid making the diagram overly complex. Amplifier 722 is designed and constructed to generate a voltage on amplifier output 724 proportional to the current supplied from inductor 702 to upper base 114. In the example system, amplifier output 724 is coupled to a voltage divider consisting of resistors 726 and 728 that include a loop referencing upper power rail 612. The node between resistors 726 and 728 is coupled to the anode of diode 730, and the cathode of diode 730 is coupled to feedback terminal 712. In operation, current feedback 706 generates a feedback signal proportional to the current. Once the current-proportional feedback signal rises above the feedback signal generated by voltage feedback 704 (e.g., forward biasing diode 730), the feedback provided to driver 700 is controlled or dominated by current feedback 706.

[0095] When the buck converter 622 passes through switch 426 ( Figure 4 When the inductor 702 is disconnected from the upper base 114, no current flows through the inductor 702, and therefore the driver 700 regulates the output voltage solely based on the feedback signal provided from the voltage feedback 704. For example, the driver 700 and the voltage feedback 704 may be designed and constructed to regulate the output voltage to 5 V with little or no current flowing through the inductor 702. However, when the buck converter 622 is coupled to the upper base 114 via the switch 426, current is driven to the upper base 114. Specifically, when the switch 426 is closed or open, the buck converter 622 first drives the turn-on current to the upper base 114. In the example system, because no current is supplied before the switch 426 is closed, the turn-on current is based solely on the voltage output associated with the feedback signal from the voltage feedback 704 (i.e., the feedback signal from the current feedback 706 is 0 or lower).

[0096] As the current ramps up, the contribution of the feedback signal from current feedback 706 also ramps up, and ultimately the feedback signal from current feedback 706 forward biases diode 730 and helps provide a feedback signal to feedback terminal 712, thereby driving the output voltage down. That is, after providing the turn-on current, buck converter 622 provides steady-state current based on the feedback signals from voltage feedback 704 and current feedback 706. In the example system, the transfer function of the feedback path can be dominated by the integral component. That is, when it comes to proportional-integral-derivative (PID) control, the transfer function of the feedback path can be dominated by the integral component, this PI, or only integral. As a result, as the feedback signal applied to feedback terminal 712 ramps up, there is control hysteresis. Therefore, the turn-on current reaches a higher peak value than the steady-state current. Conversely, the steady-state current is lower than the peak value of the turn-on current.

[0097] Although in the example system, the transfer function of the feedback path allows the on-state current to be higher than the steady-state current, the relationship can be implemented in any suitable manner. For example, and as by Figure 4 This implies that controller 416 can drive a current setpoint signal to buck converter 622, wherein the current setpoint signal initially indicates a higher on-state current, and then controller 416 can reduce the current setpoint signal to indicate a lower steady-state current.

[0098] Still referencing Figure 7 The driver 700 can take many suitable forms, and Figure 7 This illustrates an example implementation. Example driver 700 includes an upper FET 750, a lower FET 752, a gate driver 754, a PWM controller 756, and a differential amplifier 758. The upper FET 750 (as it is named in the figure) has a drain coupled to an upper power rail 612, a source coupled to a switching node terminal 710, and a gate coupled to the gate driver 754. The lower FET 752 (as it is named in the figure) has a drain coupled to the switching node terminal 710, a source coupled to a loop (e.g., upper terminal 140), and a gate coupled to the gate driver 754. When the upper FET 750 is on and the lower FET 752 is off, the upper power rail 612 is coupled to the switching node terminal 710 (charging mode of inductor 702). Conversely, when the lower FET 752 is on and the upper FET 750 is off, the loop is coupled to the inductor 702 (discharging mode of inductor 702). Example FETs 750 and 752 are shown as integrated with driver 700 (e.g., on the same die as other components or in a co-package with other components); however, in other cases, such as for higher ampere numbers, one or both of FETs 750 and 752 may be discrete components external to driver 700.

[0099] Gate driver 754 is coupled to the gates of FETs 750 and 752. In response to the state of control input 760, gate driver 754 controls the on-state of FETs 750 and 752. Specifically, the gate driver can provide voltage and current to control the on-state of the FETs. Furthermore, gate driver 754 can impose timing constraints between the on-states of the FETs to ensure that the upper power rail 612 is not unintentionally shorted into a loop, a phenomenon known as breakdown.

[0100] The PWM controller 756 defines an error input 762 and a drive output 764 coupled to a control input 760. The error input 762 receives a signal indicating the voltage error between the setpoint voltage and the feedback signal. The PWM controller drives a pulse-width modulation (PWM) signal to the drive output 764, wherein the duty cycle and / or frequency of the PWM signal controls the voltage output 714 of the buck converter 622. The PWM controller 756 can operate the buck converter 622 using any suitable control scheme, such as current-mode control where the peak current during each changing mode controls the transition from charging to discharging mode, or voltage-mode control where the peak current during each charging mode is controlled by a voltage ramp signal that crosses with the error signal provided to the error input 762.

[0101] Still referencing Figure 7 Example driver 700 includes differential amplifier 758. Example differential amplifier 758 defines a first input coupled to feedback terminal 712 and coupled to voltage reference V. REF The second input of 766, where V REF 766 is a voltage representing the set-point voltage of the buck converter 622. The example differential amplifier 758 defines a differential output 768 coupled to the error input 762, which includes a low-pass filter 770, illustratively shown as a series resistor and capacitor. In various examples, the gain of the differential amplifier 758 and the response of the low-pass filter 770 may fully or partially define the transfer function of the feedback loop of the buck converter 622. However, it is desirable that the transfer function be implemented in any suitable manner.

[0102] Figure 7 The discussion is based on the upper current source 424 implemented as a buck converter 622. However, it should now be understood that the description of the buck converter 622's operation of injecting current into the upper base 114, and the description of the lower current source 434 implemented as a buck converter 624 for injecting current into the lower base 122, is repetitive and will not be repeated to avoid making the explanation too lengthy. That is, the buck converter 624 operates similarly, except that the buck converter 624 draws power from the lower power rail 618 having a voltage at the reference lower terminal 142.

[0103] Figure 8This diagram shows a partial schematic and block diagram of an example switch assembly 400. In some cases, the switch assembly is powered by a power source that is separate from and different from the controlled power supply flowing through terminals 140 and 142 of the switch assembly 400. In other cases, and as... Figure 8 As shown, the switch assembly can obtain operating power from a controlled power supply. For this purpose, example isolated power supply 600 defines a power input 810 coupled to upper terminal 140 and a neutral or ground 800. Although Figure 8 A ground 800 is shown passing through the switch assembly 400, but in other cases, the ground may be external to the switch assembly 400. The isolated power supply 600 thus receives operating power from a controlled power supply. As discussed above, the voltage and current of the controlled power supply may relate to a neutral or ground connection different from the circuit on the secondary side of the transformer 602, allowing the upper current source 424 and the lower current source 434 to drive charge carriers to their respective bases relative to the voltages on their respective collector-emitter junctions. Therefore, the neutral connection to the isolated power supply 600 is shown as a ground connection.

[0104] Figure 9 A method according to at least some embodiments is illustrated. Specifically, the method begins (block 900) and includes: blocking current flow from the upper terminal of a switching assembly to the lower terminal of the switching assembly by a transistor (block 902); and then conducting a first load current from the upper terminal to the lower terminal in response to an assertion of a conduction signal (block 904). Conducting the first load current from the upper terminal to the lower terminal (i.e., block 904) can be achieved by: closing the upper main FET coupled between the upper terminal and the upper collector-emitter of the transistor (block 906); closing the lower main FET coupled between the lower collector-emitter of the transistor and the lower terminal (block 908); driving a first on-state current from the upper current source to the upper base of the transistor (block 910); and then providing a first steady-state current from the upper current source to the upper base, the first steady-state current being lower than the first on-state current (block 912). Thereafter, the method ends (block 914) and may restart, for example, where the current flows in the opposite direction.

[0105] Many electrical connections in the figures are shown as direct couplings without interventional devices, but this is not explicitly stated in the above description. However, this paragraph should serve as a preliminary basis for the claims to refer to any electrical connection as a “direct coupling” for the electrical connections shown in the figures without interventional devices. Furthermore, this paragraph should not preclude the term “direct coupling” from referring to a base connected to the collector-emitter junction via a transistor.

[0106] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Those skilled in the art will recognize numerous variations and modifications upon fully understanding the above disclosure. The appended claims are intended to be interpreted as encompassing all such variations and modifications.

Claims

1. A method for operating a switch assembly, the method comprising: The transistor blocks the current flow from the upper terminal of the switch assembly to the lower terminal of the switch assembly; And then, in response to the assertion of the conducted signal, The first load current is conducted from the upper terminal to the lower terminal in the following manner: Closed coupling between the upper terminal and the upper collector-emitter of the transistor; A lower main FET is closed-coupled between the lower collector-emitter of the transistor and the lower terminal; The first turn-on current is driven from the upper current source to the upper base of the transistor; And then A first steady-state current is provided from the upper current source to the upper base, and the first steady-state current is lower than the first turn-on current.

2. The method of claim 1, further comprising interrupting the first load current by disconnecting the lower main FET, and then arranging the transistor to block the current from the upper terminal to the lower terminal.

3. The method according to claim 2, further comprising: The transistor blocks the current flow from the lower terminal to the upper terminal; And then, in response to the assertion of the conducted signal, The second load current is conducted from the lower terminal to the upper terminal in the following manner: Close the lower main FET; Close the upper main FET; The second turn-on current is driven from the lower current source to the lower base of the transistor; And then A second steady-state current is provided from the lower current source to the lower base, the second steady-state current being lower than the second turn-on current.

4. The method according to claim 3, wherein the first steady-state current is equal to the second steady-state current.

5. The method according to claim 3: Driving the first on-current from the upper current source includes driving the first on-current from the upper power converter based on a first upper feedback obtained from the output voltage of the upper power converter; The provision of the first steady-state current from the upper current source includes providing the first steady-state current from the upper power converter based on a second upper feedback obtained from the current provided by the upper power converter; Driving the second on-current from the lower current source includes driving the second on-current from the lower power converter based on a first lower feedback obtained from the output voltage of the lower power converter; and Providing the second steady-state current from the lower current source includes providing the second steady-state current from the lower power converter based on a second lower feedback obtained from the current provided by the lower power converter.

6. The method according to claim 3, further comprising extracting the energy of the first on-state current and the first steady-state current from the upper terminal, and extracting the energy of the second on-state current and the second steady-state current from the upper terminal.

7. The method according to claim 1: Driving the first on-current from the upper current source includes driving the first on-current from the upper power converter based on first feedback obtained from the output voltage of the upper power converter; and The provision of the first steady-state current from the upper power converter includes providing the first steady-state current from the upper power converter based on a second feedback obtained from the current provided by the upper power converter.

8. The method according to claim 1: Driving the first on-current from the upper current source includes driving the first on-current from the upper power converter based on a first setting point; and Providing the first steady-state current from the current source includes driving the first steady-state current from the power converter based on a second setpoint different from the first setpoint.

9. The method according to claim 1, further comprising extracting the energy of the first on-state current and the first steady-state current from the upper terminal.

10. A switch assembly comprising: Upper and lower terminals; A transistor is defined as having an upper base, an upper collector-emitter junction, a lower base, and a lower collector-emitter junction. An upper current source having a sink input coupled to the upper terminal and a source output; The upper master FET is defined as a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter, and a gate; The lower main FET is defined as a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate; A controller, coupled to the gate of the upper main FET and the gate of the lower main FET, is configured to, for a first applied voltage across the upper and lower terminals: Assert the gate of the upper master FET; Assert the gate of the lower main FET; The current source is configured to provide a first on-state current to the upper base of the transistor and then to provide a first steady-state current to the upper base, the first steady-state current being lower than the first on-state current.

11. The switch assembly of claim 10, further comprising: The upper base FET is defined as a first lead coupled to the source output of the upper current source, a second lead coupled to the upper base, and a gate. The controller is coupled to the gate of the upper base FET, and when the controller configures the upper current source, the controller is configured to assert the gate of the upper base FET to couple the source output to the upper base.

12. The switch assembly of claim 10, further comprising: A lower current source having a sink input coupled to the lower terminal and a source output; and Wherein, for a second applied voltage across the upper and lower terminals, the polarity of the second applied voltage is opposite to that of the first applied voltage, the controller is configured to: Assert the gate of the lower main FET; Assert the gate of the upper master FET; The lower current source is configured to provide a second on-state current to the lower base of the transistor and then to provide a second steady-state current to the lower base, the second steady-state current being lower than the second on-state current.

13. The switching assembly of claim 12, wherein the current source is a switching power converter designed and constructed to control the output current as a controlled variable during at least the provision of the first steady-state current.

14. The switching assembly of claim 12, wherein the current source is a switching power converter designed and constructed to control the output current as a controlled variable during the provision of the first on-state current and during the provision of the first steady-state current.

15. The switch assembly of claim 12, further comprising: The upper base FET is defined as a first lead coupled to the source output of the upper current source, a second lead coupled to the upper base, and a gate. The lower base FET is defined as a first lead coupled to the source output of the lower current source, a second lead coupled to the lower base, and a gate. The controller is coupled to the gate of the upper base FET and the gate of the lower base FET; When the controller configures the upper current source, the controller is configured to assert the gate of the upper base FET to couple the source output of the upper current source to the upper base; and When the controller configures the lower current source, the controller is configured to assert the gate of the lower base FET to couple the source output of the lower current source to the lower base.

16. The switch assembly of claim 10, further comprising: A power supply is defined as having an upper power rail and a lower power rail. The power converter is configured to apply an upper rail voltage to the upper power rail, the upper rail voltage being referenced to the upper terminal; and The power converter is configured to apply a lower rail voltage to the lower power rail, the lower rail voltage being referenced to the lower terminal.

17. The switch assembly of claim 16, wherein the power supply has a power input coupled to the upper terminal.

18. The switching assembly of claim 10, wherein the current source is a switching power converter designed and constructed to control the output current as a controlled variable during at least the provision of the first steady-state current.

19. The switching assembly of claim 10, wherein the current source is a switching power converter designed and constructed to control the output current as a controlled variable during the provision of the first on-state current and during the provision of the first steady-state current.

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