Photoelectric co-packaging device and preparation method thereof

Abstract

The invention discloses a photoelectric co-packaging device and a preparation method thereof, and relates to the technical field of optical communication, the photoelectric co-packaging device comprises a substrate, an optical chip, an electric chip, an optical fiber array unit and an optical waveguide, the optical chip is electrically connected between the substrate and the electric chip, the electric chip is used for providing a driving signal and a control signal for the optical chip, and the optical fiber array unit is electrically connected with the substrate. The optical chip is provided with a plurality of optical couplers, the optical fiber array unit comprises a plurality of optical fibers in one-to-one correspondence with the plurality of optical couplers, and the optical waveguide is formed through a photon lead bonding method and is used for coupling each optical coupler to the corresponding optical fiber. Optical port position offset caused by warping of the optical chip and fiber core position offset caused by manufacturing tolerance of the optical fiber array are effectively compensated, coupling efficiency is improved, the energy efficiency ratio of the optical communication device is further improved, packaging difficulty is reduced, meanwhile, the optical chip is arranged between the substrate and the electric chip, heat dissipation of the electric chip is facilitated, and the service life of the electric chip is prolonged. The overall reliability and the long-term working stability of the photoelectric co-packaging device can be improved.

Description

Optoelectronic co-packaged devices and their fabrication methods Technical Field

[0001] This invention relates to the field of optical communication technology, and in particular to an optoelectronic co-packaged device and its fabrication method. Background Technology

[0002] With the development of optical communication technology towards higher speeds and larger capacities, optoelectronic co-packaging technology has become a research hotspot due to its ability to effectively shorten electrical signal transmission paths, reduce parasitic parameters, and improve system integration. However, existing optoelectronic co-packaging devices still face many challenges in practical applications. For example, during the manufacturing and packaging process of optical chips, warping deformation can easily occur due to differences in the thermal expansion coefficients of materials and process stress, leading to misalignment of the optical couplers on the optical chip. When the alignment accuracy between the optical coupler and the optical fiber in the fiber array unit is insufficient, it will significantly increase optical coupling loss and reduce optical signal transmission efficiency. This places extremely high precision requirements on the packaging process, thereby increasing the packaging difficulty. Summary of the Invention

[0003] The main objective of this invention is to propose an optoelectronic co-packaged device and its fabrication method, aiming to reduce the packaging difficulty.

[0004] To achieve the above objectives, the present invention proposes an optoelectronic co-packaged device comprising: a substrate, an optical chip, an electrical chip, an optical fiber array unit, and an optical waveguide. The optical chip is electrically connected between the substrate and the electrical chip, and the electrical chip is used to provide driving signals and control signals to the optical chip. The optical chip has multiple optical couplers. The optical fiber array unit includes multiple optical fibers, and each optical fiber corresponds one-to-one with a multiple optical coupler. The optical waveguide is formed by photonic wire bonding and is used to couple each optical coupler to the corresponding optical fiber.

[0005] In one embodiment, the optical chip has a through-silicon via (TSV), which is electrically connected to the substrate and the electrical chip.

[0006] In one embodiment, the electrical chip is electrically connected to the optical chip via bump bonding.

[0007] This invention also proposes a method for fabricating an optoelectronic co-packaged device, wherein the optoelectronic co-packaged device is based on the above-mentioned optoelectronic co-packaged device, and the fabrication method includes:

[0008] A substrate and an optical fiber array unit are provided; an electrical chip and an optical chip are fabricated, wherein the electrical chip includes a battery core body and a first connection bump disposed on the back side of the battery core body, and the optical chip includes an optical core body, a second connection bump disposed on the back side of the optical core body, and a metal layer under the first bump disposed on the front side of the optical core body; the first connection bump on the back side of the electrical chip is bonded to the metal layer under the first bump on the front side of the optical chip; the second connection bump on the back side of the optical chip is soldered to a ball grid array of the substrate, wherein the second connection bump is electrically connected to the metal layer under the first bump; the optical fiber array unit is mounted to the substrate, and an optical waveguide is fabricated by photonic wire bonding, so that the optical coupler of the optical chip is coupled to the optical fiber in the optical fiber array unit through the optical waveguide.

[0009] In one embodiment, the fabrication of the optical chip includes: bonding the front side of the optical core wafer to a carrier wafer; grinding and polishing the back side of the optical core wafer to reduce the thickness of the optical core wafer to a preset thickness; fabricating through-silicon vias (TSVs) within the optical core wafer; sequentially fabricating a redistribution layer and a second connection bump on the back side of the optical core wafer; removing the carrier wafer from the front side of the optical core wafer; and dicing the optical core wafer.

[0010] In one embodiment, the fabrication of a through-silicon via (TSV) within the optical core wafer includes: etching a TSV within the optical core wafer; depositing an insulating layer on the inner wall of the TSV and the back side of the optical core wafer; sequentially depositing a barrier layer and a thin copper seed layer on the surface of the insulating layer using a physical vapor deposition process; plating copper into the TSV using an electrochemical copper plating process; and performing chemical mechanical polishing on the back side of the wafer to form the TSV.

[0011] In one embodiment, the step of sequentially fabricating a redistribution layer and a second connection bump on the back side of the optical core wafer includes: electroplating copper on the back side of the optical core wafer to form a redistribution layer, at least a portion of the redistribution layer contacting the through-silicon via (TSV); depositing a dielectric layer on the back side of the optical core wafer; etching an opening in the dielectric layer to expose at least a portion of the redistribution layer; depositing a second bump under-metal layer within the opening; and electroplating or solder paste printing on the second bump under-metal layer to form a second connection bump.

[0012] In one embodiment, after bonding the first connection bump on the back side of the electrical chip to the first bump under the metal layer on the front side of the optical chip, and before soldering the second connection bump on the back side of the optical chip to the ball array of the substrate, the method further includes filling structural adhesive between the electrical chip and the optical chip.

[0013] In one embodiment, after the second connection bump on the back side of the optical chip is soldered to the ball array of the substrate, and before the optical fiber array unit is attached to the substrate and the optical waveguide is fabricated by photonic wire bonding, the method further includes filling structural adhesive between the optical chip and the substrate.

[0014] In one embodiment, mounting the fiber array unit to the substrate and fabricating an optical waveguide using a photonic wire bonding method, so that the optical coupler of the optical chip is coupled to the optical fiber within the fiber array unit through the optical waveguide, includes: applying photoresist to the surface of the substrate between the fiber array unit and the optical coupler; exposing the photoresist according to a preset pattern using a femtosecond laser two-photon polymerization direct writing method, causing the exposed portion of the photoresist to undergo a polymerization reaction to form a core layer; immersing the substrate in a developer solution to dissolve the unexposed portion of the photoresist; and applying an encapsulation layer to the surface of the core layer to form an optical waveguide; wherein the refractive index of the encapsulation layer is less than the refractive index of the core layer.

[0015] In the technical solution of this invention, the photonic wire bonding method can be based on the two-photon polymerization principle to customize the generation of a three-dimensional polymer optical waveguide according to the actual spatial position relationship between the optical chip coupler and the fiber array. This effectively compensates for the optical port position offset caused by the warping of the optical chip and the fiber core position offset caused by the manufacturing tolerance of the fiber array, thereby improving the coupling efficiency and thus improving the energy efficiency ratio of the optical communication device. It also significantly reduces the packaging difficulty. At the same time, the optical chip is connected between the substrate and the electrical chip, which is conducive to the heat dissipation during the operation of the electrical chip, and can improve the overall reliability and long-term working stability of the optoelectronic co-packaged device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 is a schematic diagram of an embodiment of the optoelectronic co-packaging device provided by the present invention.

[0018] Figure 2 is a schematic diagram of the optical chip included in the optoelectronic co-packaged device in Figure 1.

[0019] Figure 3 is a schematic diagram of the structure of the electrical chip included in the optoelectronic co-packaged device in Figure 1.

[0020] Figure 4 is a flowchart of the method for fabricating the optoelectronic co-packaged device provided by the present invention.

[0021] Figure 5 is a schematic diagram of the structure of the optical core wafer provided by the present invention before the thickness is reduced to a preset thickness.

[0022] Figure 6 is a schematic diagram of the structure of the optical core wafer provided by the present invention after the thickness is reduced to a preset thickness.

[0023] Figure 7 is a schematic diagram of the structure of the redistribution layer formed by electroplating copper on the back side of the optical core wafer provided by the present invention.

[0024] Figure 8 is a schematic diagram of the structure of the optical core wafer after the dielectric layer is deposited on the back side.

[0025] Figure 9 is a schematic diagram of the structure after the deposition of the second bump under the metal layer on the optical core wafer provided by the present invention.

[0026] Figure 10 is a schematic diagram of the structure of the optical core wafer provided by the present invention after electroplating or solder paste printing on the metal layer under the second bump to form the second connection bump.

[0027] Explanation of reference numerals in the attached diagram: 10. Optoelectronic co-packaged device; 1. Substrate; 2. Optical chip; 21. Through-silicon via; 22. Second connection bump; 23. Metal layer under the first bump; 24. Optical core wafer; 25. Carrier wafer; 26. Redundancy layer; 27. Dielectric layer; 28. Metal layer under the second bump; 3. Electrical chip; 31. First connection bump; 4. Fiber optic array unit; 5. Optical waveguide.

[0028] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0031] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0032] This invention proposes an optoelectronic co-packaged device 10.

[0033] Please refer to Figures 1-3. In one embodiment of the present invention, the optoelectronic co-packaged device 10 includes a substrate 1, an optical chip 2, an electrical chip 3, an optical fiber array unit 4, and an optical waveguide 5. The optical chip 2 is electrically connected between the substrate 1 and the electrical chip 3. The electrical chip 3 is used to provide driving signals and control signals to the optical chip 2. The optical chip 2 has multiple optical couplers. The optical fiber array unit 4 includes multiple optical fibers, and the multiple optical fibers correspond one-to-one with the multiple optical couplers. The optical waveguide 5 is formed by photonic wire bonding and is used to couple each optical coupler to the corresponding optical fiber.

[0034] For ease of understanding, the following explains some key terms in this embodiment: Substrate 1, which may be a PCB board, serves as the mechanical support platform and electrical connection interface for the entire optoelectronic co-packaged device 10. It is used to carry and connect components such as optical chip 2, electrical chip 3, and fiber array unit 4, and provides a signal interaction path with external circuits; Optical chip 2, which is a photonic integrated circuit (PIC), whose main function is to realize the transmission, reception, and modulation of optical signals. The optical chip 2 integrates an optical modulator, photodetector, thermo-optical components, and other passive photonic circuits, and has multiple optical couplers as optical interfaces for optical signals. The electrical chip 3 is an electronic integrated circuit (EIC) whose main function is to process high-speed electrical signals. It includes modules such as a driver, transimpedance amplifier (TIA), digital signal processor (DSP), and clock data recovery (CDR) to provide the optical chip 2 with the necessary drive and control signals to ensure stable modulation and reception of optical signals. The fiber array unit 4 (FAU) consists of multiple optical fibers and serves as the input and output channel for external optical signals. It is suitable for connection with the optical couplers on the optical chip 2.

[0035] It is understandable that the optical waveguide 5 is formed by photonic wire bonding. The optical waveguide 5 is used to couple each optical coupler to the corresponding optical fiber to achieve efficient and low-loss optical signal transmission between the optical chip 2 and the fiber array unit 4. Specifically, the optical waveguide 5 formed by photonic wire bonding can perform three-dimensional path optimization according to the actual spatial position of the optical coupler and the optical fiber, achieving high-precision alignment. It can connect the optical fibers of the fiber array to the corresponding optical couplers on the optical chip 2 one by one, point to point, significantly reducing coupling loss and crosstalk. It can also effectively compensate for the optical port position offset caused by the warping of the optical chip 2 and the fiber core position offset caused by the manufacturing tolerance of the fiber array, improve coupling efficiency, and thus improve the energy efficiency ratio of the optical communication device. It can also effectively reduce the coupling loss caused by alignment deviation, thereby effectively improving coupling efficiency and alignment tolerance, and reducing the manufacturing difficulty of the optoelectronic co-packaged device 10.

[0036] The optical chip 2 is connected between the substrate 1 and the electrical chip 3 (see Figure 1). This arrangement allows the electrical chip 3, with its higher conductivity, to be positioned above the optical chip 2. This increases the contact area between the electrical chip 3 and the external environment of the optoelectronic co-packaged device 10, thereby increasing the heat exchange area and improving the heat dissipation efficiency of the electrical chip 3. This facilitates heat dissipation during the operation of the electrical chip 3, reducing the risk of excessively high local temperatures affecting the performance and stability of both the electrical chip 3 and the optical chip 2. Ultimately, this improves the overall reliability and long-term operational stability of the optoelectronic co-packaged device 10. Furthermore, this layered structural layout effectively reduces the planar footprint of the entire optoelectronic co-packaged device 10, improving space utilization and facilitating miniaturization.

[0037] Among them, the core of the photonic wire bonding (PWB) method is based on the two-photon polymerization principle. It constructs a 3D polymer optical waveguide 5 through an automated laser direct writing process to achieve a low-loss, high-reliability optical path connection between the optical fiber array and the optical chip 2.

[0038] In a specific embodiment, the photonic wire bonding method can be summarized as "positioning and connecting the optical port – applying a photoresist layer – laser irradiation curing – development and shaping – applying a protective cladding layer". Specifically, the optical fibers of the fiber array and the optical couplers of the optical chip 2 can be initially aligned using machine vision to achieve positioning and connecting the optical port. Then, a high-speed spin coating process can be used to uniformly coat the coupling area with photosensitive photoresist to achieve photoresist layer coating. Next, ultraviolet laser is used to precisely expose the photoresist based on the two-photon polymerization principle to construct the core layer of the 3D polymer optical waveguide 5 and achieve laser irradiation curing. This allows point-to-point optical path matching between the individual optical fibers of the fiber array and the corresponding optical couplers of the optical chip 2. Then, the uncured adhesive layer can be removed by immersion in developing solution to achieve development and shaping. Finally, a low refractive index cladding layer is coated and cured to achieve protective cladding layer coating, thereby forming an optical confinement and mechanical protection structure. After completion, the coupling loss is tested. By forming an optical waveguide 5 using photonic wire bonding, each optical coupler is coupled to the corresponding optical fiber, which solves the problem of difficult alignment between the optical coupler of the optical chip 2 and the optical fiber of the fiber array. At the same time, a tapered coupling structure can be easily generated to achieve good mode field matching between the silicon-based optical waveguide 5 and the single-mode fiber, and it has high reliability and is suitable for industrial mass production.

[0039] In the technical solution of this invention, the photonic wire bonding method can be based on the two-photon polymerization principle and generate a three-dimensional polymer optical waveguide 5 according to the actual spatial position relationship between the optical chip 2, the optical coupler and the optical fiber array. This effectively compensates for the optical port position offset caused by the warping of the optical chip 2, significantly reducing the packaging difficulty. At the same time, the optical chip 2 is connected between the substrate 1 and the electrical chip 3, which is beneficial to the heat dissipation of the electrical chip 3 during operation and can improve the overall reliability and long-term working stability of the optoelectronic co-packaged device 10.

[0040] Please refer to Figures 1 and 2. In an embodiment of the present invention, the optical chip 2 is provided with a through-silicon via 21, which is electrically connected to the substrate 1 and the electrical chip 3.

[0041] Understandably, the Through Silicon Via (TSV) technology achieves electrical connection between the front and back sides of the optical chip 2 by forming a vertical conductive channel in the silicon substrate of the optical chip 2. Specifically, one end of the TSV 21 is electrically connected to the first bump under the metal layer 23 on the front side of the optical chip 2, and the other end is electrically connected to the second connection bump 22 on the back side of the optical chip 2. This allows the electronic chip 3, after being bonded to the first bump under the metal layer 23 through the first connection bump 31, to form a complete electrical signal transmission path through the TSV 21, the second connection bump 22 on the back side of the optical chip 2, and the ball grid array (BGA) of the substrate 1. This design effectively shortens the transmission distance of electrical signals inside the optical chip 2, reduces parasitic capacitance and inductance, and is beneficial to improving the transmission performance of high-frequency signals and the overall integration of the device, avoiding the signal integrity problems that traditional wire bonding methods may face at high frequencies.

[0042] Please refer to Figure 1. In an embodiment of the present invention, the electrical chip 3 is electrically connected to the optical chip 2 via bump bonding.

[0043] It is understandable that bump bonding is a technology that achieves electrical and mechanical connection between electrical chip 3 and optical chip 2 by forming a metal bump interconnect structure between the two. Specifically, the back of the electrical chip 3 has a first connection bump 31, and the front of the optical chip 2 has a first bump under metal layer 23 corresponding to the position of the first connection bump 31. The first connection bump 31 and the first bump under metal layer 23 are precisely aligned and bonded together by flip-chip bonding process (such as thermoforming, reflow soldering or ultrasonic soldering). This can shorten the transmission path of electrical signals and effectively reduce parasitic parameters (such as resistance, capacitance and inductance) in the transmission process of high-frequency signals, thereby improving the transmission rate and integrity of electrical signals and meeting the stringent requirements of high-speed optical communication systems for signal quality. Secondly, it can realize multi-pin, high-density parallel connection, which can adapt to the transmission needs of a large number of control signals, drive signals and power signals between the electrical chip 3 and the optical chip 2, which is conducive to improving the integration of the device. Furthermore, the metal bump itself has a certain mechanical buffering effect, which can alleviate the thermal stress caused by the difference in thermal expansion coefficients between the electrical chip 3 and the optical chip 2 during operation, and improve the mechanical reliability and long-term working stability of the device.

[0044] Referring to Figure 4, this invention also proposes a method for fabricating an optoelectronic co-packaged device 10. The specific structure of the optoelectronic co-packaged device 10 is as described in the above embodiments. Since the fabrication method of this optoelectronic co-packaged device 10 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here. The fabrication method includes: Step S1: Providing a substrate 1 and an optical fiber array unit 4.

[0045] Step S2: Prepare electrical chip 3 and optical chip 2.

[0046] The electronic chip 3 includes a battery cell body and a first connection bump 31 disposed on the back of the battery cell body, and the optical chip 2 includes an optical chip body, a second connection bump 22 disposed on the back of the optical chip body, and a metal layer 23 under the first bump disposed on the front of the optical chip body.

[0047] Step S3: Bond the first connection bump 31 on the back of the electrical chip 3 to the metal layer 23 under the first bump on the front of the optical chip 2.

[0048] Understandably, a flip-chip mounter can be used to place the electrode sheet with the back side facing down, flip it upside down and precisely align it with the first bump under the metal layer 23 on the front side of the optical chip 2. The first connection bump 31 and the first bump under the metal layer 23 are metallurgically bonded through thermosetting bonding or reflow soldering processes to form a stable electrical and mechanical connection, so that the electrical chip 3 and the optical chip 2 together form an optoelectronic integrated unit.

[0049] Step S4: Solder the second connection bump 22 on the back of the optical chip 2 to the ball array of the substrate 1. The second connection bump 22 is electrically connected to the metal layer 23 under the first bump.

[0050] The substrate 1 can be a PCB or an organic packaging substrate 1. BGA (Ball Grid Array) solder balls can be made at the corresponding pad positions on the substrate 1 by ball planting or solder paste printing. By placing the optoelectronic integrated unit composed of the electrical chip 3 and the optical chip 2 with the front side of the optical chip 2 facing down, the second connection bump 22 on the back side of the optical chip 2 is precisely aligned with the ball grid array solder on the substrate 1. The optoelectronic integrated unit can be soldered to the substrate 1 and other possible components (capacitors, etc.) on the substrate 1 simultaneously through the reflow soldering process.

[0051] Step S5: Attach the fiber array unit 4 to the substrate 1 and prepare the optical waveguide 5 by photonic wire bonding so that the optical coupler of the optical chip 2 is coupled to the optical fiber in the fiber array unit 4 through the optical waveguide 5.

[0052] Through the above technical solution, the photonic wire bonding method can customize the generation of a three-dimensional polymer optical waveguide 5 based on the two-photon polymerization principle and the actual spatial relationship between the optical coupler of the optical chip 2 and the fiber array. This effectively compensates for the optical port position offset caused by the warping of the optical chip 2, avoids the dependence on high-precision alignment in traditional methods, and significantly reduces the packaging difficulty. Simultaneously, the electrical chip 3 is directly bonded to the metal layer 23 under the first bump of the optical chip 2 via the first connecting bump 31, achieving a millimeter-level shortening of the electrical signal path and reducing high-speed signal transmission loss. The second connecting bump 22 of the optical chip 2 is directly welded to the ball grid array of the substrate 1. Combined with the internal electrical connection between the second connecting bump 22 and the metal layer 23 under the first bump, the need for an additional adapter board is eliminated, simplifying the electrical interconnection structure. Furthermore, placing the electrical chip 3 in the upper structure facilitates heat dissipation to the external environment through the high thermal conductivity material of the electrical chip 3, improving overall heat dissipation performance. In summary, this technical solution solves the problem of difficult optical coupling while achieving higher integration, lower signal loss, and a simpler process flow, making it suitable for application scenarios with stringent requirements for high-density optical interconnects, such as data centers and artificial intelligence clusters.

[0053] Please refer to Figures 5-10. In an embodiment of the present invention, the preparation of the optical chip 2 includes: step S21: bonding the front side of the optical core wafer 24 to the carrier wafer 25, and grinding and polishing the back side of the optical core wafer 24 to reduce the thickness of the optical core wafer 24 to a preset thickness.

[0054] It should be noted that the front side of the optical core wafer 24 contains all functional devices: silicon waveguides, germanium detectors, silicon modulators, thermal tuners, metal interconnects, as well as front optical I / O couplers and front electrical pads.

[0055] A temporary bonding agent can be spin-coated onto the front side of the optical core wafer 24. The bonding agent can be a bonding adhesive or a laminated temporary bonding film, so that the front side of the optical core wafer 24 is bonded to the carrier wafer 25 through the bonding agent. The carrier wafer 25 can protect the photonic device structure on the front side of the optical core wafer 24.

[0056] Step S22: Fabricate a through-silicon via 21 within the optical core wafer 24.

[0057] Understandably, the through-silicon via 21 can serve as a channel for vertical transmission of electrical signals, enabling electrical connections between the electrical pads on the front side and the back side of the optical core wafer 24. This can significantly shorten the transmission path of electrical signals, effectively reduce parasitic capacitance and inductance during high-frequency signal transmission, reduce signal delay and loss, improve signal integrity, and facilitate higher density interconnection on a limited chip area, thereby further improving the integration of the optoelectronic co-packaged device 10.

[0058] Step S23: A redistribution layer 26 and a second connection bump 22 are sequentially fabricated on the back side of the optical core wafer 24.

[0059] Understandably, the rewiring layer 26 can flexibly change the signal take-out position and wiring direction, thereby optimizing the interconnection layout between the electrical chip 3 and the optical chip 2 and adapting to the needs of high-density packaging.

[0060] Step S24: Remove the carrier wafer 25 from the front side of the optical core wafer 24 and dice the optical core wafer 24.

[0061] The temporary bonding between the optical core wafer 24 and the carrier wafer 25 can be released by means of thermal slip, laser stripping or solvent dissolution, so that the processed optical core wafer 24 can be separated from the carrier wafer 25. Then, the residual bonding agent on the front side of the optical core wafer 24 is cleaned to ensure that the front side of the optical core wafer 24 is clean. Then, wafer-level electrical testing can be performed to verify the conductivity of the through silicon via 21 and the redistribution layer 26. The chip is diced using a diamond blade or laser to obtain an independent optical chip 2. The chip has a characteristic structure of having a fully functional photonic device and an electrical pad on the front side, an active through silicon via 21 connected from the back side to the front side circuit, and a complex redistribution layer 26 and a second connection bump 22 for system integration on the back side.

[0062] In an embodiment of the present invention, a through-silicon via 21 is fabricated in the optical core wafer 24, including step S221: etching the via in the optical core wafer 24.

[0063] In this process, photoresist can be spin-coated on the back side of the optical core wafer 24, and the through-hole pattern can be defined by photolithography. Then, deep reactive ion etching is used to vertically etch along the patterned area until the back side of the metal pads on the front side of the optical core wafer 24 is exposed, thereby forming a deep hole structure that penetrates the silicon substrate.

[0064] Step S222: Deposit an insulating layer on the inner wall of the via and the back side of the optical core wafer 24.

[0065] Among them, under the condition of ≤300℃, silicon dioxide can be deposited on the inner wall of the through hole and the back side of the optical core wafer 24 by plasma-enhanced chemical vapor deposition to form an insulating layer covering the inner wall of the through hole and the back side of the optical core wafer 24.

[0066] Step S223: A barrier layer and a thin copper seed layer are sequentially deposited on the surface of the insulating layer using a physical vapor deposition process.

[0067] In this process, a barrier layer can be formed by depositing Ta (titanium) or TaN (titanium nitride), and then copper can be deposited to form a thin copper seed layer. Physical vapor deposition (PVD) processes have low temperatures, which can effectively control the thermal budget.

[0068] Step S224: Apply copper to the through hole using an electrochemical copper plating process.

[0069] Understandably, the electrochemical copper plating process is a room-temperature process, which can reduce the risk of thermal damage to the photonic devices (such as optical modulators and photodetectors) already fabricated on the front side of the optical core wafer 24 caused by high temperatures. At the same time, it can achieve uniform copper filling in the vias, ensuring the conductivity of the silicon vias 21. Specifically, the optical core wafer 24 with a thin copper seed layer deposited can be used as a cathode and placed in a plating solution containing copper sulfate, sulfuric acid, and additives. By applying current, copper ions are reduced and deposited on the surface of the seed layer until the vias are completely filled and a copper layer of a certain thickness is formed on the back side of the optical core wafer 24, providing a good conductive foundation for the subsequent fabrication of the redistribution layer 26.

[0070] Step S225: Perform chemical mechanical polishing on the back side of the wafer to form through-silicon vias 21.

[0071] Understandably, the aforementioned step-by-step process enables the precise fabrication of silicon vias 21 penetrating the photonic core wafer 24. After the via etching is completed, an insulating layer is first deposited on the inner wall of the via to achieve electrical isolation, preventing electrical leakage between the conductor (copper) of the silicon via 21 and the silicon substrate, and reducing the risk of copper ion diffusion into the silicon substrate. Subsequently, the deposited barrier layer further reduces the risk of copper ion diffusion into the silicon substrate, while the thin copper seed layer provides a good conductive substrate for subsequent copper electroplating, which helps ensure uniform and dense copper layer filling within the via. Furthermore, the deposition method is physical vapor deposition (PVD), which operates at a lower temperature, effectively controlling the thermal budget. Next, copper is plated into the via to form copper pillars. The electroplating process is performed at room temperature, reducing the risk of high-temperature damage to the performance of photonic devices. Finally, the back side of the wafer is polished by chemical mechanical polishing (CMP) to remove excess copper layer formed on the back side of the core wafer 24 due to overplating, and also to remove excess insulating layer, so that the top of the copper pillar is flush with the back side of the core wafer 24, forming isolated, flat silicon via 21 interconnect points, which can lay a good foundation for the subsequent fabrication of redistribution layer 26.

[0072] In an embodiment of the present invention, a redistribution layer 26 and a second connection bump 22 are sequentially prepared on the back side of the optical core wafer 24, including: step S31: electroplating copper on the back side of the optical core wafer 24 to form a redistribution layer 26, at least a portion of the redistribution layer 26 being in contact with a through silicon via 21.

[0073] In this process, Ti or Cu (copper) can be sputtered on the back side of the optical core wafer 24 to form a seed layer, and then copper can be plated to the target thickness (e.g., 2μm~5μm) through an electroplating process. Subsequently, photolithography and etching are performed to form the redistribution layer 26.

[0074] Step S32: Deposit a dielectric layer 27 on the back side of the optical core wafer 24.

[0075] The dielectric layer 27 can be deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition). The dielectric layer 27 can be made of materials such as polyimide, BCB (benzocyclobutene), silicon dioxide, or SiN (silicon nitride).

[0076] Step S33: An opening is etched on dielectric layer 27 to expose at least a portion of redistribution layer 26.

[0077] Step S34: Deposit the second bump undermetal layer 28 within the opening.

[0078] The material of the lower metal layer 28 (UBM) under the second bump can be Ti, Cu, Ni (nickel), Au (gold), etc.

[0079] Step S35: Electroplating or solder paste printing is used to form the second connecting bump 22 on the metal layer 28 below the second bump.

[0080] The material of the second connecting protrusion 22 can be a copper pillar + a tin silver cap.

[0081] Understandably, by forming a redistribution layer 26 that contacts the through-silicon via 21 through copper electroplating, effective redistribution of electrical signals and low-loss transmission are achieved. The deposited dielectric layer 27 provides reliable electrical insulation and structural support. Precise etching of openings on the dielectric layer 27 ensures accurate connection between the redistribution layer 26 and the subsequent second bump under-metal layer 28. The deposited second bump under-metal layer 28 provides excellent adhesion, diffusion barrier, and solderability for the formation of the second connection bump 22. Finally, the second connection bump 22 is formed through electroplating or solder paste printing, ensuring high consistency and reliability of the bumps. These steps work synergistically to enable stable and efficient construction of the back-side interconnect structure on the thinned optical core wafer 24, thus laying the foundation for reliable integration of the optoelectronic integrated unit with the substrate 1. This effectively avoids problems such as poor electrical contact, unstable signal transmission, or poor bonding consistency, thereby improving the performance and reliability of the entire optoelectronic co-packaged device 10.

[0082] In embodiments of the present invention, when a complex wiring structure is required, steps S31 to S33 can be repeated before step S34 to construct a multi-layer redistribution structure. Each repetition adds a dielectric layer 27 and a redistribution layer 26, achieving iterative multi-layer redistribution layer 26 to facilitate the redistribution of electrical signals from the through-silicon via 21 to the desired location of the second connection bump 22. Each layer process must be kept at a low temperature to reduce the risk of performance degradation or failure of photonic devices due to thermal stress.

[0083] In an embodiment of the present invention, after bonding the first connection bump 31 on the back side of the electrical chip 3 to the first bump under metal layer 23 on the front side of the optical chip 2, and before welding the second connection bump 22 on the back side of the optical chip 2 to the ball array of the substrate 1, the method further includes filling structural adhesive between the electrical chip 3 and the optical chip 2.

[0084] Understandably, after the electrical chip 3 and the optical chip 2 are bonded together via the first connection bump 31 and the metal layer 23 under the first bump, a tiny gap will form between them. Structural adhesive fills this gap. First, it enhances the mechanical connection strength between the electrical chip 3 and the optical chip 2, improving the overall structural stability and impact resistance, and reducing the risk of bond point detachment or poor contact due to vibration, temperature changes, or other factors during subsequent packaging processes or device use. Second, structural adhesive has excellent thermal conductivity, assisting in the heat conduction of the electrical chip 3 and the optical chip 2 to the outside, further optimizing the device's heat dissipation and reducing the impact of localized overheating on chip performance and reliability. Furthermore, structural adhesive also acts as a sealant and protectant, preventing external moisture, dust, and other contaminants from entering the bonding area, preventing oxidation or corrosion of the metal bumps, thereby extending the device's lifespan. Simultaneously, the filling with structural adhesive can reduce the stress caused by the difference in thermal expansion coefficients between the electrical chip 3 and the optical chip 2, reducing the risk of damage to the bonding bumps during thermal cycling and ensuring the long-term stability of electrical signal transmission.

[0085] In some embodiments, structural adhesive can be applied to the edge of the electrical chip 3, allowing it to naturally fill the gap between the electrical chip 3 and the optical chip 2 using capillary action. This ensures uniform filling and reduces the risk of adhesive overflow contaminating the optical surface. Then, it can be thermo-cured at a predetermined temperature to reinforce the bump connection between the electrical chip 3 and the optical chip 2, effectively absorbing thermomechanical stress and protecting the through-silicon via 21 structure and the bonding interface above it. The predetermined temperature can be in the range of 120°C to 150°C. Curing the structural adhesive allows the electrical chip 3 and the optical chip 2 to form an optoelectronic integrated unit.

[0086] In an embodiment of the present invention, after the second connection bump 22 on the back side of the optical chip 2 is soldered to the ball array of the substrate 1, and before the optical fiber array unit 4 is attached to the substrate 1 and the optical waveguide 5 is prepared by photonic wire bonding, the method further includes filling structural adhesive between the optical chip 2 and the substrate 1.

[0087] It is understandable that after the optical chip 2 is soldered to the ball array of the substrate 1 via the second connecting bump 22, there will be a certain gap between them. Filling this gap with structural adhesive can firstly further strengthen the mechanical connection between the optical chip 2 and the substrate 1, improve the structural rigidity and bending resistance of the entire optoelectronic co-packaged device 10, and ensure that the connection between the optical chip 2 and the substrate 1 is stable and reliable in subsequent operation or application environments. This reduces the risk of solder joint breakage or poor contact due to mechanical stress, so that the optoelectronic integrated unit composed of the optical chip 2 and the electronic chip 3 is firmly fixed to the substrate 1, providing a stable mechanical reference platform for the subsequent optical coupling steps of the optical chip 2 and the fiber array.

[0088] Secondly, the filling structural adhesive can also protect the welding area of ​​the second connection bump 22 at the bottom of the optical chip 2, isolate moisture and impurities in the external environment, prevent the welding point from oxidizing, corroding or being physically damaged, and further extend the service life of the device.

[0089] Meanwhile, the presence of structural adhesive can also buffer the thermal stress caused by the difference in thermal expansion coefficients between the optical chip 2 and the substrate 1 to a certain extent, reduce the damage to the welding points and the optical chip 2 itself during thermal cycling, ensure the long-term stability of optical and electrical performance, and improve the system-level temperature cycling reliability.

[0090] The filling method and curing process can refer to the filling of the structural adhesive between the electrical chip 3 and the optical chip 2 mentioned above. For example, dispensing or coating can be used to ensure that the adhesive fills the gap evenly and cures at an appropriate temperature to achieve the best bonding and protection effect.

[0091] In an embodiment of the present invention, the fiber array unit 4 is attached to the substrate 1, and the optical waveguide 5 is prepared by photonic wire bonding method so that the optical coupler of the optical chip 2 is coupled to the optical fiber in the fiber array unit 4 through the optical waveguide 5. The method includes: step S51: applying photoresist to the surface of the substrate 1 between the fiber array unit 4 and the optical coupler.

[0092] A uniform layer of photoresist can be applied by spin coating or drop coating to form a core photoresist film. The film thickness determines the cross-sectional dimensions of the subsequently formed optical waveguide 5 (for example, the thickness can be in the range of 2μm to 5μm). Then, soft baking can be performed to remove the photoresist solvent and initially stabilize the core photoresist film.

[0093] Step S52: Using the femtosecond laser two-photon polymerization direct writing method, the photoresist is exposed according to the preset pattern, so that the exposed photoresist undergoes a polymerization reaction to form a core layer.

[0094] The femtosecond laser two-photon polymerization direct writing method utilizes an ultrashort pulse laser (femtosecond level) focused inside the photoresist. Through the two-photon absorption effect, polymerization occurs only at the focal point of the photoresist molecules, thus achieving high-precision direct writing of three-dimensional structures. The preset pattern is designed based on the position of the optical coupler in the optical chip 2, the arrangement of the optical fibers in the fiber array unit 4, and the spatial path between them, ensuring that the formed core layer can accurately connect the optical coupler and the corresponding optical fiber. During the exposure process, the laser beam can be scanned along a preset trajectory by a precision moving platform, causing the polymerization reaction to form a core layer structure with a specific orientation and cross-sectional shape (such as rectangular or circular) within the photoresist. This core layer is the core transmission part of the optical waveguide 5, and its dimensional accuracy can reach the sub-micron level, effectively ensuring low-loss transmission of optical signals.

[0095] Specifically, an integrated vision system can be used to accurately measure the actual three-dimensional spatial position and offset between the fiber end face and the optical coupler of the optical chip 2. Based on the measurement data, a customized three-dimensional polymer optical waveguide 5 core layer is directly "grown" between the fiber end face and the optical coupler of the optical chip 2 using femtosecond laser two-photon polymerization direct writing technology. The path, shape and end face structure of the core layer are optimized to compensate for any remaining spatial deviation and achieve mode field matching.

[0096] Step S53: Immerse substrate 1 in developer solution to dissolve the photoresist in the unexposed areas.

[0097] Understandably, after substrate 1 is immersed in the developer, the unexposed photoresist is selectively removed, leaving only the core structure cured by two-photon polymerization. This forms a solid polymer waveguide core structure connecting the optical fiber and the optical chip 2. Hard baking can then be performed to further solidify the waveguide core structure, enhancing its mechanical strength and optical stability. The hard baking temperature can be in the range of 80℃ to 120℃ to remove residual developer and promote complete cross-linking of the photoresist, thus ensuring good structural stability and optical performance of the core layer.

[0098] Step S54: Coat the surface of the core layer with an adhesive layer to form an optical waveguide 5, wherein the refractive index of the adhesive layer is less than that of the core layer.

[0099] Understandably, a low-refractive-index polymer material can be spin-coated over the entire area between the optical fiber and the optical chip 2 as a cladding adhesive, completely covering the core layer. After curing, the cladding adhesive, together with the core layer, forms a complete optical waveguide 5 structure. The material of the cladding layer can be fluorinated acrylate or silicone-modified epoxy resin.

[0100] In the technical solution of this invention, a combined architecture of optical chip 2 integrated with through-silicon vias 21 and photonic wire bonding is proposed, and an optoelectronic packaging device for 3D optical engines and its fabrication method are described. Compared with existing integrated packaging, it has higher integration, better heat dissipation performance, lower channel loss, and lower mounting difficulty. In the optoelectronic packaging device of this invention, the electrical chip 3 is located on the top layer of the optoelectronic packaging device, the optical chip 2 is located in the middle layer, and the substrate 1 is located on the bottom layer, forming a vertical stacked structure. The electrical chip 3 is directly connected to the optical chip 2 through a flip-flop mounting method, and finally connected to the substrate 1 through the through-silicon vias 21 integrated inside the optical chip 2. Using photonic wire bonding technology, the optical fibers of the fiber array are connected point-to-point to the corresponding optical ports of the optical chip 2, adapting to the warping of the optical chip 2 and solving the warping problem faced in high-density optical port coupling.

[0101] In this embodiment, the through-silicon via 21 is integrated into the optical chip 2, which can further reduce the module size and improve the integration. The high-conductivity electrical chip 3 is placed on the upper layer, which is beneficial to the heat dissipation of the entire module. The optical fiber and the optical coupler of the optical chip 2 are coupled through the optical waveguide 5 formed by photonic wire bonding, which can solve the problem that the optical chip 2 warps and the optical fiber array cannot be coupled. The through-silicon via 21 vertically connects the electrical chip 3 and the bottom substrate 1, which can avoid the excessively long electrical connection channel through the adapter board and TMV (Through-MoldVia), reduce signal transmission loss, and the optical fiber array and the optical port do not need to be aligned with high precision, which improves the packaging tolerance and greatly reduces the mounting difficulty of the optical fiber array.

[0102] The above are merely exemplary embodiments of the present invention and do not limit the scope of the patent of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of the present invention.

Claims

1. A photoelectric co-packaged device, characterized in that, include: The system comprises a substrate, an optical chip, and an electrical chip, wherein the optical chip is electrically connected between the substrate and the electrical chip, and the electrical chip is used to provide driving signals and control signals to the optical chip. The optical chip has multiple optical couplers. The system also includes an optical fiber array unit, which comprises multiple optical fibers, and each optical fiber corresponds to one of the multiple optical couplers. And an optical waveguide, formed by photonic wire bonding, for coupling each of the optical couplers to the corresponding optical fiber.

2. The optoelectronic co-packaged device as described in claim 1, characterized in that, The optical chip has a through-silicon via (TSV), which is electrically connected to the substrate and the electrical chip.

3. The optoelectronic co-packaged device as described in claim 1 or 2, characterized in that, The electrical chip is electrically connected to the optical chip via bump bonding.

4. A method for fabricating an optoelectronic co-packaged device, characterized in that, The optoelectronic co-packaged device is based on the optoelectronic co-packaged device as described in any one of claims 1-3. The fabrication method includes: providing a substrate and an optical fiber array unit; fabricating an electrical chip and an optical chip, wherein the electrical chip includes a battery core body and a first connection bump disposed on the back side of the battery core body, and the optical chip includes an optical core body, a second connection bump disposed on the back side of the optical core body, and a metal layer under the first bump disposed on the front side of the optical core body; bonding the first connection bump on the back side of the electrical chip to the metal layer under the first bump on the front side of the optical chip; soldering the second connection bump on the back side of the optical chip to a ball grid array of the substrate, wherein the second connection bump is electrically connected to the metal layer under the first bump; mounting the optical fiber array unit to the substrate, and fabricating an optical waveguide by photonic wire bonding, so that the optical coupler of the optical chip is coupled to the optical fiber in the optical fiber array unit through the optical waveguide.

5. The method for fabricating the optoelectronic co-packaged device as described in claim 4, characterized in that, The fabrication of the optical chip includes: bonding the front side of the optical core wafer to a carrier wafer; grinding and polishing the back side of the optical core wafer to reduce its thickness to a preset thickness; fabricating through-silicon vias (TSVs) within the optical core wafer; sequentially fabricating a redistribution layer and a second connection bump on the back side of the optical core wafer; removing the carrier wafer from the front side of the optical core wafer; and dicing the optical core wafer.

6. The method for fabricating the optoelectronic co-packaged device as described in claim 5, characterized in that, The process of fabricating through-silicon vias (TSVs) within the optical core wafer includes: etching TSVs within the optical core wafer; depositing an insulating layer on the inner wall of the TSVs and the back side of the optical core wafer; sequentially depositing a barrier layer and a thin copper seed layer on the surface of the insulating layer using a physical vapor deposition process; plating copper into the TSVs using an electrochemical copper plating process; and performing chemical mechanical polishing on the back side of the wafer to form the TSVs.

7. The method for fabricating an optoelectronic co-packaged device as described in claim 5, characterized in that, The step of sequentially fabricating a redistribution layer and a second connection bump on the back side of the optical core wafer includes: electroplating copper on the back side of the optical core wafer to form a redistribution layer, at least a portion of which contacts the through-silicon via; depositing a dielectric layer on the back side of the optical core wafer; etching an opening in the dielectric layer to expose at least a portion of the redistribution layer; depositing a second bump under-metal layer within the opening; and electroplating or solder paste printing on the second bump under-metal layer to form a second connection bump.

8. The method for fabricating the optoelectronic co-packaged device as described in claim 4, characterized in that, After bonding the first connection bump on the back of the electrical chip to the first bump under the metal layer on the front of the optical chip, and before soldering the second connection bump on the back of the optical chip to the ball array of the substrate, the method further includes filling structural adhesive between the electrical chip and the optical chip.

9. The method for fabricating the optoelectronic co-packaged device as described in claim 4, characterized in that, After the second connection bump on the back of the optical chip is soldered to the ball array of the substrate, and before the optical fiber array unit is attached to the substrate and the optical waveguide is prepared by photonic wire bonding, the method further includes filling structural adhesive between the optical chip and the substrate.

10. The method for fabricating the optoelectronic co-packaged device as described in claim 4, characterized in that, The step of mounting the fiber array unit to the substrate and fabricating an optical waveguide using photonic wire bonding to couple the optical coupler of the optical chip to the optical fiber within the fiber array unit via the optical waveguide includes: applying photoresist to the surface of the substrate between the fiber array unit and the optical coupler; exposing the photoresist according to a preset pattern using a femtosecond laser two-photon polymerization direct writing method to cause the exposed portion of the photoresist to undergo a polymerization reaction to form a core layer; immersing the substrate in a developer to dissolve the unexposed portion of the photoresist; and applying an encapsulation layer to the surface of the core layer to form an optical waveguide; wherein the refractive index of the encapsulation layer is less than the refractive index of the core layer.

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