Digital in-memory computing architecture based on full adder architecture
By designing a digital in-memory computing architecture based on a full adder architecture, and using 10 MOS transistors to implement the addition function, the problems of high power consumption and large area in the full adder architecture are solved, and efficient and accurate calculation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2025-12-16
- Publication Date
- 2026-05-01
AI Technical Summary
The existing full adder architecture has a large number of transistors, resulting in high power consumption and large area, making it difficult to meet the requirements of reducing power consumption and chip area.
The digital in-memory computing architecture based on the full adder architecture is adopted, including a first XOR gate circuit, a second XOR gate circuit and a carry circuit. By reducing the number of transistors, it is designed with 10 MOS transistors to realize the addition function, and an inverter is used to ensure the calculation accuracy.
It effectively reduces the power consumption and footprint of the full adder architecture, achieves efficient calculation of the addition function, and maintains calculation accuracy when multiple full adders are cascaded.
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Figure CN121957531A_ABST
Abstract
Description
Digital in-memory computing architecture based on full adder architecture Technical Field
[0001] This application relates to the field of electronic circuit technology, and in particular to a digital in-memory computing architecture based on a full adder architecture. Background Technology
[0002] With the rapid development of artificial intelligence, in-memory computing architecture integrates multiply-accumulate units into memory, eliminating data transmission channels and effectively improving system energy efficiency. As the basic arithmetic unit in in-memory computing architecture, reducing the power consumption and area of the full adder architecture is of great significance in effectively reducing chip area and power consumption.
[0003] In the prior art, various full adder architectures have been designed using different logics such as complementary CMOS logic, transmission transistor logic, transmission gate logic, differential logic, and hybrid logic. The number of CMOS transistors required in the above full adder architectures is relatively large, and the power consumption and area occupied by the full adder architecture are positively correlated with the number of CMOS transistors used to implement the full adder. Therefore, there is an urgent need for a full adder architecture that can effectively reduce power consumption and area occupied. Summary of the Invention
[0004] Therefore, it is necessary to provide a digital in-memory computing architecture based on a full adder architecture to address the aforementioned technical problems. This full adder architecture can reduce power consumption and area.
[0005] In a first aspect, this application provides a digital in-memory computing architecture based on a full adder architecture, the full adder architecture including a first XOR gate circuit, a second XOR gate circuit and a carry circuit;
[0006] The two input terminals of the first XOR gate circuit are connected to the first input signal and the second input signal, respectively. The output terminal of the first XOR gate circuit is connected to the first input terminal of the second XOR gate circuit and the first input terminal of the carry circuit. The output terminal of the first XOR gate circuit is used to output the first XOR signal. The first XOR gate circuit includes 4 MOS transistors. The first input signal is the carry input signal, the second input signal is either the addend signal or the augend signal, the addend signal and the augend signal are inverted signals, and the carry input signal is a positive signal.
[0007] The second input terminal of the second XOR gate circuit is connected to the third input signal, and the output terminal of the second XOR gate circuit is used to output the positive sum signal. The second XOR gate circuit includes 4 MOS transistors; the third input signal is one of the addend signal and the augend signal other than the second input signal.
[0008] The second and third input terminals of the carry circuit are connected to the second and third input signals, respectively. The output terminal of the carry circuit is used to output a carry output signal from the second and third input signals according to the first XOR signal. The carry output signal is an inverted signal.
[0009] In one embodiment, the full adder architecture further includes a first inverter; the first inverter is connected to the output of a second XOR gate circuit for outputting an inverted sum signal.
[0010] In one embodiment, the full adder architecture further includes a second inverter; the second inverter is connected to the output of the carry circuit and is used to output a positive carry output signal.
[0011] In one embodiment, the first XOR gate circuit includes a third inverter and a first gate diffuse input unit;
[0012] The input terminal of the third inverter and the first terminal of the first gate diffusion input unit are both connected to the first input signal, and the output terminal of the third inverter is connected to the second terminal of the first gate diffusion input unit.
[0013] The third terminal of the first gate diffusion input unit is connected to the second input signal, and the fourth terminal of the first gate diffusion input unit is connected to the first input terminal of the second XOR gate circuit.
[0014] In one embodiment, the third inverter includes a first PMOS transistor and a first NMOS transistor, and the first gate diffused input unit includes a second PMOS transistor and a second NMOS transistor;
[0015] The source of the first PMOS transistor is connected to the power supply, the source of the first NMOS transistor is grounded, the gate of the first PMOS transistor, the gate of the first NMOS transistor, and the source of the second PMOS transistor are all connected to the first input signal, and the drain of the first PMOS transistor and the drain of the first NMOS transistor are all connected to the source of the second NMOS transistor.
[0016] The gates of the second PMOS transistor and the second NMOS transistor are both connected to the second input signal, and the drains of the second PMOS transistor and the second NMOS transistor are both connected to the first input terminal of the second XOR gate circuit.
[0017] In one embodiment, the second XOR gate circuit includes a fourth inverter and a second gate diffuse input unit;
[0018] The input terminal of the fourth inverter and the first terminal of the second gate diffusion input unit are both connected to the output terminal of the first XOR gate circuit, and the output terminal of the fourth inverter is connected to the second terminal of the second gate diffusion input unit.
[0019] The third terminal of the second gate diffusion input unit is connected to the third input signal, and the fourth terminal of the second gate diffusion input unit is used to output a positive-phase sum signal.
[0020] In one embodiment, the second inverter includes a third PMOS transistor and a third NMOS transistor, and the second gate diffused input unit includes a fourth PMOS transistor and a fourth NMOS transistor;
[0021] The source of the third PMOS transistor is connected to the power supply, the source of the third NMOS transistor is grounded, the gate of the third PMOS transistor, the gate of the third NMOS transistor and the source of the fourth PMOS transistor are all connected to the output of the first XOR gate circuit, and the drain of the third PMOS transistor and the drain of the third NMOS transistor are all connected to the source of the fourth NMOS transistor.
[0022] The gates of the fourth PMOS transistor and the fourth NMOS transistor are both connected to the third input signal. The drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor, which is used to output a positive sum signal.
[0023] In one embodiment, the carry circuit includes a fifth PMOS transistor and a fifth NMOS transistor;
[0024] The gates of the fifth PMOS transistor and the fifth NMOS transistor are both connected to the output of the first XOR gate circuit. The source of the fifth PMOS transistor is connected to the third input signal, the source of the fifth NMOS transistor is connected to the second input signal, and the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor. This is used to output a carry output signal from the second and third input signals according to the first XOR signal.
[0025] In one embodiment, a carry circuit is used to take the second input signal as a carry output signal when the value of the first XOR signal is 1.
[0026] In one embodiment, a carry circuit is used to take the third input signal as a carry output signal when the value of the first XOR signal is 0.
[0027] The aforementioned in-memory computing architecture based on a full adder includes a first XOR gate, a second XOR gate, and a carry circuit. The two inputs of the first XOR gate are connected to a first input signal and a second input signal, respectively. The output of the first XOR gate is connected to the first input of both the second XOR gate and the carry circuit. The output of the first XOR gate is used to output the first XOR signal. The first XOR gate includes four MOS transistors. The first input signal is the carry input signal, and the second input signal is either the addend signal or the augend signal. The first XOR signal is an inverted signal, and the carry input signal is a positive signal. The second input terminal of the second XOR gate is connected to the third input signal, and the output terminal of the second XOR gate is used to output the positive sum signal. The second XOR gate includes four MOS transistors. The third input signal is one of the addend and augend signals other than the second input signal. The second and third input terminals of the carry circuit are connected to the second input signal and the third input signal, respectively. The output terminal of the carry circuit is used to output the carry output signal from the second input signal and the third input signal according to the first XOR signal. The carry output signal is an inverted signal. The input signals of the aforementioned full adder architecture include a positive carry-in signal and an inverted addend and augend signal. By XORing the input signals with two XOR gates, the sum of the carry-in signal, addend signal, and augend signal can be obtained, effectively realizing the addition function. Furthermore, compared to the full adder in the existing FD-CIM chip architecture which requires 28 MOS transistors, the aforementioned full adder architecture only requires 10 MOS transistors, effectively reducing the number of required MOS transistors, thereby effectively reducing power consumption and area. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 is a schematic diagram of the full adder architecture in one embodiment;
[0030] Figure 2 is a schematic diagram of the full adder architecture in another embodiment;
[0031] Figure 3 is a schematic diagram of the adder circuit structure in one embodiment;
[0032] Figure 4 is a schematic diagram of the full adder architecture in another embodiment;
[0033] Figure 5 is a schematic diagram of the full adder architecture in another embodiment. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0036] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0037] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0038] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.
[0039] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0040] With the rapid development of Artificial Intelligence (AI) and its applications, frequent and large-scale data transfers between the central processing unit (CPU) and memory circuits via limited bus bandwidth are required. This is widely recognized as the biggest bottleneck in the traditional von Neumann architecture. Deep neural networks, as one of the most successful algorithms applied to image recognition in the field of AI, require extensive read / write, multiplication, and addition operations on input and weight data. This means a greater number of data transfers and higher energy consumption. Notably, under different AI tasks, the energy consumed by reading and writing data far exceeds the energy consumed by computing data. In deep neural network processors based on the traditional von Neumann architecture, both input and weight data must first be stored in corresponding memory units, then sent via the bus to the corresponding digital processing units for multiplication and addition operations, and finally the results are read out. The limited number of memory access interfaces restricts the number of multiplication and accumulation (MAC) operations performed per cycle, further significantly impacting the overall system throughput. To overcome this bottleneck in the von Neumann architecture, the Computing-in-Memory (CIM) architecture was proposed. This architecture integrates the MAC unit into memory, such as static random access memory (SRAM), resulting in the SRAM-CIM architecture. This system architecture not only retains the storage and read / write functions inherent in the memory circuitry itself, but also supports different logical or multiply-accumulate operations. This significantly reduces frequent bus interactions between the CPU and memory circuitry, further reducing the amount of data movement and improving system energy efficiency. In deep neural network processors based on the CIM architecture, weight data can be directly used for MAC operations without being read, directly yielding the final multiply-accumulate result. Therefore, the system throughput is no longer limited by the finite memory read interface.
[0041] Currently, based on the different circuit design schemes of the MAC units within SRAM-CIM, SRAM-CIM architectures can be divided into two main categories: the first is based on a mixed-signal circuit design, called Analog-mixed-signal CIM (AMS-CIM); the second is based on a fully digital logic circuit design, called Full-digital CIM (FD-CIM). With advancements in process nodes and advanced tape-out processes, chip components are more susceptible to non-ideal effects (such as process, voltage, and temperature), causing errors in AMS-CIM calculations and thus affecting the accuracy of AI tasks. Conversely, FD-CIM, through the use of robust digital logic, can almost eliminate many non-ideal effects. The adoption of a fully digital in-memory computing architecture faces the problem of the area of the adder tree. Large-scale adder trees occupy most of the area of the entire macrocell. In the existing technology, various full adder architectures have been designed through different logics such as complementary CMOS logic, transmission transistor logic, transmission gate logic, differential logic and hybrid logic. For example, in order to optimize the area and power consumption of FD-CIM, the full adder architecture adopts a 28-transistor (T) structure or a 14T structure.
[0042] However, the existing full adder architecture requires a large number of transistors, and the power consumption and area of the full adder architecture are positively correlated with the number of CMOS transistors used to implement the full adder. Therefore, there is an urgent need for a full adder architecture that can effectively reduce power consumption and area.
[0043] In view of this, embodiments of this application provide a digital in-memory computing architecture based on a full adder architecture, which can effectively reduce power consumption and area.
[0044] In an exemplary embodiment, as shown in FIG1, a full adder architecture is provided, including a first XOR gate circuit 10, a second XOR gate circuit 20, and a carry circuit 30.
[0045] The two input terminals of the first XOR gate circuit 10 are connected to the first input signal and the second input signal, respectively. The output terminal of the first XOR gate circuit 10 is connected to the first input terminal of the second XOR gate circuit 20 and the first input terminal of the carry circuit 30. The output terminal of the first XOR gate circuit 10 is used to output the first XOR signal. The first XOR gate circuit 10 includes 4 MOS transistors.
[0046] The second input terminal of the second XOR gate circuit 20 is connected to the third input signal, and the output terminal of the second XOR gate circuit 20 is used to output the positive sum signal. The second XOR gate circuit 20 includes 4 MOS transistors.
[0047] The first input signal is the carry input signal, the second input signal is either the addend signal or the augend signal, the third input signal is either the addend signal or the augend signal other than the second input signal, the addend signal and the augend signal are inverted signals, and the carry input signal is a positive signal.
[0048] That is, the first input signal is a positive phase signal, while the second and third input signals are negative phase signals.
[0049] For example, as shown in Figure 1, the first input signal can be a positive carry input signal Ci, and the second input signal can be an inverted addend signal. The third input signal is the inverted addend signal. For the first XOR gate circuit 10, its first input terminal 1 is connected to the carry input signal Ci, and its second input terminal 2 is connected to the addend signal. The connection is made by the first XOR gate circuit 10, which pairs the carry input signal C and the addend signal. After the XOR operation, its output terminal 3 outputs the first XOR signal (Ci). For the second XOR gate circuit 20, its first input terminal 4 is connected to the augend signal. The second input terminal 5 is connected to the first XOR signal, and the second XOR gate circuit 20 is connected to the augend signal. After being XORed with the first XOR signal, its output terminal 6 outputs the sum signal S. .
[0050] The specific relationship between the input signal and the sum signal can be found in Table 1 below. Table 1 is the logic truth table corresponding to the sum signal.
[0051] Table 1
[0052]
[0053] Optionally, the second and third input terminals of the carry circuit 30 are connected to the second and third input signals, respectively, and the output terminal of the carry circuit 30 is used to output a carry output signal from the second and third input signals according to the first XOR signal. The carry output signal is an inverted signal, and the carry circuit includes two MOS transistors.
[0054] For example, referring to FIG1, the first input terminal 7 of the carry circuit 30 is connected to the output terminal 3 of the first XOR gate circuit 10, that is, connected to the first XOR signal; the second input terminal 8 of the carry circuit 30 is connected to the second input signal; and the third input terminal 9 of the carry circuit 30 is connected to the third input signal.
[0055] Optionally, the carry circuit 30 can be a multiplexer, with the first XOR signal serving as the control signal for the carry circuit 30, selecting one input signal from the second and third input signals as the carry output signal.
[0056] It should be noted that the carry output signal output from the output terminal of the carry circuit 30 is an inverted signal. Therefore, when this carry output signal is used as the carry input signal of another full adder, it is necessary to invert the carry output signal through an inverter.
[0057] The aforementioned full adder architecture includes a first XOR gate, a second XOR gate, and a carry circuit. The two inputs of the first XOR gate are connected to a first input signal and a second input signal, respectively. The output of the first XOR gate is connected to the first input of both the second XOR gate and the carry circuit. The output of the first XOR gate is used to output the first XOR signal. The first XOR gate includes four MOS transistors. The first input signal is the carry input signal, and the second input signal is either the addend signal or the augend signal. Both the addend signal and the augend signal are inverted signals. The carry input signal is a positive-phase signal; the second input terminal of the second XOR gate is connected to the third input signal, and the output terminal of the second XOR gate is used to output a positive-phase sum signal. The second XOR gate includes four MOS transistors; the third input signal is one of the addend and augend signals other than the second input signal; the second and third input terminals of the carry circuit are connected to the second and third input signals respectively, and the output terminal of the carry circuit is used to output a carry output signal from the second and third input signals according to the first XOR signal. The carry output signal is an inverted signal. The input signals of the aforementioned full adder architecture include a positive carry-in signal and an inverted addend and augend signal. By XORing the input signals with two XOR gates, the sum of the carry-in signal, addend signal, and augend signal can be obtained, effectively realizing the addition function. Furthermore, compared to the full adder in the existing FD-CIM chip architecture which requires 28 MOS transistors, the aforementioned full adder architecture only requires 10 MOS transistors, effectively reducing the number of required MOS transistors, thereby effectively reducing power consumption and area.
[0058] In an exemplary embodiment, as shown in FIG2, the full adder architecture further includes a first inverter 40. The first inverter 40 is connected to the output of the second XOR gate circuit 20 for outputting an inverted sum signal.
[0059] Optionally, the inverter is used to invert the signal and can also be used to solve the threshold loss so that the sum signal and the carry output signal reach the full voltage swing, thereby avoiding the accumulation of losses when multiple full adder architectures are cascaded, which would lead to incorrect calculation results.
[0060] Optionally, the first inverter 40 can invert the sum signal output by the second XOR gate circuit 20 and restore the full swing of the sum signal to obtain an inverted sum signal. .
[0061] Referring to Figure 2, the first inverter 40 may include a PMOS transistor Q1 and a CMOS transistor Q2. The source of the PMOS transistor Q1 is connected to the power supply, and the source of the NMOS transistor Q2 is grounded. The gates of both the PMOS transistor Q1 and the NMOS transistor Q2 are connected to the output of the second XOR gate circuit 20. The drain of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q2, and the inverter outputs an inverted sum signal. .
[0062] The full adder architecture also includes a second inverter 50, which is connected to the output of the carry circuit 30 and is used to output a positive carry output signal.
[0063] The second inverter 50 can invert the carry output signal output by the carry circuit 30 to obtain a positive carry output signal Co.
[0064] The second inverter 50 has a similar circuit structure to the first inverter 40. Referring to Figure 2, the second inverter 50 also includes a PMOS transistor Q3 and an NMOS transistor Q4. The source of the PMOS transistor Q3 is connected to the power supply, and the source of the NMOS transistor Q4 is grounded. The gates of both the PMOS transistor Q3 and the NMOS transistor Q4 are connected to the output terminal of the carry circuit 30. The drain of the PMOS transistor Q3 is connected to the drain of the NMOS transistor Q4, outputting a positive carry output signal. .
[0065] Optionally, since the above full adder requires a positive carry input signal, an inverted add signal, and an addee signal, and outputs a positive carry output signal and an inverted sum signal, multiple full adders can work well together when cascaded. In two adjacent full adders, the sum signal and carry output signal output by the previous full adder can be used as the input signals of the next full adder.
[0066] For example, as shown in Figure 3, an exemplary adder circuit includes multiple cascaded full adder architectures. Adjacent full adder architectures can cooperate well. The input of this adder is an inverted 4-bit addend. [0]、 [1]、 [2]、 [3] and the addend [0]、 [1]、 [2]、 [3] The output of the adder circuit is an inverted 5-bit sum signal. It is understandable that inputting the positive carry output signal from the fourth full adder architecture into an inverter will result in an inverted carry output signal. [4] The inverted carry output signal is used as the adder signal for the next stage adder circuit.
[0067] In existing technologies, when implementing a full adder architecture based on positive input signals (addend, augend, and carry input signals are all positive signals) and XOR gates, the output sum signal and carry output signal need to be connected to buffers to address threshold loss. Each buffer consists of at least two inverters, which increases the overall transistor count (at least eight more transistors are needed in the original full adder architecture). However, in this embodiment, based on the above analysis, in a full adder architecture based on inverted addend and augend signals and XOR gates, the output sum signal and carry output signal each only need to be connected to an inverter. This solves the threshold loss problem for the sum and carry output signals and also facilitates cooperation with the next stage of the full adder architecture when cascaded.
[0068] In the full adder architecture of this application embodiment, including the output buffer, a total of 14 transistors are required to realize the addition function, which can effectively reduce power consumption and area. Furthermore, multiple full adder architectures are cascaded, and the full adder architectures can cooperate effectively with each other. At the same time, the accuracy of the calculation is ensured by the output buffer (first inverter and second inverter).
[0069] In one embodiment, as shown in FIG4, the first XOR gate circuit 10 includes a third inverter 11 and a first gate diffusion input unit 12; the input terminal of the third inverter 11 and the first terminal of the first gate diffusion input unit 12 are both connected to the first input signal, the output terminal of the third inverter 11 is connected to the second terminal of the first gate diffusion input unit 12; the third terminal of the first gate diffusion input unit 12 is connected to the second input signal, and the fourth terminal of the first gate diffusion input unit 12 is connected to the first input terminal of the second XOR gate circuit 20.
[0070] For example, as shown in Figures 4 and 5, in this embodiment of the application, the first input signal is the carry input signal Ci in positive phase, and the second input signal is the addend signal in negative phase. The third input signal is the inverted addend signal. For example, the input terminal of the third inverter 11 and the first terminal of the first gate diffusion input unit 12 Both are connected to the carry input signal Ci, and the output of the third inverter 11 is connected to the second terminal of the first gate diffusion input unit 12. Connection; the third terminal of the first gate diffusion input unit 12 With addend signal Connection, fourth terminal of the first gate diffusion input unit 12 It is connected to the first input terminal of the second XOR gate circuit 20.
[0071] Optionally, referring to Figure 5, the circuit structure of the third inverter 11 is similar to that of the first inverter 40, including a first PMOS transistor Q5 and a first NMOS transistor Q6, and the first gate diffusion input unit 12 includes a second PMOS transistor Q7 and a second NMOS transistor Q8.
[0072] The source of the first PMOS transistor Q5 is connected to the power supply, the source of the first NMOS transistor Q6 is grounded, the gates of the first PMOS transistor Q5, the first NMOS transistor Q6, and the source of the second PMOS transistor Q7 are all connected to the first input signal, the drains of the first PMOS transistor Q5 and the first NMOS transistor Q6 are all connected to the source of the second NMOS transistor Q8; the gates of the second PMOS transistor Q7 and the second NMOS transistor Q8 are all connected to the second input signal, and the drains of the second PMOS transistor Q7 and the second NMOS transistor Q8 are all connected to the first input terminal of the second XOR gate circuit 20.
[0073] In the first XOR gate circuit mentioned above, the XOR of the first input signal and the second input signal is realized by using four MOSFETs, which can effectively reduce the number of MOSFETs.
[0074] In one embodiment, as shown in FIG4, the second XOR gate circuit 20 includes a fourth inverter 21 and a second gate diffusion input unit 22; the input terminal of the fourth inverter 21 and the first terminal of the second gate diffusion input unit 22 are both connected to the output terminal of the first XOR gate circuit 10, and the output terminal of the fourth inverter 21 is connected to the second terminal of the second gate diffusion input unit 22; the third terminal of the second gate diffusion input unit 22 is connected to the third input signal, and the fourth terminal of the second gate diffusion input unit 22 is used to output a positive sum signal.
[0075] For example, referring to Figures 4 and 5, the input terminal of the fourth inverter 21 and the first terminal of the second gate diffusion input unit 22 All are connected to the output of the first XOR gate circuit 10, and the output of the fourth inverter 21 is connected to the second terminal of the second gate diffusion input unit 22. Connection; the third terminal of the second gate diffusion input unit 22 With the addend signal Connection, fourth terminal of the second gate diffusion input unit 22 Used to output the positive-phase sum signal S.
[0076] Optionally, the circuit structure of the fourth inverter 21 is similar to that of the first inverter 40, including the third PMOS transistor Q9 and the third NMOS transistor Q10, and the second gate diffusion input unit 22 includes the fourth PMOS transistor Q11 and the fourth NMOS transistor Q12.
[0077] The source of the third PMOS transistor Q9 is connected to the power supply, the source of the third NMOS transistor Q10 is grounded, the gates of the third PMOS transistor Q9, the third NMOS transistor Q10, and the source of the fourth PMOS transistor Q11 are all connected to the output of the first XOR gate circuit 10, the drains of the third PMOS transistor Q9 and the third NMOS transistor Q10 are all connected to the source of the fourth NMOS transistor Q12; the gates of the fourth PMOS transistor Q11 and the fourth NMOS transistor Q12 are all connected to the third input signal, and the drains of the fourth PMOS transistor Q11 and the fourth NMOS transistor Q12 are connected to output a positive sum signal S.
[0078] In the second XOR gate circuit described above, the XOR operation between the third input signal and the first XOR signal is achieved through four MOSFETs, which effectively reduces the number of MOSFETs.
[0079] In one embodiment, as shown in Figures 4 and 5, the carry circuit 30 includes a fifth PMOS transistor Q13 and a fifth NMOS transistor Q14; the gates of both the fifth PMOS transistor Q13 and the fifth NMOS transistor Q14 are connected to the output of the first XOR gate circuit 10, the source of the fifth PMOS transistor Q13 is connected to the third input signal, the source of the fifth NMOS transistor Q14 is connected to the second input signal, and the drain of the fifth PMOS transistor Q13 is connected to the drain of the fifth NMOS transistor Q14, for outputting a carry output signal from the second input signal and the third input signal according to the first XOR signal.
[0080] Optionally, after the gates of the fifth PMOS transistor Q13 and the fifth NMOS transistor Q14 are connected, a first XOR signal is applied, and a carry output signal is output from the second input signal and the third input signal (i.e., the addend signal and the augend signal) according to the value of the first XOR signal. .
[0081] When the value of the first XOR signal is 1, the carry circuit 30 uses the second input signal as the carry output signal; when the value of the first XOR signal is 0, the carry circuit 30 uses the third input signal as the carry output signal.
[0082] The following is an example illustrating how the carry circuit determines the correctness of the carry output signal:
[0083] When the first carry input signal Ci and the second input signal Conversely, if the value of the first XOR signal is 1, the second input signal is selected. This is the carry output signal. For example, when A and Ci are both 0, the carry after adding A, B, and Ci normally should be 0. However, in this embodiment, the output carry signal is an inverted signal to accommodate the subsequent requirement of using a single inverter as a buffer. Therefore, the carry output signal should be 1 at this time, which is consistent with the selection of the second input signal. The carry output signal is consistent with this. When A and Ci are both 1, the carry after normal addition of A, B, and Ci should be 1. Similarly, in this embodiment, the carry output signal should be 0, which is consistent with the selection of the second input signal. To ensure consistency between the carry and output signals.
[0084] When the first carry input signal Ci and the second input signal When the values are the same, the value of the first XOR signal is 0, and the third input signal is selected. This is the carry output signal. For example, when A and C are opposite, the carry after A, B, and Ci are added normally is determined by B (when A and B are 1 and C is 0, the carry is 1; when A and B are 0 and C is 1, the carry is 0; when A is 1 and B and C is 0, the carry is 0; when A is 0 and B and C is 1, the carry is 1). However, in this embodiment, the output carry signal is an inverted signal to accommodate the subsequent requirement of using a single inverter as a buffer. Therefore, the carry output signal should be... This, when XORed with the first signal, results in a value of 0, thus selecting the third input signal. To ensure consistency between the carry and output signals.
[0085] For details on the specific implementation methods and beneficial effects of the digital in-memory computing architecture based on the full adder architecture, please refer to the relevant descriptions in the above full adder architecture implementation methods, which will not be repeated here.
[0086] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0088] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A digital in-memory computing architecture based on a full adder architecture, characterized in that, The full adder architecture includes a first XOR gate, a second XOR gate, and a carry circuit. The two inputs of the first XOR gate are connected to a first input signal and a second input signal, respectively. The output of the first XOR gate is connected to both the first input of the second XOR gate and the first input of the carry circuit. The output of the first XOR gate is used to output a first XOR signal. The first XOR gate includes four MOS transistors. The first input signal is a carry input signal, the second input signal is either the addend signal or the augend signal, the addend signal and the augend signal are inverted signals, and the carry input signal is a positive signal. The second input terminal of the second XOR gate circuit is connected to the third input signal, and the output terminal of the second XOR gate circuit is used to output a positive sum signal. The second XOR gate circuit includes four MOS transistors. The third input signal is one of the addend signal and the augend signal other than the second input signal. The second and third input terminals of the carry circuit are respectively connected to the second input signal and the third input signal. The output terminal of the carry circuit is used to output a carry output signal from the second input signal and the third input signal according to the first XOR signal. The carry output signal is an inverted signal. The carry circuit includes two MOS transistors.
2. The digital in-memory computing architecture according to claim 1, characterized in that, The full adder architecture also includes a first inverter; the first inverter is connected to the output of the second XOR gate circuit and is used to output an inverted sum signal.
3. The digital in-memory computing architecture according to claim 1 or 2, characterized in that, The full adder architecture also includes a second inverter; the second inverter is connected to the output terminal of the carry circuit and is used to output a positive carry output signal.
4. The digital in-memory computing architecture according to claim 1, characterized in that, The first XOR gate circuit includes a third inverter and a first gate diffusion input unit; the input terminal of the third inverter and the first terminal of the first gate diffusion input unit are both connected to the first input signal, the output terminal of the third inverter is connected to the second terminal of the first gate diffusion input unit; the third terminal of the first gate diffusion input unit is connected to the second input signal, and the fourth terminal of the first gate diffusion input unit is connected to the first input terminal of the second XOR gate circuit.
5. The digital in-memory computing architecture according to claim 4, characterized in that, The third inverter includes a first PMOS transistor and a first NMOS transistor, and the first gate diffusion input unit includes a second PMOS transistor and a second NMOS transistor. The source of the first PMOS transistor is connected to the power supply, the source of the first NMOS transistor is grounded, the gate of the first PMOS transistor, the gate of the first NMOS transistor, and the source of the second PMOS transistor are all connected to the first input signal, and the drain of the first PMOS transistor and the drain of the first NMOS transistor are all connected to the source of the second NMOS transistor. The gate of the second PMOS transistor and the gate of the second NMOS transistor are both connected to the second input signal, and the drain of the second PMOS transistor and the drain of the second NMOS transistor are both connected to the first input terminal of the second XOR gate circuit.
6. The digital in-memory computing architecture according to claim 1, characterized in that, The second XOR gate circuit includes a fourth inverter and a second gate diffusion input unit; the input terminal of the fourth inverter and the first terminal of the second gate diffusion input unit are both connected to the output terminal of the first XOR gate circuit, and the output terminal of the fourth inverter is connected to the second terminal of the second gate diffusion input unit; the third terminal of the second gate diffusion input unit is connected to the third input signal, and the fourth terminal of the second gate diffusion input unit is used to output the positive sum signal.
7. The digital in-memory computing architecture according to claim 6, characterized in that, The fourth inverter includes a third PMOS transistor and a third NMOS transistor, and the second gate diffusion input unit includes a fourth PMOS transistor and a fourth NMOS transistor. The source of the third PMOS transistor is connected to the power supply, and the source of the third NMOS transistor is grounded. The gates of the third PMOS transistor, the third NMOS transistor, and the fourth PMOS transistor are all connected to the output terminal of the first XOR gate circuit. The drains of the third PMOS transistor and the third NMOS transistor are both connected to the source of the fourth NMOS transistor. The gates of the fourth PMOS transistor and the fourth NMOS transistor are both connected to the third input signal, and the drains of the fourth PMOS transistor and the fourth NMOS transistor are connected to output the positive sum signal.
8. The digital in-memory computing architecture according to claim 1, characterized in that, The carry circuit includes a fifth PMOS transistor and a fifth NMOS transistor; the gates of the fifth PMOS transistor and the fifth NMOS transistor are both connected to the output terminal of the first XOR gate circuit, the source of the fifth PMOS transistor is connected to the third input signal, the source of the fifth NMOS transistor is connected to the second input signal, and the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, for outputting the carry output signal from the second input signal and the third input signal according to the first XOR signal.
9. The digital in-memory computing architecture according to claim 1, characterized in that, The carry circuit is used to take the second input signal as the carry output signal when the value of the first XOR signal is 1.
10. The digital in-memory computing architecture according to claim 1, characterized in that, The carry circuit is used to take the third input signal as the carry output signal when the value of the first XOR signal is 0.